2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2010 Cavium Networks
9 #include <linux/module.h>
10 #include <linux/delay.h>
12 #include <asm/atomic.h>
14 #include <asm/octeon/octeon.h>
15 #include <asm/octeon/cvmx-uctlx-defs.h>
17 static atomic_t octeon2_usb_clock_start_cnt = ATOMIC_INIT(0);
19 void octeon2_usb_clocks_start(void)
22 union cvmx_uctlx_if_ena if_ena;
23 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
24 union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
25 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
27 unsigned long io_clk_64_to_ns;
29 if (atomic_inc_return(&octeon2_usb_clock_start_cnt) != 1)
32 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
35 * Step 1: Wait for voltages stable. That surely happened
36 * before starting the kernel.
38 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
42 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
44 /* Step 3: Configure the reference clock, PHY, and HCLK */
45 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
47 clk_rst_ctl.s.p_por = 1;
48 clk_rst_ctl.s.hrst = 0;
49 clk_rst_ctl.s.p_prst = 0;
50 clk_rst_ctl.s.h_clkdiv_rst = 0;
51 clk_rst_ctl.s.o_clkdiv_rst = 0;
52 clk_rst_ctl.s.h_clkdiv_en = 0;
53 clk_rst_ctl.s.o_clkdiv_en = 0;
54 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
58 clk_rst_ctl.s.p_refclk_sel = 0;
59 clk_rst_ctl.s.p_refclk_div = 0;
60 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
63 div = octeon_get_io_clock_rate() / 130000000ull;
91 clk_rst_ctl.s.h_div = div;
92 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
94 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
95 clk_rst_ctl.s.h_clkdiv_en = 1;
96 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
98 clk_rst_ctl.s.h_clkdiv_rst = 1;
99 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
101 /* 3e: delay 64 io clocks */
102 ndelay(io_clk_64_to_ns);
105 * Step 4: Program the power-on reset field in the UCTL
106 * clock-reset-control register.
108 clk_rst_ctl.s.p_por = 0;
109 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
111 /* Step 5: Wait 1 ms for the PHY clock to start. */
115 * Step 6: Program the reset input from automatic test
116 * equipment field in the UPHY CSR
118 uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
119 uphy_ctl_status.s.ate_reset = 1;
120 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
122 /* Step 7: Wait for at least 10ns. */
125 /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
126 uphy_ctl_status.s.ate_reset = 0;
127 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
130 * Step 9: Wait for at least 20ns for UPHY to output PHY clock
131 * signals and OHCI_CLK48
135 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
137 clk_rst_ctl.s.o_clkdiv_rst = 1;
138 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
141 clk_rst_ctl.s.o_clkdiv_en = 1;
142 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
145 ndelay(io_clk_64_to_ns);
148 * Step 11: Program the PHY reset field:
149 * UCTL0_CLK_RST_CTL[P_PRST] = 1
151 clk_rst_ctl.s.p_prst = 1;
152 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
154 /* Step 12: Wait 1 uS. */
157 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
158 clk_rst_ctl.s.hrst = 1;
159 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
161 /* Now we can set some other registers. */
163 for (i = 0; i <= 1; i++) {
164 port_ctl_status.u64 =
165 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
166 /* Set txvreftune to 15 to obtain complient 'eye' diagram. */
167 port_ctl_status.s.txvreftune = 15;
168 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
169 port_ctl_status.u64);
172 EXPORT_SYMBOL(octeon2_usb_clocks_start);
174 void octeon2_usb_clocks_stop(void)
176 union cvmx_uctlx_if_ena if_ena;
178 if (atomic_dec_return(&octeon2_usb_clock_start_cnt) != 0)
183 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
185 EXPORT_SYMBOL(octeon2_usb_clocks_stop);