2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
18 * This file is licenced under the GPL.
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/usb/hcd.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/dmapool.h>
38 #include <linux/workqueue.h>
39 #include <linux/debugfs.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
45 #include <asm/byteorder.h>
48 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
49 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51 /*-------------------------------------------------------------------------*/
53 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
55 /* For initializing controller (mask in an HCFS mode too) */
56 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
57 #define OHCI_INTR_INIT \
58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
59 | OHCI_INTR_RD | OHCI_INTR_WDH)
62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
66 #ifdef CONFIG_ARCH_OMAP
67 /* OMAP doesn't support IR (no SMM; not needed) */
71 /*-------------------------------------------------------------------------*/
73 static const char hcd_name [] = "ohci_hcd";
75 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80 static int ohci_init (struct ohci_hcd *ohci);
81 static void ohci_stop (struct usb_hcd *hcd);
83 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
84 static int ohci_restart (struct ohci_hcd *ohci);
88 static void quirk_amd_pll(int state);
89 static void amd_iso_dev_put(void);
90 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
92 static inline void quirk_amd_pll(int state)
96 static inline void amd_iso_dev_put(void)
100 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
107 #include "ohci-hub.c"
108 #include "ohci-dbg.c"
109 #include "ohci-mem.c"
114 * On architectures with edge-triggered interrupts we must never return
117 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
118 #define IRQ_NOTMINE IRQ_HANDLED
120 #define IRQ_NOTMINE IRQ_NONE
124 /* Some boards misreport power switching/overcurrent */
125 static int distrust_firmware = 1;
126 module_param (distrust_firmware, bool, 0);
127 MODULE_PARM_DESC (distrust_firmware,
128 "true to distrust firmware power/overcurrent setup");
130 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
131 static int no_handshake = 0;
132 module_param (no_handshake, bool, 0);
133 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
135 /*-------------------------------------------------------------------------*/
138 * queue up an urb for anything except the root hub
140 static int ohci_urb_enqueue (
145 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
147 urb_priv_t *urb_priv;
148 unsigned int pipe = urb->pipe;
153 #ifdef OHCI_VERBOSE_DEBUG
154 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
157 /* every endpoint has a ed, locate and maybe (re)initialize it */
158 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
161 /* for the private part of the URB we need the number of TDs (size) */
164 /* td_submit_urb() doesn't yet handle these */
165 if (urb->transfer_buffer_length > 4096)
168 /* 1 TD for setup, 1 for ACK, plus ... */
171 // case PIPE_INTERRUPT:
174 /* one TD for every 4096 Bytes (can be upto 8K) */
175 size += urb->transfer_buffer_length / 4096;
176 /* ... and for any remaining bytes ... */
177 if ((urb->transfer_buffer_length % 4096) != 0)
179 /* ... and maybe a zero length packet to wrap it up */
182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 && (urb->transfer_buffer_length
184 % usb_maxpacket (urb->dev, pipe,
185 usb_pipeout (pipe))) == 0)
188 case PIPE_ISOCHRONOUS: /* number of packets from URB */
189 size = urb->number_of_packets;
193 /* allocate the private part of the URB */
194 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
198 INIT_LIST_HEAD (&urb_priv->pending);
199 urb_priv->length = size;
202 /* allocate the TDs (deferring hash chain updates) */
203 for (i = 0; i < size; i++) {
204 urb_priv->td [i] = td_alloc (ohci, mem_flags);
205 if (!urb_priv->td [i]) {
206 urb_priv->length = i;
207 urb_free_priv (ohci, urb_priv);
212 spin_lock_irqsave (&ohci->lock, flags);
214 /* don't submit to a dead HC */
215 if (!HCD_HW_ACCESSIBLE(hcd)) {
219 if (!HC_IS_RUNNING(hcd->state)) {
223 retval = usb_hcd_link_urb_to_ep(hcd, urb);
227 /* schedule the ed if needed */
228 if (ed->state == ED_IDLE) {
229 retval = ed_schedule (ohci, ed);
231 usb_hcd_unlink_urb_from_ep(hcd, urb);
234 if (ed->type == PIPE_ISOCHRONOUS) {
235 u16 frame = ohci_frame_no(ohci);
237 /* delay a few frames before the first TD */
238 frame += max_t (u16, 8, ed->interval);
239 frame &= ~(ed->interval - 1);
241 urb->start_frame = frame;
243 /* yes, only URB_ISO_ASAP is supported, and
244 * urb->start_frame is never used as input.
247 } else if (ed->type == PIPE_ISOCHRONOUS)
248 urb->start_frame = ed->last_iso + ed->interval;
250 /* fill the TDs and link them to the ed; and
251 * enable that part of the schedule, if needed
252 * and update count of queued periodic urbs
254 urb->hcpriv = urb_priv;
255 td_submit_urb (ohci, urb);
259 urb_free_priv (ohci, urb_priv);
260 spin_unlock_irqrestore (&ohci->lock, flags);
265 * decouple the URB from the HC queues (TDs, urb_priv).
266 * reporting is always done
267 * asynchronously, and we might be dealing with an urb that's
268 * partially transferred, or an ED with other urbs being unlinked.
270 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
272 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
276 #ifdef OHCI_VERBOSE_DEBUG
277 urb_print(urb, "UNLINK", 1, status);
280 spin_lock_irqsave (&ohci->lock, flags);
281 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
284 } else if (HC_IS_RUNNING(hcd->state)) {
285 urb_priv_t *urb_priv;
287 /* Unless an IRQ completed the unlink while it was being
288 * handed to us, flag it for unlink and giveback, and force
289 * some upcoming INTR_SF to call finish_unlinks()
291 urb_priv = urb->hcpriv;
293 if (urb_priv->ed->state == ED_OPER)
294 start_ed_unlink (ohci, urb_priv->ed);
298 * with HC dead, we won't respect hc queue pointers
299 * any more ... just clean up every urb's memory.
302 finish_urb(ohci, urb, status);
304 spin_unlock_irqrestore (&ohci->lock, flags);
308 /*-------------------------------------------------------------------------*/
310 /* frees config/altsetting state for endpoints,
311 * including ED memory, dummy TD, and bulk/intr data toggle
315 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
317 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
319 struct ed *ed = ep->hcpriv;
320 unsigned limit = 1000;
322 /* ASSERT: any requests/urbs are being unlinked */
323 /* ASSERT: nobody can be submitting urbs for this any more */
329 spin_lock_irqsave (&ohci->lock, flags);
331 if (!HC_IS_RUNNING (hcd->state)) {
334 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
335 ohci->eds_scheduled--;
336 finish_unlinks (ohci, 0);
340 case ED_UNLINK: /* wait for hw to finish? */
341 /* major IRQ delivery trouble loses INTR_SF too... */
343 ohci_warn(ohci, "ED unlink timeout\n");
344 if (quirk_zfmicro(ohci)) {
345 ohci_warn(ohci, "Attempting ZF TD recovery\n");
346 ohci->ed_to_check = ed;
351 spin_unlock_irqrestore (&ohci->lock, flags);
352 schedule_timeout_uninterruptible(1);
354 case ED_IDLE: /* fully unlinked */
355 if (list_empty (&ed->td_list)) {
356 td_free (ohci, ed->dummy);
360 /* else FALL THROUGH */
362 /* caller was supposed to have unlinked any requests;
363 * that's not our job. can't recover; must leak ed.
365 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
366 ed, ep->desc.bEndpointAddress, ed->state,
367 list_empty (&ed->td_list) ? "" : " (has tds)");
368 td_free (ohci, ed->dummy);
372 spin_unlock_irqrestore (&ohci->lock, flags);
375 static int ohci_get_frame (struct usb_hcd *hcd)
377 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
379 return ohci_frame_no(ohci);
382 static void ohci_usb_reset (struct ohci_hcd *ohci)
384 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
385 ohci->hc_control &= OHCI_CTRL_RWC;
386 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
389 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
390 * other cases where the next software may expect clean state from the
391 * "firmware". this is bus-neutral, unlike shutdown() methods.
394 ohci_shutdown (struct usb_hcd *hcd)
396 struct ohci_hcd *ohci;
398 ohci = hcd_to_ohci (hcd);
399 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
400 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
402 /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
403 ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
404 OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
406 ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
408 /* flush the writes */
409 (void) ohci_readl (ohci, &ohci->regs->control);
412 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
414 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
415 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
416 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
417 && !list_empty(&ed->td_list);
420 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
421 * an interrupt TD but neglects to add it to the donelist. On systems with
422 * this chipset, we need to periodically check the state of the queues to look
423 * for such "lost" TDs.
425 static void unlink_watchdog_func(unsigned long _ohci)
429 unsigned seen_count = 0;
431 struct ed **seen = NULL;
432 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
434 spin_lock_irqsave(&ohci->lock, flags);
435 max = ohci->eds_scheduled;
439 if (ohci->ed_to_check)
442 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
446 for (i = 0; i < NUM_INTS; i++) {
447 struct ed *ed = ohci->periodic[i];
452 /* scan this branch of the periodic schedule tree */
453 for (temp = 0; temp < seen_count; temp++) {
454 if (seen[temp] == ed) {
455 /* we've checked it and what's after */
462 seen[seen_count++] = ed;
463 if (!check_ed(ohci, ed)) {
468 /* HC's TD list is empty, but HCD sees at least one
469 * TD that's not been sent through the donelist.
471 ohci->ed_to_check = ed;
474 /* The HC may wait until the next frame to report the
475 * TD as done through the donelist and INTR_WDH. (We
476 * just *assume* it's not a multi-TD interrupt URB;
477 * those could defer the IRQ more than one frame, using
478 * DI...) Check again after the next INTR_SF.
480 ohci_writel(ohci, OHCI_INTR_SF,
481 &ohci->regs->intrstatus);
482 ohci_writel(ohci, OHCI_INTR_SF,
483 &ohci->regs->intrenable);
485 /* flush those writes */
486 (void) ohci_readl(ohci, &ohci->regs->control);
493 if (ohci->eds_scheduled)
494 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
496 spin_unlock_irqrestore(&ohci->lock, flags);
499 /*-------------------------------------------------------------------------*
501 *-------------------------------------------------------------------------*/
503 /* init memory, and kick BIOS/SMM off */
505 static int ohci_init (struct ohci_hcd *ohci)
508 struct usb_hcd *hcd = ohci_to_hcd(ohci);
510 if (distrust_firmware)
511 ohci->flags |= OHCI_QUIRK_HUB_POWER;
514 ohci->regs = hcd->regs;
516 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
517 * was never needed for most non-PCI systems ... remove the code?
521 /* SMM owns the HC? not for long! */
522 if (!no_handshake && ohci_readl (ohci,
523 &ohci->regs->control) & OHCI_CTRL_IR) {
526 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
528 /* this timeout is arbitrary. we make it long, so systems
529 * depending on usb keyboards may be usable even if the
530 * BIOS/SMM code seems pretty broken.
532 temp = 500; /* arbitrary: five seconds */
534 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
535 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
536 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
539 ohci_err (ohci, "USB HC takeover failed!"
540 " (BIOS/SMM bug)\n");
544 ohci_usb_reset (ohci);
548 /* Disable HC interrupts */
549 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
551 /* flush the writes, and save key bits like RWC */
552 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
553 ohci->hc_control |= OHCI_CTRL_RWC;
555 /* Read the number of ports unless overridden */
556 if (ohci->num_ports == 0)
557 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
562 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
563 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
567 if ((ret = ohci_mem_init (ohci)) < 0)
570 create_debug_files (ohci);
576 /*-------------------------------------------------------------------------*/
578 /* Start an OHCI controller, set the BUS operational
579 * resets USB and controller
582 static int ohci_run (struct ohci_hcd *ohci)
585 int first = ohci->fminterval == 0;
586 struct usb_hcd *hcd = ohci_to_hcd(ohci);
590 /* boot firmware should have set this up (5.1.1.3.1) */
593 val = ohci_readl (ohci, &ohci->regs->fminterval);
594 ohci->fminterval = val & 0x3fff;
595 if (ohci->fminterval != FI)
596 ohci_dbg (ohci, "fminterval delta %d\n",
597 ohci->fminterval - FI);
598 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
599 /* also: power/overcurrent flags in roothub.a */
602 /* Reset USB nearly "by the book". RemoteWakeupConnected has
603 * to be checked in case boot firmware (BIOS/SMM/...) has set up
604 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
605 * If the bus glue detected wakeup capability then it should
606 * already be enabled; if so we'll just enable it again.
608 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
609 device_set_wakeup_capable(hcd->self.controller, 1);
611 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
615 case OHCI_USB_SUSPEND:
616 case OHCI_USB_RESUME:
617 ohci->hc_control &= OHCI_CTRL_RWC;
618 ohci->hc_control |= OHCI_USB_RESUME;
619 val = 10 /* msec wait */;
621 // case OHCI_USB_RESET:
623 ohci->hc_control &= OHCI_CTRL_RWC;
624 ohci->hc_control |= OHCI_USB_RESET;
625 val = 50 /* msec wait */;
628 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
630 (void) ohci_readl (ohci, &ohci->regs->control);
633 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
635 /* 2msec timelimit here means no irqs/preempt */
636 spin_lock_irq (&ohci->lock);
639 /* HC Reset requires max 10 us delay */
640 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
641 val = 30; /* ... allow extra time */
642 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
644 spin_unlock_irq (&ohci->lock);
645 ohci_err (ohci, "USB HC reset timed out!\n");
651 /* now we're in the SUSPEND state ... must go OPERATIONAL
652 * within 2msec else HC enters RESUME
654 * ... but some hardware won't init fmInterval "by the book"
655 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
656 * this if we write fmInterval after we're OPERATIONAL.
657 * Unclear about ALi, ServerWorks, and others ... this could
658 * easily be a longstanding bug in chip init on Linux.
660 if (ohci->flags & OHCI_QUIRK_INITRESET) {
661 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
662 // flush those writes
663 (void) ohci_readl (ohci, &ohci->regs->control);
666 /* Tell the controller where the control and bulk lists are
667 * The lists are empty now. */
668 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
669 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
671 /* a reset clears this */
672 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
674 periodic_reinit (ohci);
676 /* some OHCI implementations are finicky about how they init.
677 * bogus values here mean not even enumeration could work.
679 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
680 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
681 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
682 ohci->flags |= OHCI_QUIRK_INITRESET;
683 ohci_dbg (ohci, "enabling initreset quirk\n");
686 spin_unlock_irq (&ohci->lock);
687 ohci_err (ohci, "init err (%08x %04x)\n",
688 ohci_readl (ohci, &ohci->regs->fminterval),
689 ohci_readl (ohci, &ohci->regs->periodicstart));
693 /* use rhsc irqs after khubd is fully initialized */
694 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
695 hcd->uses_new_polling = 1;
697 /* start controller operations */
698 ohci->hc_control &= OHCI_CTRL_RWC;
699 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
700 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
701 hcd->state = HC_STATE_RUNNING;
703 /* wake on ConnectStatusChange, matching external hubs */
704 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
706 /* Choose the interrupts we care about now, others later on demand */
707 mask = OHCI_INTR_INIT;
708 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
709 ohci_writel (ohci, mask, &ohci->regs->intrenable);
711 /* handle root hub init quirks ... */
712 val = roothub_a (ohci);
713 val &= ~(RH_A_PSM | RH_A_OCPM);
714 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
715 /* NSC 87560 and maybe others */
717 val &= ~(RH_A_POTPGT | RH_A_NPS);
718 ohci_writel (ohci, val, &ohci->regs->roothub.a);
719 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
720 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
721 /* hub power always on; required for AMD-756 and some
722 * Mac platforms. ganged overcurrent reporting, if any.
725 ohci_writel (ohci, val, &ohci->regs->roothub.a);
727 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
728 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
729 &ohci->regs->roothub.b);
730 // flush those writes
731 (void) ohci_readl (ohci, &ohci->regs->control);
733 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
734 spin_unlock_irq (&ohci->lock);
736 // POTPGT delay is bits 24-31, in 2 ms units.
737 mdelay ((val >> 23) & 0x1fe);
738 hcd->state = HC_STATE_RUNNING;
740 if (quirk_zfmicro(ohci)) {
741 /* Create timer to watch for bad queue state on ZF Micro */
742 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
743 (unsigned long) ohci);
745 ohci->eds_scheduled = 0;
746 ohci->ed_to_check = NULL;
754 /*-------------------------------------------------------------------------*/
756 /* an interrupt happens */
758 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
760 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
761 struct ohci_regs __iomem *regs = ohci->regs;
764 /* Read interrupt status (and flush pending writes). We ignore the
765 * optimization of checking the LSB of hcca->done_head; it doesn't
766 * work on all systems (edge triggering for OHCI can be a factor).
768 ints = ohci_readl(ohci, ®s->intrstatus);
770 /* Check for an all 1's result which is a typical consequence
771 * of dead, unclocked, or unplugged (CardBus...) devices
773 if (ints == ~(u32)0) {
775 ohci_dbg (ohci, "device removed!\n");
779 /* We only care about interrupts that are enabled */
780 ints &= ohci_readl(ohci, ®s->intrenable);
782 /* interrupt for some other device? */
786 if (ints & OHCI_INTR_UE) {
787 // e.g. due to PCI Master/Target Abort
788 if (quirk_nec(ohci)) {
789 /* Workaround for a silicon bug in some NEC chips used
790 * in Apple's PowerBooks. Adapted from Darwin code.
792 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
794 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
796 schedule_work (&ohci->nec_work);
799 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
803 ohci_usb_reset (ohci);
806 if (ints & OHCI_INTR_RHSC) {
807 ohci_vdbg(ohci, "rhsc\n");
808 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
809 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
812 /* NOTE: Vendors didn't always make the same implementation
813 * choices for RHSC. Many followed the spec; RHSC triggers
814 * on an edge, like setting and maybe clearing a port status
815 * change bit. With others it's level-triggered, active
816 * until khubd clears all the port status change bits. We'll
817 * always disable it here and rely on polling until khubd
820 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
821 usb_hcd_poll_rh_status(hcd);
824 /* For connect and disconnect events, we expect the controller
825 * to turn on RHSC along with RD. But for remote wakeup events
826 * this might not happen.
828 else if (ints & OHCI_INTR_RD) {
829 ohci_vdbg(ohci, "resume detect\n");
830 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
831 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
832 if (ohci->autostop) {
833 spin_lock (&ohci->lock);
834 ohci_rh_resume (ohci);
835 spin_unlock (&ohci->lock);
837 usb_hcd_resume_root_hub(hcd);
840 if (ints & OHCI_INTR_WDH) {
841 spin_lock (&ohci->lock);
843 spin_unlock (&ohci->lock);
846 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
847 spin_lock(&ohci->lock);
848 if (ohci->ed_to_check) {
849 struct ed *ed = ohci->ed_to_check;
851 if (check_ed(ohci, ed)) {
852 /* HC thinks the TD list is empty; HCD knows
853 * at least one TD is outstanding
855 if (--ohci->zf_delay == 0) {
856 struct td *td = list_entry(
860 "Reclaiming orphan TD %p\n",
862 takeback_td(ohci, td);
863 ohci->ed_to_check = NULL;
866 ohci->ed_to_check = NULL;
868 spin_unlock(&ohci->lock);
871 /* could track INTR_SO to reduce available PCI/... bandwidth */
873 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
874 * when there's still unlinking to be done (next frame).
876 spin_lock (&ohci->lock);
877 if (ohci->ed_rm_list)
878 finish_unlinks (ohci, ohci_frame_no(ohci));
879 if ((ints & OHCI_INTR_SF) != 0
881 && !ohci->ed_to_check
882 && HC_IS_RUNNING(hcd->state))
883 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
884 spin_unlock (&ohci->lock);
886 if (HC_IS_RUNNING(hcd->state)) {
887 ohci_writel (ohci, ints, ®s->intrstatus);
888 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
889 // flush those writes
890 (void) ohci_readl (ohci, &ohci->regs->control);
896 /*-------------------------------------------------------------------------*/
898 static void ohci_stop (struct usb_hcd *hcd)
900 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
904 flush_scheduled_work();
906 ohci_usb_reset (ohci);
907 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
908 free_irq(hcd->irq, hcd);
911 if (quirk_zfmicro(ohci))
912 del_timer(&ohci->unlink_watchdog);
913 if (quirk_amdiso(ohci))
916 remove_debug_files (ohci);
917 ohci_mem_cleanup (ohci);
919 dma_free_coherent (hcd->self.controller,
921 ohci->hcca, ohci->hcca_dma);
927 /*-------------------------------------------------------------------------*/
929 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
931 /* must not be called from interrupt context */
932 static int ohci_restart (struct ohci_hcd *ohci)
936 struct urb_priv *priv;
938 spin_lock_irq(&ohci->lock);
941 /* Recycle any "live" eds/tds (and urbs). */
942 if (!list_empty (&ohci->pending))
943 ohci_dbg(ohci, "abort schedule...\n");
944 list_for_each_entry (priv, &ohci->pending, pending) {
945 struct urb *urb = priv->td[0]->urb;
946 struct ed *ed = priv->ed;
950 ed->state = ED_UNLINK;
951 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
952 ed_deschedule (ohci, ed);
954 ed->ed_next = ohci->ed_rm_list;
956 ohci->ed_rm_list = ed;
961 ohci_dbg(ohci, "bogus ed %p state %d\n",
966 urb->unlinked = -ESHUTDOWN;
968 finish_unlinks (ohci, 0);
969 spin_unlock_irq(&ohci->lock);
971 /* paranoia, in case that didn't work: */
973 /* empty the interrupt branches */
974 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
975 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
977 /* no EDs to remove */
978 ohci->ed_rm_list = NULL;
980 /* empty control and bulk lists */
981 ohci->ed_controltail = NULL;
982 ohci->ed_bulktail = NULL;
984 if ((temp = ohci_run (ohci)) < 0) {
985 ohci_err (ohci, "can't restart, %d\n", temp);
988 ohci_dbg(ohci, "restart complete\n");
994 /*-------------------------------------------------------------------------*/
996 MODULE_AUTHOR (DRIVER_AUTHOR);
997 MODULE_DESCRIPTION(DRIVER_DESC);
998 MODULE_LICENSE ("GPL");
1001 #include "ohci-pci.c"
1002 #define PCI_DRIVER ohci_pci_driver
1005 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1006 #include "ohci-sa1111.c"
1007 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1010 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1011 #include "ohci-s3c2410.c"
1012 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1015 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1016 #include "ohci-omap.c"
1017 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1020 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1021 #include "ohci-omap3.c"
1022 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1025 #ifdef CONFIG_ARCH_LH7A404
1026 #include "ohci-lh7a404.c"
1027 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
1030 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1031 #include "ohci-pxa27x.c"
1032 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1035 #ifdef CONFIG_ARCH_EP93XX
1036 #include "ohci-ep93xx.c"
1037 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1040 #ifdef CONFIG_MIPS_ALCHEMY
1041 #include "ohci-au1xxx.c"
1042 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1045 #ifdef CONFIG_PNX8550
1046 #include "ohci-pnx8550.c"
1047 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1050 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1051 #include "ohci-ppc-soc.c"
1052 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1055 #ifdef CONFIG_ARCH_AT91
1056 #include "ohci-at91.c"
1057 #define PLATFORM_DRIVER ohci_hcd_at91_driver
1060 #ifdef CONFIG_ARCH_PNX4008
1061 #include "ohci-pnx4008.c"
1062 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1065 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1066 #include "ohci-da8xx.c"
1067 #define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1070 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1071 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1072 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1073 defined(CONFIG_CPU_SUBTYPE_SH7786)
1074 #include "ohci-sh.c"
1075 #define PLATFORM_DRIVER ohci_hcd_sh_driver
1079 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1080 #include "ohci-ppc-of.c"
1081 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1084 #ifdef CONFIG_PLAT_SPEAR
1085 #include "ohci-spear.c"
1086 #define PLATFORM_DRIVER spear_ohci_hcd_driver
1089 #ifdef CONFIG_PPC_PS3
1090 #include "ohci-ps3.c"
1091 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1094 #ifdef CONFIG_USB_OHCI_HCD_SSB
1095 #include "ohci-ssb.c"
1096 #define SSB_OHCI_DRIVER ssb_ohci_driver
1099 #ifdef CONFIG_MFD_SM501
1100 #include "ohci-sm501.c"
1101 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1104 #ifdef CONFIG_MFD_TC6393XB
1105 #include "ohci-tmio.c"
1106 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1109 #ifdef CONFIG_MACH_JZ4740
1110 #include "ohci-jz4740.c"
1111 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1114 #ifdef CONFIG_USB_OCTEON_OHCI
1115 #include "ohci-octeon.c"
1116 #define PLATFORM_DRIVER ohci_octeon_driver
1119 #if !defined(PCI_DRIVER) && \
1120 !defined(PLATFORM_DRIVER) && \
1121 !defined(OMAP1_PLATFORM_DRIVER) && \
1122 !defined(OMAP3_PLATFORM_DRIVER) && \
1123 !defined(OF_PLATFORM_DRIVER) && \
1124 !defined(SA1111_DRIVER) && \
1125 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1126 !defined(SM501_OHCI_DRIVER) && \
1127 !defined(TMIO_OHCI_DRIVER) && \
1128 !defined(SSB_OHCI_DRIVER)
1129 #error "missing bus glue for ohci-hcd"
1132 static int __init ohci_hcd_mod_init(void)
1139 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1140 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1141 sizeof (struct ed), sizeof (struct td));
1142 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1145 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1146 if (!ohci_debug_root) {
1152 #ifdef PS3_SYSTEM_BUS_DRIVER
1153 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1158 #ifdef PLATFORM_DRIVER
1159 retval = platform_driver_register(&PLATFORM_DRIVER);
1161 goto error_platform;
1164 #ifdef OMAP1_PLATFORM_DRIVER
1165 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1167 goto error_omap1_platform;
1170 #ifdef OMAP3_PLATFORM_DRIVER
1171 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1173 goto error_omap3_platform;
1176 #ifdef OF_PLATFORM_DRIVER
1177 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1179 goto error_of_platform;
1182 #ifdef SA1111_DRIVER
1183 retval = sa1111_driver_register(&SA1111_DRIVER);
1189 retval = pci_register_driver(&PCI_DRIVER);
1194 #ifdef SSB_OHCI_DRIVER
1195 retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1200 #ifdef SM501_OHCI_DRIVER
1201 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1206 #ifdef TMIO_OHCI_DRIVER
1207 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1215 #ifdef TMIO_OHCI_DRIVER
1216 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1219 #ifdef SM501_OHCI_DRIVER
1220 platform_driver_unregister(&SM501_OHCI_DRIVER);
1223 #ifdef SSB_OHCI_DRIVER
1224 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1228 pci_unregister_driver(&PCI_DRIVER);
1231 #ifdef SA1111_DRIVER
1232 sa1111_driver_unregister(&SA1111_DRIVER);
1235 #ifdef OF_PLATFORM_DRIVER
1236 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1239 #ifdef PLATFORM_DRIVER
1240 platform_driver_unregister(&PLATFORM_DRIVER);
1243 #ifdef OMAP1_PLATFORM_DRIVER
1244 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1245 error_omap1_platform:
1247 #ifdef OMAP3_PLATFORM_DRIVER
1248 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1249 error_omap3_platform:
1251 #ifdef PS3_SYSTEM_BUS_DRIVER
1252 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1256 debugfs_remove(ohci_debug_root);
1257 ohci_debug_root = NULL;
1261 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1264 module_init(ohci_hcd_mod_init);
1266 static void __exit ohci_hcd_mod_exit(void)
1268 #ifdef TMIO_OHCI_DRIVER
1269 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1271 #ifdef SM501_OHCI_DRIVER
1272 platform_driver_unregister(&SM501_OHCI_DRIVER);
1274 #ifdef SSB_OHCI_DRIVER
1275 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1278 pci_unregister_driver(&PCI_DRIVER);
1280 #ifdef SA1111_DRIVER
1281 sa1111_driver_unregister(&SA1111_DRIVER);
1283 #ifdef OF_PLATFORM_DRIVER
1284 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1286 #ifdef PLATFORM_DRIVER
1287 platform_driver_unregister(&PLATFORM_DRIVER);
1289 #ifdef OMAP3_PLATFORM_DRIVER
1290 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1292 #ifdef PS3_SYSTEM_BUS_DRIVER
1293 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1296 debugfs_remove(ohci_debug_root);
1298 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1300 module_exit(ohci_hcd_mod_exit);