drivers/usb/host/ohci-hcd.c

   1 /*
   2  * Open Host Controller Interface (OHCI) driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   7  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   8  *
   9  * [ Initialisation is based on Linus'  ]
  10  * [ uhci code and gregs ohci fragments ]
  11  * [ (C) Copyright 1999 Linus Torvalds  ]
  12  * [ (C) Copyright 1999 Gregory P. Smith]
  13  *
  14  *
  15  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  16  * interfaces (though some non-x86 Intel chips use it).  It supports
  17  * smarter hardware than UHCI.  A download link for the spec available
  18  * through the http://www.usb.org website.
  19  *
  20  * This file is licenced under the GPL.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/pci.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/ioport.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/hcd.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmapool.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/debugfs.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/unaligned.h>
  46 #include <asm/byteorder.h>
  47
  48
  49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  51
  52 /*-------------------------------------------------------------------------*/
  53
  54 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  55
  56 /* For initializing controller (mask in an HCFS mode too) */
  57 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  58 #define OHCI_INTR_INIT \
  59                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  60                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  61
  62 #ifdef __hppa__
  63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  64 #define IR_DISABLE
  65 #endif
  66
  67 #ifdef CONFIG_ARCH_OMAP
  68 /* OMAP doesn't support IR (no SMM; not needed) */
  69 #define IR_DISABLE
  70 #endif
  71
  72 /*-------------------------------------------------------------------------*/
  73
  74 static const char       hcd_name [] = "ohci_hcd";
  75
  76 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  77
  78 #include "ohci.h"
  79 #include "pci-quirks.h"
  80
  81 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  82 static void ohci_stop (struct usb_hcd *hcd);
  83 #ifdef CONFIG_PCI
  84 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
  85 #else
  86 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
  87 {
  88         return;
  89 }
  90 #endif
  91
  92
  93 #include "ohci-hub.c"
  94 #include "ohci-dbg.c"
  95 #include "ohci-mem.c"
  96 #include "ohci-q.c"
  97
  98
  99 /*
 100  * On architectures with edge-triggered interrupts we must never return
 101  * IRQ_NONE.
 102  */
 103 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
 104 #define IRQ_NOTMINE     IRQ_HANDLED
 105 #else
 106 #define IRQ_NOTMINE     IRQ_NONE
 107 #endif
 108
 109
 110 /* Some boards misreport power switching/overcurrent */
 111 static bool distrust_firmware = 1;
 112 module_param (distrust_firmware, bool, 0);
 113 MODULE_PARM_DESC (distrust_firmware,
 114         "true to distrust firmware power/overcurrent setup");
 115
 116 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 117 static bool no_handshake = 0;
 118 module_param (no_handshake, bool, 0);
 119 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 120
 121 /*-------------------------------------------------------------------------*/
 122
 123 /*
 124  * queue up an urb for anything except the root hub
 125  */
 126 static int ohci_urb_enqueue (
 127         struct usb_hcd  *hcd,
 128         struct urb      *urb,
 129         gfp_t           mem_flags
 130 ) {
 131         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 132         struct ed       *ed;
 133         urb_priv_t      *urb_priv;
 134         unsigned int    pipe = urb->pipe;
 135         int             i, size = 0;
 136         unsigned long   flags;
 137         int             retval = 0;
 138
 139 #ifdef OHCI_VERBOSE_DEBUG
 140         urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
 141 #endif
 142
 143         /* every endpoint has a ed, locate and maybe (re)initialize it */
 144         if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
 145                 return -ENOMEM;
 146
 147         /* for the private part of the URB we need the number of TDs (size) */
 148         switch (ed->type) {
 149                 case PIPE_CONTROL:
 150                         /* td_submit_urb() doesn't yet handle these */
 151                         if (urb->transfer_buffer_length > 4096)
 152                                 return -EMSGSIZE;
 153
 154                         /* 1 TD for setup, 1 for ACK, plus ... */
 155                         size = 2;
 156                         /* FALLTHROUGH */
 157                 // case PIPE_INTERRUPT:
 158                 // case PIPE_BULK:
 159                 default:
 160                         /* one TD for every 4096 Bytes (can be up to 8K) */
 161                         size += urb->transfer_buffer_length / 4096;
 162                         /* ... and for any remaining bytes ... */
 163                         if ((urb->transfer_buffer_length % 4096) != 0)
 164                                 size++;
 165                         /* ... and maybe a zero length packet to wrap it up */
 166                         if (size == 0)
 167                                 size++;
 168                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 169                                 && (urb->transfer_buffer_length
 170                                         % usb_maxpacket (urb->dev, pipe,
 171                                                 usb_pipeout (pipe))) == 0)
 172                                 size++;
 173                         break;
 174                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 175                         size = urb->number_of_packets;
 176                         break;
 177         }
 178
 179         /* allocate the private part of the URB */
 180         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 181                         mem_flags);
 182         if (!urb_priv)
 183                 return -ENOMEM;
 184         INIT_LIST_HEAD (&urb_priv->pending);
 185         urb_priv->length = size;
 186         urb_priv->ed = ed;
 187
 188         /* allocate the TDs (deferring hash chain updates) */
 189         for (i = 0; i < size; i++) {
 190                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 191                 if (!urb_priv->td [i]) {
 192                         urb_priv->length = i;
 193                         urb_free_priv (ohci, urb_priv);
 194                         return -ENOMEM;
 195                 }
 196         }
 197
 198         spin_lock_irqsave (&ohci->lock, flags);
 199
 200         /* don't submit to a dead HC */
 201         if (!HCD_HW_ACCESSIBLE(hcd)) {
 202                 retval = -ENODEV;
 203                 goto fail;
 204         }
 205         if (ohci->rh_state != OHCI_RH_RUNNING) {
 206                 retval = -ENODEV;
 207                 goto fail;
 208         }
 209         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 210         if (retval)
 211                 goto fail;
 212
 213         /* schedule the ed if needed */
 214         if (ed->state == ED_IDLE) {
 215                 retval = ed_schedule (ohci, ed);
 216                 if (retval < 0) {
 217                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 218                         goto fail;
 219                 }
 220                 if (ed->type == PIPE_ISOCHRONOUS) {
 221                         u16     frame = ohci_frame_no(ohci);
 222
 223                         /* delay a few frames before the first TD */
 224                         frame += max_t (u16, 8, ed->interval);
 225                         frame &= ~(ed->interval - 1);
 226                         frame |= ed->branch;
 227                         urb->start_frame = frame;
 228                 }
 229         } else if (ed->type == PIPE_ISOCHRONOUS) {
 230                 u16     next = ohci_frame_no(ohci) + 1;
 231                 u16     frame = ed->last_iso + ed->interval;
 232
 233                 /* Behind the scheduling threshold? */
 234                 if (unlikely(tick_before(frame, next))) {
 235
 236                         /* USB_ISO_ASAP: Round up to the first available slot */
 237                         if (urb->transfer_flags & URB_ISO_ASAP) {
 238                                 frame += (next - frame + ed->interval - 1) &
 239                                                 -ed->interval;
 240
 241                         /*
 242                          * Not ASAP: Use the next slot in the stream.  If
 243                          * the entire URB falls before the threshold, fail.
 244                          */
 245                         } else {
 246                                 if (tick_before(frame + ed->interval *
 247                                         (urb->number_of_packets - 1), next)) {
 248                                         retval = -EXDEV;
 249                                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 250                                         goto fail;
 251                                 }
 252
 253                                 /*
 254                                  * Some OHCI hardware doesn't handle late TDs
 255                                  * correctly.  After retiring them it proceeds
 256                                  * to the next ED instead of the next TD.
 257                                  * Therefore we have to omit the late TDs
 258                                  * entirely.
 259                                  */
 260                                 urb_priv->td_cnt = DIV_ROUND_UP(
 261                                                 (u16) (next - frame),
 262                                                 ed->interval);
 263                         }
 264                 }
 265                 urb->start_frame = frame;
 266         }
 267
 268         /* fill the TDs and link them to the ed; and
 269          * enable that part of the schedule, if needed
 270          * and update count of queued periodic urbs
 271          */
 272         urb->hcpriv = urb_priv;
 273         td_submit_urb (ohci, urb);
 274
 275 fail:
 276         if (retval)
 277                 urb_free_priv (ohci, urb_priv);
 278         spin_unlock_irqrestore (&ohci->lock, flags);
 279         return retval;
 280 }
 281
 282 /*
 283  * decouple the URB from the HC queues (TDs, urb_priv).
 284  * reporting is always done
 285  * asynchronously, and we might be dealing with an urb that's
 286  * partially transferred, or an ED with other urbs being unlinked.
 287  */
 288 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 289 {
 290         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 291         unsigned long           flags;
 292         int                     rc;
 293
 294 #ifdef OHCI_VERBOSE_DEBUG
 295         urb_print(urb, "UNLINK", 1, status);
 296 #endif
 297
 298         spin_lock_irqsave (&ohci->lock, flags);
 299         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 300         if (rc) {
 301                 ;       /* Do nothing */
 302         } else if (ohci->rh_state == OHCI_RH_RUNNING) {
 303                 urb_priv_t  *urb_priv;
 304
 305                 /* Unless an IRQ completed the unlink while it was being
 306                  * handed to us, flag it for unlink and giveback, and force
 307                  * some upcoming INTR_SF to call finish_unlinks()
 308                  */
 309                 urb_priv = urb->hcpriv;
 310                 if (urb_priv) {
 311                         if (urb_priv->ed->state == ED_OPER)
 312                                 start_ed_unlink (ohci, urb_priv->ed);
 313                 }
 314         } else {
 315                 /*
 316                  * with HC dead, we won't respect hc queue pointers
 317                  * any more ... just clean up every urb's memory.
 318                  */
 319                 if (urb->hcpriv)
 320                         finish_urb(ohci, urb, status);
 321         }
 322         spin_unlock_irqrestore (&ohci->lock, flags);
 323         return rc;
 324 }
 325
 326 /*-------------------------------------------------------------------------*/
 327
 328 /* frees config/altsetting state for endpoints,
 329  * including ED memory, dummy TD, and bulk/intr data toggle
 330  */
 331
 332 static void
 333 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 334 {
 335         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 336         unsigned long           flags;
 337         struct ed               *ed = ep->hcpriv;
 338         unsigned                limit = 1000;
 339
 340         /* ASSERT:  any requests/urbs are being unlinked */
 341         /* ASSERT:  nobody can be submitting urbs for this any more */
 342
 343         if (!ed)
 344                 return;
 345
 346 rescan:
 347         spin_lock_irqsave (&ohci->lock, flags);
 348
 349         if (ohci->rh_state != OHCI_RH_RUNNING) {
 350 sanitize:
 351                 ed->state = ED_IDLE;
 352                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
 353                         ohci->eds_scheduled--;
 354                 finish_unlinks (ohci, 0);
 355         }
 356
 357         switch (ed->state) {
 358         case ED_UNLINK:         /* wait for hw to finish? */
 359                 /* major IRQ delivery trouble loses INTR_SF too... */
 360                 if (limit-- == 0) {
 361                         ohci_warn(ohci, "ED unlink timeout\n");
 362                         if (quirk_zfmicro(ohci)) {
 363                                 ohci_warn(ohci, "Attempting ZF TD recovery\n");
 364                                 ohci->ed_to_check = ed;
 365                                 ohci->zf_delay = 2;
 366                         }
 367                         goto sanitize;
 368                 }
 369                 spin_unlock_irqrestore (&ohci->lock, flags);
 370                 schedule_timeout_uninterruptible(1);
 371                 goto rescan;
 372         case ED_IDLE:           /* fully unlinked */
 373                 if (list_empty (&ed->td_list)) {
 374                         td_free (ohci, ed->dummy);
 375                         ed_free (ohci, ed);
 376                         break;
 377                 }
 378                 /* else FALL THROUGH */
 379         default:
 380                 /* caller was supposed to have unlinked any requests;
 381                  * that's not our job.  can't recover; must leak ed.
 382                  */
 383                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 384                         ed, ep->desc.bEndpointAddress, ed->state,
 385                         list_empty (&ed->td_list) ? "" : " (has tds)");
 386                 td_free (ohci, ed->dummy);
 387                 break;
 388         }
 389         ep->hcpriv = NULL;
 390         spin_unlock_irqrestore (&ohci->lock, flags);
 391 }
 392
 393 static int ohci_get_frame (struct usb_hcd *hcd)
 394 {
 395         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 396
 397         return ohci_frame_no(ohci);
 398 }
 399
 400 static void ohci_usb_reset (struct ohci_hcd *ohci)
 401 {
 402         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 403         ohci->hc_control &= OHCI_CTRL_RWC;
 404         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 405         ohci->rh_state = OHCI_RH_HALTED;
 406 }
 407
 408 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 409  * other cases where the next software may expect clean state from the
 410  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 411  */
 412 static void
 413 ohci_shutdown (struct usb_hcd *hcd)
 414 {
 415         struct ohci_hcd *ohci;
 416
 417         ohci = hcd_to_ohci (hcd);
 418         ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
 419
 420         /* Software reset, after which the controller goes into SUSPEND */
 421         ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
 422         ohci_readl(ohci, &ohci->regs->cmdstatus);       /* flush the writes */
 423         udelay(10);
 424
 425         ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
 426 }
 427
 428 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
 429 {
 430         return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
 431                 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
 432                         == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
 433                 && !list_empty(&ed->td_list);
 434 }
 435
 436 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
 437  * an interrupt TD but neglects to add it to the donelist.  On systems with
 438  * this chipset, we need to periodically check the state of the queues to look
 439  * for such "lost" TDs.
 440  */
 441 static void unlink_watchdog_func(unsigned long _ohci)
 442 {
 443         unsigned long   flags;
 444         unsigned        max;
 445         unsigned        seen_count = 0;
 446         unsigned        i;
 447         struct ed       **seen = NULL;
 448         struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
 449
 450         spin_lock_irqsave(&ohci->lock, flags);
 451         max = ohci->eds_scheduled;
 452         if (!max)
 453                 goto done;
 454
 455         if (ohci->ed_to_check)
 456                 goto out;
 457
 458         seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
 459         if (!seen)
 460                 goto out;
 461
 462         for (i = 0; i < NUM_INTS; i++) {
 463                 struct ed       *ed = ohci->periodic[i];
 464
 465                 while (ed) {
 466                         unsigned        temp;
 467
 468                         /* scan this branch of the periodic schedule tree */
 469                         for (temp = 0; temp < seen_count; temp++) {
 470                                 if (seen[temp] == ed) {
 471                                         /* we've checked it and what's after */
 472                                         ed = NULL;
 473                                         break;
 474                                 }
 475                         }
 476                         if (!ed)
 477                                 break;
 478                         seen[seen_count++] = ed;
 479                         if (!check_ed(ohci, ed)) {
 480                                 ed = ed->ed_next;
 481                                 continue;
 482                         }
 483
 484                         /* HC's TD list is empty, but HCD sees at least one
 485                          * TD that's not been sent through the donelist.
 486                          */
 487                         ohci->ed_to_check = ed;
 488                         ohci->zf_delay = 2;
 489
 490                         /* The HC may wait until the next frame to report the
 491                          * TD as done through the donelist and INTR_WDH.  (We
 492                          * just *assume* it's not a multi-TD interrupt URB;
 493                          * those could defer the IRQ more than one frame, using
 494                          * DI...)  Check again after the next INTR_SF.
 495                          */
 496                         ohci_writel(ohci, OHCI_INTR_SF,
 497                                         &ohci->regs->intrstatus);
 498                         ohci_writel(ohci, OHCI_INTR_SF,
 499                                         &ohci->regs->intrenable);
 500
 501                         /* flush those writes */
 502                         (void) ohci_readl(ohci, &ohci->regs->control);
 503
 504                         goto out;
 505                 }
 506         }
 507 out:
 508         kfree(seen);
 509         if (ohci->eds_scheduled)
 510                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 511 done:
 512         spin_unlock_irqrestore(&ohci->lock, flags);
 513 }
 514
 515 /*-------------------------------------------------------------------------*
 516  * HC functions
 517  *-------------------------------------------------------------------------*/
 518
 519 /* init memory, and kick BIOS/SMM off */
 520
 521 static int ohci_init (struct ohci_hcd *ohci)
 522 {
 523         int ret;
 524         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 525
 526         if (distrust_firmware)
 527                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 528
 529         ohci->rh_state = OHCI_RH_HALTED;
 530         ohci->regs = hcd->regs;
 531
 532         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 533          * was never needed for most non-PCI systems ... remove the code?
 534          */
 535
 536 #ifndef IR_DISABLE
 537         /* SMM owns the HC?  not for long! */
 538         if (!no_handshake && ohci_readl (ohci,
 539                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 540                 u32 temp;
 541
 542                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 543
 544                 /* this timeout is arbitrary.  we make it long, so systems
 545                  * depending on usb keyboards may be usable even if the
 546                  * BIOS/SMM code seems pretty broken.
 547                  */
 548                 temp = 500;     /* arbitrary: five seconds */
 549
 550                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 551                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 552                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 553                         msleep (10);
 554                         if (--temp == 0) {
 555                                 ohci_err (ohci, "USB HC takeover failed!"
 556                                         "  (BIOS/SMM bug)\n");
 557                                 return -EBUSY;
 558                         }
 559                 }
 560                 ohci_usb_reset (ohci);
 561         }
 562 #endif
 563
 564         /* Disable HC interrupts */
 565         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 566
 567         /* flush the writes, and save key bits like RWC */
 568         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 569                 ohci->hc_control |= OHCI_CTRL_RWC;
 570
 571         /* Read the number of ports unless overridden */
 572         if (ohci->num_ports == 0)
 573                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 574
 575         if (ohci->hcca)
 576                 return 0;
 577
 578         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 579                         sizeof *ohci->hcca, &ohci->hcca_dma, 0);
 580         if (!ohci->hcca)
 581                 return -ENOMEM;
 582
 583         if ((ret = ohci_mem_init (ohci)) < 0)
 584                 ohci_stop (hcd);
 585         else {
 586                 create_debug_files (ohci);
 587         }
 588
 589         return ret;
 590 }
 591
 592 /*-------------------------------------------------------------------------*/
 593
 594 /* Start an OHCI controller, set the BUS operational
 595  * resets USB and controller
 596  * enable interrupts
 597  */
 598 static int ohci_run (struct ohci_hcd *ohci)
 599 {
 600         u32                     mask, val;
 601         int                     first = ohci->fminterval == 0;
 602         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 603
 604         ohci->rh_state = OHCI_RH_HALTED;
 605
 606         /* boot firmware should have set this up (5.1.1.3.1) */
 607         if (first) {
 608
 609                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 610                 ohci->fminterval = val & 0x3fff;
 611                 if (ohci->fminterval != FI)
 612                         ohci_dbg (ohci, "fminterval delta %d\n",
 613                                 ohci->fminterval - FI);
 614                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 615                 /* also: power/overcurrent flags in roothub.a */
 616         }
 617
 618         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 619          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 620          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 621          * If the bus glue detected wakeup capability then it should
 622          * already be enabled; if so we'll just enable it again.
 623          */
 624         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 625                 device_set_wakeup_capable(hcd->self.controller, 1);
 626
 627         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 628         case OHCI_USB_OPER:
 629                 val = 0;
 630                 break;
 631         case OHCI_USB_SUSPEND:
 632         case OHCI_USB_RESUME:
 633                 ohci->hc_control &= OHCI_CTRL_RWC;
 634                 ohci->hc_control |= OHCI_USB_RESUME;
 635                 val = 10 /* msec wait */;
 636                 break;
 637         // case OHCI_USB_RESET:
 638         default:
 639                 ohci->hc_control &= OHCI_CTRL_RWC;
 640                 ohci->hc_control |= OHCI_USB_RESET;
 641                 val = 50 /* msec wait */;
 642                 break;
 643         }
 644         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 645         // flush the writes
 646         (void) ohci_readl (ohci, &ohci->regs->control);
 647         msleep(val);
 648
 649         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 650
 651         /* 2msec timelimit here means no irqs/preempt */
 652         spin_lock_irq (&ohci->lock);
 653
 654 retry:
 655         /* HC Reset requires max 10 us delay */
 656         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 657         val = 30;       /* ... allow extra time */
 658         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 659                 if (--val == 0) {
 660                         spin_unlock_irq (&ohci->lock);
 661                         ohci_err (ohci, "USB HC reset timed out!\n");
 662                         return -1;
 663                 }
 664                 udelay (1);
 665         }
 666
 667         /* now we're in the SUSPEND state ... must go OPERATIONAL
 668          * within 2msec else HC enters RESUME
 669          *
 670          * ... but some hardware won't init fmInterval "by the book"
 671          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 672          * this if we write fmInterval after we're OPERATIONAL.
 673          * Unclear about ALi, ServerWorks, and others ... this could
 674          * easily be a longstanding bug in chip init on Linux.
 675          */
 676         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 677                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 678                 // flush those writes
 679                 (void) ohci_readl (ohci, &ohci->regs->control);
 680         }
 681
 682         /* Tell the controller where the control and bulk lists are
 683          * The lists are empty now. */
 684         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 685         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 686
 687         /* a reset clears this */
 688         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 689
 690         periodic_reinit (ohci);
 691
 692         /* some OHCI implementations are finicky about how they init.
 693          * bogus values here mean not even enumeration could work.
 694          */
 695         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 696                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 697                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 698                         ohci->flags |= OHCI_QUIRK_INITRESET;
 699                         ohci_dbg (ohci, "enabling initreset quirk\n");
 700                         goto retry;
 701                 }
 702                 spin_unlock_irq (&ohci->lock);
 703                 ohci_err (ohci, "init err (%08x %04x)\n",
 704                         ohci_readl (ohci, &ohci->regs->fminterval),
 705                         ohci_readl (ohci, &ohci->regs->periodicstart));
 706                 return -EOVERFLOW;
 707         }
 708
 709         /* use rhsc irqs after khubd is fully initialized */
 710         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 711         hcd->uses_new_polling = 1;
 712
 713         /* start controller operations */
 714         ohci->hc_control &= OHCI_CTRL_RWC;
 715         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 716         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 717         ohci->rh_state = OHCI_RH_RUNNING;
 718
 719         /* wake on ConnectStatusChange, matching external hubs */
 720         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 721
 722         /* Choose the interrupts we care about now, others later on demand */
 723         mask = OHCI_INTR_INIT;
 724         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 725         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 726
 727         /* handle root hub init quirks ... */
 728         val = roothub_a (ohci);
 729         val &= ~(RH_A_PSM | RH_A_OCPM);
 730         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 731                 /* NSC 87560 and maybe others */
 732                 val |= RH_A_NOCP;
 733                 val &= ~(RH_A_POTPGT | RH_A_NPS);
 734                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 735         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 736                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 737                 /* hub power always on; required for AMD-756 and some
 738                  * Mac platforms.  ganged overcurrent reporting, if any.
 739                  */
 740                 val |= RH_A_NPS;
 741                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 742         }
 743         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 744         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 745                                                 &ohci->regs->roothub.b);
 746         // flush those writes
 747         (void) ohci_readl (ohci, &ohci->regs->control);
 748
 749         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 750         spin_unlock_irq (&ohci->lock);
 751
 752         // POTPGT delay is bits 24-31, in 2 ms units.
 753         mdelay ((val >> 23) & 0x1fe);
 754
 755         if (quirk_zfmicro(ohci)) {
 756                 /* Create timer to watch for bad queue state on ZF Micro */
 757                 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
 758                                 (unsigned long) ohci);
 759
 760                 ohci->eds_scheduled = 0;
 761                 ohci->ed_to_check = NULL;
 762         }
 763
 764         ohci_dump (ohci, 1);
 765
 766         return 0;
 767 }
 768
 769 /* ohci_setup routine for generic controller initialization */
 770
 771 int ohci_setup(struct usb_hcd *hcd)
 772 {
 773         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 774
 775         ohci_hcd_init(ohci);
 776
 777         return ohci_init(ohci);
 778 }
 779 EXPORT_SYMBOL_GPL(ohci_setup);
 780
 781 /* ohci_start routine for generic controller start of all OHCI bus glue */
 782 static int ohci_start(struct usb_hcd *hcd)
 783 {
 784         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 785         int     ret;
 786
 787         ret = ohci_run(ohci);
 788         if (ret < 0) {
 789                 ohci_err(ohci, "can't start\n");
 790                 ohci_stop(hcd);
 791         }
 792         return ret;
 793 }
 794
 795 /*-------------------------------------------------------------------------*/
 796
 797 /* an interrupt happens */
 798
 799 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 800 {
 801         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 802         struct ohci_regs __iomem *regs = ohci->regs;
 803         int                     ints;
 804
 805         /* Read interrupt status (and flush pending writes).  We ignore the
 806          * optimization of checking the LSB of hcca->done_head; it doesn't
 807          * work on all systems (edge triggering for OHCI can be a factor).
 808          */
 809         ints = ohci_readl(ohci, &regs->intrstatus);
 810
 811         /* Check for an all 1's result which is a typical consequence
 812          * of dead, unclocked, or unplugged (CardBus...) devices
 813          */
 814         if (ints == ~(u32)0) {
 815                 ohci->rh_state = OHCI_RH_HALTED;
 816                 ohci_dbg (ohci, "device removed!\n");
 817                 usb_hc_died(hcd);
 818                 return IRQ_HANDLED;
 819         }
 820
 821         /* We only care about interrupts that are enabled */
 822         ints &= ohci_readl(ohci, &regs->intrenable);
 823
 824         /* interrupt for some other device? */
 825         if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
 826                 return IRQ_NOTMINE;
 827
 828         if (ints & OHCI_INTR_UE) {
 829                 // e.g. due to PCI Master/Target Abort
 830                 if (quirk_nec(ohci)) {
 831                         /* Workaround for a silicon bug in some NEC chips used
 832                          * in Apple's PowerBooks. Adapted from Darwin code.
 833                          */
 834                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 835
 836                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 837
 838                         schedule_work (&ohci->nec_work);
 839                 } else {
 840                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 841                         ohci->rh_state = OHCI_RH_HALTED;
 842                         usb_hc_died(hcd);
 843                 }
 844
 845                 ohci_dump (ohci, 1);
 846                 ohci_usb_reset (ohci);
 847         }
 848
 849         if (ints & OHCI_INTR_RHSC) {
 850                 ohci_vdbg(ohci, "rhsc\n");
 851                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 852                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 853                                 &regs->intrstatus);
 854
 855                 /* NOTE: Vendors didn't always make the same implementation
 856                  * choices for RHSC.  Many followed the spec; RHSC triggers
 857                  * on an edge, like setting and maybe clearing a port status
 858                  * change bit.  With others it's level-triggered, active
 859                  * until khubd clears all the port status change bits.  We'll
 860                  * always disable it here and rely on polling until khubd
 861                  * re-enables it.
 862                  */
 863                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 864                 usb_hcd_poll_rh_status(hcd);
 865         }
 866
 867         /* For connect and disconnect events, we expect the controller
 868          * to turn on RHSC along with RD.  But for remote wakeup events
 869          * this might not happen.
 870          */
 871         else if (ints & OHCI_INTR_RD) {
 872                 ohci_vdbg(ohci, "resume detect\n");
 873                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 874                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 875                 if (ohci->autostop) {
 876                         spin_lock (&ohci->lock);
 877                         ohci_rh_resume (ohci);
 878                         spin_unlock (&ohci->lock);
 879                 } else
 880                         usb_hcd_resume_root_hub(hcd);
 881         }
 882
 883         if (ints & OHCI_INTR_WDH) {
 884                 spin_lock (&ohci->lock);
 885                 dl_done_list (ohci);
 886                 spin_unlock (&ohci->lock);
 887         }
 888
 889         if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
 890                 spin_lock(&ohci->lock);
 891                 if (ohci->ed_to_check) {
 892                         struct ed *ed = ohci->ed_to_check;
 893
 894                         if (check_ed(ohci, ed)) {
 895                                 /* HC thinks the TD list is empty; HCD knows
 896                                  * at least one TD is outstanding
 897                                  */
 898                                 if (--ohci->zf_delay == 0) {
 899                                         struct td *td = list_entry(
 900                                                 ed->td_list.next,
 901                                                 struct td, td_list);
 902                                         ohci_warn(ohci,
 903                                                   "Reclaiming orphan TD %p\n",
 904                                                   td);
 905                                         takeback_td(ohci, td);
 906                                         ohci->ed_to_check = NULL;
 907                                 }
 908                         } else
 909                                 ohci->ed_to_check = NULL;
 910                 }
 911                 spin_unlock(&ohci->lock);
 912         }
 913
 914         /* could track INTR_SO to reduce available PCI/... bandwidth */
 915
 916         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 917          * when there's still unlinking to be done (next frame).
 918          */
 919         spin_lock (&ohci->lock);
 920         if (ohci->ed_rm_list)
 921                 finish_unlinks (ohci, ohci_frame_no(ohci));
 922         if ((ints & OHCI_INTR_SF) != 0
 923                         && !ohci->ed_rm_list
 924                         && !ohci->ed_to_check
 925                         && ohci->rh_state == OHCI_RH_RUNNING)
 926                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 927         spin_unlock (&ohci->lock);
 928
 929         if (ohci->rh_state == OHCI_RH_RUNNING) {
 930                 ohci_writel (ohci, ints, &regs->intrstatus);
 931                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 932                 // flush those writes
 933                 (void) ohci_readl (ohci, &ohci->regs->control);
 934         }
 935
 936         return IRQ_HANDLED;
 937 }
 938
 939 /*-------------------------------------------------------------------------*/
 940
 941 static void ohci_stop (struct usb_hcd *hcd)
 942 {
 943         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 944
 945         ohci_dump (ohci, 1);
 946
 947         if (quirk_nec(ohci))
 948                 flush_work(&ohci->nec_work);
 949
 950         ohci_usb_reset (ohci);
 951         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 952         free_irq(hcd->irq, hcd);
 953         hcd->irq = 0;
 954
 955         if (quirk_zfmicro(ohci))
 956                 del_timer(&ohci->unlink_watchdog);
 957         if (quirk_amdiso(ohci))
 958                 usb_amd_dev_put();
 959
 960         remove_debug_files (ohci);
 961         ohci_mem_cleanup (ohci);
 962         if (ohci->hcca) {
 963                 dma_free_coherent (hcd->self.controller,
 964                                 sizeof *ohci->hcca,
 965                                 ohci->hcca, ohci->hcca_dma);
 966                 ohci->hcca = NULL;
 967                 ohci->hcca_dma = 0;
 968         }
 969 }
 970
 971 /*-------------------------------------------------------------------------*/
 972
 973 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 974
 975 /* must not be called from interrupt context */
 976 int ohci_restart(struct ohci_hcd *ohci)
 977 {
 978         int temp;
 979         int i;
 980         struct urb_priv *priv;
 981
 982         ohci_init(ohci);
 983         spin_lock_irq(&ohci->lock);
 984         ohci->rh_state = OHCI_RH_HALTED;
 985
 986         /* Recycle any "live" eds/tds (and urbs). */
 987         if (!list_empty (&ohci->pending))
 988                 ohci_dbg(ohci, "abort schedule...\n");
 989         list_for_each_entry (priv, &ohci->pending, pending) {
 990                 struct urb      *urb = priv->td[0]->urb;
 991                 struct ed       *ed = priv->ed;
 992
 993                 switch (ed->state) {
 994                 case ED_OPER:
 995                         ed->state = ED_UNLINK;
 996                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
 997                         ed_deschedule (ohci, ed);
 998
 999                         ed->ed_next = ohci->ed_rm_list;
1000                         ed->ed_prev = NULL;
1001                         ohci->ed_rm_list = ed;
1002                         /* FALLTHROUGH */
1003                 case ED_UNLINK:
1004                         break;
1005                 default:
1006                         ohci_dbg(ohci, "bogus ed %p state %d\n",
1007                                         ed, ed->state);
1008                 }
1009
1010                 if (!urb->unlinked)
1011                         urb->unlinked = -ESHUTDOWN;
1012         }
1013         finish_unlinks (ohci, 0);
1014         spin_unlock_irq(&ohci->lock);
1015
1016         /* paranoia, in case that didn't work: */
1017
1018         /* empty the interrupt branches */
1019         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1020         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1021
1022         /* no EDs to remove */
1023         ohci->ed_rm_list = NULL;
1024
1025         /* empty control and bulk lists */
1026         ohci->ed_controltail = NULL;
1027         ohci->ed_bulktail    = NULL;
1028
1029         if ((temp = ohci_run (ohci)) < 0) {
1030                 ohci_err (ohci, "can't restart, %d\n", temp);
1031                 return temp;
1032         }
1033         ohci_dbg(ohci, "restart complete\n");
1034         return 0;
1035 }
1036 EXPORT_SYMBOL_GPL(ohci_restart);
1037
1038 #endif
1039
1040 #ifdef CONFIG_PM
1041
1042 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1043 {
1044         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1045         unsigned long   flags;
1046
1047         /* Disable irq emission and mark HW unaccessible. Use
1048          * the spinlock to properly synchronize with possible pending
1049          * RH suspend or resume activity.
1050          */
1051         spin_lock_irqsave (&ohci->lock, flags);
1052         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1053         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1054
1055         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1056         spin_unlock_irqrestore (&ohci->lock, flags);
1057
1058         return 0;
1059 }
1060 EXPORT_SYMBOL_GPL(ohci_suspend);
1061
1062
1063 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1064 {
1065         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
1066         int                     port;
1067         bool                    need_reinit = false;
1068
1069         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1070
1071         /* Make sure resume from hibernation re-enumerates everything */
1072         if (hibernated)
1073                 ohci_usb_reset(ohci);
1074
1075         /* See if the controller is already running or has been reset */
1076         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1077         if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1078                 need_reinit = true;
1079         } else {
1080                 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1081                 case OHCI_USB_OPER:
1082                 case OHCI_USB_RESET:
1083                         need_reinit = true;
1084                 }
1085         }
1086
1087         /* If needed, reinitialize and suspend the root hub */
1088         if (need_reinit) {
1089                 spin_lock_irq(&ohci->lock);
1090                 ohci_rh_resume(ohci);
1091                 ohci_rh_suspend(ohci, 0);
1092                 spin_unlock_irq(&ohci->lock);
1093         }
1094
1095         /* Normally just turn on port power and enable interrupts */
1096         else {
1097                 ohci_dbg(ohci, "powerup ports\n");
1098                 for (port = 0; port < ohci->num_ports; port++)
1099                         ohci_writel(ohci, RH_PS_PPS,
1100                                         &ohci->regs->roothub.portstatus[port]);
1101
1102                 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1103                 ohci_readl(ohci, &ohci->regs->intrenable);
1104                 msleep(20);
1105         }
1106
1107         usb_hcd_resume_root_hub(hcd);
1108
1109         return 0;
1110 }
1111 EXPORT_SYMBOL_GPL(ohci_resume);
1112
1113 #endif
1114
1115 /*-------------------------------------------------------------------------*/
1116
1117 /*
1118  * Generic structure: This gets copied for platform drivers so that
1119  * individual entries can be overridden as needed.
1120  */
1121
1122 static const struct hc_driver ohci_hc_driver = {
1123         .description =          hcd_name,
1124         .product_desc =         "OHCI Host Controller",
1125         .hcd_priv_size =        sizeof(struct ohci_hcd),
1126
1127         /*
1128          * generic hardware linkage
1129         */
1130         .irq =                  ohci_irq,
1131         .flags =                HCD_MEMORY | HCD_USB11,
1132
1133         /*
1134         * basic lifecycle operations
1135         */
1136         .reset =                ohci_setup,
1137         .start =                ohci_start,
1138         .stop =                 ohci_stop,
1139         .shutdown =             ohci_shutdown,
1140
1141         /*
1142          * managing i/o requests and associated device resources
1143         */
1144         .urb_enqueue =          ohci_urb_enqueue,
1145         .urb_dequeue =          ohci_urb_dequeue,
1146         .endpoint_disable =     ohci_endpoint_disable,
1147
1148         /*
1149         * scheduling support
1150         */
1151         .get_frame_number =     ohci_get_frame,
1152
1153         /*
1154         * root hub support
1155         */
1156         .hub_status_data =      ohci_hub_status_data,
1157         .hub_control =          ohci_hub_control,
1158 #ifdef CONFIG_PM
1159         .bus_suspend =          ohci_bus_suspend,
1160         .bus_resume =           ohci_bus_resume,
1161 #endif
1162         .start_port_reset =     ohci_start_port_reset,
1163 };
1164
1165 void ohci_init_driver(struct hc_driver *drv,
1166                 const struct ohci_driver_overrides *over)
1167 {
1168         /* Copy the generic table to drv and then apply the overrides */
1169         *drv = ohci_hc_driver;
1170
1171         drv->product_desc = over->product_desc;
1172         drv->hcd_priv_size += over->extra_priv_size;
1173         if (over->reset)
1174                 drv->reset = over->reset;
1175 }
1176 EXPORT_SYMBOL_GPL(ohci_init_driver);
1177
1178 /*-------------------------------------------------------------------------*/
1179
1180 MODULE_AUTHOR (DRIVER_AUTHOR);
1181 MODULE_DESCRIPTION(DRIVER_DESC);
1182 MODULE_LICENSE ("GPL");
1183
1184 #ifdef CONFIG_PCI
1185 #include "ohci-pci.c"
1186 #define PCI_DRIVER              ohci_pci_driver
1187 #endif
1188
1189 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1190 #include "ohci-sa1111.c"
1191 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1192 #endif
1193
1194 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1195 #include "ohci-s3c2410.c"
1196 #define S3C2410_PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1197 #endif
1198
1199 #ifdef CONFIG_USB_OHCI_EXYNOS
1200 #include "ohci-exynos.c"
1201 #define EXYNOS_PLATFORM_DRIVER  exynos_ohci_driver
1202 #endif
1203
1204 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1205 #include "ohci-omap.c"
1206 #define OMAP1_PLATFORM_DRIVER   ohci_hcd_omap_driver
1207 #endif
1208
1209 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1210 #include "ohci-omap3.c"
1211 #define OMAP3_PLATFORM_DRIVER   ohci_hcd_omap3_driver
1212 #endif
1213
1214 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1215 #include "ohci-pxa27x.c"
1216 #define PLATFORM_DRIVER         ohci_hcd_pxa27x_driver
1217 #endif
1218
1219 #ifdef CONFIG_ARCH_EP93XX
1220 #include "ohci-ep93xx.c"
1221 #define EP93XX_PLATFORM_DRIVER  ohci_hcd_ep93xx_driver
1222 #endif
1223
1224 #ifdef CONFIG_ARCH_AT91
1225 #include "ohci-at91.c"
1226 #define AT91_PLATFORM_DRIVER    ohci_hcd_at91_driver
1227 #endif
1228
1229 #ifdef CONFIG_ARCH_LPC32XX
1230 #include "ohci-nxp.c"
1231 #define NXP_PLATFORM_DRIVER     usb_hcd_nxp_driver
1232 #endif
1233
1234 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1235 #include "ohci-da8xx.c"
1236 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1237 #endif
1238
1239 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1240 #include "ohci-ppc-of.c"
1241 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1242 #endif
1243
1244 #ifdef CONFIG_PLAT_SPEAR
1245 #include "ohci-spear.c"
1246 #define SPEAR_PLATFORM_DRIVER   spear_ohci_hcd_driver
1247 #endif
1248
1249 #ifdef CONFIG_PPC_PS3
1250 #include "ohci-ps3.c"
1251 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1252 #endif
1253
1254 #ifdef CONFIG_MFD_SM501
1255 #include "ohci-sm501.c"
1256 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1257 #endif
1258
1259 #ifdef CONFIG_MFD_TC6393XB
1260 #include "ohci-tmio.c"
1261 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1262 #endif
1263
1264 #ifdef CONFIG_MACH_JZ4740
1265 #include "ohci-jz4740.c"
1266 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1267 #endif
1268
1269 #ifdef CONFIG_USB_OCTEON_OHCI
1270 #include "ohci-octeon.c"
1271 #define PLATFORM_DRIVER         ohci_octeon_driver
1272 #endif
1273
1274 #ifdef CONFIG_TILE_USB
1275 #include "ohci-tilegx.c"
1276 #define PLATFORM_DRIVER         ohci_hcd_tilegx_driver
1277 #endif
1278
1279 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
1280 #include "ohci-platform.c"
1281 #define PLATFORM_DRIVER         ohci_platform_driver
1282 #endif
1283
1284 #if     !defined(PCI_DRIVER) &&         \
1285         !defined(PLATFORM_DRIVER) &&    \
1286         !defined(OMAP1_PLATFORM_DRIVER) &&      \
1287         !defined(OMAP3_PLATFORM_DRIVER) &&      \
1288         !defined(OF_PLATFORM_DRIVER) && \
1289         !defined(SA1111_DRIVER) &&      \
1290         !defined(PS3_SYSTEM_BUS_DRIVER) && \
1291         !defined(SM501_OHCI_DRIVER) && \
1292         !defined(TMIO_OHCI_DRIVER) && \
1293         !defined(S3C2410_PLATFORM_DRIVER) && \
1294         !defined(EXYNOS_PLATFORM_DRIVER) && \
1295         !defined(EP93XX_PLATFORM_DRIVER) && \
1296         !defined(AT91_PLATFORM_DRIVER) && \
1297         !defined(NXP_PLATFORM_DRIVER) && \
1298         !defined(DAVINCI_PLATFORM_DRIVER) && \
1299         !defined(SPEAR_PLATFORM_DRIVER)
1300 #error "missing bus glue for ohci-hcd"
1301 #endif
1302
1303 static int __init ohci_hcd_mod_init(void)
1304 {
1305         int retval = 0;
1306
1307         if (usb_disabled())
1308                 return -ENODEV;
1309
1310         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1311         pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1312                 sizeof (struct ed), sizeof (struct td));
1313         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1314
1315 #ifdef DEBUG
1316         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1317         if (!ohci_debug_root) {
1318                 retval = -ENOENT;
1319                 goto error_debug;
1320         }
1321 #endif
1322
1323 #ifdef PS3_SYSTEM_BUS_DRIVER
1324         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1325         if (retval < 0)
1326                 goto error_ps3;
1327 #endif
1328
1329 #ifdef PLATFORM_DRIVER
1330         retval = platform_driver_register(&PLATFORM_DRIVER);
1331         if (retval < 0)
1332                 goto error_platform;
1333 #endif
1334
1335 #ifdef OMAP1_PLATFORM_DRIVER
1336         retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1337         if (retval < 0)
1338                 goto error_omap1_platform;
1339 #endif
1340
1341 #ifdef OMAP3_PLATFORM_DRIVER
1342         retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1343         if (retval < 0)
1344                 goto error_omap3_platform;
1345 #endif
1346
1347 #ifdef OF_PLATFORM_DRIVER
1348         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1349         if (retval < 0)
1350                 goto error_of_platform;
1351 #endif
1352
1353 #ifdef SA1111_DRIVER
1354         retval = sa1111_driver_register(&SA1111_DRIVER);
1355         if (retval < 0)
1356                 goto error_sa1111;
1357 #endif
1358
1359 #ifdef PCI_DRIVER
1360         retval = pci_register_driver(&PCI_DRIVER);
1361         if (retval < 0)
1362                 goto error_pci;
1363 #endif
1364
1365 #ifdef SM501_OHCI_DRIVER
1366         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1367         if (retval < 0)
1368                 goto error_sm501;
1369 #endif
1370
1371 #ifdef TMIO_OHCI_DRIVER
1372         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1373         if (retval < 0)
1374                 goto error_tmio;
1375 #endif
1376
1377 #ifdef S3C2410_PLATFORM_DRIVER
1378         retval = platform_driver_register(&S3C2410_PLATFORM_DRIVER);
1379         if (retval < 0)
1380                 goto error_s3c2410;
1381 #endif
1382
1383 #ifdef EXYNOS_PLATFORM_DRIVER
1384         retval = platform_driver_register(&EXYNOS_PLATFORM_DRIVER);
1385         if (retval < 0)
1386                 goto error_exynos;
1387 #endif
1388
1389 #ifdef EP93XX_PLATFORM_DRIVER
1390         retval = platform_driver_register(&EP93XX_PLATFORM_DRIVER);
1391         if (retval < 0)
1392                 goto error_ep93xx;
1393 #endif
1394
1395 #ifdef AT91_PLATFORM_DRIVER
1396         retval = platform_driver_register(&AT91_PLATFORM_DRIVER);
1397         if (retval < 0)
1398                 goto error_at91;
1399 #endif
1400
1401 #ifdef NXP_PLATFORM_DRIVER
1402         retval = platform_driver_register(&NXP_PLATFORM_DRIVER);
1403         if (retval < 0)
1404                 goto error_nxp;
1405 #endif
1406
1407 #ifdef DAVINCI_PLATFORM_DRIVER
1408         retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1409         if (retval < 0)
1410                 goto error_davinci;
1411 #endif
1412
1413 #ifdef SPEAR_PLATFORM_DRIVER
1414         retval = platform_driver_register(&SPEAR_PLATFORM_DRIVER);
1415         if (retval < 0)
1416                 goto error_spear;
1417 #endif
1418
1419         return retval;
1420
1421         /* Error path */
1422 #ifdef SPEAR_PLATFORM_DRIVER
1423         platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1424  error_spear:
1425 #endif
1426 #ifdef DAVINCI_PLATFORM_DRIVER
1427         platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1428  error_davinci:
1429 #endif
1430 #ifdef NXP_PLATFORM_DRIVER
1431         platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1432  error_nxp:
1433 #endif
1434 #ifdef AT91_PLATFORM_DRIVER
1435         platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1436  error_at91:
1437 #endif
1438 #ifdef EP93XX_PLATFORM_DRIVER
1439         platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1440  error_ep93xx:
1441 #endif
1442 #ifdef EXYNOS_PLATFORM_DRIVER
1443         platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1444  error_exynos:
1445 #endif
1446 #ifdef S3C2410_PLATFORM_DRIVER
1447         platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1448  error_s3c2410:
1449 #endif
1450 #ifdef TMIO_OHCI_DRIVER
1451         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1452  error_tmio:
1453 #endif
1454 #ifdef SM501_OHCI_DRIVER
1455         platform_driver_unregister(&SM501_OHCI_DRIVER);
1456  error_sm501:
1457 #endif
1458 #ifdef PCI_DRIVER
1459         pci_unregister_driver(&PCI_DRIVER);
1460  error_pci:
1461 #endif
1462 #ifdef SA1111_DRIVER
1463         sa1111_driver_unregister(&SA1111_DRIVER);
1464  error_sa1111:
1465 #endif
1466 #ifdef OF_PLATFORM_DRIVER
1467         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1468  error_of_platform:
1469 #endif
1470 #ifdef OMAP3_PLATFORM_DRIVER
1471         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1472  error_omap3_platform:
1473 #endif
1474 #ifdef OMAP1_PLATFORM_DRIVER
1475         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1476  error_omap1_platform:
1477 #endif
1478 #ifdef PLATFORM_DRIVER
1479         platform_driver_unregister(&PLATFORM_DRIVER);
1480  error_platform:
1481 #endif
1482 #ifdef PS3_SYSTEM_BUS_DRIVER
1483         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1484  error_ps3:
1485 #endif
1486 #ifdef DEBUG
1487         debugfs_remove(ohci_debug_root);
1488         ohci_debug_root = NULL;
1489  error_debug:
1490 #endif
1491
1492         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1493         return retval;
1494 }
1495 module_init(ohci_hcd_mod_init);
1496
1497 static void __exit ohci_hcd_mod_exit(void)
1498 {
1499 #ifdef SPEAR_PLATFORM_DRIVER
1500         platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1501 #endif
1502 #ifdef DAVINCI_PLATFORM_DRIVER
1503         platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1504 #endif
1505 #ifdef NXP_PLATFORM_DRIVER
1506         platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1507 #endif
1508 #ifdef AT91_PLATFORM_DRIVER
1509         platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1510 #endif
1511 #ifdef EP93XX_PLATFORM_DRIVER
1512         platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1513 #endif
1514 #ifdef EXYNOS_PLATFORM_DRIVER
1515         platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1516 #endif
1517 #ifdef S3C2410_PLATFORM_DRIVER
1518         platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1519 #endif
1520 #ifdef TMIO_OHCI_DRIVER
1521         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1522 #endif
1523 #ifdef SM501_OHCI_DRIVER
1524         platform_driver_unregister(&SM501_OHCI_DRIVER);
1525 #endif
1526 #ifdef PCI_DRIVER
1527         pci_unregister_driver(&PCI_DRIVER);
1528 #endif
1529 #ifdef SA1111_DRIVER
1530         sa1111_driver_unregister(&SA1111_DRIVER);
1531 #endif
1532 #ifdef OF_PLATFORM_DRIVER
1533         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1534 #endif
1535 #ifdef OMAP3_PLATFORM_DRIVER
1536         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1537 #endif
1538 #ifdef OMAP1_PLATFORM_DRIVER
1539         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1540 #endif
1541 #ifdef PLATFORM_DRIVER
1542         platform_driver_unregister(&PLATFORM_DRIVER);
1543 #endif
1544 #ifdef PS3_SYSTEM_BUS_DRIVER
1545         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1546 #endif
1547 #ifdef DEBUG
1548         debugfs_remove(ohci_debug_root);
1549 #endif
1550         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1551 }
1552 module_exit(ohci_hcd_mod_exit);
1553