2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 /* For initializing controller (mask in an HCFS mode too) */
55 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
56 #define OHCI_INTR_INIT \
57 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
58 | OHCI_INTR_RD | OHCI_INTR_WDH)
61 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
65 #ifdef CONFIG_ARCH_OMAP
66 /* OMAP doesn't support IR (no SMM; not needed) */
70 /*-------------------------------------------------------------------------*/
72 static const char hcd_name [] = "ohci_hcd";
74 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77 #include "pci-quirks.h"
79 static void ohci_dump(struct ohci_hcd *ohci);
80 static void ohci_stop(struct usb_hcd *hcd);
89 * On architectures with edge-triggered interrupts we must never return
92 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
93 #define IRQ_NOTMINE IRQ_HANDLED
95 #define IRQ_NOTMINE IRQ_NONE
99 /* Some boards misreport power switching/overcurrent */
100 static bool distrust_firmware = 1;
101 module_param (distrust_firmware, bool, 0);
102 MODULE_PARM_DESC (distrust_firmware,
103 "true to distrust firmware power/overcurrent setup");
105 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
106 static bool no_handshake = 0;
107 module_param (no_handshake, bool, 0);
108 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
110 /*-------------------------------------------------------------------------*/
112 static int number_of_tds(struct urb *urb)
114 int len, i, num, this_sg_len;
115 struct scatterlist *sg;
117 len = urb->transfer_buffer_length;
118 i = urb->num_mapped_sgs;
120 if (len > 0 && i > 0) { /* Scatter-gather transfer */
124 this_sg_len = min_t(int, sg_dma_len(sg), len);
125 num += DIV_ROUND_UP(this_sg_len, 4096);
127 if (--i <= 0 || len <= 0)
132 } else { /* Non-SG transfer */
133 /* one TD for every 4096 Bytes (could be up to 8K) */
134 num = DIV_ROUND_UP(len, 4096);
140 * queue up an urb for anything except the root hub
142 static int ohci_urb_enqueue (
147 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
149 urb_priv_t *urb_priv;
150 unsigned int pipe = urb->pipe;
155 /* every endpoint has a ed, locate and maybe (re)initialize it */
156 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
159 /* for the private part of the URB we need the number of TDs (size) */
162 /* td_submit_urb() doesn't yet handle these */
163 if (urb->transfer_buffer_length > 4096)
166 /* 1 TD for setup, 1 for ACK, plus ... */
169 // case PIPE_INTERRUPT:
172 size += number_of_tds(urb);
173 /* maybe a zero-length packet to wrap it up */
176 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
177 && (urb->transfer_buffer_length
178 % usb_maxpacket (urb->dev, pipe,
179 usb_pipeout (pipe))) == 0)
182 case PIPE_ISOCHRONOUS: /* number of packets from URB */
183 size = urb->number_of_packets;
187 /* allocate the private part of the URB */
188 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
192 INIT_LIST_HEAD (&urb_priv->pending);
193 urb_priv->length = size;
196 /* allocate the TDs (deferring hash chain updates) */
197 for (i = 0; i < size; i++) {
198 urb_priv->td [i] = td_alloc (ohci, mem_flags);
199 if (!urb_priv->td [i]) {
200 urb_priv->length = i;
201 urb_free_priv (ohci, urb_priv);
206 spin_lock_irqsave (&ohci->lock, flags);
208 /* don't submit to a dead HC */
209 if (!HCD_HW_ACCESSIBLE(hcd)) {
213 if (ohci->rh_state != OHCI_RH_RUNNING) {
217 retval = usb_hcd_link_urb_to_ep(hcd, urb);
221 /* schedule the ed if needed */
222 if (ed->state == ED_IDLE) {
223 retval = ed_schedule (ohci, ed);
225 usb_hcd_unlink_urb_from_ep(hcd, urb);
228 if (ed->type == PIPE_ISOCHRONOUS) {
229 u16 frame = ohci_frame_no(ohci);
231 /* delay a few frames before the first TD */
232 frame += max_t (u16, 8, ed->interval);
233 frame &= ~(ed->interval - 1);
235 urb->start_frame = frame;
236 ed->last_iso = frame + ed->interval * (size - 1);
238 } else if (ed->type == PIPE_ISOCHRONOUS) {
239 u16 next = ohci_frame_no(ohci) + 1;
240 u16 frame = ed->last_iso + ed->interval;
241 u16 length = ed->interval * (size - 1);
243 /* Behind the scheduling threshold? */
244 if (unlikely(tick_before(frame, next))) {
246 /* URB_ISO_ASAP: Round up to the first available slot */
247 if (urb->transfer_flags & URB_ISO_ASAP) {
248 frame += (next - frame + ed->interval - 1) &
252 * Not ASAP: Use the next slot in the stream,
257 * Some OHCI hardware doesn't handle late TDs
258 * correctly. After retiring them it proceeds
259 * to the next ED instead of the next TD.
260 * Therefore we have to omit the late TDs
263 urb_priv->td_cnt = DIV_ROUND_UP(
264 (u16) (next - frame),
266 if (urb_priv->td_cnt >= urb_priv->length) {
267 ++urb_priv->td_cnt; /* Mark it */
268 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
274 urb->start_frame = frame;
275 ed->last_iso = frame + length;
278 /* fill the TDs and link them to the ed; and
279 * enable that part of the schedule, if needed
280 * and update count of queued periodic urbs
282 urb->hcpriv = urb_priv;
283 td_submit_urb (ohci, urb);
287 urb_free_priv (ohci, urb_priv);
288 spin_unlock_irqrestore (&ohci->lock, flags);
293 * decouple the URB from the HC queues (TDs, urb_priv).
294 * reporting is always done
295 * asynchronously, and we might be dealing with an urb that's
296 * partially transferred, or an ED with other urbs being unlinked.
298 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
300 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
303 urb_priv_t *urb_priv;
305 spin_lock_irqsave (&ohci->lock, flags);
306 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
309 /* Unless an IRQ completed the unlink while it was being
310 * handed to us, flag it for unlink and giveback, and force
311 * some upcoming INTR_SF to call finish_unlinks()
313 urb_priv = urb->hcpriv;
314 if (urb_priv->ed->state == ED_OPER)
315 start_ed_unlink(ohci, urb_priv->ed);
317 if (ohci->rh_state != OHCI_RH_RUNNING) {
318 /* With HC dead, we can clean up right away */
319 finish_unlinks(ohci, 0);
322 spin_unlock_irqrestore (&ohci->lock, flags);
326 /*-------------------------------------------------------------------------*/
328 /* frees config/altsetting state for endpoints,
329 * including ED memory, dummy TD, and bulk/intr data toggle
333 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
335 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
337 struct ed *ed = ep->hcpriv;
338 unsigned limit = 1000;
340 /* ASSERT: any requests/urbs are being unlinked */
341 /* ASSERT: nobody can be submitting urbs for this any more */
347 spin_lock_irqsave (&ohci->lock, flags);
349 if (ohci->rh_state != OHCI_RH_RUNNING) {
352 finish_unlinks (ohci, 0);
356 case ED_UNLINK: /* wait for hw to finish? */
357 /* major IRQ delivery trouble loses INTR_SF too... */
359 ohci_warn(ohci, "ED unlink timeout\n");
362 spin_unlock_irqrestore (&ohci->lock, flags);
363 schedule_timeout_uninterruptible(1);
365 case ED_IDLE: /* fully unlinked */
366 if (list_empty (&ed->td_list)) {
367 td_free (ohci, ed->dummy);
371 /* else FALL THROUGH */
373 /* caller was supposed to have unlinked any requests;
374 * that's not our job. can't recover; must leak ed.
376 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
377 ed, ep->desc.bEndpointAddress, ed->state,
378 list_empty (&ed->td_list) ? "" : " (has tds)");
379 td_free (ohci, ed->dummy);
383 spin_unlock_irqrestore (&ohci->lock, flags);
386 static int ohci_get_frame (struct usb_hcd *hcd)
388 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
390 return ohci_frame_no(ohci);
393 static void ohci_usb_reset (struct ohci_hcd *ohci)
395 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
396 ohci->hc_control &= OHCI_CTRL_RWC;
397 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
398 ohci->rh_state = OHCI_RH_HALTED;
401 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
402 * other cases where the next software may expect clean state from the
403 * "firmware". this is bus-neutral, unlike shutdown() methods.
406 ohci_shutdown (struct usb_hcd *hcd)
408 struct ohci_hcd *ohci;
410 ohci = hcd_to_ohci (hcd);
411 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
413 /* Software reset, after which the controller goes into SUSPEND */
414 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
415 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
418 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
421 /*-------------------------------------------------------------------------*
423 *-------------------------------------------------------------------------*/
425 /* init memory, and kick BIOS/SMM off */
427 static int ohci_init (struct ohci_hcd *ohci)
430 struct usb_hcd *hcd = ohci_to_hcd(ohci);
432 /* Accept arbitrarily long scatter-gather lists */
433 hcd->self.sg_tablesize = ~0;
435 if (distrust_firmware)
436 ohci->flags |= OHCI_QUIRK_HUB_POWER;
438 ohci->rh_state = OHCI_RH_HALTED;
439 ohci->regs = hcd->regs;
441 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
442 * was never needed for most non-PCI systems ... remove the code?
446 /* SMM owns the HC? not for long! */
447 if (!no_handshake && ohci_readl (ohci,
448 &ohci->regs->control) & OHCI_CTRL_IR) {
451 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
453 /* this timeout is arbitrary. we make it long, so systems
454 * depending on usb keyboards may be usable even if the
455 * BIOS/SMM code seems pretty broken.
457 temp = 500; /* arbitrary: five seconds */
459 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
460 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
461 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
464 ohci_err (ohci, "USB HC takeover failed!"
465 " (BIOS/SMM bug)\n");
469 ohci_usb_reset (ohci);
473 /* Disable HC interrupts */
474 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
476 /* flush the writes, and save key bits like RWC */
477 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
478 ohci->hc_control |= OHCI_CTRL_RWC;
480 /* Read the number of ports unless overridden */
481 if (ohci->num_ports == 0)
482 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
487 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
488 sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL);
492 if ((ret = ohci_mem_init (ohci)) < 0)
495 create_debug_files (ohci);
501 /*-------------------------------------------------------------------------*/
503 /* Start an OHCI controller, set the BUS operational
504 * resets USB and controller
507 static int ohci_run (struct ohci_hcd *ohci)
510 int first = ohci->fminterval == 0;
511 struct usb_hcd *hcd = ohci_to_hcd(ohci);
513 ohci->rh_state = OHCI_RH_HALTED;
515 /* boot firmware should have set this up (5.1.1.3.1) */
518 val = ohci_readl (ohci, &ohci->regs->fminterval);
519 ohci->fminterval = val & 0x3fff;
520 if (ohci->fminterval != FI)
521 ohci_dbg (ohci, "fminterval delta %d\n",
522 ohci->fminterval - FI);
523 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
524 /* also: power/overcurrent flags in roothub.a */
527 /* Reset USB nearly "by the book". RemoteWakeupConnected has
528 * to be checked in case boot firmware (BIOS/SMM/...) has set up
529 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
530 * If the bus glue detected wakeup capability then it should
531 * already be enabled; if so we'll just enable it again.
533 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
534 device_set_wakeup_capable(hcd->self.controller, 1);
536 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
540 case OHCI_USB_SUSPEND:
541 case OHCI_USB_RESUME:
542 ohci->hc_control &= OHCI_CTRL_RWC;
543 ohci->hc_control |= OHCI_USB_RESUME;
544 val = 10 /* msec wait */;
546 // case OHCI_USB_RESET:
548 ohci->hc_control &= OHCI_CTRL_RWC;
549 ohci->hc_control |= OHCI_USB_RESET;
550 val = 50 /* msec wait */;
553 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
555 (void) ohci_readl (ohci, &ohci->regs->control);
558 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
560 /* 2msec timelimit here means no irqs/preempt */
561 spin_lock_irq (&ohci->lock);
564 /* HC Reset requires max 10 us delay */
565 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
566 val = 30; /* ... allow extra time */
567 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
569 spin_unlock_irq (&ohci->lock);
570 ohci_err (ohci, "USB HC reset timed out!\n");
576 /* now we're in the SUSPEND state ... must go OPERATIONAL
577 * within 2msec else HC enters RESUME
579 * ... but some hardware won't init fmInterval "by the book"
580 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
581 * this if we write fmInterval after we're OPERATIONAL.
582 * Unclear about ALi, ServerWorks, and others ... this could
583 * easily be a longstanding bug in chip init on Linux.
585 if (ohci->flags & OHCI_QUIRK_INITRESET) {
586 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
587 // flush those writes
588 (void) ohci_readl (ohci, &ohci->regs->control);
591 /* Tell the controller where the control and bulk lists are
592 * The lists are empty now. */
593 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
594 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
596 /* a reset clears this */
597 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
599 periodic_reinit (ohci);
601 /* some OHCI implementations are finicky about how they init.
602 * bogus values here mean not even enumeration could work.
604 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
605 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
606 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
607 ohci->flags |= OHCI_QUIRK_INITRESET;
608 ohci_dbg (ohci, "enabling initreset quirk\n");
611 spin_unlock_irq (&ohci->lock);
612 ohci_err (ohci, "init err (%08x %04x)\n",
613 ohci_readl (ohci, &ohci->regs->fminterval),
614 ohci_readl (ohci, &ohci->regs->periodicstart));
618 /* use rhsc irqs after khubd is fully initialized */
619 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
620 hcd->uses_new_polling = 1;
622 /* start controller operations */
623 ohci->hc_control &= OHCI_CTRL_RWC;
624 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
625 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
626 ohci->rh_state = OHCI_RH_RUNNING;
628 /* wake on ConnectStatusChange, matching external hubs */
629 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
631 /* Choose the interrupts we care about now, others later on demand */
632 mask = OHCI_INTR_INIT;
633 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
634 ohci_writel (ohci, mask, &ohci->regs->intrenable);
636 /* handle root hub init quirks ... */
637 val = roothub_a (ohci);
638 val &= ~(RH_A_PSM | RH_A_OCPM);
639 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
640 /* NSC 87560 and maybe others */
642 val &= ~(RH_A_POTPGT | RH_A_NPS);
643 ohci_writel (ohci, val, &ohci->regs->roothub.a);
644 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
645 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
646 /* hub power always on; required for AMD-756 and some
647 * Mac platforms. ganged overcurrent reporting, if any.
650 ohci_writel (ohci, val, &ohci->regs->roothub.a);
652 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
653 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
654 &ohci->regs->roothub.b);
655 // flush those writes
656 (void) ohci_readl (ohci, &ohci->regs->control);
658 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
659 spin_unlock_irq (&ohci->lock);
661 // POTPGT delay is bits 24-31, in 2 ms units.
662 mdelay ((val >> 23) & 0x1fe);
669 /* ohci_setup routine for generic controller initialization */
671 int ohci_setup(struct usb_hcd *hcd)
673 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
677 return ohci_init(ohci);
679 EXPORT_SYMBOL_GPL(ohci_setup);
681 /* ohci_start routine for generic controller start of all OHCI bus glue */
682 static int ohci_start(struct usb_hcd *hcd)
684 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
687 ret = ohci_run(ohci);
689 ohci_err(ohci, "can't start\n");
695 /*-------------------------------------------------------------------------*/
697 /* an interrupt happens */
699 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
701 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
702 struct ohci_regs __iomem *regs = ohci->regs;
705 /* Read interrupt status (and flush pending writes). We ignore the
706 * optimization of checking the LSB of hcca->done_head; it doesn't
707 * work on all systems (edge triggering for OHCI can be a factor).
709 ints = ohci_readl(ohci, ®s->intrstatus);
711 /* Check for an all 1's result which is a typical consequence
712 * of dead, unclocked, or unplugged (CardBus...) devices
714 if (ints == ~(u32)0) {
715 ohci->rh_state = OHCI_RH_HALTED;
716 ohci_dbg (ohci, "device removed!\n");
721 /* We only care about interrupts that are enabled */
722 ints &= ohci_readl(ohci, ®s->intrenable);
724 /* interrupt for some other device? */
725 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
728 if (ints & OHCI_INTR_UE) {
729 // e.g. due to PCI Master/Target Abort
730 if (quirk_nec(ohci)) {
731 /* Workaround for a silicon bug in some NEC chips used
732 * in Apple's PowerBooks. Adapted from Darwin code.
734 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
736 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
738 schedule_work (&ohci->nec_work);
740 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
741 ohci->rh_state = OHCI_RH_HALTED;
746 ohci_usb_reset (ohci);
749 if (ints & OHCI_INTR_RHSC) {
750 ohci_dbg(ohci, "rhsc\n");
751 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
752 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
755 /* NOTE: Vendors didn't always make the same implementation
756 * choices for RHSC. Many followed the spec; RHSC triggers
757 * on an edge, like setting and maybe clearing a port status
758 * change bit. With others it's level-triggered, active
759 * until khubd clears all the port status change bits. We'll
760 * always disable it here and rely on polling until khubd
763 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
764 usb_hcd_poll_rh_status(hcd);
767 /* For connect and disconnect events, we expect the controller
768 * to turn on RHSC along with RD. But for remote wakeup events
769 * this might not happen.
771 else if (ints & OHCI_INTR_RD) {
772 ohci_dbg(ohci, "resume detect\n");
773 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
774 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
775 if (ohci->autostop) {
776 spin_lock (&ohci->lock);
777 ohci_rh_resume (ohci);
778 spin_unlock (&ohci->lock);
780 usb_hcd_resume_root_hub(hcd);
783 spin_lock(&ohci->lock);
784 if (ints & OHCI_INTR_WDH)
785 update_done_list(ohci);
787 /* could track INTR_SO to reduce available PCI/... bandwidth */
789 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
790 * when there's still unlinking to be done (next frame).
792 process_done_list(ohci);
793 if (ohci->ed_rm_list)
794 finish_unlinks (ohci, ohci_frame_no(ohci));
795 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
796 && ohci->rh_state == OHCI_RH_RUNNING)
797 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
799 if (ohci->rh_state == OHCI_RH_RUNNING) {
800 ohci_writel (ohci, ints, ®s->intrstatus);
801 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
802 // flush those writes
803 (void) ohci_readl (ohci, &ohci->regs->control);
805 spin_unlock(&ohci->lock);
810 /*-------------------------------------------------------------------------*/
812 static void ohci_stop (struct usb_hcd *hcd)
814 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
819 flush_work(&ohci->nec_work);
821 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
822 ohci_usb_reset(ohci);
823 free_irq(hcd->irq, hcd);
826 if (quirk_amdiso(ohci))
829 remove_debug_files (ohci);
830 ohci_mem_cleanup (ohci);
832 dma_free_coherent (hcd->self.controller,
834 ohci->hcca, ohci->hcca_dma);
840 /*-------------------------------------------------------------------------*/
842 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
844 /* must not be called from interrupt context */
845 int ohci_restart(struct ohci_hcd *ohci)
849 struct urb_priv *priv;
852 spin_lock_irq(&ohci->lock);
853 ohci->rh_state = OHCI_RH_HALTED;
855 /* Recycle any "live" eds/tds (and urbs). */
856 if (!list_empty (&ohci->pending))
857 ohci_dbg(ohci, "abort schedule...\n");
858 list_for_each_entry (priv, &ohci->pending, pending) {
859 struct urb *urb = priv->td[0]->urb;
860 struct ed *ed = priv->ed;
864 ed->state = ED_UNLINK;
865 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
866 ed_deschedule (ohci, ed);
868 ed->ed_next = ohci->ed_rm_list;
870 ohci->ed_rm_list = ed;
875 ohci_dbg(ohci, "bogus ed %p state %d\n",
880 urb->unlinked = -ESHUTDOWN;
882 finish_unlinks (ohci, 0);
883 spin_unlock_irq(&ohci->lock);
885 /* paranoia, in case that didn't work: */
887 /* empty the interrupt branches */
888 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
889 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
891 /* no EDs to remove */
892 ohci->ed_rm_list = NULL;
894 /* empty control and bulk lists */
895 ohci->ed_controltail = NULL;
896 ohci->ed_bulktail = NULL;
898 if ((temp = ohci_run (ohci)) < 0) {
899 ohci_err (ohci, "can't restart, %d\n", temp);
902 ohci_dbg(ohci, "restart complete\n");
905 EXPORT_SYMBOL_GPL(ohci_restart);
911 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
913 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
917 /* Disable irq emission and mark HW unaccessible. Use
918 * the spinlock to properly synchronize with possible pending
919 * RH suspend or resume activity.
921 spin_lock_irqsave (&ohci->lock, flags);
922 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
923 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
925 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
926 spin_unlock_irqrestore (&ohci->lock, flags);
928 synchronize_irq(hcd->irq);
930 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
931 ohci_resume(hcd, false);
936 EXPORT_SYMBOL_GPL(ohci_suspend);
939 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
941 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
943 bool need_reinit = false;
945 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
947 /* Make sure resume from hibernation re-enumerates everything */
949 ohci_usb_reset(ohci);
951 /* See if the controller is already running or has been reset */
952 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
953 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
956 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
963 /* If needed, reinitialize and suspend the root hub */
965 spin_lock_irq(&ohci->lock);
966 ohci_rh_resume(ohci);
967 ohci_rh_suspend(ohci, 0);
968 spin_unlock_irq(&ohci->lock);
971 /* Normally just turn on port power and enable interrupts */
973 ohci_dbg(ohci, "powerup ports\n");
974 for (port = 0; port < ohci->num_ports; port++)
975 ohci_writel(ohci, RH_PS_PPS,
976 &ohci->regs->roothub.portstatus[port]);
978 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
979 ohci_readl(ohci, &ohci->regs->intrenable);
983 usb_hcd_resume_root_hub(hcd);
987 EXPORT_SYMBOL_GPL(ohci_resume);
991 /*-------------------------------------------------------------------------*/
994 * Generic structure: This gets copied for platform drivers so that
995 * individual entries can be overridden as needed.
998 static const struct hc_driver ohci_hc_driver = {
999 .description = hcd_name,
1000 .product_desc = "OHCI Host Controller",
1001 .hcd_priv_size = sizeof(struct ohci_hcd),
1004 * generic hardware linkage
1007 .flags = HCD_MEMORY | HCD_USB11,
1010 * basic lifecycle operations
1012 .reset = ohci_setup,
1013 .start = ohci_start,
1015 .shutdown = ohci_shutdown,
1018 * managing i/o requests and associated device resources
1020 .urb_enqueue = ohci_urb_enqueue,
1021 .urb_dequeue = ohci_urb_dequeue,
1022 .endpoint_disable = ohci_endpoint_disable,
1025 * scheduling support
1027 .get_frame_number = ohci_get_frame,
1032 .hub_status_data = ohci_hub_status_data,
1033 .hub_control = ohci_hub_control,
1035 .bus_suspend = ohci_bus_suspend,
1036 .bus_resume = ohci_bus_resume,
1038 .start_port_reset = ohci_start_port_reset,
1041 void ohci_init_driver(struct hc_driver *drv,
1042 const struct ohci_driver_overrides *over)
1044 /* Copy the generic table to drv and then apply the overrides */
1045 *drv = ohci_hc_driver;
1048 drv->product_desc = over->product_desc;
1049 drv->hcd_priv_size += over->extra_priv_size;
1051 drv->reset = over->reset;
1054 EXPORT_SYMBOL_GPL(ohci_init_driver);
1056 /*-------------------------------------------------------------------------*/
1058 MODULE_AUTHOR (DRIVER_AUTHOR);
1059 MODULE_DESCRIPTION(DRIVER_DESC);
1060 MODULE_LICENSE ("GPL");
1062 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1063 #include "ohci-sa1111.c"
1064 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1067 #ifdef CONFIG_USB_OHCI_HCD_DAVINCI
1068 #include "ohci-da8xx.c"
1069 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1072 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1073 #include "ohci-ppc-of.c"
1074 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1077 #ifdef CONFIG_PPC_PS3
1078 #include "ohci-ps3.c"
1079 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1082 #ifdef CONFIG_MFD_SM501
1083 #include "ohci-sm501.c"
1084 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1087 #ifdef CONFIG_MFD_TC6393XB
1088 #include "ohci-tmio.c"
1089 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1092 #ifdef CONFIG_MACH_JZ4740
1093 #include "ohci-jz4740.c"
1094 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1097 #ifdef CONFIG_USB_OCTEON_OHCI
1098 #include "ohci-octeon.c"
1099 #define PLATFORM_DRIVER ohci_octeon_driver
1102 #ifdef CONFIG_TILE_USB
1103 #include "ohci-tilegx.c"
1104 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1107 static int __init ohci_hcd_mod_init(void)
1114 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1115 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1116 sizeof (struct ed), sizeof (struct td));
1117 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1119 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1120 if (!ohci_debug_root) {
1125 #ifdef PS3_SYSTEM_BUS_DRIVER
1126 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1131 #ifdef PLATFORM_DRIVER
1132 retval = platform_driver_register(&PLATFORM_DRIVER);
1134 goto error_platform;
1137 #ifdef OF_PLATFORM_DRIVER
1138 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1140 goto error_of_platform;
1143 #ifdef SA1111_DRIVER
1144 retval = sa1111_driver_register(&SA1111_DRIVER);
1149 #ifdef SM501_OHCI_DRIVER
1150 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1155 #ifdef TMIO_OHCI_DRIVER
1156 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1161 #ifdef DAVINCI_PLATFORM_DRIVER
1162 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1170 #ifdef DAVINCI_PLATFORM_DRIVER
1171 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1174 #ifdef TMIO_OHCI_DRIVER
1175 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1178 #ifdef SM501_OHCI_DRIVER
1179 platform_driver_unregister(&SM501_OHCI_DRIVER);
1182 #ifdef SA1111_DRIVER
1183 sa1111_driver_unregister(&SA1111_DRIVER);
1186 #ifdef OF_PLATFORM_DRIVER
1187 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1190 #ifdef PLATFORM_DRIVER
1191 platform_driver_unregister(&PLATFORM_DRIVER);
1194 #ifdef PS3_SYSTEM_BUS_DRIVER
1195 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1198 debugfs_remove(ohci_debug_root);
1199 ohci_debug_root = NULL;
1202 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1205 module_init(ohci_hcd_mod_init);
1207 static void __exit ohci_hcd_mod_exit(void)
1209 #ifdef DAVINCI_PLATFORM_DRIVER
1210 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1212 #ifdef TMIO_OHCI_DRIVER
1213 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1215 #ifdef SM501_OHCI_DRIVER
1216 platform_driver_unregister(&SM501_OHCI_DRIVER);
1218 #ifdef SA1111_DRIVER
1219 sa1111_driver_unregister(&SA1111_DRIVER);
1221 #ifdef OF_PLATFORM_DRIVER
1222 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1224 #ifdef PLATFORM_DRIVER
1225 platform_driver_unregister(&PLATFORM_DRIVER);
1227 #ifdef PS3_SYSTEM_BUS_DRIVER
1228 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1230 debugfs_remove(ohci_debug_root);
1231 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1233 module_exit(ohci_hcd_mod_exit);