drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/slab.h>
  12
  13 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  14 {
  15         int             last = urb_priv->length - 1;
  16
  17         if (last >= 0) {
  18                 int             i;
  19                 struct td       *td;
  20
  21                 for (i = 0; i <= last; i++) {
  22                         td = urb_priv->td [i];
  23                         if (td)
  24                                 td_free (hc, td);
  25                 }
  26         }
  27
  28         list_del (&urb_priv->pending);
  29         kfree (urb_priv);
  30 }
  31
  32 /*-------------------------------------------------------------------------*/
  33
  34 /*
  35  * URB goes back to driver, and isn't reissued.
  36  * It's completely gone from HC data structures.
  37  * PRECONDITION:  ohci lock held, irqs blocked.
  38  */
  39 static void
  40 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  41 __releases(ohci->lock)
  42 __acquires(ohci->lock)
  43 {
  44          struct device *dev = ohci_to_hcd(ohci)->self.controller;
  45         // ASSERT (urb->hcpriv != 0);
  46
  47         urb_free_priv (ohci, urb->hcpriv);
  48         urb->hcpriv = NULL;
  49         if (likely(status == -EINPROGRESS))
  50                 status = 0;
  51
  52         switch (usb_pipetype (urb->pipe)) {
  53         case PIPE_ISOCHRONOUS:
  54                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  55                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  56                         if (quirk_amdiso(ohci))
  57                                 usb_amd_quirk_pll_enable();
  58                         if (quirk_amdprefetch(ohci))
  59                                 sb800_prefetch(dev, 0);
  60                 }
  61                 break;
  62         case PIPE_INTERRUPT:
  63                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  64                 break;
  65         }
  66
  67 #ifdef OHCI_VERBOSE_DEBUG
  68         urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
  69 #endif
  70
  71         /* urb->complete() can reenter this HCD */
  72         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  73         spin_unlock (&ohci->lock);
  74         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  75         spin_lock (&ohci->lock);
  76
  77         /* stop periodic dma if it's not needed */
  78         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  79                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  80                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  81                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  82         }
  83 }
  84
  85
  86 /*-------------------------------------------------------------------------*
  87  * ED handling functions
  88  *-------------------------------------------------------------------------*/
  89
  90 /* search for the right schedule branch to use for a periodic ed.
  91  * does some load balancing; returns the branch, or negative errno.
  92  */
  93 static int balance (struct ohci_hcd *ohci, int interval, int load)
  94 {
  95         int     i, branch = -ENOSPC;
  96
  97         /* iso periods can be huge; iso tds specify frame numbers */
  98         if (interval > NUM_INTS)
  99                 interval = NUM_INTS;
 100
 101         /* search for the least loaded schedule branch of that period
 102          * that has enough bandwidth left unreserved.
 103          */
 104         for (i = 0; i < interval ; i++) {
 105                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 106                         int     j;
 107
 108                         /* usb 1.1 says 90% of one frame */
 109                         for (j = i; j < NUM_INTS; j += interval) {
 110                                 if ((ohci->load [j] + load) > 900)
 111                                         break;
 112                         }
 113                         if (j < NUM_INTS)
 114                                 continue;
 115                         branch = i;
 116                 }
 117         }
 118         return branch;
 119 }
 120
 121 /*-------------------------------------------------------------------------*/
 122
 123 /* both iso and interrupt requests have periods; this routine puts them
 124  * into the schedule tree in the apppropriate place.  most iso devices use
 125  * 1msec periods, but that's not required.
 126  */
 127 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 128 {
 129         unsigned        i;
 130
 131         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 132                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 133                 ed, ed->branch, ed->load, ed->interval);
 134
 135         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 136                 struct ed       **prev = &ohci->periodic [i];
 137                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 138                 struct ed       *here = *prev;
 139
 140                 /* sorting each branch by period (slow before fast)
 141                  * lets us share the faster parts of the tree.
 142                  * (plus maybe: put interrupt eds before iso)
 143                  */
 144                 while (here && ed != here) {
 145                         if (ed->interval > here->interval)
 146                                 break;
 147                         prev = &here->ed_next;
 148                         prev_p = &here->hwNextED;
 149                         here = *prev;
 150                 }
 151                 if (ed != here) {
 152                         ed->ed_next = here;
 153                         if (here)
 154                                 ed->hwNextED = *prev_p;
 155                         wmb ();
 156                         *prev = ed;
 157                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 158                         wmb();
 159                 }
 160                 ohci->load [i] += ed->load;
 161         }
 162         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 163 }
 164
 165 /* link an ed into one of the HC chains */
 166
 167 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 168 {
 169         int     branch;
 170
 171         ed->state = ED_OPER;
 172         ed->ed_prev = NULL;
 173         ed->ed_next = NULL;
 174         ed->hwNextED = 0;
 175         if (quirk_zfmicro(ohci)
 176                         && (ed->type == PIPE_INTERRUPT)
 177                         && !(ohci->eds_scheduled++))
 178                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 179         wmb ();
 180
 181         /* we care about rm_list when setting CLE/BLE in case the HC was at
 182          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 183          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 184          *
 185          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 186          * periodic ones are singly linked (ed_next). that's because the
 187          * periodic schedule encodes a tree like figure 3-5 in the ohci
 188          * spec:  each qh can have several "previous" nodes, and the tree
 189          * doesn't have unused/idle descriptors.
 190          */
 191         switch (ed->type) {
 192         case PIPE_CONTROL:
 193                 if (ohci->ed_controltail == NULL) {
 194                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 195                         ohci_writel (ohci, ed->dma,
 196                                         &ohci->regs->ed_controlhead);
 197                 } else {
 198                         ohci->ed_controltail->ed_next = ed;
 199                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 200                                                                 ed->dma);
 201                 }
 202                 ed->ed_prev = ohci->ed_controltail;
 203                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 204                         wmb();
 205                         ohci->hc_control |= OHCI_CTRL_CLE;
 206                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 207                         ohci_writel (ohci, ohci->hc_control,
 208                                         &ohci->regs->control);
 209                 }
 210                 ohci->ed_controltail = ed;
 211                 break;
 212
 213         case PIPE_BULK:
 214                 if (ohci->ed_bulktail == NULL) {
 215                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 216                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 217                 } else {
 218                         ohci->ed_bulktail->ed_next = ed;
 219                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 220                                                                 ed->dma);
 221                 }
 222                 ed->ed_prev = ohci->ed_bulktail;
 223                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 224                         wmb();
 225                         ohci->hc_control |= OHCI_CTRL_BLE;
 226                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 227                         ohci_writel (ohci, ohci->hc_control,
 228                                         &ohci->regs->control);
 229                 }
 230                 ohci->ed_bulktail = ed;
 231                 break;
 232
 233         // case PIPE_INTERRUPT:
 234         // case PIPE_ISOCHRONOUS:
 235         default:
 236                 branch = balance (ohci, ed->interval, ed->load);
 237                 if (branch < 0) {
 238                         ohci_dbg (ohci,
 239                                 "ERR %d, interval %d msecs, load %d\n",
 240                                 branch, ed->interval, ed->load);
 241                         // FIXME if there are TDs queued, fail them!
 242                         return branch;
 243                 }
 244                 ed->branch = branch;
 245                 periodic_link (ohci, ed);
 246         }
 247
 248         /* the HC may not see the schedule updates yet, but if it does
 249          * then they'll be properly ordered.
 250          */
 251         return 0;
 252 }
 253
 254 /*-------------------------------------------------------------------------*/
 255
 256 /* scan the periodic table to find and unlink this ED */
 257 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 258 {
 259         int     i;
 260
 261         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 262                 struct ed       *temp;
 263                 struct ed       **prev = &ohci->periodic [i];
 264                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 265
 266                 while (*prev && (temp = *prev) != ed) {
 267                         prev_p = &temp->hwNextED;
 268                         prev = &temp->ed_next;
 269                 }
 270                 if (*prev) {
 271                         *prev_p = ed->hwNextED;
 272                         *prev = ed->ed_next;
 273                 }
 274                 ohci->load [i] -= ed->load;
 275         }
 276         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 277
 278         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 279                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 280                 ed, ed->branch, ed->load, ed->interval);
 281 }
 282
 283 /* unlink an ed from one of the HC chains.
 284  * just the link to the ed is unlinked.
 285  * the link from the ed still points to another operational ed or 0
 286  * so the HC can eventually finish the processing of the unlinked ed
 287  * (assuming it already started that, which needn't be true).
 288  *
 289  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 290  * it won't.  ED_SKIP means the HC will finish its current transaction,
 291  * but won't start anything new.  The TD queue may still grow; device
 292  * drivers don't know about this HCD-internal state.
 293  *
 294  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 295  *
 296  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 297  *    immediately.  HC should be working on them.
 298  *
 299  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 300  *    to care about this ED; safe to disable the endpoint.
 301  *
 302  * When finish_unlinks() runs later, after SOF interrupt, it will often
 303  * complete one or more URB unlinks before making that state change.
 304  */
 305 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 306 {
 307         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 308         wmb ();
 309         ed->state = ED_UNLINK;
 310
 311         /* To deschedule something from the control or bulk list, just
 312          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 313          * head/current registers until later, and "later" isn't very
 314          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 315          * the HC is reading the ED queues (while we modify them).
 316          *
 317          * For now, ed_schedule() is "later".  It might be good paranoia
 318          * to scrub those registers in finish_unlinks(), in case of bugs
 319          * that make the HC try to use them.
 320          */
 321         switch (ed->type) {
 322         case PIPE_CONTROL:
 323                 /* remove ED from the HC's list: */
 324                 if (ed->ed_prev == NULL) {
 325                         if (!ed->hwNextED) {
 326                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 327                                 ohci_writel (ohci, ohci->hc_control,
 328                                                 &ohci->regs->control);
 329                                 // a ohci_readl() later syncs CLE with the HC
 330                         } else
 331                                 ohci_writel (ohci,
 332                                         hc32_to_cpup (ohci, &ed->hwNextED),
 333                                         &ohci->regs->ed_controlhead);
 334                 } else {
 335                         ed->ed_prev->ed_next = ed->ed_next;
 336                         ed->ed_prev->hwNextED = ed->hwNextED;
 337                 }
 338                 /* remove ED from the HCD's list: */
 339                 if (ohci->ed_controltail == ed) {
 340                         ohci->ed_controltail = ed->ed_prev;
 341                         if (ohci->ed_controltail)
 342                                 ohci->ed_controltail->ed_next = NULL;
 343                 } else if (ed->ed_next) {
 344                         ed->ed_next->ed_prev = ed->ed_prev;
 345                 }
 346                 break;
 347
 348         case PIPE_BULK:
 349                 /* remove ED from the HC's list: */
 350                 if (ed->ed_prev == NULL) {
 351                         if (!ed->hwNextED) {
 352                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 353                                 ohci_writel (ohci, ohci->hc_control,
 354                                                 &ohci->regs->control);
 355                                 // a ohci_readl() later syncs BLE with the HC
 356                         } else
 357                                 ohci_writel (ohci,
 358                                         hc32_to_cpup (ohci, &ed->hwNextED),
 359                                         &ohci->regs->ed_bulkhead);
 360                 } else {
 361                         ed->ed_prev->ed_next = ed->ed_next;
 362                         ed->ed_prev->hwNextED = ed->hwNextED;
 363                 }
 364                 /* remove ED from the HCD's list: */
 365                 if (ohci->ed_bulktail == ed) {
 366                         ohci->ed_bulktail = ed->ed_prev;
 367                         if (ohci->ed_bulktail)
 368                                 ohci->ed_bulktail->ed_next = NULL;
 369                 } else if (ed->ed_next) {
 370                         ed->ed_next->ed_prev = ed->ed_prev;
 371                 }
 372                 break;
 373
 374         // case PIPE_INTERRUPT:
 375         // case PIPE_ISOCHRONOUS:
 376         default:
 377                 periodic_unlink (ohci, ed);
 378                 break;
 379         }
 380 }
 381
 382
 383 /*-------------------------------------------------------------------------*/
 384
 385 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 386  * of enumeration, usb_set_configuration() or usb_set_interface().
 387  */
 388 static struct ed *ed_get (
 389         struct ohci_hcd         *ohci,
 390         struct usb_host_endpoint *ep,
 391         struct usb_device       *udev,
 392         unsigned int            pipe,
 393         int                     interval
 394 ) {
 395         struct ed               *ed;
 396         unsigned long           flags;
 397
 398         spin_lock_irqsave (&ohci->lock, flags);
 399
 400         if (!(ed = ep->hcpriv)) {
 401                 struct td       *td;
 402                 int             is_out;
 403                 u32             info;
 404
 405                 ed = ed_alloc (ohci, GFP_ATOMIC);
 406                 if (!ed) {
 407                         /* out of memory */
 408                         goto done;
 409                 }
 410
 411                 /* dummy td; end of td list for ed */
 412                 td = td_alloc (ohci, GFP_ATOMIC);
 413                 if (!td) {
 414                         /* out of memory */
 415                         ed_free (ohci, ed);
 416                         ed = NULL;
 417                         goto done;
 418                 }
 419                 ed->dummy = td;
 420                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 421                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 422                 ed->state = ED_IDLE;
 423
 424                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 425
 426                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 427                  * succeeds ... otherwise we wouldn't need "pipe".
 428                  */
 429                 info = usb_pipedevice (pipe);
 430                 ed->type = usb_pipetype(pipe);
 431
 432                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 433                 info |= usb_endpoint_maxp(&ep->desc) << 16;
 434                 if (udev->speed == USB_SPEED_LOW)
 435                         info |= ED_LOWSPEED;
 436                 /* only control transfers store pids in tds */
 437                 if (ed->type != PIPE_CONTROL) {
 438                         info |= is_out ? ED_OUT : ED_IN;
 439                         if (ed->type != PIPE_BULK) {
 440                                 /* periodic transfers... */
 441                                 if (ed->type == PIPE_ISOCHRONOUS)
 442                                         info |= ED_ISO;
 443                                 else if (interval > 32) /* iso can be bigger */
 444                                         interval = 32;
 445                                 ed->interval = interval;
 446                                 ed->load = usb_calc_bus_time (
 447                                         udev->speed, !is_out,
 448                                         ed->type == PIPE_ISOCHRONOUS,
 449                                         usb_endpoint_maxp(&ep->desc))
 450                                                 / 1000;
 451                         }
 452                 }
 453                 ed->hwINFO = cpu_to_hc32(ohci, info);
 454
 455                 ep->hcpriv = ed;
 456         }
 457
 458 done:
 459         spin_unlock_irqrestore (&ohci->lock, flags);
 460         return ed;
 461 }
 462
 463 /*-------------------------------------------------------------------------*/
 464
 465 /* request unlinking of an endpoint from an operational HC.
 466  * put the ep on the rm_list
 467  * real work is done at the next start frame (SF) hardware interrupt
 468  * caller guarantees HCD is running, so hardware access is safe,
 469  * and that ed->state is ED_OPER
 470  */
 471 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 472 {
 473         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 474         ed_deschedule (ohci, ed);
 475
 476         /* rm_list is just singly linked, for simplicity */
 477         ed->ed_next = ohci->ed_rm_list;
 478         ed->ed_prev = NULL;
 479         ohci->ed_rm_list = ed;
 480
 481         /* enable SOF interrupt */
 482         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 483         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 484         // flush those writes, and get latest HCCA contents
 485         (void) ohci_readl (ohci, &ohci->regs->control);
 486
 487         /* SF interrupt might get delayed; record the frame counter value that
 488          * indicates when the HC isn't looking at it, so concurrent unlinks
 489          * behave.  frame_no wraps every 2^16 msec, and changes right before
 490          * SF is triggered.
 491          */
 492         ed->tick = ohci_frame_no(ohci) + 1;
 493
 494 }
 495
 496 /*-------------------------------------------------------------------------*
 497  * TD handling functions
 498  *-------------------------------------------------------------------------*/
 499
 500 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 501
 502 static void
 503 td_fill (struct ohci_hcd *ohci, u32 info,
 504         dma_addr_t data, int len,
 505         struct urb *urb, int index)
 506 {
 507         struct td               *td, *td_pt;
 508         struct urb_priv         *urb_priv = urb->hcpriv;
 509         int                     is_iso = info & TD_ISO;
 510         int                     hash;
 511
 512         // ASSERT (index < urb_priv->length);
 513
 514         /* aim for only one interrupt per urb.  mostly applies to control
 515          * and iso; other urbs rarely need more than one TD per urb.
 516          * this way, only final tds (or ones with an error) cause IRQs.
 517          * at least immediately; use DI=6 in case any control request is
 518          * tempted to die part way through.  (and to force the hc to flush
 519          * its donelist soonish, even on unlink paths.)
 520          *
 521          * NOTE: could delay interrupts even for the last TD, and get fewer
 522          * interrupts ... increasing per-urb latency by sharing interrupts.
 523          * Drivers that queue bulk urbs may request that behavior.
 524          */
 525         if (index != (urb_priv->length - 1)
 526                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 527                 info |= TD_DI_SET (6);
 528
 529         /* use this td as the next dummy */
 530         td_pt = urb_priv->td [index];
 531
 532         /* fill the old dummy TD */
 533         td = urb_priv->td [index] = urb_priv->ed->dummy;
 534         urb_priv->ed->dummy = td_pt;
 535
 536         td->ed = urb_priv->ed;
 537         td->next_dl_td = NULL;
 538         td->index = index;
 539         td->urb = urb;
 540         td->data_dma = data;
 541         if (!len)
 542                 data = 0;
 543
 544         td->hwINFO = cpu_to_hc32 (ohci, info);
 545         if (is_iso) {
 546                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 547                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 548                                                 (data & 0x0FFF) | 0xE000);
 549                 td->ed->last_iso = info & 0xffff;
 550         } else {
 551                 td->hwCBP = cpu_to_hc32 (ohci, data);
 552         }
 553         if (data)
 554                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 555         else
 556                 td->hwBE = 0;
 557         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 558
 559         /* append to queue */
 560         list_add_tail (&td->td_list, &td->ed->td_list);
 561
 562         /* hash it for later reverse mapping */
 563         hash = TD_HASH_FUNC (td->td_dma);
 564         td->td_hash = ohci->td_hash [hash];
 565         ohci->td_hash [hash] = td;
 566
 567         /* HC might read the TD (or cachelines) right away ... */
 568         wmb ();
 569         td->ed->hwTailP = td->hwNextTD;
 570 }
 571
 572 /*-------------------------------------------------------------------------*/
 573
 574 /* Prepare all TDs of a transfer, and queue them onto the ED.
 575  * Caller guarantees HC is active.
 576  * Usually the ED is already on the schedule, so TDs might be
 577  * processed as soon as they're queued.
 578  */
 579 static void td_submit_urb (
 580         struct ohci_hcd *ohci,
 581         struct urb      *urb
 582 ) {
 583         struct urb_priv *urb_priv = urb->hcpriv;
 584         struct device *dev = ohci_to_hcd(ohci)->self.controller;
 585         dma_addr_t      data;
 586         int             data_len = urb->transfer_buffer_length;
 587         int             cnt = 0;
 588         u32             info = 0;
 589         int             is_out = usb_pipeout (urb->pipe);
 590         int             periodic = 0;
 591
 592         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 593          * use the device toggle bits for resetting, and rely on the fact
 594          * that resetting toggle is meaningless if the endpoint is active.
 595          */
 596         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 597                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 598                         is_out, 1);
 599                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 600         }
 601
 602         list_add (&urb_priv->pending, &ohci->pending);
 603
 604         if (data_len)
 605                 data = urb->transfer_dma;
 606         else
 607                 data = 0;
 608
 609         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 610          * using TD_CC_GET, as well as by seeing them on the done list.
 611          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 612          */
 613         switch (urb_priv->ed->type) {
 614
 615         /* Bulk and interrupt are identical except for where in the schedule
 616          * their EDs live.
 617          */
 618         case PIPE_INTERRUPT:
 619                 /* ... and periodic urbs have extra accounting */
 620                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 621                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 622                 /* FALLTHROUGH */
 623         case PIPE_BULK:
 624                 info = is_out
 625                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 626                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 627                 /* TDs _could_ transfer up to 8K each */
 628                 while (data_len > 4096) {
 629                         td_fill (ohci, info, data, 4096, urb, cnt);
 630                         data += 4096;
 631                         data_len -= 4096;
 632                         cnt++;
 633                 }
 634                 /* maybe avoid ED halt on final TD short read */
 635                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 636                         info |= TD_R;
 637                 td_fill (ohci, info, data, data_len, urb, cnt);
 638                 cnt++;
 639                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 640                                 && cnt < urb_priv->length) {
 641                         td_fill (ohci, info, 0, 0, urb, cnt);
 642                         cnt++;
 643                 }
 644                 /* maybe kickstart bulk list */
 645                 if (urb_priv->ed->type == PIPE_BULK) {
 646                         wmb ();
 647                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 648                 }
 649                 break;
 650
 651         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 652          * any DATA phase works normally, and the STATUS ack is special.
 653          */
 654         case PIPE_CONTROL:
 655                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 656                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 657                 if (data_len > 0) {
 658                         info = TD_CC | TD_R | TD_T_DATA1;
 659                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 660                         /* NOTE:  mishandles transfers >8K, some >4K */
 661                         td_fill (ohci, info, data, data_len, urb, cnt++);
 662                 }
 663                 info = (is_out || data_len == 0)
 664                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 665                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 666                 td_fill (ohci, info, data, 0, urb, cnt++);
 667                 /* maybe kickstart control list */
 668                 wmb ();
 669                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 670                 break;
 671
 672         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 673          * Each TD could handle multiple consecutive frames (interval 1);
 674          * we could often reduce the number of TDs here.
 675          */
 676         case PIPE_ISOCHRONOUS:
 677                 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
 678                                 cnt++) {
 679                         int     frame = urb->start_frame;
 680
 681                         // FIXME scheduling should handle frame counter
 682                         // roll-around ... exotic case (and OHCI has
 683                         // a 2^16 iso range, vs other HCs max of 2^10)
 684                         frame += cnt * urb->interval;
 685                         frame &= 0xffff;
 686                         td_fill (ohci, TD_CC | TD_ISO | frame,
 687                                 data + urb->iso_frame_desc [cnt].offset,
 688                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 689                 }
 690                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
 691                         if (quirk_amdiso(ohci))
 692                                 usb_amd_quirk_pll_disable();
 693                         if (quirk_amdprefetch(ohci))
 694                                 sb800_prefetch(dev, 1);
 695                 }
 696                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 697                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 698                 break;
 699         }
 700
 701         /* start periodic dma if needed */
 702         if (periodic) {
 703                 wmb ();
 704                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 705                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 706         }
 707
 708         // ASSERT (urb_priv->length == cnt);
 709 }
 710
 711 /*-------------------------------------------------------------------------*
 712  * Done List handling functions
 713  *-------------------------------------------------------------------------*/
 714
 715 /* calculate transfer length/status and update the urb */
 716 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 717 {
 718         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 719         int     cc = 0;
 720         int     status = -EINPROGRESS;
 721
 722         list_del (&td->td_list);
 723
 724         /* ISO ... drivers see per-TD length/status */
 725         if (tdINFO & TD_ISO) {
 726                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
 727                 int     dlen = 0;
 728
 729                 /* NOTE:  assumes FC in tdINFO == 0, and that
 730                  * only the first of 0..MAXPSW psws is used.
 731                  */
 732
 733                 cc = (tdPSW >> 12) & 0xF;
 734                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 735                         return status;
 736
 737                 if (usb_pipeout (urb->pipe))
 738                         dlen = urb->iso_frame_desc [td->index].length;
 739                 else {
 740                         /* short reads are always OK for ISO */
 741                         if (cc == TD_DATAUNDERRUN)
 742                                 cc = TD_CC_NOERROR;
 743                         dlen = tdPSW & 0x3ff;
 744                 }
 745                 urb->actual_length += dlen;
 746                 urb->iso_frame_desc [td->index].actual_length = dlen;
 747                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 748
 749                 if (cc != TD_CC_NOERROR)
 750                         ohci_vdbg (ohci,
 751                                 "urb %p iso td %p (%d) len %d cc %d\n",
 752                                 urb, td, 1 + td->index, dlen, cc);
 753
 754         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 755          * except that "setup" bytes aren't counted and "short" transfers
 756          * might not be reported as errors.
 757          */
 758         } else {
 759                 int     type = usb_pipetype (urb->pipe);
 760                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 761
 762                 cc = TD_CC_GET (tdINFO);
 763
 764                 /* update packet status if needed (short is normally ok) */
 765                 if (cc == TD_DATAUNDERRUN
 766                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 767                         cc = TD_CC_NOERROR;
 768                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 769                         status = cc_to_error[cc];
 770
 771                 /* count all non-empty packets except control SETUP packet */
 772                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 773                         if (td->hwCBP == 0)
 774                                 urb->actual_length += tdBE - td->data_dma + 1;
 775                         else
 776                                 urb->actual_length +=
 777                                           hc32_to_cpup (ohci, &td->hwCBP)
 778                                         - td->data_dma;
 779                 }
 780
 781                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 782                         ohci_vdbg (ohci,
 783                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 784                                 urb, td, 1 + td->index, cc,
 785                                 urb->actual_length,
 786                                 urb->transfer_buffer_length);
 787         }
 788         return status;
 789 }
 790
 791 /*-------------------------------------------------------------------------*/
 792
 793 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
 794 {
 795         struct urb              *urb = td->urb;
 796         urb_priv_t              *urb_priv = urb->hcpriv;
 797         struct ed               *ed = td->ed;
 798         struct list_head        *tmp = td->td_list.next;
 799         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 800
 801         /* clear ed halt; this is the td that caused it, but keep it inactive
 802          * until its urb->complete() has a chance to clean up.
 803          */
 804         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 805         wmb ();
 806         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 807
 808         /* Get rid of all later tds from this urb.  We don't have
 809          * to be careful: no errors and nothing was transferred.
 810          * Also patch the ed so it looks as if those tds completed normally.
 811          */
 812         while (tmp != &ed->td_list) {
 813                 struct td       *next;
 814
 815                 next = list_entry (tmp, struct td, td_list);
 816                 tmp = next->td_list.next;
 817
 818                 if (next->urb != urb)
 819                         break;
 820
 821                 /* NOTE: if multi-td control DATA segments get supported,
 822                  * this urb had one of them, this td wasn't the last td
 823                  * in that segment (TD_R clear), this ed halted because
 824                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 825                  * then we need to leave the control STATUS packet queued
 826                  * and clear ED_SKIP.
 827                  */
 828
 829                 list_del(&next->td_list);
 830                 urb_priv->td_cnt++;
 831                 ed->hwHeadP = next->hwNextTD | toggle;
 832         }
 833
 834         /* help for troubleshooting:  report anything that
 835          * looks odd ... that doesn't include protocol stalls
 836          * (or maybe some other things)
 837          */
 838         switch (cc) {
 839         case TD_DATAUNDERRUN:
 840                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 841                         break;
 842                 /* fallthrough */
 843         case TD_CC_STALL:
 844                 if (usb_pipecontrol (urb->pipe))
 845                         break;
 846                 /* fallthrough */
 847         default:
 848                 ohci_dbg (ohci,
 849                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 850                         urb, urb->dev->devpath,
 851                         usb_pipeendpoint (urb->pipe),
 852                         usb_pipein (urb->pipe) ? "in" : "out",
 853                         hc32_to_cpu (ohci, td->hwINFO),
 854                         cc, cc_to_error [cc]);
 855         }
 856 }
 857
 858 /* replies to the request have to be on a FIFO basis so
 859  * we unreverse the hc-reversed done-list
 860  */
 861 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 862 {
 863         u32             td_dma;
 864         struct td       *td_rev = NULL;
 865         struct td       *td = NULL;
 866
 867         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 868         ohci->hcca->done_head = 0;
 869         wmb();
 870
 871         /* get TD from hc's singly linked list, and
 872          * prepend to ours.  ed->td_list changes later.
 873          */
 874         while (td_dma) {
 875                 int             cc;
 876
 877                 td = dma_to_td (ohci, td_dma);
 878                 if (!td) {
 879                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 880                         break;
 881                 }
 882
 883                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 884                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 885
 886                 /* Non-iso endpoints can halt on error; un-halt,
 887                  * and dequeue any other TDs from this urb.
 888                  * No other TD could have caused the halt.
 889                  */
 890                 if (cc != TD_CC_NOERROR
 891                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 892                         ed_halted(ohci, td, cc);
 893
 894                 td->next_dl_td = td_rev;
 895                 td_rev = td;
 896                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 897         }
 898         return td_rev;
 899 }
 900
 901 /*-------------------------------------------------------------------------*/
 902
 903 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 904 static void
 905 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 906 {
 907         struct ed       *ed, **last;
 908
 909 rescan_all:
 910         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 911                 struct list_head        *entry, *tmp;
 912                 int                     completed, modified;
 913                 __hc32                  *prev;
 914
 915                 /* only take off EDs that the HC isn't using, accounting for
 916                  * frame counter wraps and EDs with partially retired TDs
 917                  */
 918                 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
 919                         if (tick_before (tick, ed->tick)) {
 920 skip_ed:
 921                                 last = &ed->ed_next;
 922                                 continue;
 923                         }
 924
 925                         if (!list_empty (&ed->td_list)) {
 926                                 struct td       *td;
 927                                 u32             head;
 928
 929                                 td = list_entry (ed->td_list.next, struct td,
 930                                                         td_list);
 931                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 932                                                                 TD_MASK;
 933
 934                                 /* INTR_WDH may need to clean up first */
 935                                 if (td->td_dma != head) {
 936                                         if (ed == ohci->ed_to_check)
 937                                                 ohci->ed_to_check = NULL;
 938                                         else
 939                                                 goto skip_ed;
 940                                 }
 941                         }
 942                 }
 943
 944                 /* reentrancy:  if we drop the schedule lock, someone might
 945                  * have modified this list.  normally it's just prepending
 946                  * entries (which we'd ignore), but paranoia won't hurt.
 947                  */
 948                 *last = ed->ed_next;
 949                 ed->ed_next = NULL;
 950                 modified = 0;
 951
 952                 /* unlink urbs as requested, but rescan the list after
 953                  * we call a completion since it might have unlinked
 954                  * another (earlier) urb
 955                  *
 956                  * When we get here, the HC doesn't see this ed.  But it
 957                  * must not be rescheduled until all completed URBs have
 958                  * been given back to the driver.
 959                  */
 960 rescan_this:
 961                 completed = 0;
 962                 prev = &ed->hwHeadP;
 963                 list_for_each_safe (entry, tmp, &ed->td_list) {
 964                         struct td       *td;
 965                         struct urb      *urb;
 966                         urb_priv_t      *urb_priv;
 967                         __hc32          savebits;
 968                         u32             tdINFO;
 969
 970                         td = list_entry (entry, struct td, td_list);
 971                         urb = td->urb;
 972                         urb_priv = td->urb->hcpriv;
 973
 974                         if (!urb->unlinked) {
 975                                 prev = &td->hwNextTD;
 976                                 continue;
 977                         }
 978
 979                         /* patch pointer hc uses */
 980                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 981                         *prev = td->hwNextTD | savebits;
 982
 983                         /* If this was unlinked, the TD may not have been
 984                          * retired ... so manually save the data toggle.
 985                          * The controller ignores the value we save for
 986                          * control and ISO endpoints.
 987                          */
 988                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
 989                         if ((tdINFO & TD_T) == TD_T_DATA0)
 990                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
 991                         else if ((tdINFO & TD_T) == TD_T_DATA1)
 992                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
 993
 994                         /* HC may have partly processed this TD */
 995                         td_done (ohci, urb, td);
 996                         urb_priv->td_cnt++;
 997
 998                         /* if URB is done, clean up */
 999                         if (urb_priv->td_cnt == urb_priv->length) {
1000                                 modified = completed = 1;
1001                                 finish_urb(ohci, urb, 0);
1002                         }
1003                 }
1004                 if (completed && !list_empty (&ed->td_list))
1005                         goto rescan_this;
1006
1007                 /* ED's now officially unlinked, hc doesn't see */
1008                 ed->state = ED_IDLE;
1009                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1010                         ohci->eds_scheduled--;
1011                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1012                 ed->hwNextED = 0;
1013                 wmb ();
1014                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1015
1016                 /* but if there's work queued, reschedule */
1017                 if (!list_empty (&ed->td_list)) {
1018                         if (ohci->rh_state == OHCI_RH_RUNNING)
1019                                 ed_schedule (ohci, ed);
1020                 }
1021
1022                 if (modified)
1023                         goto rescan_all;
1024         }
1025
1026         /* maybe reenable control and bulk lists */
1027         if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1028                 u32     command = 0, control = 0;
1029
1030                 if (ohci->ed_controltail) {
1031                         command |= OHCI_CLF;
1032                         if (quirk_zfmicro(ohci))
1033                                 mdelay(1);
1034                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1035                                 control |= OHCI_CTRL_CLE;
1036                                 ohci_writel (ohci, 0,
1037                                         &ohci->regs->ed_controlcurrent);
1038                         }
1039                 }
1040                 if (ohci->ed_bulktail) {
1041                         command |= OHCI_BLF;
1042                         if (quirk_zfmicro(ohci))
1043                                 mdelay(1);
1044                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1045                                 control |= OHCI_CTRL_BLE;
1046                                 ohci_writel (ohci, 0,
1047                                         &ohci->regs->ed_bulkcurrent);
1048                         }
1049                 }
1050
1051                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1052                 if (control) {
1053                         ohci->hc_control |= control;
1054                         if (quirk_zfmicro(ohci))
1055                                 mdelay(1);
1056                         ohci_writel (ohci, ohci->hc_control,
1057                                         &ohci->regs->control);
1058                 }
1059                 if (command) {
1060                         if (quirk_zfmicro(ohci))
1061                                 mdelay(1);
1062                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1063                 }
1064         }
1065 }
1066
1067
1068
1069 /*-------------------------------------------------------------------------*/
1070
1071 /*
1072  * Used to take back a TD from the host controller. This would normally be
1073  * called from within dl_done_list, however it may be called directly if the
1074  * HC no longer sees the TD and it has not appeared on the donelist (after
1075  * two frames).  This bug has been observed on ZF Micro systems.
1076  */
1077 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1078 {
1079         struct urb      *urb = td->urb;
1080         urb_priv_t      *urb_priv = urb->hcpriv;
1081         struct ed       *ed = td->ed;
1082         int             status;
1083
1084         /* update URB's length and status from TD */
1085         status = td_done(ohci, urb, td);
1086         urb_priv->td_cnt++;
1087
1088         /* If all this urb's TDs are done, call complete() */
1089         if (urb_priv->td_cnt == urb_priv->length)
1090                 finish_urb(ohci, urb, status);
1091
1092         /* clean schedule:  unlink EDs that are no longer busy */
1093         if (list_empty(&ed->td_list)) {
1094                 if (ed->state == ED_OPER)
1095                         start_ed_unlink(ohci, ed);
1096
1097         /* ... reenabling halted EDs only after fault cleanup */
1098         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1099                         == cpu_to_hc32(ohci, ED_SKIP)) {
1100                 td = list_entry(ed->td_list.next, struct td, td_list);
1101                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1102                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1103                         /* ... hc may need waking-up */
1104                         switch (ed->type) {
1105                         case PIPE_CONTROL:
1106                                 ohci_writel(ohci, OHCI_CLF,
1107                                                 &ohci->regs->cmdstatus);
1108                                 break;
1109                         case PIPE_BULK:
1110                                 ohci_writel(ohci, OHCI_BLF,
1111                                                 &ohci->regs->cmdstatus);
1112                                 break;
1113                         }
1114                 }
1115         }
1116 }
1117
1118 /*
1119  * Process normal completions (error or success) and clean the schedules.
1120  *
1121  * This is the main path for handing urbs back to drivers.  The only other
1122  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1123  * instead of scanning the (re-reversed) donelist as this does.  There's
1124  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1125  * with TDs that appear to be orphaned are directly reclaimed.
1126  */
1127 static void
1128 dl_done_list (struct ohci_hcd *ohci)
1129 {
1130         struct td       *td = dl_reverse_done_list (ohci);
1131
1132         while (td) {
1133                 struct td       *td_next = td->next_dl_td;
1134                 struct ed       *ed = td->ed;
1135
1136                 /*
1137                  * Some OHCI controllers (NVIDIA for sure, maybe others)
1138                  * occasionally forget to add TDs to the done queue.  Since
1139                  * TDs for a given endpoint are always processed in order,
1140                  * if we find a TD on the donelist then all of its
1141                  * predecessors must be finished as well.
1142                  */
1143                 for (;;) {
1144                         struct td       *td2;
1145
1146                         td2 = list_first_entry(&ed->td_list, struct td,
1147                                         td_list);
1148                         if (td2 == td)
1149                                 break;
1150                         takeback_td(ohci, td2);
1151                 }
1152
1153                 takeback_td(ohci, td);
1154                 td = td_next;
1155         }
1156 }