drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11
  12 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  13 {
  14         int             last = urb_priv->length - 1;
  15
  16         if (last >= 0) {
  17                 int             i;
  18                 struct td       *td;
  19
  20                 for (i = 0; i <= last; i++) {
  21                         td = urb_priv->td [i];
  22                         if (td)
  23                                 td_free (hc, td);
  24                 }
  25         }
  26
  27         list_del (&urb_priv->pending);
  28         kfree (urb_priv);
  29 }
  30
  31 /*-------------------------------------------------------------------------*/
  32
  33 /*
  34  * URB goes back to driver, and isn't reissued.
  35  * It's completely gone from HC data structures.
  36  * PRECONDITION:  ohci lock held, irqs blocked.
  37  */
  38 static void
  39 finish_urb (struct ohci_hcd *ohci, struct urb *urb)
  40 __releases(ohci->lock)
  41 __acquires(ohci->lock)
  42 {
  43         // ASSERT (urb->hcpriv != 0);
  44
  45         urb_free_priv (ohci, urb->hcpriv);
  46         urb->hcpriv = NULL;
  47
  48         spin_lock (&urb->lock);
  49         if (likely (urb->status == -EINPROGRESS))
  50                 urb->status = 0;
  51         /* report short control reads right even though the data TD always
  52          * has TD_R set.  (much simpler, but creates the 1-td limit.)
  53          */
  54         if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK)
  55                         && unlikely (usb_pipecontrol (urb->pipe))
  56                         && urb->actual_length < urb->transfer_buffer_length
  57                         && usb_pipein (urb->pipe)
  58                         && urb->status == 0) {
  59                 urb->status = -EREMOTEIO;
  60         }
  61         spin_unlock (&urb->lock);
  62
  63         switch (usb_pipetype (urb->pipe)) {
  64         case PIPE_ISOCHRONOUS:
  65                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  66                 break;
  67         case PIPE_INTERRUPT:
  68                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  69                 break;
  70         }
  71
  72 #ifdef OHCI_VERBOSE_DEBUG
  73         urb_print (urb, "RET", usb_pipeout (urb->pipe));
  74 #endif
  75
  76         /* urb->complete() can reenter this HCD */
  77         spin_unlock (&ohci->lock);
  78         usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb);
  79         spin_lock (&ohci->lock);
  80
  81         /* stop periodic dma if it's not needed */
  82         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  83                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  84                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  85                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  86         }
  87 }
  88
  89
  90 /*-------------------------------------------------------------------------*
  91  * ED handling functions
  92  *-------------------------------------------------------------------------*/
  93
  94 /* search for the right schedule branch to use for a periodic ed.
  95  * does some load balancing; returns the branch, or negative errno.
  96  */
  97 static int balance (struct ohci_hcd *ohci, int interval, int load)
  98 {
  99         int     i, branch = -ENOSPC;
 100
 101         /* iso periods can be huge; iso tds specify frame numbers */
 102         if (interval > NUM_INTS)
 103                 interval = NUM_INTS;
 104
 105         /* search for the least loaded schedule branch of that period
 106          * that has enough bandwidth left unreserved.
 107          */
 108         for (i = 0; i < interval ; i++) {
 109                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 110                         int     j;
 111
 112                         /* usb 1.1 says 90% of one frame */
 113                         for (j = i; j < NUM_INTS; j += interval) {
 114                                 if ((ohci->load [j] + load) > 900)
 115                                         break;
 116                         }
 117                         if (j < NUM_INTS)
 118                                 continue;
 119                         branch = i;
 120                 }
 121         }
 122         return branch;
 123 }
 124
 125 /*-------------------------------------------------------------------------*/
 126
 127 /* both iso and interrupt requests have periods; this routine puts them
 128  * into the schedule tree in the apppropriate place.  most iso devices use
 129  * 1msec periods, but that's not required.
 130  */
 131 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 132 {
 133         unsigned        i;
 134
 135         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 136                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 137                 ed, ed->branch, ed->load, ed->interval);
 138
 139         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 140                 struct ed       **prev = &ohci->periodic [i];
 141                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 142                 struct ed       *here = *prev;
 143
 144                 /* sorting each branch by period (slow before fast)
 145                  * lets us share the faster parts of the tree.
 146                  * (plus maybe: put interrupt eds before iso)
 147                  */
 148                 while (here && ed != here) {
 149                         if (ed->interval > here->interval)
 150                                 break;
 151                         prev = &here->ed_next;
 152                         prev_p = &here->hwNextED;
 153                         here = *prev;
 154                 }
 155                 if (ed != here) {
 156                         ed->ed_next = here;
 157                         if (here)
 158                                 ed->hwNextED = *prev_p;
 159                         wmb ();
 160                         *prev = ed;
 161                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 162                         wmb();
 163                 }
 164                 ohci->load [i] += ed->load;
 165         }
 166         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 167 }
 168
 169 /* link an ed into one of the HC chains */
 170
 171 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 172 {
 173         int     branch;
 174
 175         if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING)
 176                 return -EAGAIN;
 177
 178         ed->state = ED_OPER;
 179         ed->ed_prev = NULL;
 180         ed->ed_next = NULL;
 181         ed->hwNextED = 0;
 182         if (quirk_zfmicro(ohci)
 183                         && (ed->type == PIPE_INTERRUPT)
 184                         && !(ohci->eds_scheduled++))
 185                 mod_timer(&ohci->unlink_watchdog, round_jiffies_relative(HZ));
 186         wmb ();
 187
 188         /* we care about rm_list when setting CLE/BLE in case the HC was at
 189          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 190          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 191          *
 192          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 193          * periodic ones are singly linked (ed_next). that's because the
 194          * periodic schedule encodes a tree like figure 3-5 in the ohci
 195          * spec:  each qh can have several "previous" nodes, and the tree
 196          * doesn't have unused/idle descriptors.
 197          */
 198         switch (ed->type) {
 199         case PIPE_CONTROL:
 200                 if (ohci->ed_controltail == NULL) {
 201                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 202                         ohci_writel (ohci, ed->dma,
 203                                         &ohci->regs->ed_controlhead);
 204                 } else {
 205                         ohci->ed_controltail->ed_next = ed;
 206                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 207                                                                 ed->dma);
 208                 }
 209                 ed->ed_prev = ohci->ed_controltail;
 210                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 211                         wmb();
 212                         ohci->hc_control |= OHCI_CTRL_CLE;
 213                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 214                         ohci_writel (ohci, ohci->hc_control,
 215                                         &ohci->regs->control);
 216                 }
 217                 ohci->ed_controltail = ed;
 218                 break;
 219
 220         case PIPE_BULK:
 221                 if (ohci->ed_bulktail == NULL) {
 222                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 223                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 224                 } else {
 225                         ohci->ed_bulktail->ed_next = ed;
 226                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 227                                                                 ed->dma);
 228                 }
 229                 ed->ed_prev = ohci->ed_bulktail;
 230                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 231                         wmb();
 232                         ohci->hc_control |= OHCI_CTRL_BLE;
 233                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 234                         ohci_writel (ohci, ohci->hc_control,
 235                                         &ohci->regs->control);
 236                 }
 237                 ohci->ed_bulktail = ed;
 238                 break;
 239
 240         // case PIPE_INTERRUPT:
 241         // case PIPE_ISOCHRONOUS:
 242         default:
 243                 branch = balance (ohci, ed->interval, ed->load);
 244                 if (branch < 0) {
 245                         ohci_dbg (ohci,
 246                                 "ERR %d, interval %d msecs, load %d\n",
 247                                 branch, ed->interval, ed->load);
 248                         // FIXME if there are TDs queued, fail them!
 249                         return branch;
 250                 }
 251                 ed->branch = branch;
 252                 periodic_link (ohci, ed);
 253         }
 254
 255         /* the HC may not see the schedule updates yet, but if it does
 256          * then they'll be properly ordered.
 257          */
 258         return 0;
 259 }
 260
 261 /*-------------------------------------------------------------------------*/
 262
 263 /* scan the periodic table to find and unlink this ED */
 264 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 265 {
 266         int     i;
 267
 268         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 269                 struct ed       *temp;
 270                 struct ed       **prev = &ohci->periodic [i];
 271                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 272
 273                 while (*prev && (temp = *prev) != ed) {
 274                         prev_p = &temp->hwNextED;
 275                         prev = &temp->ed_next;
 276                 }
 277                 if (*prev) {
 278                         *prev_p = ed->hwNextED;
 279                         *prev = ed->ed_next;
 280                 }
 281                 ohci->load [i] -= ed->load;
 282         }
 283         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 284
 285         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 286                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 287                 ed, ed->branch, ed->load, ed->interval);
 288 }
 289
 290 /* unlink an ed from one of the HC chains.
 291  * just the link to the ed is unlinked.
 292  * the link from the ed still points to another operational ed or 0
 293  * so the HC can eventually finish the processing of the unlinked ed
 294  * (assuming it already started that, which needn't be true).
 295  *
 296  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 297  * it won't.  ED_SKIP means the HC will finish its current transaction,
 298  * but won't start anything new.  The TD queue may still grow; device
 299  * drivers don't know about this HCD-internal state.
 300  *
 301  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 302  *
 303  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 304  *    immediately.  HC should be working on them.
 305  *
 306  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 307  *    to care about this ED; safe to disable the endpoint.
 308  *
 309  * When finish_unlinks() runs later, after SOF interrupt, it will often
 310  * complete one or more URB unlinks before making that state change.
 311  */
 312 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 313 {
 314         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 315         wmb ();
 316         ed->state = ED_UNLINK;
 317
 318         /* To deschedule something from the control or bulk list, just
 319          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 320          * head/current registers until later, and "later" isn't very
 321          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 322          * the HC is reading the ED queues (while we modify them).
 323          *
 324          * For now, ed_schedule() is "later".  It might be good paranoia
 325          * to scrub those registers in finish_unlinks(), in case of bugs
 326          * that make the HC try to use them.
 327          */
 328         switch (ed->type) {
 329         case PIPE_CONTROL:
 330                 /* remove ED from the HC's list: */
 331                 if (ed->ed_prev == NULL) {
 332                         if (!ed->hwNextED) {
 333                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 334                                 ohci_writel (ohci, ohci->hc_control,
 335                                                 &ohci->regs->control);
 336                                 // a ohci_readl() later syncs CLE with the HC
 337                         } else
 338                                 ohci_writel (ohci,
 339                                         hc32_to_cpup (ohci, &ed->hwNextED),
 340                                         &ohci->regs->ed_controlhead);
 341                 } else {
 342                         ed->ed_prev->ed_next = ed->ed_next;
 343                         ed->ed_prev->hwNextED = ed->hwNextED;
 344                 }
 345                 /* remove ED from the HCD's list: */
 346                 if (ohci->ed_controltail == ed) {
 347                         ohci->ed_controltail = ed->ed_prev;
 348                         if (ohci->ed_controltail)
 349                                 ohci->ed_controltail->ed_next = NULL;
 350                 } else if (ed->ed_next) {
 351                         ed->ed_next->ed_prev = ed->ed_prev;
 352                 }
 353                 break;
 354
 355         case PIPE_BULK:
 356                 /* remove ED from the HC's list: */
 357                 if (ed->ed_prev == NULL) {
 358                         if (!ed->hwNextED) {
 359                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 360                                 ohci_writel (ohci, ohci->hc_control,
 361                                                 &ohci->regs->control);
 362                                 // a ohci_readl() later syncs BLE with the HC
 363                         } else
 364                                 ohci_writel (ohci,
 365                                         hc32_to_cpup (ohci, &ed->hwNextED),
 366                                         &ohci->regs->ed_bulkhead);
 367                 } else {
 368                         ed->ed_prev->ed_next = ed->ed_next;
 369                         ed->ed_prev->hwNextED = ed->hwNextED;
 370                 }
 371                 /* remove ED from the HCD's list: */
 372                 if (ohci->ed_bulktail == ed) {
 373                         ohci->ed_bulktail = ed->ed_prev;
 374                         if (ohci->ed_bulktail)
 375                                 ohci->ed_bulktail->ed_next = NULL;
 376                 } else if (ed->ed_next) {
 377                         ed->ed_next->ed_prev = ed->ed_prev;
 378                 }
 379                 break;
 380
 381         // case PIPE_INTERRUPT:
 382         // case PIPE_ISOCHRONOUS:
 383         default:
 384                 periodic_unlink (ohci, ed);
 385                 break;
 386         }
 387 }
 388
 389
 390 /*-------------------------------------------------------------------------*/
 391
 392 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 393  * of enumeration, usb_set_configuration() or usb_set_interface().
 394  */
 395 static struct ed *ed_get (
 396         struct ohci_hcd         *ohci,
 397         struct usb_host_endpoint *ep,
 398         struct usb_device       *udev,
 399         unsigned int            pipe,
 400         int                     interval
 401 ) {
 402         struct ed               *ed;
 403         unsigned long           flags;
 404
 405         spin_lock_irqsave (&ohci->lock, flags);
 406
 407         if (!(ed = ep->hcpriv)) {
 408                 struct td       *td;
 409                 int             is_out;
 410                 u32             info;
 411
 412                 ed = ed_alloc (ohci, GFP_ATOMIC);
 413                 if (!ed) {
 414                         /* out of memory */
 415                         goto done;
 416                 }
 417
 418                 /* dummy td; end of td list for ed */
 419                 td = td_alloc (ohci, GFP_ATOMIC);
 420                 if (!td) {
 421                         /* out of memory */
 422                         ed_free (ohci, ed);
 423                         ed = NULL;
 424                         goto done;
 425                 }
 426                 ed->dummy = td;
 427                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 428                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 429                 ed->state = ED_IDLE;
 430
 431                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 432
 433                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 434                  * suceeds ... otherwise we wouldn't need "pipe".
 435                  */
 436                 info = usb_pipedevice (pipe);
 437                 ed->type = usb_pipetype(pipe);
 438
 439                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 440                 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
 441                 if (udev->speed == USB_SPEED_LOW)
 442                         info |= ED_LOWSPEED;
 443                 /* only control transfers store pids in tds */
 444                 if (ed->type != PIPE_CONTROL) {
 445                         info |= is_out ? ED_OUT : ED_IN;
 446                         if (ed->type != PIPE_BULK) {
 447                                 /* periodic transfers... */
 448                                 if (ed->type == PIPE_ISOCHRONOUS)
 449                                         info |= ED_ISO;
 450                                 else if (interval > 32) /* iso can be bigger */
 451                                         interval = 32;
 452                                 ed->interval = interval;
 453                                 ed->load = usb_calc_bus_time (
 454                                         udev->speed, !is_out,
 455                                         ed->type == PIPE_ISOCHRONOUS,
 456                                         le16_to_cpu(ep->desc.wMaxPacketSize))
 457                                                 / 1000;
 458                         }
 459                 }
 460                 ed->hwINFO = cpu_to_hc32(ohci, info);
 461
 462                 ep->hcpriv = ed;
 463         }
 464
 465 done:
 466         spin_unlock_irqrestore (&ohci->lock, flags);
 467         return ed;
 468 }
 469
 470 /*-------------------------------------------------------------------------*/
 471
 472 /* request unlinking of an endpoint from an operational HC.
 473  * put the ep on the rm_list
 474  * real work is done at the next start frame (SF) hardware interrupt
 475  * caller guarantees HCD is running, so hardware access is safe,
 476  * and that ed->state is ED_OPER
 477  */
 478 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 479 {
 480         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 481         ed_deschedule (ohci, ed);
 482
 483         /* rm_list is just singly linked, for simplicity */
 484         ed->ed_next = ohci->ed_rm_list;
 485         ed->ed_prev = NULL;
 486         ohci->ed_rm_list = ed;
 487
 488         /* enable SOF interrupt */
 489         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 490         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 491         // flush those writes, and get latest HCCA contents
 492         (void) ohci_readl (ohci, &ohci->regs->control);
 493
 494         /* SF interrupt might get delayed; record the frame counter value that
 495          * indicates when the HC isn't looking at it, so concurrent unlinks
 496          * behave.  frame_no wraps every 2^16 msec, and changes right before
 497          * SF is triggered.
 498          */
 499         ed->tick = ohci_frame_no(ohci) + 1;
 500
 501 }
 502
 503 /*-------------------------------------------------------------------------*
 504  * TD handling functions
 505  *-------------------------------------------------------------------------*/
 506
 507 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 508
 509 static void
 510 td_fill (struct ohci_hcd *ohci, u32 info,
 511         dma_addr_t data, int len,
 512         struct urb *urb, int index)
 513 {
 514         struct td               *td, *td_pt;
 515         struct urb_priv         *urb_priv = urb->hcpriv;
 516         int                     is_iso = info & TD_ISO;
 517         int                     hash;
 518
 519         // ASSERT (index < urb_priv->length);
 520
 521         /* aim for only one interrupt per urb.  mostly applies to control
 522          * and iso; other urbs rarely need more than one TD per urb.
 523          * this way, only final tds (or ones with an error) cause IRQs.
 524          * at least immediately; use DI=6 in case any control request is
 525          * tempted to die part way through.  (and to force the hc to flush
 526          * its donelist soonish, even on unlink paths.)
 527          *
 528          * NOTE: could delay interrupts even for the last TD, and get fewer
 529          * interrupts ... increasing per-urb latency by sharing interrupts.
 530          * Drivers that queue bulk urbs may request that behavior.
 531          */
 532         if (index != (urb_priv->length - 1)
 533                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 534                 info |= TD_DI_SET (6);
 535
 536         /* use this td as the next dummy */
 537         td_pt = urb_priv->td [index];
 538
 539         /* fill the old dummy TD */
 540         td = urb_priv->td [index] = urb_priv->ed->dummy;
 541         urb_priv->ed->dummy = td_pt;
 542
 543         td->ed = urb_priv->ed;
 544         td->next_dl_td = NULL;
 545         td->index = index;
 546         td->urb = urb;
 547         td->data_dma = data;
 548         if (!len)
 549                 data = 0;
 550
 551         td->hwINFO = cpu_to_hc32 (ohci, info);
 552         if (is_iso) {
 553                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 554                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 555                                                 (data & 0x0FFF) | 0xE000);
 556                 td->ed->last_iso = info & 0xffff;
 557         } else {
 558                 td->hwCBP = cpu_to_hc32 (ohci, data);
 559         }
 560         if (data)
 561                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 562         else
 563                 td->hwBE = 0;
 564         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 565
 566         /* append to queue */
 567         list_add_tail (&td->td_list, &td->ed->td_list);
 568
 569         /* hash it for later reverse mapping */
 570         hash = TD_HASH_FUNC (td->td_dma);
 571         td->td_hash = ohci->td_hash [hash];
 572         ohci->td_hash [hash] = td;
 573
 574         /* HC might read the TD (or cachelines) right away ... */
 575         wmb ();
 576         td->ed->hwTailP = td->hwNextTD;
 577 }
 578
 579 /*-------------------------------------------------------------------------*/
 580
 581 /* Prepare all TDs of a transfer, and queue them onto the ED.
 582  * Caller guarantees HC is active.
 583  * Usually the ED is already on the schedule, so TDs might be
 584  * processed as soon as they're queued.
 585  */
 586 static void td_submit_urb (
 587         struct ohci_hcd *ohci,
 588         struct urb      *urb
 589 ) {
 590         struct urb_priv *urb_priv = urb->hcpriv;
 591         dma_addr_t      data;
 592         int             data_len = urb->transfer_buffer_length;
 593         int             cnt = 0;
 594         u32             info = 0;
 595         int             is_out = usb_pipeout (urb->pipe);
 596         int             periodic = 0;
 597
 598         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 599          * use the device toggle bits for resetting, and rely on the fact
 600          * that resetting toggle is meaningless if the endpoint is active.
 601          */
 602         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 603                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 604                         is_out, 1);
 605                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 606         }
 607
 608         urb_priv->td_cnt = 0;
 609         list_add (&urb_priv->pending, &ohci->pending);
 610
 611         if (data_len)
 612                 data = urb->transfer_dma;
 613         else
 614                 data = 0;
 615
 616         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 617          * using TD_CC_GET, as well as by seeing them on the done list.
 618          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 619          */
 620         switch (urb_priv->ed->type) {
 621
 622         /* Bulk and interrupt are identical except for where in the schedule
 623          * their EDs live.
 624          */
 625         case PIPE_INTERRUPT:
 626                 /* ... and periodic urbs have extra accounting */
 627                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 628                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 629                 /* FALLTHROUGH */
 630         case PIPE_BULK:
 631                 info = is_out
 632                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 633                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 634                 /* TDs _could_ transfer up to 8K each */
 635                 while (data_len > 4096) {
 636                         td_fill (ohci, info, data, 4096, urb, cnt);
 637                         data += 4096;
 638                         data_len -= 4096;
 639                         cnt++;
 640                 }
 641                 /* maybe avoid ED halt on final TD short read */
 642                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 643                         info |= TD_R;
 644                 td_fill (ohci, info, data, data_len, urb, cnt);
 645                 cnt++;
 646                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 647                                 && cnt < urb_priv->length) {
 648                         td_fill (ohci, info, 0, 0, urb, cnt);
 649                         cnt++;
 650                 }
 651                 /* maybe kickstart bulk list */
 652                 if (urb_priv->ed->type == PIPE_BULK) {
 653                         wmb ();
 654                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 655                 }
 656                 break;
 657
 658         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 659          * any DATA phase works normally, and the STATUS ack is special.
 660          */
 661         case PIPE_CONTROL:
 662                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 663                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 664                 if (data_len > 0) {
 665                         info = TD_CC | TD_R | TD_T_DATA1;
 666                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 667                         /* NOTE:  mishandles transfers >8K, some >4K */
 668                         td_fill (ohci, info, data, data_len, urb, cnt++);
 669                 }
 670                 info = (is_out || data_len == 0)
 671                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 672                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 673                 td_fill (ohci, info, data, 0, urb, cnt++);
 674                 /* maybe kickstart control list */
 675                 wmb ();
 676                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 677                 break;
 678
 679         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 680          * Each TD could handle multiple consecutive frames (interval 1);
 681          * we could often reduce the number of TDs here.
 682          */
 683         case PIPE_ISOCHRONOUS:
 684                 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
 685                         int     frame = urb->start_frame;
 686
 687                         // FIXME scheduling should handle frame counter
 688                         // roll-around ... exotic case (and OHCI has
 689                         // a 2^16 iso range, vs other HCs max of 2^10)
 690                         frame += cnt * urb->interval;
 691                         frame &= 0xffff;
 692                         td_fill (ohci, TD_CC | TD_ISO | frame,
 693                                 data + urb->iso_frame_desc [cnt].offset,
 694                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 695                 }
 696                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 697                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 698                 break;
 699         }
 700
 701         /* start periodic dma if needed */
 702         if (periodic) {
 703                 wmb ();
 704                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 705                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 706         }
 707
 708         // ASSERT (urb_priv->length == cnt);
 709 }
 710
 711 /*-------------------------------------------------------------------------*
 712  * Done List handling functions
 713  *-------------------------------------------------------------------------*/
 714
 715 /* calculate transfer length/status and update the urb
 716  * PRECONDITION:  irqsafe (only for urb->status locking)
 717  */
 718 static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 719 {
 720         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 721         int     cc = 0;
 722
 723         list_del (&td->td_list);
 724
 725         /* ISO ... drivers see per-TD length/status */
 726         if (tdINFO & TD_ISO) {
 727                 u16     tdPSW = ohci_hwPSW (ohci, td, 0);
 728                 int     dlen = 0;
 729
 730                 /* NOTE:  assumes FC in tdINFO == 0, and that
 731                  * only the first of 0..MAXPSW psws is used.
 732                  */
 733
 734                 cc = (tdPSW >> 12) & 0xF;
 735                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 736                         return;
 737
 738                 if (usb_pipeout (urb->pipe))
 739                         dlen = urb->iso_frame_desc [td->index].length;
 740                 else {
 741                         /* short reads are always OK for ISO */
 742                         if (cc == TD_DATAUNDERRUN)
 743                                 cc = TD_CC_NOERROR;
 744                         dlen = tdPSW & 0x3ff;
 745                 }
 746                 urb->actual_length += dlen;
 747                 urb->iso_frame_desc [td->index].actual_length = dlen;
 748                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 749
 750                 if (cc != TD_CC_NOERROR)
 751                         ohci_vdbg (ohci,
 752                                 "urb %p iso td %p (%d) len %d cc %d\n",
 753                                 urb, td, 1 + td->index, dlen, cc);
 754
 755         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 756          * except that "setup" bytes aren't counted and "short" transfers
 757          * might not be reported as errors.
 758          */
 759         } else {
 760                 int     type = usb_pipetype (urb->pipe);
 761                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 762
 763                 cc = TD_CC_GET (tdINFO);
 764
 765                 /* update packet status if needed (short is normally ok) */
 766                 if (cc == TD_DATAUNDERRUN
 767                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 768                         cc = TD_CC_NOERROR;
 769                 if (cc != TD_CC_NOERROR && cc < 0x0E) {
 770                         spin_lock (&urb->lock);
 771                         if (urb->status == -EINPROGRESS)
 772                                 urb->status = cc_to_error [cc];
 773                         spin_unlock (&urb->lock);
 774                 }
 775
 776                 /* count all non-empty packets except control SETUP packet */
 777                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 778                         if (td->hwCBP == 0)
 779                                 urb->actual_length += tdBE - td->data_dma + 1;
 780                         else
 781                                 urb->actual_length +=
 782                                           hc32_to_cpup (ohci, &td->hwCBP)
 783                                         - td->data_dma;
 784                 }
 785
 786                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 787                         ohci_vdbg (ohci,
 788                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 789                                 urb, td, 1 + td->index, cc,
 790                                 urb->actual_length,
 791                                 urb->transfer_buffer_length);
 792         }
 793 }
 794
 795 /*-------------------------------------------------------------------------*/
 796
 797 static inline struct td *
 798 ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
 799 {
 800         struct urb              *urb = td->urb;
 801         struct ed               *ed = td->ed;
 802         struct list_head        *tmp = td->td_list.next;
 803         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 804
 805         /* clear ed halt; this is the td that caused it, but keep it inactive
 806          * until its urb->complete() has a chance to clean up.
 807          */
 808         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 809         wmb ();
 810         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 811
 812         /* put any later tds from this urb onto the donelist, after 'td',
 813          * order won't matter here: no errors, and nothing was transferred.
 814          * also patch the ed so it looks as if those tds completed normally.
 815          */
 816         while (tmp != &ed->td_list) {
 817                 struct td       *next;
 818                 __hc32          info;
 819
 820                 next = list_entry (tmp, struct td, td_list);
 821                 tmp = next->td_list.next;
 822
 823                 if (next->urb != urb)
 824                         break;
 825
 826                 /* NOTE: if multi-td control DATA segments get supported,
 827                  * this urb had one of them, this td wasn't the last td
 828                  * in that segment (TD_R clear), this ed halted because
 829                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 830                  * then we need to leave the control STATUS packet queued
 831                  * and clear ED_SKIP.
 832                  */
 833                 info = next->hwINFO;
 834                 info |= cpu_to_hc32 (ohci, TD_DONE);
 835                 info &= ~cpu_to_hc32 (ohci, TD_CC);
 836                 next->hwINFO = info;
 837
 838                 next->next_dl_td = rev;
 839                 rev = next;
 840
 841                 ed->hwHeadP = next->hwNextTD | toggle;
 842         }
 843
 844         /* help for troubleshooting:  report anything that
 845          * looks odd ... that doesn't include protocol stalls
 846          * (or maybe some other things)
 847          */
 848         switch (cc) {
 849         case TD_DATAUNDERRUN:
 850                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 851                         break;
 852                 /* fallthrough */
 853         case TD_CC_STALL:
 854                 if (usb_pipecontrol (urb->pipe))
 855                         break;
 856                 /* fallthrough */
 857         default:
 858                 ohci_dbg (ohci,
 859                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 860                         urb, urb->dev->devpath,
 861                         usb_pipeendpoint (urb->pipe),
 862                         usb_pipein (urb->pipe) ? "in" : "out",
 863                         hc32_to_cpu (ohci, td->hwINFO),
 864                         cc, cc_to_error [cc]);
 865         }
 866
 867         return rev;
 868 }
 869
 870 /* replies to the request have to be on a FIFO basis so
 871  * we unreverse the hc-reversed done-list
 872  */
 873 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 874 {
 875         u32             td_dma;
 876         struct td       *td_rev = NULL;
 877         struct td       *td = NULL;
 878
 879         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 880         ohci->hcca->done_head = 0;
 881         wmb();
 882
 883         /* get TD from hc's singly linked list, and
 884          * prepend to ours.  ed->td_list changes later.
 885          */
 886         while (td_dma) {
 887                 int             cc;
 888
 889                 td = dma_to_td (ohci, td_dma);
 890                 if (!td) {
 891                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 892                         break;
 893                 }
 894
 895                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 896                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 897
 898                 /* Non-iso endpoints can halt on error; un-halt,
 899                  * and dequeue any other TDs from this urb.
 900                  * No other TD could have caused the halt.
 901                  */
 902                 if (cc != TD_CC_NOERROR
 903                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 904                         td_rev = ed_halted (ohci, td, cc, td_rev);
 905
 906                 td->next_dl_td = td_rev;
 907                 td_rev = td;
 908                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 909         }
 910         return td_rev;
 911 }
 912
 913 /*-------------------------------------------------------------------------*/
 914
 915 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 916 static void
 917 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 918 {
 919         struct ed       *ed, **last;
 920
 921 rescan_all:
 922         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 923                 struct list_head        *entry, *tmp;
 924                 int                     completed, modified;
 925                 __hc32                  *prev;
 926
 927                 /* only take off EDs that the HC isn't using, accounting for
 928                  * frame counter wraps and EDs with partially retired TDs
 929                  */
 930                 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
 931                         if (tick_before (tick, ed->tick)) {
 932 skip_ed:
 933                                 last = &ed->ed_next;
 934                                 continue;
 935                         }
 936
 937                         if (!list_empty (&ed->td_list)) {
 938                                 struct td       *td;
 939                                 u32             head;
 940
 941                                 td = list_entry (ed->td_list.next, struct td,
 942                                                         td_list);
 943                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 944                                                                 TD_MASK;
 945
 946                                 /* INTR_WDH may need to clean up first */
 947                                 if (td->td_dma != head) {
 948                                         if (ed == ohci->ed_to_check)
 949                                                 ohci->ed_to_check = NULL;
 950                                         else
 951                                                 goto skip_ed;
 952                                 }
 953                         }
 954                 }
 955
 956                 /* reentrancy:  if we drop the schedule lock, someone might
 957                  * have modified this list.  normally it's just prepending
 958                  * entries (which we'd ignore), but paranoia won't hurt.
 959                  */
 960                 *last = ed->ed_next;
 961                 ed->ed_next = NULL;
 962                 modified = 0;
 963
 964                 /* unlink urbs as requested, but rescan the list after
 965                  * we call a completion since it might have unlinked
 966                  * another (earlier) urb
 967                  *
 968                  * When we get here, the HC doesn't see this ed.  But it
 969                  * must not be rescheduled until all completed URBs have
 970                  * been given back to the driver.
 971                  */
 972 rescan_this:
 973                 completed = 0;
 974                 prev = &ed->hwHeadP;
 975                 list_for_each_safe (entry, tmp, &ed->td_list) {
 976                         struct td       *td;
 977                         struct urb      *urb;
 978                         urb_priv_t      *urb_priv;
 979                         __hc32          savebits;
 980
 981                         td = list_entry (entry, struct td, td_list);
 982                         urb = td->urb;
 983                         urb_priv = td->urb->hcpriv;
 984
 985                         if (urb->status == -EINPROGRESS) {
 986                                 prev = &td->hwNextTD;
 987                                 continue;
 988                         }
 989
 990                         /* patch pointer hc uses */
 991                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 992                         *prev = td->hwNextTD | savebits;
 993
 994                         /* HC may have partly processed this TD */
 995                         td_done (ohci, urb, td);
 996                         urb_priv->td_cnt++;
 997
 998                         /* if URB is done, clean up */
 999                         if (urb_priv->td_cnt == urb_priv->length) {
1000                                 modified = completed = 1;
1001                                 finish_urb (ohci, urb);
1002                         }
1003                 }
1004                 if (completed && !list_empty (&ed->td_list))
1005                         goto rescan_this;
1006
1007                 /* ED's now officially unlinked, hc doesn't see */
1008                 ed->state = ED_IDLE;
1009                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1010                         ohci->eds_scheduled--;
1011                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1012                 ed->hwNextED = 0;
1013                 wmb ();
1014                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1015
1016                 /* but if there's work queued, reschedule */
1017                 if (!list_empty (&ed->td_list)) {
1018                         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
1019                                 ed_schedule (ohci, ed);
1020                 }
1021
1022                 if (modified)
1023                         goto rescan_all;
1024         }
1025
1026         /* maybe reenable control and bulk lists */
1027         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
1028                         && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
1029                         && !ohci->ed_rm_list) {
1030                 u32     command = 0, control = 0;
1031
1032                 if (ohci->ed_controltail) {
1033                         command |= OHCI_CLF;
1034                         if (quirk_zfmicro(ohci))
1035                                 mdelay(1);
1036                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1037                                 control |= OHCI_CTRL_CLE;
1038                                 ohci_writel (ohci, 0,
1039                                         &ohci->regs->ed_controlcurrent);
1040                         }
1041                 }
1042                 if (ohci->ed_bulktail) {
1043                         command |= OHCI_BLF;
1044                         if (quirk_zfmicro(ohci))
1045                                 mdelay(1);
1046                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1047                                 control |= OHCI_CTRL_BLE;
1048                                 ohci_writel (ohci, 0,
1049                                         &ohci->regs->ed_bulkcurrent);
1050                         }
1051                 }
1052
1053                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1054                 if (control) {
1055                         ohci->hc_control |= control;
1056                         if (quirk_zfmicro(ohci))
1057                                 mdelay(1);
1058                         ohci_writel (ohci, ohci->hc_control,
1059                                         &ohci->regs->control);
1060                 }
1061                 if (command) {
1062                         if (quirk_zfmicro(ohci))
1063                                 mdelay(1);
1064                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1065                 }
1066         }
1067 }
1068
1069
1070
1071 /*-------------------------------------------------------------------------*/
1072
1073 /*
1074  * Used to take back a TD from the host controller. This would normally be
1075  * called from within dl_done_list, however it may be called directly if the
1076  * HC no longer sees the TD and it has not appeared on the donelist (after
1077  * two frames).  This bug has been observed on ZF Micro systems.
1078  */
1079 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1080 {
1081         struct urb      *urb = td->urb;
1082         urb_priv_t      *urb_priv = urb->hcpriv;
1083         struct ed       *ed = td->ed;
1084
1085         /* update URB's length and status from TD */
1086         td_done(ohci, urb, td);
1087         urb_priv->td_cnt++;
1088
1089         /* If all this urb's TDs are done, call complete() */
1090         if (urb_priv->td_cnt == urb_priv->length)
1091                 finish_urb(ohci, urb);
1092
1093         /* clean schedule:  unlink EDs that are no longer busy */
1094         if (list_empty(&ed->td_list)) {
1095                 if (ed->state == ED_OPER)
1096                         start_ed_unlink(ohci, ed);
1097
1098         /* ... reenabling halted EDs only after fault cleanup */
1099         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1100                         == cpu_to_hc32(ohci, ED_SKIP)) {
1101                 td = list_entry(ed->td_list.next, struct td, td_list);
1102                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1103                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1104                         /* ... hc may need waking-up */
1105                         switch (ed->type) {
1106                         case PIPE_CONTROL:
1107                                 ohci_writel(ohci, OHCI_CLF,
1108                                                 &ohci->regs->cmdstatus);
1109                                 break;
1110                         case PIPE_BULK:
1111                                 ohci_writel(ohci, OHCI_BLF,
1112                                                 &ohci->regs->cmdstatus);
1113                                 break;
1114                         }
1115                 }
1116         }
1117 }
1118
1119 /*
1120  * Process normal completions (error or success) and clean the schedules.
1121  *
1122  * This is the main path for handing urbs back to drivers.  The only other
1123  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1124  * instead of scanning the (re-reversed) donelist as this does.  There's
1125  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1126  * with TDs that appear to be orphaned are directly reclaimed.
1127  */
1128 static void
1129 dl_done_list (struct ohci_hcd *ohci)
1130 {
1131         struct td       *td = dl_reverse_done_list (ohci);
1132
1133         while (td) {
1134                 struct td       *td_next = td->next_dl_td;
1135                 takeback_td(ohci, td);
1136                 td = td_next;
1137         }
1138 }