drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/slab.h>
  12
  13 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  14 {
  15         int             last = urb_priv->length - 1;
  16
  17         if (last >= 0) {
  18                 int             i;
  19                 struct td       *td;
  20
  21                 for (i = 0; i <= last; i++) {
  22                         td = urb_priv->td [i];
  23                         if (td)
  24                                 td_free (hc, td);
  25                 }
  26         }
  27
  28         list_del (&urb_priv->pending);
  29         kfree (urb_priv);
  30 }
  31
  32 /*-------------------------------------------------------------------------*/
  33
  34 /*
  35  * URB goes back to driver, and isn't reissued.
  36  * It's completely gone from HC data structures.
  37  * PRECONDITION:  ohci lock held, irqs blocked.
  38  */
  39 static void
  40 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  41 __releases(ohci->lock)
  42 __acquires(ohci->lock)
  43 {
  44         struct device *dev = ohci_to_hcd(ohci)->self.controller;
  45         struct usb_host_endpoint *ep = urb->ep;
  46         struct urb_priv *urb_priv;
  47
  48         // ASSERT (urb->hcpriv != 0);
  49
  50  restart:
  51         urb_free_priv (ohci, urb->hcpriv);
  52         urb->hcpriv = NULL;
  53         if (likely(status == -EINPROGRESS))
  54                 status = 0;
  55
  56         switch (usb_pipetype (urb->pipe)) {
  57         case PIPE_ISOCHRONOUS:
  58                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  59                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  60                         if (quirk_amdiso(ohci))
  61                                 usb_amd_quirk_pll_enable();
  62                         if (quirk_amdprefetch(ohci))
  63                                 sb800_prefetch(dev, 0);
  64                 }
  65                 break;
  66         case PIPE_INTERRUPT:
  67                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  68                 break;
  69         }
  70
  71         /* urb->complete() can reenter this HCD */
  72         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  73         spin_unlock (&ohci->lock);
  74         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  75         spin_lock (&ohci->lock);
  76
  77         /* stop periodic dma if it's not needed */
  78         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  79                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  80                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  81                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  82         }
  83
  84         /*
  85          * An isochronous URB that is sumitted too late won't have any TDs
  86          * (marked by the fact that the td_cnt value is larger than the
  87          * actual number of TDs).  If the next URB on this endpoint is like
  88          * that, give it back now.
  89          */
  90         if (!list_empty(&ep->urb_list)) {
  91                 urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
  92                 urb_priv = urb->hcpriv;
  93                 if (urb_priv->td_cnt > urb_priv->length) {
  94                         status = 0;
  95                         goto restart;
  96                 }
  97         }
  98 }
  99
 100
 101 /*-------------------------------------------------------------------------*
 102  * ED handling functions
 103  *-------------------------------------------------------------------------*/
 104
 105 /* search for the right schedule branch to use for a periodic ed.
 106  * does some load balancing; returns the branch, or negative errno.
 107  */
 108 static int balance (struct ohci_hcd *ohci, int interval, int load)
 109 {
 110         int     i, branch = -ENOSPC;
 111
 112         /* iso periods can be huge; iso tds specify frame numbers */
 113         if (interval > NUM_INTS)
 114                 interval = NUM_INTS;
 115
 116         /* search for the least loaded schedule branch of that period
 117          * that has enough bandwidth left unreserved.
 118          */
 119         for (i = 0; i < interval ; i++) {
 120                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 121                         int     j;
 122
 123                         /* usb 1.1 says 90% of one frame */
 124                         for (j = i; j < NUM_INTS; j += interval) {
 125                                 if ((ohci->load [j] + load) > 900)
 126                                         break;
 127                         }
 128                         if (j < NUM_INTS)
 129                                 continue;
 130                         branch = i;
 131                 }
 132         }
 133         return branch;
 134 }
 135
 136 /*-------------------------------------------------------------------------*/
 137
 138 /* both iso and interrupt requests have periods; this routine puts them
 139  * into the schedule tree in the apppropriate place.  most iso devices use
 140  * 1msec periods, but that's not required.
 141  */
 142 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 143 {
 144         unsigned        i;
 145
 146         ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 147                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 148                 ed, ed->branch, ed->load, ed->interval);
 149
 150         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 151                 struct ed       **prev = &ohci->periodic [i];
 152                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 153                 struct ed       *here = *prev;
 154
 155                 /* sorting each branch by period (slow before fast)
 156                  * lets us share the faster parts of the tree.
 157                  * (plus maybe: put interrupt eds before iso)
 158                  */
 159                 while (here && ed != here) {
 160                         if (ed->interval > here->interval)
 161                                 break;
 162                         prev = &here->ed_next;
 163                         prev_p = &here->hwNextED;
 164                         here = *prev;
 165                 }
 166                 if (ed != here) {
 167                         ed->ed_next = here;
 168                         if (here)
 169                                 ed->hwNextED = *prev_p;
 170                         wmb ();
 171                         *prev = ed;
 172                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 173                         wmb();
 174                 }
 175                 ohci->load [i] += ed->load;
 176         }
 177         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 178 }
 179
 180 /* link an ed into one of the HC chains */
 181
 182 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 183 {
 184         int     branch;
 185
 186         ed->state = ED_OPER;
 187         ed->ed_prev = NULL;
 188         ed->ed_next = NULL;
 189         ed->hwNextED = 0;
 190         if (quirk_zfmicro(ohci)
 191                         && (ed->type == PIPE_INTERRUPT)
 192                         && !(ohci->eds_scheduled++))
 193                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 194         wmb ();
 195
 196         /* we care about rm_list when setting CLE/BLE in case the HC was at
 197          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 198          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 199          *
 200          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 201          * periodic ones are singly linked (ed_next). that's because the
 202          * periodic schedule encodes a tree like figure 3-5 in the ohci
 203          * spec:  each qh can have several "previous" nodes, and the tree
 204          * doesn't have unused/idle descriptors.
 205          */
 206         switch (ed->type) {
 207         case PIPE_CONTROL:
 208                 if (ohci->ed_controltail == NULL) {
 209                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 210                         ohci_writel (ohci, ed->dma,
 211                                         &ohci->regs->ed_controlhead);
 212                 } else {
 213                         ohci->ed_controltail->ed_next = ed;
 214                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 215                                                                 ed->dma);
 216                 }
 217                 ed->ed_prev = ohci->ed_controltail;
 218                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 219                         wmb();
 220                         ohci->hc_control |= OHCI_CTRL_CLE;
 221                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 222                         ohci_writel (ohci, ohci->hc_control,
 223                                         &ohci->regs->control);
 224                 }
 225                 ohci->ed_controltail = ed;
 226                 break;
 227
 228         case PIPE_BULK:
 229                 if (ohci->ed_bulktail == NULL) {
 230                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 231                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 232                 } else {
 233                         ohci->ed_bulktail->ed_next = ed;
 234                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 235                                                                 ed->dma);
 236                 }
 237                 ed->ed_prev = ohci->ed_bulktail;
 238                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 239                         wmb();
 240                         ohci->hc_control |= OHCI_CTRL_BLE;
 241                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 242                         ohci_writel (ohci, ohci->hc_control,
 243                                         &ohci->regs->control);
 244                 }
 245                 ohci->ed_bulktail = ed;
 246                 break;
 247
 248         // case PIPE_INTERRUPT:
 249         // case PIPE_ISOCHRONOUS:
 250         default:
 251                 branch = balance (ohci, ed->interval, ed->load);
 252                 if (branch < 0) {
 253                         ohci_dbg (ohci,
 254                                 "ERR %d, interval %d msecs, load %d\n",
 255                                 branch, ed->interval, ed->load);
 256                         // FIXME if there are TDs queued, fail them!
 257                         return branch;
 258                 }
 259                 ed->branch = branch;
 260                 periodic_link (ohci, ed);
 261         }
 262
 263         /* the HC may not see the schedule updates yet, but if it does
 264          * then they'll be properly ordered.
 265          */
 266         return 0;
 267 }
 268
 269 /*-------------------------------------------------------------------------*/
 270
 271 /* scan the periodic table to find and unlink this ED */
 272 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 273 {
 274         int     i;
 275
 276         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 277                 struct ed       *temp;
 278                 struct ed       **prev = &ohci->periodic [i];
 279                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 280
 281                 while (*prev && (temp = *prev) != ed) {
 282                         prev_p = &temp->hwNextED;
 283                         prev = &temp->ed_next;
 284                 }
 285                 if (*prev) {
 286                         *prev_p = ed->hwNextED;
 287                         *prev = ed->ed_next;
 288                 }
 289                 ohci->load [i] -= ed->load;
 290         }
 291         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 292
 293         ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 294                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 295                 ed, ed->branch, ed->load, ed->interval);
 296 }
 297
 298 /* unlink an ed from one of the HC chains.
 299  * just the link to the ed is unlinked.
 300  * the link from the ed still points to another operational ed or 0
 301  * so the HC can eventually finish the processing of the unlinked ed
 302  * (assuming it already started that, which needn't be true).
 303  *
 304  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 305  * it won't.  ED_SKIP means the HC will finish its current transaction,
 306  * but won't start anything new.  The TD queue may still grow; device
 307  * drivers don't know about this HCD-internal state.
 308  *
 309  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 310  *
 311  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 312  *    immediately.  HC should be working on them.
 313  *
 314  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 315  *    to care about this ED; safe to disable the endpoint.
 316  *
 317  * When finish_unlinks() runs later, after SOF interrupt, it will often
 318  * complete one or more URB unlinks before making that state change.
 319  */
 320 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 321 {
 322         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 323         wmb ();
 324         ed->state = ED_UNLINK;
 325
 326         /* To deschedule something from the control or bulk list, just
 327          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 328          * head/current registers until later, and "later" isn't very
 329          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 330          * the HC is reading the ED queues (while we modify them).
 331          *
 332          * For now, ed_schedule() is "later".  It might be good paranoia
 333          * to scrub those registers in finish_unlinks(), in case of bugs
 334          * that make the HC try to use them.
 335          */
 336         switch (ed->type) {
 337         case PIPE_CONTROL:
 338                 /* remove ED from the HC's list: */
 339                 if (ed->ed_prev == NULL) {
 340                         if (!ed->hwNextED) {
 341                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 342                                 ohci_writel (ohci, ohci->hc_control,
 343                                                 &ohci->regs->control);
 344                                 // a ohci_readl() later syncs CLE with the HC
 345                         } else
 346                                 ohci_writel (ohci,
 347                                         hc32_to_cpup (ohci, &ed->hwNextED),
 348                                         &ohci->regs->ed_controlhead);
 349                 } else {
 350                         ed->ed_prev->ed_next = ed->ed_next;
 351                         ed->ed_prev->hwNextED = ed->hwNextED;
 352                 }
 353                 /* remove ED from the HCD's list: */
 354                 if (ohci->ed_controltail == ed) {
 355                         ohci->ed_controltail = ed->ed_prev;
 356                         if (ohci->ed_controltail)
 357                                 ohci->ed_controltail->ed_next = NULL;
 358                 } else if (ed->ed_next) {
 359                         ed->ed_next->ed_prev = ed->ed_prev;
 360                 }
 361                 break;
 362
 363         case PIPE_BULK:
 364                 /* remove ED from the HC's list: */
 365                 if (ed->ed_prev == NULL) {
 366                         if (!ed->hwNextED) {
 367                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 368                                 ohci_writel (ohci, ohci->hc_control,
 369                                                 &ohci->regs->control);
 370                                 // a ohci_readl() later syncs BLE with the HC
 371                         } else
 372                                 ohci_writel (ohci,
 373                                         hc32_to_cpup (ohci, &ed->hwNextED),
 374                                         &ohci->regs->ed_bulkhead);
 375                 } else {
 376                         ed->ed_prev->ed_next = ed->ed_next;
 377                         ed->ed_prev->hwNextED = ed->hwNextED;
 378                 }
 379                 /* remove ED from the HCD's list: */
 380                 if (ohci->ed_bulktail == ed) {
 381                         ohci->ed_bulktail = ed->ed_prev;
 382                         if (ohci->ed_bulktail)
 383                                 ohci->ed_bulktail->ed_next = NULL;
 384                 } else if (ed->ed_next) {
 385                         ed->ed_next->ed_prev = ed->ed_prev;
 386                 }
 387                 break;
 388
 389         // case PIPE_INTERRUPT:
 390         // case PIPE_ISOCHRONOUS:
 391         default:
 392                 periodic_unlink (ohci, ed);
 393                 break;
 394         }
 395 }
 396
 397
 398 /*-------------------------------------------------------------------------*/
 399
 400 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 401  * of enumeration, usb_set_configuration() or usb_set_interface().
 402  */
 403 static struct ed *ed_get (
 404         struct ohci_hcd         *ohci,
 405         struct usb_host_endpoint *ep,
 406         struct usb_device       *udev,
 407         unsigned int            pipe,
 408         int                     interval
 409 ) {
 410         struct ed               *ed;
 411         unsigned long           flags;
 412
 413         spin_lock_irqsave (&ohci->lock, flags);
 414
 415         if (!(ed = ep->hcpriv)) {
 416                 struct td       *td;
 417                 int             is_out;
 418                 u32             info;
 419
 420                 ed = ed_alloc (ohci, GFP_ATOMIC);
 421                 if (!ed) {
 422                         /* out of memory */
 423                         goto done;
 424                 }
 425
 426                 /* dummy td; end of td list for ed */
 427                 td = td_alloc (ohci, GFP_ATOMIC);
 428                 if (!td) {
 429                         /* out of memory */
 430                         ed_free (ohci, ed);
 431                         ed = NULL;
 432                         goto done;
 433                 }
 434                 ed->dummy = td;
 435                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 436                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 437                 ed->state = ED_IDLE;
 438
 439                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 440
 441                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 442                  * succeeds ... otherwise we wouldn't need "pipe".
 443                  */
 444                 info = usb_pipedevice (pipe);
 445                 ed->type = usb_pipetype(pipe);
 446
 447                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 448                 info |= usb_endpoint_maxp(&ep->desc) << 16;
 449                 if (udev->speed == USB_SPEED_LOW)
 450                         info |= ED_LOWSPEED;
 451                 /* only control transfers store pids in tds */
 452                 if (ed->type != PIPE_CONTROL) {
 453                         info |= is_out ? ED_OUT : ED_IN;
 454                         if (ed->type != PIPE_BULK) {
 455                                 /* periodic transfers... */
 456                                 if (ed->type == PIPE_ISOCHRONOUS)
 457                                         info |= ED_ISO;
 458                                 else if (interval > 32) /* iso can be bigger */
 459                                         interval = 32;
 460                                 ed->interval = interval;
 461                                 ed->load = usb_calc_bus_time (
 462                                         udev->speed, !is_out,
 463                                         ed->type == PIPE_ISOCHRONOUS,
 464                                         usb_endpoint_maxp(&ep->desc))
 465                                                 / 1000;
 466                         }
 467                 }
 468                 ed->hwINFO = cpu_to_hc32(ohci, info);
 469
 470                 ep->hcpriv = ed;
 471         }
 472
 473 done:
 474         spin_unlock_irqrestore (&ohci->lock, flags);
 475         return ed;
 476 }
 477
 478 /*-------------------------------------------------------------------------*/
 479
 480 /* request unlinking of an endpoint from an operational HC.
 481  * put the ep on the rm_list
 482  * real work is done at the next start frame (SF) hardware interrupt
 483  * caller guarantees HCD is running, so hardware access is safe,
 484  * and that ed->state is ED_OPER
 485  */
 486 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 487 {
 488         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 489         ed_deschedule (ohci, ed);
 490
 491         /* rm_list is just singly linked, for simplicity */
 492         ed->ed_next = ohci->ed_rm_list;
 493         ed->ed_prev = NULL;
 494         ohci->ed_rm_list = ed;
 495
 496         /* enable SOF interrupt */
 497         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 498         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 499         // flush those writes, and get latest HCCA contents
 500         (void) ohci_readl (ohci, &ohci->regs->control);
 501
 502         /* SF interrupt might get delayed; record the frame counter value that
 503          * indicates when the HC isn't looking at it, so concurrent unlinks
 504          * behave.  frame_no wraps every 2^16 msec, and changes right before
 505          * SF is triggered.
 506          */
 507         ed->tick = ohci_frame_no(ohci) + 1;
 508
 509 }
 510
 511 /*-------------------------------------------------------------------------*
 512  * TD handling functions
 513  *-------------------------------------------------------------------------*/
 514
 515 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 516
 517 static void
 518 td_fill (struct ohci_hcd *ohci, u32 info,
 519         dma_addr_t data, int len,
 520         struct urb *urb, int index)
 521 {
 522         struct td               *td, *td_pt;
 523         struct urb_priv         *urb_priv = urb->hcpriv;
 524         int                     is_iso = info & TD_ISO;
 525         int                     hash;
 526
 527         // ASSERT (index < urb_priv->length);
 528
 529         /* aim for only one interrupt per urb.  mostly applies to control
 530          * and iso; other urbs rarely need more than one TD per urb.
 531          * this way, only final tds (or ones with an error) cause IRQs.
 532          * at least immediately; use DI=6 in case any control request is
 533          * tempted to die part way through.  (and to force the hc to flush
 534          * its donelist soonish, even on unlink paths.)
 535          *
 536          * NOTE: could delay interrupts even for the last TD, and get fewer
 537          * interrupts ... increasing per-urb latency by sharing interrupts.
 538          * Drivers that queue bulk urbs may request that behavior.
 539          */
 540         if (index != (urb_priv->length - 1)
 541                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 542                 info |= TD_DI_SET (6);
 543
 544         /* use this td as the next dummy */
 545         td_pt = urb_priv->td [index];
 546
 547         /* fill the old dummy TD */
 548         td = urb_priv->td [index] = urb_priv->ed->dummy;
 549         urb_priv->ed->dummy = td_pt;
 550
 551         td->ed = urb_priv->ed;
 552         td->next_dl_td = NULL;
 553         td->index = index;
 554         td->urb = urb;
 555         td->data_dma = data;
 556         if (!len)
 557                 data = 0;
 558
 559         td->hwINFO = cpu_to_hc32 (ohci, info);
 560         if (is_iso) {
 561                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 562                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 563                                                 (data & 0x0FFF) | 0xE000);
 564         } else {
 565                 td->hwCBP = cpu_to_hc32 (ohci, data);
 566         }
 567         if (data)
 568                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 569         else
 570                 td->hwBE = 0;
 571         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 572
 573         /* append to queue */
 574         list_add_tail (&td->td_list, &td->ed->td_list);
 575
 576         /* hash it for later reverse mapping */
 577         hash = TD_HASH_FUNC (td->td_dma);
 578         td->td_hash = ohci->td_hash [hash];
 579         ohci->td_hash [hash] = td;
 580
 581         /* HC might read the TD (or cachelines) right away ... */
 582         wmb ();
 583         td->ed->hwTailP = td->hwNextTD;
 584 }
 585
 586 /*-------------------------------------------------------------------------*/
 587
 588 /* Prepare all TDs of a transfer, and queue them onto the ED.
 589  * Caller guarantees HC is active.
 590  * Usually the ED is already on the schedule, so TDs might be
 591  * processed as soon as they're queued.
 592  */
 593 static void td_submit_urb (
 594         struct ohci_hcd *ohci,
 595         struct urb      *urb
 596 ) {
 597         struct urb_priv *urb_priv = urb->hcpriv;
 598         struct device *dev = ohci_to_hcd(ohci)->self.controller;
 599         dma_addr_t      data;
 600         int             data_len = urb->transfer_buffer_length;
 601         int             cnt = 0;
 602         u32             info = 0;
 603         int             is_out = usb_pipeout (urb->pipe);
 604         int             periodic = 0;
 605
 606         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 607          * use the device toggle bits for resetting, and rely on the fact
 608          * that resetting toggle is meaningless if the endpoint is active.
 609          */
 610         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 611                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 612                         is_out, 1);
 613                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 614         }
 615
 616         list_add (&urb_priv->pending, &ohci->pending);
 617
 618         if (data_len)
 619                 data = urb->transfer_dma;
 620         else
 621                 data = 0;
 622
 623         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 624          * using TD_CC_GET, as well as by seeing them on the done list.
 625          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 626          */
 627         switch (urb_priv->ed->type) {
 628
 629         /* Bulk and interrupt are identical except for where in the schedule
 630          * their EDs live.
 631          */
 632         case PIPE_INTERRUPT:
 633                 /* ... and periodic urbs have extra accounting */
 634                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 635                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 636                 /* FALLTHROUGH */
 637         case PIPE_BULK:
 638                 info = is_out
 639                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 640                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 641                 /* TDs _could_ transfer up to 8K each */
 642                 while (data_len > 4096) {
 643                         td_fill (ohci, info, data, 4096, urb, cnt);
 644                         data += 4096;
 645                         data_len -= 4096;
 646                         cnt++;
 647                 }
 648                 /* maybe avoid ED halt on final TD short read */
 649                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 650                         info |= TD_R;
 651                 td_fill (ohci, info, data, data_len, urb, cnt);
 652                 cnt++;
 653                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 654                                 && cnt < urb_priv->length) {
 655                         td_fill (ohci, info, 0, 0, urb, cnt);
 656                         cnt++;
 657                 }
 658                 /* maybe kickstart bulk list */
 659                 if (urb_priv->ed->type == PIPE_BULK) {
 660                         wmb ();
 661                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 662                 }
 663                 break;
 664
 665         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 666          * any DATA phase works normally, and the STATUS ack is special.
 667          */
 668         case PIPE_CONTROL:
 669                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 670                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 671                 if (data_len > 0) {
 672                         info = TD_CC | TD_R | TD_T_DATA1;
 673                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 674                         /* NOTE:  mishandles transfers >8K, some >4K */
 675                         td_fill (ohci, info, data, data_len, urb, cnt++);
 676                 }
 677                 info = (is_out || data_len == 0)
 678                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 679                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 680                 td_fill (ohci, info, data, 0, urb, cnt++);
 681                 /* maybe kickstart control list */
 682                 wmb ();
 683                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 684                 break;
 685
 686         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 687          * Each TD could handle multiple consecutive frames (interval 1);
 688          * we could often reduce the number of TDs here.
 689          */
 690         case PIPE_ISOCHRONOUS:
 691                 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
 692                                 cnt++) {
 693                         int     frame = urb->start_frame;
 694
 695                         // FIXME scheduling should handle frame counter
 696                         // roll-around ... exotic case (and OHCI has
 697                         // a 2^16 iso range, vs other HCs max of 2^10)
 698                         frame += cnt * urb->interval;
 699                         frame &= 0xffff;
 700                         td_fill (ohci, TD_CC | TD_ISO | frame,
 701                                 data + urb->iso_frame_desc [cnt].offset,
 702                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 703                 }
 704                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
 705                         if (quirk_amdiso(ohci))
 706                                 usb_amd_quirk_pll_disable();
 707                         if (quirk_amdprefetch(ohci))
 708                                 sb800_prefetch(dev, 1);
 709                 }
 710                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 711                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 712                 break;
 713         }
 714
 715         /* start periodic dma if needed */
 716         if (periodic) {
 717                 wmb ();
 718                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 719                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 720         }
 721
 722         // ASSERT (urb_priv->length == cnt);
 723 }
 724
 725 /*-------------------------------------------------------------------------*
 726  * Done List handling functions
 727  *-------------------------------------------------------------------------*/
 728
 729 /* calculate transfer length/status and update the urb */
 730 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 731 {
 732         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 733         int     cc = 0;
 734         int     status = -EINPROGRESS;
 735
 736         list_del (&td->td_list);
 737
 738         /* ISO ... drivers see per-TD length/status */
 739         if (tdINFO & TD_ISO) {
 740                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
 741                 int     dlen = 0;
 742
 743                 /* NOTE:  assumes FC in tdINFO == 0, and that
 744                  * only the first of 0..MAXPSW psws is used.
 745                  */
 746
 747                 cc = (tdPSW >> 12) & 0xF;
 748                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 749                         return status;
 750
 751                 if (usb_pipeout (urb->pipe))
 752                         dlen = urb->iso_frame_desc [td->index].length;
 753                 else {
 754                         /* short reads are always OK for ISO */
 755                         if (cc == TD_DATAUNDERRUN)
 756                                 cc = TD_CC_NOERROR;
 757                         dlen = tdPSW & 0x3ff;
 758                 }
 759                 urb->actual_length += dlen;
 760                 urb->iso_frame_desc [td->index].actual_length = dlen;
 761                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 762
 763                 if (cc != TD_CC_NOERROR)
 764                         ohci_dbg(ohci,
 765                                 "urb %p iso td %p (%d) len %d cc %d\n",
 766                                 urb, td, 1 + td->index, dlen, cc);
 767
 768         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 769          * except that "setup" bytes aren't counted and "short" transfers
 770          * might not be reported as errors.
 771          */
 772         } else {
 773                 int     type = usb_pipetype (urb->pipe);
 774                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 775
 776                 cc = TD_CC_GET (tdINFO);
 777
 778                 /* update packet status if needed (short is normally ok) */
 779                 if (cc == TD_DATAUNDERRUN
 780                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 781                         cc = TD_CC_NOERROR;
 782                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 783                         status = cc_to_error[cc];
 784
 785                 /* count all non-empty packets except control SETUP packet */
 786                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 787                         if (td->hwCBP == 0)
 788                                 urb->actual_length += tdBE - td->data_dma + 1;
 789                         else
 790                                 urb->actual_length +=
 791                                           hc32_to_cpup (ohci, &td->hwCBP)
 792                                         - td->data_dma;
 793                 }
 794
 795                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 796                         ohci_dbg(ohci,
 797                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 798                                 urb, td, 1 + td->index, cc,
 799                                 urb->actual_length,
 800                                 urb->transfer_buffer_length);
 801         }
 802         return status;
 803 }
 804
 805 /*-------------------------------------------------------------------------*/
 806
 807 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
 808 {
 809         struct urb              *urb = td->urb;
 810         urb_priv_t              *urb_priv = urb->hcpriv;
 811         struct ed               *ed = td->ed;
 812         struct list_head        *tmp = td->td_list.next;
 813         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 814
 815         /* clear ed halt; this is the td that caused it, but keep it inactive
 816          * until its urb->complete() has a chance to clean up.
 817          */
 818         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 819         wmb ();
 820         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 821
 822         /* Get rid of all later tds from this urb.  We don't have
 823          * to be careful: no errors and nothing was transferred.
 824          * Also patch the ed so it looks as if those tds completed normally.
 825          */
 826         while (tmp != &ed->td_list) {
 827                 struct td       *next;
 828
 829                 next = list_entry (tmp, struct td, td_list);
 830                 tmp = next->td_list.next;
 831
 832                 if (next->urb != urb)
 833                         break;
 834
 835                 /* NOTE: if multi-td control DATA segments get supported,
 836                  * this urb had one of them, this td wasn't the last td
 837                  * in that segment (TD_R clear), this ed halted because
 838                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 839                  * then we need to leave the control STATUS packet queued
 840                  * and clear ED_SKIP.
 841                  */
 842
 843                 list_del(&next->td_list);
 844                 urb_priv->td_cnt++;
 845                 ed->hwHeadP = next->hwNextTD | toggle;
 846         }
 847
 848         /* help for troubleshooting:  report anything that
 849          * looks odd ... that doesn't include protocol stalls
 850          * (or maybe some other things)
 851          */
 852         switch (cc) {
 853         case TD_DATAUNDERRUN:
 854                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 855                         break;
 856                 /* fallthrough */
 857         case TD_CC_STALL:
 858                 if (usb_pipecontrol (urb->pipe))
 859                         break;
 860                 /* fallthrough */
 861         default:
 862                 ohci_dbg (ohci,
 863                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 864                         urb, urb->dev->devpath,
 865                         usb_pipeendpoint (urb->pipe),
 866                         usb_pipein (urb->pipe) ? "in" : "out",
 867                         hc32_to_cpu (ohci, td->hwINFO),
 868                         cc, cc_to_error [cc]);
 869         }
 870 }
 871
 872 /* replies to the request have to be on a FIFO basis so
 873  * we unreverse the hc-reversed done-list
 874  */
 875 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 876 {
 877         u32             td_dma;
 878         struct td       *td_rev = NULL;
 879         struct td       *td = NULL;
 880
 881         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 882         ohci->hcca->done_head = 0;
 883         wmb();
 884
 885         /* get TD from hc's singly linked list, and
 886          * prepend to ours.  ed->td_list changes later.
 887          */
 888         while (td_dma) {
 889                 int             cc;
 890
 891                 td = dma_to_td (ohci, td_dma);
 892                 if (!td) {
 893                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 894                         break;
 895                 }
 896
 897                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 898                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 899
 900                 /* Non-iso endpoints can halt on error; un-halt,
 901                  * and dequeue any other TDs from this urb.
 902                  * No other TD could have caused the halt.
 903                  */
 904                 if (cc != TD_CC_NOERROR
 905                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 906                         ed_halted(ohci, td, cc);
 907
 908                 td->next_dl_td = td_rev;
 909                 td_rev = td;
 910                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 911         }
 912         return td_rev;
 913 }
 914
 915 /*-------------------------------------------------------------------------*/
 916
 917 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 918 static void
 919 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 920 {
 921         struct ed       *ed, **last;
 922
 923 rescan_all:
 924         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 925                 struct list_head        *entry, *tmp;
 926                 int                     completed, modified;
 927                 __hc32                  *prev;
 928
 929                 /* only take off EDs that the HC isn't using, accounting for
 930                  * frame counter wraps and EDs with partially retired TDs
 931                  */
 932                 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
 933                         if (tick_before (tick, ed->tick)) {
 934 skip_ed:
 935                                 last = &ed->ed_next;
 936                                 continue;
 937                         }
 938
 939                         if (!list_empty (&ed->td_list)) {
 940                                 struct td       *td;
 941                                 u32             head;
 942
 943                                 td = list_entry (ed->td_list.next, struct td,
 944                                                         td_list);
 945                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 946                                                                 TD_MASK;
 947
 948                                 /* INTR_WDH may need to clean up first */
 949                                 if (td->td_dma != head) {
 950                                         if (ed == ohci->ed_to_check)
 951                                                 ohci->ed_to_check = NULL;
 952                                         else
 953                                                 goto skip_ed;
 954                                 }
 955                         }
 956                 }
 957
 958                 /* reentrancy:  if we drop the schedule lock, someone might
 959                  * have modified this list.  normally it's just prepending
 960                  * entries (which we'd ignore), but paranoia won't hurt.
 961                  */
 962                 *last = ed->ed_next;
 963                 ed->ed_next = NULL;
 964                 modified = 0;
 965
 966                 /* unlink urbs as requested, but rescan the list after
 967                  * we call a completion since it might have unlinked
 968                  * another (earlier) urb
 969                  *
 970                  * When we get here, the HC doesn't see this ed.  But it
 971                  * must not be rescheduled until all completed URBs have
 972                  * been given back to the driver.
 973                  */
 974 rescan_this:
 975                 completed = 0;
 976                 prev = &ed->hwHeadP;
 977                 list_for_each_safe (entry, tmp, &ed->td_list) {
 978                         struct td       *td;
 979                         struct urb      *urb;
 980                         urb_priv_t      *urb_priv;
 981                         __hc32          savebits;
 982                         u32             tdINFO;
 983
 984                         td = list_entry (entry, struct td, td_list);
 985                         urb = td->urb;
 986                         urb_priv = td->urb->hcpriv;
 987
 988                         if (!urb->unlinked) {
 989                                 prev = &td->hwNextTD;
 990                                 continue;
 991                         }
 992
 993                         /* patch pointer hc uses */
 994                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 995                         *prev = td->hwNextTD | savebits;
 996
 997                         /* If this was unlinked, the TD may not have been
 998                          * retired ... so manually save the data toggle.
 999                          * The controller ignores the value we save for
1000                          * control and ISO endpoints.
1001                          */
1002                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
1003                         if ((tdINFO & TD_T) == TD_T_DATA0)
1004                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
1005                         else if ((tdINFO & TD_T) == TD_T_DATA1)
1006                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1007
1008                         /* HC may have partly processed this TD */
1009                         td_done (ohci, urb, td);
1010                         urb_priv->td_cnt++;
1011
1012                         /* if URB is done, clean up */
1013                         if (urb_priv->td_cnt >= urb_priv->length) {
1014                                 modified = completed = 1;
1015                                 finish_urb(ohci, urb, 0);
1016                         }
1017                 }
1018                 if (completed && !list_empty (&ed->td_list))
1019                         goto rescan_this;
1020
1021                 /* ED's now officially unlinked, hc doesn't see */
1022                 ed->state = ED_IDLE;
1023                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1024                         ohci->eds_scheduled--;
1025                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1026                 ed->hwNextED = 0;
1027                 wmb ();
1028                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1029
1030                 /* but if there's work queued, reschedule */
1031                 if (!list_empty (&ed->td_list)) {
1032                         if (ohci->rh_state == OHCI_RH_RUNNING)
1033                                 ed_schedule (ohci, ed);
1034                 }
1035
1036                 if (modified)
1037                         goto rescan_all;
1038         }
1039
1040         /* maybe reenable control and bulk lists */
1041         if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1042                 u32     command = 0, control = 0;
1043
1044                 if (ohci->ed_controltail) {
1045                         command |= OHCI_CLF;
1046                         if (quirk_zfmicro(ohci))
1047                                 mdelay(1);
1048                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1049                                 control |= OHCI_CTRL_CLE;
1050                                 ohci_writel (ohci, 0,
1051                                         &ohci->regs->ed_controlcurrent);
1052                         }
1053                 }
1054                 if (ohci->ed_bulktail) {
1055                         command |= OHCI_BLF;
1056                         if (quirk_zfmicro(ohci))
1057                                 mdelay(1);
1058                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1059                                 control |= OHCI_CTRL_BLE;
1060                                 ohci_writel (ohci, 0,
1061                                         &ohci->regs->ed_bulkcurrent);
1062                         }
1063                 }
1064
1065                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1066                 if (control) {
1067                         ohci->hc_control |= control;
1068                         if (quirk_zfmicro(ohci))
1069                                 mdelay(1);
1070                         ohci_writel (ohci, ohci->hc_control,
1071                                         &ohci->regs->control);
1072                 }
1073                 if (command) {
1074                         if (quirk_zfmicro(ohci))
1075                                 mdelay(1);
1076                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1077                 }
1078         }
1079 }
1080
1081
1082
1083 /*-------------------------------------------------------------------------*/
1084
1085 /*
1086  * Used to take back a TD from the host controller. This would normally be
1087  * called from within dl_done_list, however it may be called directly if the
1088  * HC no longer sees the TD and it has not appeared on the donelist (after
1089  * two frames).  This bug has been observed on ZF Micro systems.
1090  */
1091 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1092 {
1093         struct urb      *urb = td->urb;
1094         urb_priv_t      *urb_priv = urb->hcpriv;
1095         struct ed       *ed = td->ed;
1096         int             status;
1097
1098         /* update URB's length and status from TD */
1099         status = td_done(ohci, urb, td);
1100         urb_priv->td_cnt++;
1101
1102         /* If all this urb's TDs are done, call complete() */
1103         if (urb_priv->td_cnt >= urb_priv->length)
1104                 finish_urb(ohci, urb, status);
1105
1106         /* clean schedule:  unlink EDs that are no longer busy */
1107         if (list_empty(&ed->td_list)) {
1108                 if (ed->state == ED_OPER)
1109                         start_ed_unlink(ohci, ed);
1110
1111         /* ... reenabling halted EDs only after fault cleanup */
1112         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1113                         == cpu_to_hc32(ohci, ED_SKIP)) {
1114                 td = list_entry(ed->td_list.next, struct td, td_list);
1115                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1116                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1117                         /* ... hc may need waking-up */
1118                         switch (ed->type) {
1119                         case PIPE_CONTROL:
1120                                 ohci_writel(ohci, OHCI_CLF,
1121                                                 &ohci->regs->cmdstatus);
1122                                 break;
1123                         case PIPE_BULK:
1124                                 ohci_writel(ohci, OHCI_BLF,
1125                                                 &ohci->regs->cmdstatus);
1126                                 break;
1127                         }
1128                 }
1129         }
1130 }
1131
1132 /*
1133  * Process normal completions (error or success) and clean the schedules.
1134  *
1135  * This is the main path for handing urbs back to drivers.  The only other
1136  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1137  * instead of scanning the (re-reversed) donelist as this does.  There's
1138  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1139  * with TDs that appear to be orphaned are directly reclaimed.
1140  */
1141 static void
1142 dl_done_list (struct ohci_hcd *ohci)
1143 {
1144         struct td       *td = dl_reverse_done_list (ohci);
1145
1146         while (td) {
1147                 struct td       *td_next = td->next_dl_td;
1148                 struct ed       *ed = td->ed;
1149
1150                 /*
1151                  * Some OHCI controllers (NVIDIA for sure, maybe others)
1152                  * occasionally forget to add TDs to the done queue.  Since
1153                  * TDs for a given endpoint are always processed in order,
1154                  * if we find a TD on the donelist then all of its
1155                  * predecessors must be finished as well.
1156                  */
1157                 for (;;) {
1158                         struct td       *td2;
1159
1160                         td2 = list_first_entry(&ed->td_list, struct td,
1161                                         td_list);
1162                         if (td2 == td)
1163                                 break;
1164                         takeback_td(ohci, td2);
1165                 }
1166
1167                 takeback_td(ohci, td);
1168                 td = td_next;
1169         }
1170 }