2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/config.h>
26 #ifdef CONFIG_USB_DEBUG
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/ioport.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/smp_lock.h>
40 #include <linux/errno.h>
41 #include <linux/unistd.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/debugfs.h>
46 #include <linux/dmapool.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/usb.h>
49 #include <linux/bitops.h>
51 #include <asm/uaccess.h>
54 #include <asm/system.h>
56 #include "../core/hcd.h"
62 #define DRIVER_VERSION "v2.3"
63 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
64 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
66 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
69 * debug = 0, no debugging messages
70 * debug = 1, dump failed URB's except for stalls
71 * debug = 2, dump all failed URB's (including stalls)
72 * show all queues in /debug/uhci/[pci_addr]
73 * debug = 3, show all TD's in URB's when dumping
80 module_param(debug, int, S_IRUGO | S_IWUSR);
81 MODULE_PARM_DESC(debug, "Debug level");
83 #define ERRBUF_LEN (32 * 1024)
85 static kmem_cache_t *uhci_up_cachep; /* urb_priv */
87 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
88 static void wakeup_rh(struct uhci_hcd *uhci);
89 static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
91 /* If a transfer is still active after this much time, turn off FSBR */
92 #define IDLE_TIMEOUT msecs_to_jiffies(50)
93 #define FSBR_DELAY msecs_to_jiffies(50)
95 /* When we timeout an idle transfer for FSBR, we'll switch it over to */
96 /* depth first traversal. We'll do it in groups of this number of TD's */
97 /* to make sure it doesn't hog all of the bandwidth */
98 #define DEPTH_INTERVAL 5
100 #include "uhci-debug.c"
102 #include "uhci-hub.c"
105 * Make sure the controller is completely inactive, unable to
106 * generate interrupts or do DMA.
108 static void reset_hc(struct uhci_hcd *uhci)
112 /* Turn off PIRQ enable and SMI enable. (This also turns off the
113 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
115 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
118 /* Reset the HC - this will force us to get a
119 * new notification of any already connected
120 * ports due to the virtual disconnect that it
123 outw(USBCMD_HCRESET, uhci->io_addr + USBCMD);
126 if (inw(uhci->io_addr + USBCMD) & USBCMD_HCRESET)
127 dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n");
129 /* Just to be safe, disable interrupt requests and
130 * make sure the controller is stopped.
132 outw(0, uhci->io_addr + USBINTR);
133 outw(0, uhci->io_addr + USBCMD);
135 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
136 * bits in the port status and control registers.
137 * We have to clear them by hand.
139 for (port = 0; port < uhci->rh_numports; ++port)
140 outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));
142 uhci->port_c_suspend = uhci->suspended_ports =
143 uhci->resuming_ports = 0;
144 uhci->rh_state = UHCI_RH_RESET;
145 uhci->is_stopped = UHCI_IS_STOPPED;
146 uhci_to_hcd(uhci)->state = HC_STATE_HALT;
147 uhci_to_hcd(uhci)->poll_rh = 0;
151 * Last rites for a defunct/nonfunctional controller
152 * or one we don't want to use any more.
154 static void hc_died(struct uhci_hcd *uhci)
157 uhci->hc_inaccessible = 1;
161 * Initialize a controller that was newly discovered or has just been
162 * resumed. In either case we can't be sure of its previous state.
164 static void check_and_reset_hc(struct uhci_hcd *uhci)
167 unsigned int cmd, intr;
170 * When restarting a suspended controller, we expect all the
171 * settings to be the same as we left them:
173 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
174 * Controller is stopped and configured with EGSM set;
175 * No interrupts enabled except possibly Resume Detect.
177 * If any of these conditions are violated we do a complete reset.
179 pci_read_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, &legsup);
180 if (legsup & ~(USBLEGSUP_RO | USBLEGSUP_RWC)) {
181 dev_dbg(uhci_dev(uhci), "%s: legsup = 0x%04x\n",
182 __FUNCTION__, legsup);
186 cmd = inw(uhci->io_addr + USBCMD);
187 if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) {
188 dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n",
193 intr = inw(uhci->io_addr + USBINTR);
194 if (intr & (~USBINTR_RESUME)) {
195 dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n",
202 dev_dbg(uhci_dev(uhci), "Performing full reset\n");
207 * Store the basic register settings needed by the controller.
209 static void configure_hc(struct uhci_hcd *uhci)
211 /* Set the frame length to the default: 1 ms exactly */
212 outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);
214 /* Store the frame list base address */
215 outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);
217 /* Set the current frame number */
218 outw(uhci->frame_number, uhci->io_addr + USBFRNUM);
220 /* Mark controller as running before we enable interrupts */
221 uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
225 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
230 static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
234 switch (to_pci_dev(uhci_dev(uhci))->vendor) {
238 case PCI_VENDOR_ID_GENESYS:
239 /* Genesys Logic's GL880S controllers don't generate
240 * resume-detect interrupts.
244 case PCI_VENDOR_ID_INTEL:
245 /* Some of Intel's USB controllers have a bug that causes
246 * resume-detect interrupts if any port has an over-current
247 * condition. To make matters worse, some motherboards
248 * hardwire unused USB ports' over-current inputs active!
249 * To prevent problems, we will not enable resume-detect
250 * interrupts if any ports are OC.
252 for (port = 0; port < uhci->rh_numports; ++port) {
253 if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
262 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
263 __releases(uhci->lock)
264 __acquires(uhci->lock)
269 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
270 dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__,
271 (auto_stop ? " (auto-stop)" : ""));
273 /* If we get a suspend request when we're already auto-stopped
274 * then there's nothing to do.
276 if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) {
277 uhci->rh_state = new_state;
281 /* Enable resume-detect interrupts if they work.
282 * Then enter Global Suspend mode, still configured.
284 uhci->working_RD = 1;
285 int_enable = USBINTR_RESUME;
286 if (resume_detect_interrupts_are_broken(uhci)) {
287 uhci->working_RD = int_enable = 0;
289 outw(int_enable, uhci->io_addr + USBINTR);
290 outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD);
294 /* If we're auto-stopping then no devices have been attached
295 * for a while, so there shouldn't be any active URBs and the
296 * controller should stop after a few microseconds. Otherwise
297 * we will give the controller one frame to stop.
299 if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) {
300 uhci->rh_state = UHCI_RH_SUSPENDING;
301 spin_unlock_irq(&uhci->lock);
303 spin_lock_irq(&uhci->lock);
304 if (uhci->hc_inaccessible) /* Died */
307 if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH))
308 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
310 uhci_get_current_frame_number(uhci);
313 uhci->rh_state = new_state;
314 uhci->is_stopped = UHCI_IS_STOPPED;
315 uhci_to_hcd(uhci)->poll_rh = !int_enable;
317 uhci_scan_schedule(uhci, NULL);
320 static void start_rh(struct uhci_hcd *uhci)
322 uhci->is_stopped = 0;
325 /* Mark it configured and running with a 64-byte max packet.
326 * All interrupts are enabled, even though RESUME won't do anything.
328 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD);
329 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
330 uhci->io_addr + USBINTR);
332 uhci->rh_state = UHCI_RH_RUNNING;
333 uhci_to_hcd(uhci)->poll_rh = 1;
336 static void wakeup_rh(struct uhci_hcd *uhci)
337 __releases(uhci->lock)
338 __acquires(uhci->lock)
340 dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__,
341 uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
342 " (auto-start)" : "");
344 /* If we are auto-stopped then no devices are attached so there's
345 * no need for wakeup signals. Otherwise we send Global Resume
348 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
349 uhci->rh_state = UHCI_RH_RESUMING;
350 outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF,
351 uhci->io_addr + USBCMD);
352 spin_unlock_irq(&uhci->lock);
354 spin_lock_irq(&uhci->lock);
355 if (uhci->hc_inaccessible) /* Died */
358 /* End Global Resume and wait for EOP to be sent */
359 outw(USBCMD_CF, uhci->io_addr + USBCMD);
362 if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR)
363 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
368 /* Restart root hub polling */
369 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
372 static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
374 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
375 unsigned short status;
379 * Read the interrupt status, and write it back to clear the
380 * interrupt cause. Contrary to the UHCI specification, the
381 * "HC Halted" status bit is persistent: it is RO, not R/WC.
383 status = inw(uhci->io_addr + USBSTS);
384 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
386 outw(status, uhci->io_addr + USBSTS); /* Clear it */
388 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
389 if (status & USBSTS_HSE)
390 dev_err(uhci_dev(uhci), "host system error, "
392 if (status & USBSTS_HCPE)
393 dev_err(uhci_dev(uhci), "host controller process "
394 "error, something bad happened!\n");
395 if (status & USBSTS_HCH) {
396 spin_lock_irqsave(&uhci->lock, flags);
397 if (uhci->rh_state >= UHCI_RH_RUNNING) {
398 dev_err(uhci_dev(uhci),
399 "host controller halted, "
403 /* Force a callback in case there are
405 mod_timer(&hcd->rh_timer, jiffies);
407 spin_unlock_irqrestore(&uhci->lock, flags);
411 if (status & USBSTS_RD)
412 usb_hcd_poll_rh_status(hcd);
414 spin_lock_irqsave(&uhci->lock, flags);
415 uhci_scan_schedule(uhci, regs);
416 spin_unlock_irqrestore(&uhci->lock, flags);
423 * Store the current frame number in uhci->frame_number if the controller
426 static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
428 if (!uhci->is_stopped)
429 uhci->frame_number = inw(uhci->io_addr + USBFRNUM);
433 * De-allocate all resources
435 static void release_uhci(struct uhci_hcd *uhci)
439 for (i = 0; i < UHCI_NUM_SKELQH; i++)
440 uhci_free_qh(uhci, uhci->skelqh[i]);
442 uhci_free_td(uhci, uhci->term_td);
444 dma_pool_destroy(uhci->qh_pool);
446 dma_pool_destroy(uhci->td_pool);
448 kfree(uhci->frame_cpu);
450 dma_free_coherent(uhci_dev(uhci),
451 UHCI_NUMFRAMES * sizeof(*uhci->frame),
452 uhci->frame, uhci->frame_dma_handle);
454 debugfs_remove(uhci->dentry);
457 static int uhci_reset(struct usb_hcd *hcd)
459 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
460 unsigned io_size = (unsigned) hcd->rsrc_len;
463 uhci->io_addr = (unsigned long) hcd->rsrc_start;
465 /* The UHCI spec says devices must have 2 ports, and goes on to say
466 * they may have more but gives no way to determine how many there
467 * are. However according to the UHCI spec, Bit 7 of the port
468 * status and control register is always set to 1. So we try to
469 * use this to our advantage. Another common failure mode when
470 * a nonexistent register is addressed is to return all ones, so
471 * we test for that also.
473 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
474 unsigned int portstatus;
476 portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2));
477 if (!(portstatus & 0x0080) || portstatus == 0xffff)
481 dev_info(uhci_dev(uhci), "detected %d ports\n", port);
483 /* Anything greater than 7 is weird so we'll ignore it. */
484 if (port > UHCI_RH_MAXCHILD) {
485 dev_info(uhci_dev(uhci), "port count misdetected? "
486 "forcing to 2 ports\n");
489 uhci->rh_numports = port;
491 /* Kick BIOS off this hardware and reset if the controller
492 * isn't already safely quiescent.
494 check_and_reset_hc(uhci);
498 /* Make sure the controller is quiescent and that we're not using it
499 * any more. This is mainly for the benefit of programs which, like kexec,
500 * expect the hardware to be idle: not doing DMA or generating IRQs.
502 * This routine may be called in a damaged or failing kernel. Hence we
503 * do not acquire the spinlock before shutting down the controller.
505 static void uhci_shutdown(struct pci_dev *pdev)
507 struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev);
509 hc_died(hcd_to_uhci(hcd));
513 * Allocate a frame list, and then setup the skeleton
515 * The hardware doesn't really know any difference
516 * in the queues, but the order does matter for the
517 * protocols higher up. The order is:
519 * - any isochronous events handled before any
520 * of the queues. We don't do that here, because
521 * we'll create the actual TD entries on demand.
522 * - The first queue is the interrupt queue.
523 * - The second queue is the control queue, split into low- and full-speed
524 * - The third queue is bulk queue.
525 * - The fourth queue is the bandwidth reclamation queue, which loops back
526 * to the full-speed control queue.
528 static int uhci_start(struct usb_hcd *hcd)
530 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
533 struct dentry *dentry;
535 hcd->uses_new_polling = 1;
536 if (pci_find_capability(to_pci_dev(uhci_dev(uhci)), PCI_CAP_ID_PM))
537 hcd->can_wakeup = 1; /* Assume it supports PME# */
539 dentry = debugfs_create_file(hcd->self.bus_name,
540 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci,
541 &uhci_debug_operations);
543 dev_err(uhci_dev(uhci),
544 "couldn't create uhci debugfs entry\n");
546 goto err_create_debug_entry;
548 uhci->dentry = dentry;
551 uhci->fsbrtimeout = 0;
553 spin_lock_init(&uhci->lock);
554 INIT_LIST_HEAD(&uhci->qh_remove_list);
556 INIT_LIST_HEAD(&uhci->td_remove_list);
558 INIT_LIST_HEAD(&uhci->urb_remove_list);
560 INIT_LIST_HEAD(&uhci->urb_list);
562 INIT_LIST_HEAD(&uhci->complete_list);
564 init_waitqueue_head(&uhci->waitqh);
566 uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
567 UHCI_NUMFRAMES * sizeof(*uhci->frame),
568 &uhci->frame_dma_handle, 0);
570 dev_err(uhci_dev(uhci), "unable to allocate "
571 "consistent memory for frame list\n");
572 goto err_alloc_frame;
574 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
576 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
578 if (!uhci->frame_cpu) {
579 dev_err(uhci_dev(uhci), "unable to allocate "
580 "memory for frame pointers\n");
581 goto err_alloc_frame_cpu;
584 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
585 sizeof(struct uhci_td), 16, 0);
586 if (!uhci->td_pool) {
587 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
588 goto err_create_td_pool;
591 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
592 sizeof(struct uhci_qh), 16, 0);
593 if (!uhci->qh_pool) {
594 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
595 goto err_create_qh_pool;
598 uhci->term_td = uhci_alloc_td(uhci);
599 if (!uhci->term_td) {
600 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
601 goto err_alloc_term_td;
604 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
605 uhci->skelqh[i] = uhci_alloc_qh(uhci);
606 if (!uhci->skelqh[i]) {
607 dev_err(uhci_dev(uhci), "unable to allocate QH\n");
608 goto err_alloc_skelqh;
613 * 8 Interrupt queues; link all higher int queues to int1,
614 * then link int1 to control and control to bulk
616 uhci->skel_int128_qh->link =
617 uhci->skel_int64_qh->link =
618 uhci->skel_int32_qh->link =
619 uhci->skel_int16_qh->link =
620 uhci->skel_int8_qh->link =
621 uhci->skel_int4_qh->link =
622 uhci->skel_int2_qh->link =
623 cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH;
624 uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH;
626 uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
627 uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH;
628 uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH;
630 /* This dummy TD is to work around a bug in Intel PIIX controllers */
631 uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) |
632 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
633 uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
635 uhci->skel_term_qh->link = UHCI_PTR_TERM;
636 uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
639 * Fill the frame list: make all entries point to the proper
642 * The interrupt queues will be interleaved as evenly as possible.
643 * There's not much to be done about period-1 interrupts; they have
644 * to occur in every frame. But we can schedule period-2 interrupts
645 * in odd-numbered frames, period-4 interrupts in frames congruent
646 * to 2 (mod 4), and so on. This way each frame only has two
647 * interrupt QHs, which will help spread out bandwidth utilization.
649 for (i = 0; i < UHCI_NUMFRAMES; i++) {
653 * ffs (Find First bit Set) does exactly what we need:
654 * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6],
655 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc.
656 * ffs > 6 => not on any high-period queue, so use
657 * skel_int1_qh = skelqh[7].
658 * Add UHCI_NUMFRAMES to insure at least one bit is set.
660 irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES);
664 /* Only place we don't use the frame list routines */
665 uhci->frame[i] = UHCI_PTR_QH |
666 cpu_to_le32(uhci->skelqh[irq]->dma_handle);
670 * Some architectures require a full mb() to enforce completion of
671 * the memory writes above before the I/O transfers in configure_hc().
683 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
685 uhci_free_qh(uhci, uhci->skelqh[i]);
688 uhci_free_td(uhci, uhci->term_td);
691 dma_pool_destroy(uhci->qh_pool);
694 dma_pool_destroy(uhci->td_pool);
697 kfree(uhci->frame_cpu);
700 dma_free_coherent(uhci_dev(uhci),
701 UHCI_NUMFRAMES * sizeof(*uhci->frame),
702 uhci->frame, uhci->frame_dma_handle);
705 debugfs_remove(uhci->dentry);
707 err_create_debug_entry:
711 static void uhci_stop(struct usb_hcd *hcd)
713 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
715 spin_lock_irq(&uhci->lock);
716 if (!uhci->hc_inaccessible)
718 uhci_scan_schedule(uhci, NULL);
719 spin_unlock_irq(&uhci->lock);
725 static int uhci_rh_suspend(struct usb_hcd *hcd)
727 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
729 spin_lock_irq(&uhci->lock);
730 if (!uhci->hc_inaccessible) /* Not dead */
731 suspend_rh(uhci, UHCI_RH_SUSPENDED);
732 spin_unlock_irq(&uhci->lock);
736 static int uhci_rh_resume(struct usb_hcd *hcd)
738 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
741 spin_lock_irq(&uhci->lock);
742 if (uhci->hc_inaccessible) {
743 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
744 dev_warn(uhci_dev(uhci), "HC isn't running!\n");
747 /* Otherwise the HC is dead */
750 spin_unlock_irq(&uhci->lock);
754 static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message)
756 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
759 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
761 spin_lock_irq(&uhci->lock);
762 if (uhci->hc_inaccessible) /* Dead or already suspended */
765 #ifndef CONFIG_USB_SUSPEND
766 /* Otherwise this would never happen */
767 suspend_rh(uhci, UHCI_RH_SUSPENDED);
770 if (uhci->rh_state > UHCI_RH_SUSPENDED) {
771 dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
772 hcd->state = HC_STATE_RUNNING;
777 /* All PCI host controllers are required to disable IRQ generation
778 * at the source, so we must turn off PIRQ.
780 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
781 uhci->hc_inaccessible = 1;
784 /* FIXME: Enable non-PME# remote wakeup? */
787 spin_unlock_irq(&uhci->lock);
791 static int uhci_resume(struct usb_hcd *hcd)
793 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
795 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
797 if (uhci->rh_state == UHCI_RH_RESET) /* Dead */
799 spin_lock_irq(&uhci->lock);
801 /* FIXME: Disable non-PME# remote wakeup? */
803 uhci->hc_inaccessible = 0;
805 /* The BIOS may have changed the controller settings during a
806 * system wakeup. Check it and reconfigure to avoid problems.
808 check_and_reset_hc(uhci);
811 #ifndef CONFIG_USB_SUSPEND
812 /* Otherwise this would never happen */
815 if (uhci->rh_state == UHCI_RH_RESET)
816 suspend_rh(uhci, UHCI_RH_SUSPENDED);
818 spin_unlock_irq(&uhci->lock);
820 if (!uhci->working_RD) {
821 /* Suspended root hub needs to be polled */
823 usb_hcd_poll_rh_status(hcd);
829 /* Wait until all the URBs for a particular device/endpoint are gone */
830 static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
831 struct usb_host_endpoint *ep)
833 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
835 wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list));
838 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
840 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
845 /* Minimize latency by avoiding the spinlock */
846 local_irq_save(flags);
847 is_stopped = uhci->is_stopped;
849 frame_number = (is_stopped ? uhci->frame_number :
850 inw(uhci->io_addr + USBFRNUM));
851 local_irq_restore(flags);
855 static const char hcd_name[] = "uhci_hcd";
857 static const struct hc_driver uhci_driver = {
858 .description = hcd_name,
859 .product_desc = "UHCI Host Controller",
860 .hcd_priv_size = sizeof(struct uhci_hcd),
862 /* Generic hardware linkage */
866 /* Basic lifecycle operations */
870 .suspend = uhci_suspend,
871 .resume = uhci_resume,
872 .hub_suspend = uhci_rh_suspend,
873 .hub_resume = uhci_rh_resume,
877 .urb_enqueue = uhci_urb_enqueue,
878 .urb_dequeue = uhci_urb_dequeue,
880 .endpoint_disable = uhci_hcd_endpoint_disable,
881 .get_frame_number = uhci_hcd_get_frame_number,
883 .hub_status_data = uhci_hub_status_data,
884 .hub_control = uhci_hub_control,
887 static const struct pci_device_id uhci_pci_ids[] = { {
888 /* handle any USB UHCI controller */
889 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0),
890 .driver_data = (unsigned long) &uhci_driver,
891 }, { /* end: all zeroes */ }
894 MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
896 static struct pci_driver uhci_pci_driver = {
897 .name = (char *)hcd_name,
898 .id_table = uhci_pci_ids,
900 .probe = usb_hcd_pci_probe,
901 .remove = usb_hcd_pci_remove,
902 .shutdown = uhci_shutdown,
905 .suspend = usb_hcd_pci_suspend,
906 .resume = usb_hcd_pci_resume,
910 static int __init uhci_hcd_init(void)
912 int retval = -ENOMEM;
914 printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n");
920 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
925 uhci_debugfs_root = debugfs_create_dir("uhci", NULL);
926 if (!uhci_debugfs_root)
929 uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
930 sizeof(struct urb_priv), 0, 0, NULL, NULL);
934 retval = pci_register_driver(&uhci_pci_driver);
941 if (kmem_cache_destroy(uhci_up_cachep))
942 warn("not all urb_priv's were freed!");
945 debugfs_remove(uhci_debugfs_root);
955 static void __exit uhci_hcd_cleanup(void)
957 pci_unregister_driver(&uhci_pci_driver);
959 if (kmem_cache_destroy(uhci_up_cachep))
960 warn("not all urb_priv's were freed!");
962 debugfs_remove(uhci_debugfs_root);
966 module_init(uhci_hcd_init);
967 module_exit(uhci_hcd_cleanup);
969 MODULE_AUTHOR(DRIVER_AUTHOR);
970 MODULE_DESCRIPTION(DRIVER_DESC);
971 MODULE_LICENSE("GPL");