2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define XHCI_INIT_VALUE 0x0
27 /* Add verbose debugging later, just print everything for now */
29 void xhci_dbg_regs(struct xhci_hcd *xhci)
33 xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
35 temp = readl(&xhci->cap_regs->hc_capbase);
36 xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
37 &xhci->cap_regs->hc_capbase, temp);
38 xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
39 (unsigned int) HC_LENGTH(temp));
41 xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
42 (unsigned int) HC_VERSION(temp));
45 xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
47 temp = readl(&xhci->cap_regs->run_regs_off);
48 xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
49 &xhci->cap_regs->run_regs_off,
50 (unsigned int) temp & RTSOFF_MASK);
51 xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
53 temp = readl(&xhci->cap_regs->db_off);
54 xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
55 xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
58 static void xhci_print_cap_regs(struct xhci_hcd *xhci)
62 xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
64 temp = readl(&xhci->cap_regs->hc_capbase);
65 xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
67 xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
68 (unsigned int) HC_LENGTH(temp));
69 xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
70 (unsigned int) HC_VERSION(temp));
72 temp = readl(&xhci->cap_regs->hcs_params1);
73 xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
75 xhci_dbg(xhci, " Max device slots: %u\n",
76 (unsigned int) HCS_MAX_SLOTS(temp));
77 xhci_dbg(xhci, " Max interrupters: %u\n",
78 (unsigned int) HCS_MAX_INTRS(temp));
79 xhci_dbg(xhci, " Max ports: %u\n",
80 (unsigned int) HCS_MAX_PORTS(temp));
82 temp = readl(&xhci->cap_regs->hcs_params2);
83 xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
85 xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
86 (unsigned int) HCS_IST(temp));
87 xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
88 (unsigned int) HCS_ERST_MAX(temp));
90 temp = readl(&xhci->cap_regs->hcs_params3);
91 xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
93 xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
94 (unsigned int) HCS_U1_LATENCY(temp));
95 xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
96 (unsigned int) HCS_U2_LATENCY(temp));
98 temp = readl(&xhci->cap_regs->hcc_params);
99 xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
100 xhci_dbg(xhci, " HC generates %s bit addresses\n",
101 HCC_64BIT_ADDR(temp) ? "64" : "32");
103 xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
105 temp = readl(&xhci->cap_regs->run_regs_off);
106 xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
109 static void xhci_print_command_reg(struct xhci_hcd *xhci)
113 temp = readl(&xhci->op_regs->command);
114 xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
115 xhci_dbg(xhci, " HC is %s\n",
116 (temp & CMD_RUN) ? "running" : "being stopped");
117 xhci_dbg(xhci, " HC has %sfinished hard reset\n",
118 (temp & CMD_RESET) ? "not " : "");
119 xhci_dbg(xhci, " Event Interrupts %s\n",
120 (temp & CMD_EIE) ? "enabled " : "disabled");
121 xhci_dbg(xhci, " Host System Error Interrupts %s\n",
122 (temp & CMD_HSEIE) ? "enabled " : "disabled");
123 xhci_dbg(xhci, " HC has %sfinished light reset\n",
124 (temp & CMD_LRESET) ? "not " : "");
127 static void xhci_print_status(struct xhci_hcd *xhci)
131 temp = readl(&xhci->op_regs->status);
132 xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
133 xhci_dbg(xhci, " Event ring is %sempty\n",
134 (temp & STS_EINT) ? "not " : "");
135 xhci_dbg(xhci, " %sHost System Error\n",
136 (temp & STS_FATAL) ? "WARNING: " : "No ");
137 xhci_dbg(xhci, " HC is %s\n",
138 (temp & STS_HALT) ? "halted" : "running");
141 static void xhci_print_op_regs(struct xhci_hcd *xhci)
143 xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
144 xhci_print_command_reg(xhci);
145 xhci_print_status(xhci);
148 static void xhci_print_ports(struct xhci_hcd *xhci)
150 __le32 __iomem *addr;
153 char *names[NUM_PORT_REGS] = {
160 ports = HCS_MAX_PORTS(xhci->hcs_params1);
161 addr = &xhci->op_regs->port_status_base;
162 for (i = 0; i < ports; i++) {
163 for (j = 0; j < NUM_PORT_REGS; ++j) {
164 xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
166 (unsigned int) readl(addr));
172 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
174 struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
179 addr = &ir_set->irq_pending;
181 if (temp == XHCI_INIT_VALUE)
184 xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
186 xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
189 addr = &ir_set->irq_control;
191 xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
194 addr = &ir_set->erst_size;
196 xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
199 addr = &ir_set->rsvd;
201 if (temp != XHCI_INIT_VALUE)
202 xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
203 addr, (unsigned int)temp);
205 addr = &ir_set->erst_base;
206 temp_64 = xhci_read_64(xhci, addr);
207 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
210 addr = &ir_set->erst_dequeue;
211 temp_64 = xhci_read_64(xhci, addr);
212 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
216 void xhci_print_run_regs(struct xhci_hcd *xhci)
221 xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
222 temp = readl(&xhci->run_regs->microframe_index);
223 xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
224 &xhci->run_regs->microframe_index,
225 (unsigned int) temp);
226 for (i = 0; i < 7; ++i) {
227 temp = readl(&xhci->run_regs->rsvd[i]);
228 if (temp != XHCI_INIT_VALUE)
229 xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
230 &xhci->run_regs->rsvd[i],
231 i, (unsigned int) temp);
235 void xhci_print_registers(struct xhci_hcd *xhci)
237 xhci_print_cap_regs(xhci);
238 xhci_print_op_regs(xhci);
239 xhci_print_ports(xhci);
242 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
245 for (i = 0; i < 4; ++i)
246 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
247 i*4, trb->generic.field[i]);
251 * Debug a transfer request block (TRB).
253 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
256 u32 type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK;
259 case TRB_TYPE(TRB_LINK):
260 xhci_dbg(xhci, "Link TRB:\n");
261 xhci_print_trb_offsets(xhci, trb);
263 address = le64_to_cpu(trb->link.segment_ptr);
264 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
266 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
267 GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target)));
268 xhci_dbg(xhci, "Cycle bit = %u\n",
269 le32_to_cpu(trb->link.control) & TRB_CYCLE);
270 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
271 le32_to_cpu(trb->link.control) & LINK_TOGGLE);
272 xhci_dbg(xhci, "No Snoop bit = %u\n",
273 le32_to_cpu(trb->link.control) & TRB_NO_SNOOP);
275 case TRB_TYPE(TRB_TRANSFER):
276 address = le64_to_cpu(trb->trans_event.buffer);
278 * FIXME: look at flags to figure out if it's an address or if
279 * the data is directly in the buffer field.
281 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
283 case TRB_TYPE(TRB_COMPLETION):
284 address = le64_to_cpu(trb->event_cmd.cmd_trb);
285 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
286 xhci_dbg(xhci, "Completion status = %u\n",
287 GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status)));
288 xhci_dbg(xhci, "Flags = 0x%x\n",
289 le32_to_cpu(trb->event_cmd.flags));
292 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
293 (unsigned int) type>>10);
294 xhci_print_trb_offsets(xhci, trb);
300 * Debug a segment with an xHCI ring.
302 * @return The Link TRB of the segment, or NULL if there is no Link TRB
303 * (which is a bug, since all segments must have a Link TRB).
305 * Prints out all TRBs in the segment, even those after the Link TRB.
307 * XXX: should we print out TRBs that the HC owns? As long as we don't
308 * write, that should be fine... We shouldn't expect that the memory pointed to
309 * by the TRB is valid at all. Do we care about ones the HC owns? Probably,
312 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
316 union xhci_trb *trb = seg->trbs;
318 for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
320 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,
321 lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
322 upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
323 le32_to_cpu(trb->link.intr_target),
324 le32_to_cpu(trb->link.control));
325 addr += sizeof(*trb);
329 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
331 xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
333 (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
335 xhci_dbg(xhci, "Ring deq updated %u times\n",
337 xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
339 (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
341 xhci_dbg(xhci, "Ring enq updated %u times\n",
346 * Debugging for an xHCI ring, which is a queue broken into multiple segments.
348 * Print out each segment in the ring. Check that the DMA address in
349 * each link segment actually matches the segment's stored DMA address.
350 * Check that the link end bit is only set at the end of the ring.
351 * Check that the dequeue and enqueue pointers point to real data in this ring
352 * (not some other ring).
354 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
356 /* FIXME: Throw an error if any segment doesn't have a Link TRB */
357 struct xhci_segment *seg;
358 struct xhci_segment *first_seg = ring->first_seg;
359 xhci_debug_segment(xhci, first_seg);
361 if (!ring->enq_updates && !ring->deq_updates) {
362 xhci_dbg(xhci, " Ring has not been updated\n");
365 for (seg = first_seg->next; seg != first_seg; seg = seg->next)
366 xhci_debug_segment(xhci, seg);
369 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
370 unsigned int slot_id, unsigned int ep_index,
371 struct xhci_virt_ep *ep)
374 struct xhci_ring *ring;
376 if (ep->ep_state & EP_HAS_STREAMS) {
377 for (i = 1; i < ep->stream_info->num_streams; i++) {
378 ring = ep->stream_info->stream_rings[i];
379 xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
380 slot_id, ep_index, i);
381 xhci_debug_segment(xhci, ring->deq_seg);
387 xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
389 xhci_debug_segment(xhci, ring->deq_seg);
393 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
395 u64 addr = erst->erst_dma_addr;
397 struct xhci_erst_entry *entry;
399 for (i = 0; i < erst->num_entries; ++i) {
400 entry = &erst->entries[i];
401 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
403 lower_32_bits(le64_to_cpu(entry->seg_addr)),
404 upper_32_bits(le64_to_cpu(entry->seg_addr)),
405 le32_to_cpu(entry->seg_size),
406 le32_to_cpu(entry->rsvd));
407 addr += sizeof(*entry);
411 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
415 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
416 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
418 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
422 /* Print the last 32 bytes for 64-byte contexts */
423 static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
426 for (i = 0; i < 4; ++i) {
427 xhci_dbg(xhci, "@%p (virt) @%08llx "
428 "(dma) %#08llx - rsvd64[%d]\n",
429 &ctx[4 + i], (unsigned long long)dma,
435 char *xhci_get_slot_state(struct xhci_hcd *xhci,
436 struct xhci_container_ctx *ctx)
438 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
440 switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) {
441 case SLOT_STATE_ENABLED:
442 return "enabled/disabled";
443 case SLOT_STATE_DEFAULT:
445 case SLOT_STATE_ADDRESSED:
447 case SLOT_STATE_CONFIGURED:
454 static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
456 /* Fields are 32 bits wide, DMA addresses are in bytes */
457 int field_size = 32 / 8;
460 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
461 dma_addr_t dma = ctx->dma +
462 ((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
463 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
465 xhci_dbg(xhci, "Slot Context:\n");
466 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
468 (unsigned long long)dma, slot_ctx->dev_info);
470 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
471 &slot_ctx->dev_info2,
472 (unsigned long long)dma, slot_ctx->dev_info2);
474 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
476 (unsigned long long)dma, slot_ctx->tt_info);
478 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
479 &slot_ctx->dev_state,
480 (unsigned long long)dma, slot_ctx->dev_state);
482 for (i = 0; i < 4; ++i) {
483 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
484 &slot_ctx->reserved[i], (unsigned long long)dma,
485 slot_ctx->reserved[i], i);
490 dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
493 static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
494 struct xhci_container_ctx *ctx,
495 unsigned int last_ep)
498 int last_ep_ctx = 31;
499 /* Fields are 32 bits wide, DMA addresses are in bytes */
500 int field_size = 32 / 8;
501 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
504 last_ep_ctx = last_ep + 1;
505 for (i = 0; i < last_ep_ctx; ++i) {
506 unsigned int epaddr = xhci_get_endpoint_address(i);
507 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
508 dma_addr_t dma = ctx->dma +
509 ((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
511 xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",
512 usb_endpoint_out(epaddr) ? "OUT" : "IN",
513 epaddr & USB_ENDPOINT_NUMBER_MASK, i);
514 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
516 (unsigned long long)dma, ep_ctx->ep_info);
518 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
520 (unsigned long long)dma, ep_ctx->ep_info2);
522 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
524 (unsigned long long)dma, ep_ctx->deq);
526 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
528 (unsigned long long)dma, ep_ctx->tx_info);
530 for (j = 0; j < 3; ++j) {
531 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
532 &ep_ctx->reserved[j],
533 (unsigned long long)dma,
534 ep_ctx->reserved[j], j);
539 dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
543 void xhci_dbg_ctx(struct xhci_hcd *xhci,
544 struct xhci_container_ctx *ctx,
545 unsigned int last_ep)
548 /* Fields are 32 bits wide, DMA addresses are in bytes */
549 int field_size = 32 / 8;
550 dma_addr_t dma = ctx->dma;
551 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
553 if (ctx->type == XHCI_CTX_TYPE_INPUT) {
554 struct xhci_input_control_ctx *ctrl_ctx =
555 xhci_get_input_control_ctx(xhci, ctx);
557 xhci_warn(xhci, "Could not get input context, bad type.\n");
561 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
562 &ctrl_ctx->drop_flags, (unsigned long long)dma,
563 ctrl_ctx->drop_flags);
565 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
566 &ctrl_ctx->add_flags, (unsigned long long)dma,
567 ctrl_ctx->add_flags);
569 for (i = 0; i < 6; ++i) {
570 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
571 &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
572 ctrl_ctx->rsvd2[i], i);
577 dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
580 xhci_dbg_slot_ctx(xhci, ctx);
581 xhci_dbg_ep_ctx(xhci, ctx, last_ep);
584 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
585 const char *fmt, ...)
587 struct va_format vaf;
593 xhci_dbg(xhci, "%pV\n", &vaf);