drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/gfp.h>
  24 #include <asm/unaligned.h>
  25
  26 #include "xhci.h"
  27 #include "xhci-trace.h"
  28
  29 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  30 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  31                          PORT_RC | PORT_PLC | PORT_PE)
  32
  33 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  34 static u8 usb_bos_descriptor [] = {
  35         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  36         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  37         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  38         0x1,                            /*  __u8 bNumDeviceCaps */
  39         /* First device capability */
  40         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  41         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  42         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  43         0x00,                           /* bmAttributes, LTM off by default */
  44         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  45         0x03,                           /* bFunctionalitySupport,
  46                                            USB 3.0 speed only */
  47         0x00,                           /* bU1DevExitLat, set later. */
  48         0x00, 0x00                      /* __le16 bU2DevExitLat, set later. */
  49 };
  50
  51
  52 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  53                 struct usb_hub_descriptor *desc, int ports)
  54 {
  55         u16 temp;
  56
  57         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  58         desc->bHubContrCurrent = 0;
  59
  60         desc->bNbrPorts = ports;
  61         temp = 0;
  62         /* Bits 1:0 - support per-port power switching, or power always on */
  63         if (HCC_PPC(xhci->hcc_params))
  64                 temp |= HUB_CHAR_INDV_PORT_LPSM;
  65         else
  66                 temp |= HUB_CHAR_NO_LPSM;
  67         /* Bit  2 - root hubs are not part of a compound device */
  68         /* Bits 4:3 - individual port over current protection */
  69         temp |= HUB_CHAR_INDV_PORT_OCPM;
  70         /* Bits 6:5 - no TTs in root ports */
  71         /* Bit  7 - no port indicators */
  72         desc->wHubCharacteristics = cpu_to_le16(temp);
  73 }
  74
  75 /* Fill in the USB 2.0 roothub descriptor */
  76 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  77                 struct usb_hub_descriptor *desc)
  78 {
  79         int ports;
  80         u16 temp;
  81         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  82         u32 portsc;
  83         unsigned int i;
  84
  85         ports = xhci->num_usb2_ports;
  86
  87         xhci_common_hub_descriptor(xhci, desc, ports);
  88         desc->bDescriptorType = USB_DT_HUB;
  89         temp = 1 + (ports / 8);
  90         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  91
  92         /* The Device Removable bits are reported on a byte granularity.
  93          * If the port doesn't exist within that byte, the bit is set to 0.
  94          */
  95         memset(port_removable, 0, sizeof(port_removable));
  96         for (i = 0; i < ports; i++) {
  97                 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  98                 /* If a device is removable, PORTSC reports a 0, same as in the
  99                  * hub descriptor DeviceRemovable bits.
 100                  */
 101                 if (portsc & PORT_DEV_REMOVE)
 102                         /* This math is hairy because bit 0 of DeviceRemovable
 103                          * is reserved, and bit 1 is for port 1, etc.
 104                          */
 105                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 106         }
 107
 108         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 109          * ports on it.  The USB 2.0 specification says that there are two
 110          * variable length fields at the end of the hub descriptor:
 111          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 112          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 113          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 114          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 115          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 116          * set of ports that actually exist.
 117          */
 118         memset(desc->u.hs.DeviceRemovable, 0xff,
 119                         sizeof(desc->u.hs.DeviceRemovable));
 120         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 121                         sizeof(desc->u.hs.PortPwrCtrlMask));
 122
 123         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 124                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 125                                 sizeof(__u8));
 126 }
 127
 128 /* Fill in the USB 3.0 roothub descriptor */
 129 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 130                 struct usb_hub_descriptor *desc)
 131 {
 132         int ports;
 133         u16 port_removable;
 134         u32 portsc;
 135         unsigned int i;
 136
 137         ports = xhci->num_usb3_ports;
 138         xhci_common_hub_descriptor(xhci, desc, ports);
 139         desc->bDescriptorType = USB_DT_SS_HUB;
 140         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 141
 142         /* header decode latency should be zero for roothubs,
 143          * see section 4.23.5.2.
 144          */
 145         desc->u.ss.bHubHdrDecLat = 0;
 146         desc->u.ss.wHubDelay = 0;
 147
 148         port_removable = 0;
 149         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 150         for (i = 0; i < ports; i++) {
 151                 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
 152                 if (portsc & PORT_DEV_REMOVE)
 153                         port_removable |= 1 << (i + 1);
 154         }
 155
 156         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 157 }
 158
 159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 160                 struct usb_hub_descriptor *desc)
 161 {
 162
 163         if (hcd->speed == HCD_USB3)
 164                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 165         else
 166                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 167
 168 }
 169
 170 static unsigned int xhci_port_speed(unsigned int port_status)
 171 {
 172         if (DEV_LOWSPEED(port_status))
 173                 return USB_PORT_STAT_LOW_SPEED;
 174         if (DEV_HIGHSPEED(port_status))
 175                 return USB_PORT_STAT_HIGH_SPEED;
 176         /*
 177          * FIXME: Yes, we should check for full speed, but the core uses that as
 178          * a default in portspeed() in usb/core/hub.c (which is the only place
 179          * USB_PORT_STAT_*_SPEED is used).
 180          */
 181         return 0;
 182 }
 183
 184 /*
 185  * These bits are Read Only (RO) and should be saved and written to the
 186  * registers: 0, 3, 10:13, 30
 187  * connect status, over-current status, port speed, and device removable.
 188  * connect status and port speed are also sticky - meaning they're in
 189  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 190  */
 191 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 192 /*
 193  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 194  * bits 5:8, 9, 14:15, 25:27
 195  * link state, port power, port indicator state, "wake on" enable state
 196  */
 197 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 198 /*
 199  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 200  * bit 4 (port reset)
 201  */
 202 #define XHCI_PORT_RW1S  ((1<<4))
 203 /*
 204  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 205  * bits 1, 17, 18, 19, 20, 21, 22, 23
 206  * port enable/disable, and
 207  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 208  * over-current, reset, link state, and L1 change
 209  */
 210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 211 /*
 212  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 213  * latched in
 214  */
 215 #define XHCI_PORT_RW    ((1<<16))
 216 /*
 217  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 218  * bits 2, 24, 28:31
 219  */
 220 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 221
 222 /*
 223  * Given a port state, this function returns a value that would result in the
 224  * port being in the same state, if the value was written to the port status
 225  * control register.
 226  * Save Read Only (RO) bits and save read/write bits where
 227  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 228  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 229  */
 230 u32 xhci_port_state_to_neutral(u32 state)
 231 {
 232         /* Save read-only status and port state */
 233         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 234 }
 235
 236 /*
 237  * find slot id based on port number.
 238  * @port: The one-based port number from one of the two split roothubs.
 239  */
 240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 241                 u16 port)
 242 {
 243         int slot_id;
 244         int i;
 245         enum usb_device_speed speed;
 246
 247         slot_id = 0;
 248         for (i = 0; i < MAX_HC_SLOTS; i++) {
 249                 if (!xhci->devs[i])
 250                         continue;
 251                 speed = xhci->devs[i]->udev->speed;
 252                 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
 253                                 && xhci->devs[i]->fake_port == port) {
 254                         slot_id = i;
 255                         break;
 256                 }
 257         }
 258
 259         return slot_id;
 260 }
 261
 262 /*
 263  * Stop device
 264  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 265  * to complete.
 266  * suspend will set to 1, if suspend bit need to set in command.
 267  */
 268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 269 {
 270         struct xhci_virt_device *virt_dev;
 271         struct xhci_command *cmd;
 272         unsigned long flags;
 273         int timeleft;
 274         int ret;
 275         int i;
 276
 277         ret = 0;
 278         virt_dev = xhci->devs[slot_id];
 279         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 280         if (!cmd) {
 281                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 282                 return -ENOMEM;
 283         }
 284
 285         spin_lock_irqsave(&xhci->lock, flags);
 286         for (i = LAST_EP_INDEX; i > 0; i--) {
 287                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
 288                         xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
 289         }
 290         cmd->command_trb = xhci->cmd_ring->enqueue;
 291         list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
 292         xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
 293         xhci_ring_cmd_db(xhci);
 294         spin_unlock_irqrestore(&xhci->lock, flags);
 295
 296         /* Wait for last stop endpoint command to finish */
 297         timeleft = wait_for_completion_interruptible_timeout(
 298                         cmd->completion,
 299                         USB_CTRL_SET_TIMEOUT);
 300         if (timeleft <= 0) {
 301                 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
 302                                 timeleft == 0 ? "Timeout" : "Signal");
 303                 spin_lock_irqsave(&xhci->lock, flags);
 304                 /* The timeout might have raced with the event ring handler, so
 305                  * only delete from the list if the item isn't poisoned.
 306                  */
 307                 if (cmd->cmd_list.next != LIST_POISON1)
 308                         list_del(&cmd->cmd_list);
 309                 spin_unlock_irqrestore(&xhci->lock, flags);
 310                 ret = -ETIME;
 311                 goto command_cleanup;
 312         }
 313
 314 command_cleanup:
 315         xhci_free_command(xhci, cmd);
 316         return ret;
 317 }
 318
 319 /*
 320  * Ring device, it rings the all doorbells unconditionally.
 321  */
 322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 323 {
 324         int i;
 325
 326         for (i = 0; i < LAST_EP_INDEX + 1; i++)
 327                 if (xhci->devs[slot_id]->eps[i].ring &&
 328                     xhci->devs[slot_id]->eps[i].ring->dequeue)
 329                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 330
 331         return;
 332 }
 333
 334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 335                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 336 {
 337         /* Don't allow the USB core to disable SuperSpeed ports. */
 338         if (hcd->speed == HCD_USB3) {
 339                 xhci_dbg(xhci, "Ignoring request to disable "
 340                                 "SuperSpeed port.\n");
 341                 return;
 342         }
 343
 344         /* Write 1 to disable the port */
 345         xhci_writel(xhci, port_status | PORT_PE, addr);
 346         port_status = xhci_readl(xhci, addr);
 347         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 348                         wIndex, port_status);
 349 }
 350
 351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 352                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 353 {
 354         char *port_change_bit;
 355         u32 status;
 356
 357         switch (wValue) {
 358         case USB_PORT_FEAT_C_RESET:
 359                 status = PORT_RC;
 360                 port_change_bit = "reset";
 361                 break;
 362         case USB_PORT_FEAT_C_BH_PORT_RESET:
 363                 status = PORT_WRC;
 364                 port_change_bit = "warm(BH) reset";
 365                 break;
 366         case USB_PORT_FEAT_C_CONNECTION:
 367                 status = PORT_CSC;
 368                 port_change_bit = "connect";
 369                 break;
 370         case USB_PORT_FEAT_C_OVER_CURRENT:
 371                 status = PORT_OCC;
 372                 port_change_bit = "over-current";
 373                 break;
 374         case USB_PORT_FEAT_C_ENABLE:
 375                 status = PORT_PEC;
 376                 port_change_bit = "enable/disable";
 377                 break;
 378         case USB_PORT_FEAT_C_SUSPEND:
 379                 status = PORT_PLC;
 380                 port_change_bit = "suspend/resume";
 381                 break;
 382         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 383                 status = PORT_PLC;
 384                 port_change_bit = "link state";
 385                 break;
 386         default:
 387                 /* Should never happen */
 388                 return;
 389         }
 390         /* Change bits are all write 1 to clear */
 391         xhci_writel(xhci, port_status | status, addr);
 392         port_status = xhci_readl(xhci, addr);
 393         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 394                         port_change_bit, wIndex, port_status);
 395 }
 396
 397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 398 {
 399         int max_ports;
 400         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 401
 402         if (hcd->speed == HCD_USB3) {
 403                 max_ports = xhci->num_usb3_ports;
 404                 *port_array = xhci->usb3_ports;
 405         } else {
 406                 max_ports = xhci->num_usb2_ports;
 407                 *port_array = xhci->usb2_ports;
 408         }
 409
 410         return max_ports;
 411 }
 412
 413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 414                                 int port_id, u32 link_state)
 415 {
 416         u32 temp;
 417
 418         temp = xhci_readl(xhci, port_array[port_id]);
 419         temp = xhci_port_state_to_neutral(temp);
 420         temp &= ~PORT_PLS_MASK;
 421         temp |= PORT_LINK_STROBE | link_state;
 422         xhci_writel(xhci, temp, port_array[port_id]);
 423 }
 424
 425 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 426                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 427 {
 428         u32 temp;
 429
 430         temp = xhci_readl(xhci, port_array[port_id]);
 431         temp = xhci_port_state_to_neutral(temp);
 432
 433         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 434                 temp |= PORT_WKCONN_E;
 435         else
 436                 temp &= ~PORT_WKCONN_E;
 437
 438         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 439                 temp |= PORT_WKDISC_E;
 440         else
 441                 temp &= ~PORT_WKDISC_E;
 442
 443         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 444                 temp |= PORT_WKOC_E;
 445         else
 446                 temp &= ~PORT_WKOC_E;
 447
 448         xhci_writel(xhci, temp, port_array[port_id]);
 449 }
 450
 451 /* Test and clear port RWC bit */
 452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 453                                 int port_id, u32 port_bit)
 454 {
 455         u32 temp;
 456
 457         temp = xhci_readl(xhci, port_array[port_id]);
 458         if (temp & port_bit) {
 459                 temp = xhci_port_state_to_neutral(temp);
 460                 temp |= port_bit;
 461                 xhci_writel(xhci, temp, port_array[port_id]);
 462         }
 463 }
 464
 465 /* Updates Link Status for USB 2.1 port */
 466 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 467 {
 468         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 469                 *status |= USB_PORT_STAT_L1;
 470 }
 471
 472 /* Updates Link Status for super Speed port */
 473 static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
 474 {
 475         u32 pls = status_reg & PORT_PLS_MASK;
 476
 477         /* resume state is a xHCI internal state.
 478          * Do not report it to usb core.
 479          */
 480         if (pls == XDEV_RESUME)
 481                 return;
 482
 483         /* When the CAS bit is set then warm reset
 484          * should be performed on port
 485          */
 486         if (status_reg & PORT_CAS) {
 487                 /* The CAS bit can be set while the port is
 488                  * in any link state.
 489                  * Only roothubs have CAS bit, so we
 490                  * pretend to be in compliance mode
 491                  * unless we're already in compliance
 492                  * or the inactive state.
 493                  */
 494                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 495                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 496                         pls = USB_SS_PORT_LS_COMP_MOD;
 497                 }
 498                 /* Return also connection bit -
 499                  * hub state machine resets port
 500                  * when this bit is set.
 501                  */
 502                 pls |= USB_PORT_STAT_CONNECTION;
 503         } else {
 504                 /*
 505                  * If CAS bit isn't set but the Port is already at
 506                  * Compliance Mode, fake a connection so the USB core
 507                  * notices the Compliance state and resets the port.
 508                  * This resolves an issue generated by the SN65LVPE502CP
 509                  * in which sometimes the port enters compliance mode
 510                  * caused by a delay on the host-device negotiation.
 511                  */
 512                 if (pls == USB_SS_PORT_LS_COMP_MOD)
 513                         pls |= USB_PORT_STAT_CONNECTION;
 514         }
 515
 516         /* update status field */
 517         *status |= pls;
 518 }
 519
 520 /*
 521  * Function for Compliance Mode Quirk.
 522  *
 523  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 524  * the compliance mode timer is deleted. A port won't enter
 525  * compliance mode if it has previously entered U0.
 526  */
 527 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
 528 {
 529         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 530         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 531
 532         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 533                 return;
 534
 535         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 536                 xhci->port_status_u0 |= 1 << wIndex;
 537                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 538                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 539                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 540                                 "All USB3 ports have entered U0 already!");
 541                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 542                                 "Compliance Mode Recovery Timer Deleted.");
 543                 }
 544         }
 545 }
 546
 547 /*
 548  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 549  * 3.0 hubs use.
 550  *
 551  * Possible side effects:
 552  *  - Mark a port as being done with device resume,
 553  *    and ring the endpoint doorbells.
 554  *  - Stop the Synopsys redriver Compliance Mode polling.
 555  */
 556 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 557                 struct xhci_bus_state *bus_state,
 558                 __le32 __iomem **port_array,
 559                 u16 wIndex, u32 raw_port_status)
 560 {
 561         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 562         u32 status = 0;
 563         int slot_id;
 564
 565         /* wPortChange bits */
 566         if (raw_port_status & PORT_CSC)
 567                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 568         if (raw_port_status & PORT_PEC)
 569                 status |= USB_PORT_STAT_C_ENABLE << 16;
 570         if ((raw_port_status & PORT_OCC))
 571                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 572         if ((raw_port_status & PORT_RC))
 573                 status |= USB_PORT_STAT_C_RESET << 16;
 574         /* USB3.0 only */
 575         if (hcd->speed == HCD_USB3) {
 576                 if ((raw_port_status & PORT_PLC))
 577                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 578                 if ((raw_port_status & PORT_WRC))
 579                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 580         }
 581
 582         if (hcd->speed != HCD_USB3) {
 583                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 584                                 && (raw_port_status & PORT_POWER))
 585                         status |= USB_PORT_STAT_SUSPEND;
 586         }
 587         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 588                         !DEV_SUPERSPEED(raw_port_status)) {
 589                 if ((raw_port_status & PORT_RESET) ||
 590                                 !(raw_port_status & PORT_PE))
 591                         return 0xffffffff;
 592                 if (time_after_eq(jiffies,
 593                                         bus_state->resume_done[wIndex])) {
 594                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 595                                         wIndex + 1);
 596                         bus_state->resume_done[wIndex] = 0;
 597                         clear_bit(wIndex, &bus_state->resuming_ports);
 598                         xhci_set_link_state(xhci, port_array, wIndex,
 599                                         XDEV_U0);
 600                         xhci_dbg(xhci, "set port %d resume\n",
 601                                         wIndex + 1);
 602                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 603                                         wIndex + 1);
 604                         if (!slot_id) {
 605                                 xhci_dbg(xhci, "slot_id is zero\n");
 606                                 return 0xffffffff;
 607                         }
 608                         xhci_ring_device(xhci, slot_id);
 609                         bus_state->port_c_suspend |= 1 << wIndex;
 610                         bus_state->suspended_ports &= ~(1 << wIndex);
 611                 } else {
 612                         /*
 613                          * The resume has been signaling for less than
 614                          * 20ms. Report the port status as SUSPEND,
 615                          * let the usbcore check port status again
 616                          * and clear resume signaling later.
 617                          */
 618                         status |= USB_PORT_STAT_SUSPEND;
 619                 }
 620         }
 621         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
 622                         && (raw_port_status & PORT_POWER)
 623                         && (bus_state->suspended_ports & (1 << wIndex))) {
 624                 bus_state->suspended_ports &= ~(1 << wIndex);
 625                 if (hcd->speed != HCD_USB3)
 626                         bus_state->port_c_suspend |= 1 << wIndex;
 627         }
 628         if (raw_port_status & PORT_CONNECT) {
 629                 status |= USB_PORT_STAT_CONNECTION;
 630                 status |= xhci_port_speed(raw_port_status);
 631         }
 632         if (raw_port_status & PORT_PE)
 633                 status |= USB_PORT_STAT_ENABLE;
 634         if (raw_port_status & PORT_OC)
 635                 status |= USB_PORT_STAT_OVERCURRENT;
 636         if (raw_port_status & PORT_RESET)
 637                 status |= USB_PORT_STAT_RESET;
 638         if (raw_port_status & PORT_POWER) {
 639                 if (hcd->speed == HCD_USB3)
 640                         status |= USB_SS_PORT_STAT_POWER;
 641                 else
 642                         status |= USB_PORT_STAT_POWER;
 643         }
 644         /* Update Port Link State */
 645         if (hcd->speed == HCD_USB3) {
 646                 xhci_hub_report_usb3_link_state(&status, raw_port_status);
 647                 /*
 648                  * Verify if all USB3 Ports Have entered U0 already.
 649                  * Delete Compliance Mode Timer if so.
 650                  */
 651                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 652         } else {
 653                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 654         }
 655         if (bus_state->port_c_suspend & (1 << wIndex))
 656                 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 657
 658         return status;
 659 }
 660
 661 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 662                 u16 wIndex, char *buf, u16 wLength)
 663 {
 664         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 665         int max_ports;
 666         unsigned long flags;
 667         u32 temp, status;
 668         int retval = 0;
 669         __le32 __iomem **port_array;
 670         int slot_id;
 671         struct xhci_bus_state *bus_state;
 672         u16 link_state = 0;
 673         u16 wake_mask = 0;
 674         u16 timeout = 0;
 675
 676         max_ports = xhci_get_ports(hcd, &port_array);
 677         bus_state = &xhci->bus_state[hcd_index(hcd)];
 678
 679         spin_lock_irqsave(&xhci->lock, flags);
 680         switch (typeReq) {
 681         case GetHubStatus:
 682                 /* No power source, over-current reported per port */
 683                 memset(buf, 0, 4);
 684                 break;
 685         case GetHubDescriptor:
 686                 /* Check to make sure userspace is asking for the USB 3.0 hub
 687                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 688                  * endpoint, like external hubs do.
 689                  */
 690                 if (hcd->speed == HCD_USB3 &&
 691                                 (wLength < USB_DT_SS_HUB_SIZE ||
 692                                  wValue != (USB_DT_SS_HUB << 8))) {
 693                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 694                                         "USB 3.0 roothub.\n");
 695                         goto error;
 696                 }
 697                 xhci_hub_descriptor(hcd, xhci,
 698                                 (struct usb_hub_descriptor *) buf);
 699                 break;
 700         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 701                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 702                         goto error;
 703
 704                 if (hcd->speed != HCD_USB3)
 705                         goto error;
 706
 707                 /* Set the U1 and U2 exit latencies. */
 708                 memcpy(buf, &usb_bos_descriptor,
 709                                 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
 710                 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
 711                 buf[12] = HCS_U1_LATENCY(temp);
 712                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 713
 714                 /* Indicate whether the host has LTM support. */
 715                 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 716                 if (HCC_LTC(temp))
 717                         buf[8] |= USB_LTM_SUPPORT;
 718
 719                 spin_unlock_irqrestore(&xhci->lock, flags);
 720                 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 721         case GetPortStatus:
 722                 if (!wIndex || wIndex > max_ports)
 723                         goto error;
 724                 wIndex--;
 725                 temp = xhci_readl(xhci, port_array[wIndex]);
 726                 if (temp == 0xffffffff) {
 727                         retval = -ENODEV;
 728                         break;
 729                 }
 730                 status = xhci_get_port_status(hcd, bus_state, port_array,
 731                                 wIndex, temp);
 732                 if (status == 0xffffffff)
 733                         goto error;
 734
 735                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 736                                 wIndex, temp);
 737                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 738
 739                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 740                 break;
 741         case SetPortFeature:
 742                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 743                         link_state = (wIndex & 0xff00) >> 3;
 744                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 745                         wake_mask = wIndex & 0xff00;
 746                 /* The MSB of wIndex is the U1/U2 timeout */
 747                 timeout = (wIndex & 0xff00) >> 8;
 748                 wIndex &= 0xff;
 749                 if (!wIndex || wIndex > max_ports)
 750                         goto error;
 751                 wIndex--;
 752                 temp = xhci_readl(xhci, port_array[wIndex]);
 753                 if (temp == 0xffffffff) {
 754                         retval = -ENODEV;
 755                         break;
 756                 }
 757                 temp = xhci_port_state_to_neutral(temp);
 758                 /* FIXME: What new port features do we need to support? */
 759                 switch (wValue) {
 760                 case USB_PORT_FEAT_SUSPEND:
 761                         temp = xhci_readl(xhci, port_array[wIndex]);
 762                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 763                                 /* Resume the port to U0 first */
 764                                 xhci_set_link_state(xhci, port_array, wIndex,
 765                                                         XDEV_U0);
 766                                 spin_unlock_irqrestore(&xhci->lock, flags);
 767                                 msleep(10);
 768                                 spin_lock_irqsave(&xhci->lock, flags);
 769                         }
 770                         /* In spec software should not attempt to suspend
 771                          * a port unless the port reports that it is in the
 772                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 773                          */
 774                         temp = xhci_readl(xhci, port_array[wIndex]);
 775                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 776                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 777                                 xhci_warn(xhci, "USB core suspending device "
 778                                           "not in U0/U1/U2.\n");
 779                                 goto error;
 780                         }
 781
 782                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 783                                         wIndex + 1);
 784                         if (!slot_id) {
 785                                 xhci_warn(xhci, "slot_id is zero\n");
 786                                 goto error;
 787                         }
 788                         /* unlock to execute stop endpoint commands */
 789                         spin_unlock_irqrestore(&xhci->lock, flags);
 790                         xhci_stop_device(xhci, slot_id, 1);
 791                         spin_lock_irqsave(&xhci->lock, flags);
 792
 793                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
 794
 795                         spin_unlock_irqrestore(&xhci->lock, flags);
 796                         msleep(10); /* wait device to enter */
 797                         spin_lock_irqsave(&xhci->lock, flags);
 798
 799                         temp = xhci_readl(xhci, port_array[wIndex]);
 800                         bus_state->suspended_ports |= 1 << wIndex;
 801                         break;
 802                 case USB_PORT_FEAT_LINK_STATE:
 803                         temp = xhci_readl(xhci, port_array[wIndex]);
 804
 805                         /* Disable port */
 806                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
 807                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
 808                                 temp = xhci_port_state_to_neutral(temp);
 809                                 /*
 810                                  * Clear all change bits, so that we get a new
 811                                  * connection event.
 812                                  */
 813                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
 814                                         PORT_OCC | PORT_RC | PORT_PLC |
 815                                         PORT_CEC;
 816                                 xhci_writel(xhci, temp | PORT_PE,
 817                                         port_array[wIndex]);
 818                                 temp = xhci_readl(xhci, port_array[wIndex]);
 819                                 break;
 820                         }
 821
 822                         /* Put link in RxDetect (enable port) */
 823                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
 824                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
 825                                 xhci_set_link_state(xhci, port_array, wIndex,
 826                                                 link_state);
 827                                 temp = xhci_readl(xhci, port_array[wIndex]);
 828                                 break;
 829                         }
 830
 831                         /* Software should not attempt to set
 832                          * port link state above '3' (U3) and the port
 833                          * must be enabled.
 834                          */
 835                         if ((temp & PORT_PE) == 0 ||
 836                                 (link_state > USB_SS_PORT_LS_U3)) {
 837                                 xhci_warn(xhci, "Cannot set link state.\n");
 838                                 goto error;
 839                         }
 840
 841                         if (link_state == USB_SS_PORT_LS_U3) {
 842                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 843                                                 wIndex + 1);
 844                                 if (slot_id) {
 845                                         /* unlock to execute stop endpoint
 846                                          * commands */
 847                                         spin_unlock_irqrestore(&xhci->lock,
 848                                                                 flags);
 849                                         xhci_stop_device(xhci, slot_id, 1);
 850                                         spin_lock_irqsave(&xhci->lock, flags);
 851                                 }
 852                         }
 853
 854                         xhci_set_link_state(xhci, port_array, wIndex,
 855                                                 link_state);
 856
 857                         spin_unlock_irqrestore(&xhci->lock, flags);
 858                         msleep(20); /* wait device to enter */
 859                         spin_lock_irqsave(&xhci->lock, flags);
 860
 861                         temp = xhci_readl(xhci, port_array[wIndex]);
 862                         if (link_state == USB_SS_PORT_LS_U3)
 863                                 bus_state->suspended_ports |= 1 << wIndex;
 864                         break;
 865                 case USB_PORT_FEAT_POWER:
 866                         /*
 867                          * Turn on ports, even if there isn't per-port switching.
 868                          * HC will report connect events even before this is set.
 869                          * However, khubd will ignore the roothub events until
 870                          * the roothub is registered.
 871                          */
 872                         xhci_writel(xhci, temp | PORT_POWER,
 873                                         port_array[wIndex]);
 874
 875                         temp = xhci_readl(xhci, port_array[wIndex]);
 876                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 877
 878                         spin_unlock_irqrestore(&xhci->lock, flags);
 879                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 880                                         wIndex);
 881                         if (temp)
 882                                 usb_acpi_set_power_state(hcd->self.root_hub,
 883                                                 wIndex, true);
 884                         spin_lock_irqsave(&xhci->lock, flags);
 885                         break;
 886                 case USB_PORT_FEAT_RESET:
 887                         temp = (temp | PORT_RESET);
 888                         xhci_writel(xhci, temp, port_array[wIndex]);
 889
 890                         temp = xhci_readl(xhci, port_array[wIndex]);
 891                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 892                         break;
 893                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
 894                         xhci_set_remote_wake_mask(xhci, port_array,
 895                                         wIndex, wake_mask);
 896                         temp = xhci_readl(xhci, port_array[wIndex]);
 897                         xhci_dbg(xhci, "set port remote wake mask, "
 898                                         "actual port %d status  = 0x%x\n",
 899                                         wIndex, temp);
 900                         break;
 901                 case USB_PORT_FEAT_BH_PORT_RESET:
 902                         temp |= PORT_WR;
 903                         xhci_writel(xhci, temp, port_array[wIndex]);
 904
 905                         temp = xhci_readl(xhci, port_array[wIndex]);
 906                         break;
 907                 case USB_PORT_FEAT_U1_TIMEOUT:
 908                         if (hcd->speed != HCD_USB3)
 909                                 goto error;
 910                         temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
 911                         temp &= ~PORT_U1_TIMEOUT_MASK;
 912                         temp |= PORT_U1_TIMEOUT(timeout);
 913                         xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
 914                         break;
 915                 case USB_PORT_FEAT_U2_TIMEOUT:
 916                         if (hcd->speed != HCD_USB3)
 917                                 goto error;
 918                         temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
 919                         temp &= ~PORT_U2_TIMEOUT_MASK;
 920                         temp |= PORT_U2_TIMEOUT(timeout);
 921                         xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
 922                         break;
 923                 default:
 924                         goto error;
 925                 }
 926                 /* unblock any posted writes */
 927                 temp = xhci_readl(xhci, port_array[wIndex]);
 928                 break;
 929         case ClearPortFeature:
 930                 if (!wIndex || wIndex > max_ports)
 931                         goto error;
 932                 wIndex--;
 933                 temp = xhci_readl(xhci, port_array[wIndex]);
 934                 if (temp == 0xffffffff) {
 935                         retval = -ENODEV;
 936                         break;
 937                 }
 938                 /* FIXME: What new port features do we need to support? */
 939                 temp = xhci_port_state_to_neutral(temp);
 940                 switch (wValue) {
 941                 case USB_PORT_FEAT_SUSPEND:
 942                         temp = xhci_readl(xhci, port_array[wIndex]);
 943                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
 944                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
 945                         if (temp & PORT_RESET)
 946                                 goto error;
 947                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
 948                                 if ((temp & PORT_PE) == 0)
 949                                         goto error;
 950
 951                                 xhci_set_link_state(xhci, port_array, wIndex,
 952                                                         XDEV_RESUME);
 953                                 spin_unlock_irqrestore(&xhci->lock, flags);
 954                                 msleep(20);
 955                                 spin_lock_irqsave(&xhci->lock, flags);
 956                                 xhci_set_link_state(xhci, port_array, wIndex,
 957                                                         XDEV_U0);
 958                         }
 959                         bus_state->port_c_suspend |= 1 << wIndex;
 960
 961                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 962                                         wIndex + 1);
 963                         if (!slot_id) {
 964                                 xhci_dbg(xhci, "slot_id is zero\n");
 965                                 goto error;
 966                         }
 967                         xhci_ring_device(xhci, slot_id);
 968                         break;
 969                 case USB_PORT_FEAT_C_SUSPEND:
 970                         bus_state->port_c_suspend &= ~(1 << wIndex);
 971                 case USB_PORT_FEAT_C_RESET:
 972                 case USB_PORT_FEAT_C_BH_PORT_RESET:
 973                 case USB_PORT_FEAT_C_CONNECTION:
 974                 case USB_PORT_FEAT_C_OVER_CURRENT:
 975                 case USB_PORT_FEAT_C_ENABLE:
 976                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
 977                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
 978                                         port_array[wIndex], temp);
 979                         break;
 980                 case USB_PORT_FEAT_ENABLE:
 981                         xhci_disable_port(hcd, xhci, wIndex,
 982                                         port_array[wIndex], temp);
 983                         break;
 984                 case USB_PORT_FEAT_POWER:
 985                         xhci_writel(xhci, temp & ~PORT_POWER,
 986                                 port_array[wIndex]);
 987
 988                         spin_unlock_irqrestore(&xhci->lock, flags);
 989                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 990                                         wIndex);
 991                         if (temp)
 992                                 usb_acpi_set_power_state(hcd->self.root_hub,
 993                                                 wIndex, false);
 994                         spin_lock_irqsave(&xhci->lock, flags);
 995                         break;
 996                 default:
 997                         goto error;
 998                 }
 999                 break;
1000         default:
1001 error:
1002                 /* "stall" on error */
1003                 retval = -EPIPE;
1004         }
1005         spin_unlock_irqrestore(&xhci->lock, flags);
1006         return retval;
1007 }
1008
1009 /*
1010  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1011  * Ports are 0-indexed from the HCD point of view,
1012  * and 1-indexed from the USB core pointer of view.
1013  *
1014  * Note that the status change bits will be cleared as soon as a port status
1015  * change event is generated, so we use the saved status from that event.
1016  */
1017 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1018 {
1019         unsigned long flags;
1020         u32 temp, status;
1021         u32 mask;
1022         int i, retval;
1023         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1024         int max_ports;
1025         __le32 __iomem **port_array;
1026         struct xhci_bus_state *bus_state;
1027         bool reset_change = false;
1028
1029         max_ports = xhci_get_ports(hcd, &port_array);
1030         bus_state = &xhci->bus_state[hcd_index(hcd)];
1031
1032         /* Initial status is no changes */
1033         retval = (max_ports + 8) / 8;
1034         memset(buf, 0, retval);
1035
1036         /*
1037          * Inform the usbcore about resume-in-progress by returning
1038          * a non-zero value even if there are no status changes.
1039          */
1040         status = bus_state->resuming_ports;
1041
1042         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1043
1044         spin_lock_irqsave(&xhci->lock, flags);
1045         /* For each port, did anything change?  If so, set that bit in buf. */
1046         for (i = 0; i < max_ports; i++) {
1047                 temp = xhci_readl(xhci, port_array[i]);
1048                 if (temp == 0xffffffff) {
1049                         retval = -ENODEV;
1050                         break;
1051                 }
1052                 if ((temp & mask) != 0 ||
1053                         (bus_state->port_c_suspend & 1 << i) ||
1054                         (bus_state->resume_done[i] && time_after_eq(
1055                             jiffies, bus_state->resume_done[i]))) {
1056                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1057                         status = 1;
1058                 }
1059                 if ((temp & PORT_RC))
1060                         reset_change = true;
1061         }
1062         if (!status && !reset_change) {
1063                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1064                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1065         }
1066         spin_unlock_irqrestore(&xhci->lock, flags);
1067         return status ? retval : 0;
1068 }
1069
1070 #ifdef CONFIG_PM
1071
1072 int xhci_bus_suspend(struct usb_hcd *hcd)
1073 {
1074         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1075         int max_ports, port_index;
1076         __le32 __iomem **port_array;
1077         struct xhci_bus_state *bus_state;
1078         unsigned long flags;
1079
1080         max_ports = xhci_get_ports(hcd, &port_array);
1081         bus_state = &xhci->bus_state[hcd_index(hcd)];
1082
1083         spin_lock_irqsave(&xhci->lock, flags);
1084
1085         if (hcd->self.root_hub->do_remote_wakeup) {
1086                 if (bus_state->resuming_ports) {
1087                         spin_unlock_irqrestore(&xhci->lock, flags);
1088                         xhci_dbg(xhci, "suspend failed because "
1089                                                 "a port is resuming\n");
1090                         return -EBUSY;
1091                 }
1092         }
1093
1094         port_index = max_ports;
1095         bus_state->bus_suspended = 0;
1096         while (port_index--) {
1097                 /* suspend the port if the port is not suspended */
1098                 u32 t1, t2;
1099                 int slot_id;
1100
1101                 t1 = xhci_readl(xhci, port_array[port_index]);
1102                 t2 = xhci_port_state_to_neutral(t1);
1103
1104                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1105                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1106                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1107                                         port_index + 1);
1108                         if (slot_id) {
1109                                 spin_unlock_irqrestore(&xhci->lock, flags);
1110                                 xhci_stop_device(xhci, slot_id, 1);
1111                                 spin_lock_irqsave(&xhci->lock, flags);
1112                         }
1113                         t2 &= ~PORT_PLS_MASK;
1114                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1115                         set_bit(port_index, &bus_state->bus_suspended);
1116                 }
1117                 /* USB core sets remote wake mask for USB 3.0 hubs,
1118                  * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1119                  * is enabled, so also enable remote wake here.
1120                  */
1121                 if (hcd->self.root_hub->do_remote_wakeup) {
1122                         if (t1 & PORT_CONNECT) {
1123                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1124                                 t2 &= ~PORT_WKCONN_E;
1125                         } else {
1126                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1127                                 t2 &= ~PORT_WKDISC_E;
1128                         }
1129                 } else
1130                         t2 &= ~PORT_WAKE_BITS;
1131
1132                 t1 = xhci_port_state_to_neutral(t1);
1133                 if (t1 != t2)
1134                         xhci_writel(xhci, t2, port_array[port_index]);
1135
1136                 if (hcd->speed != HCD_USB3) {
1137                         /* enable remote wake up for USB 2.0 */
1138                         __le32 __iomem *addr;
1139                         u32 tmp;
1140
1141                         /* Get the port power control register address. */
1142                         addr = port_array[port_index] + PORTPMSC;
1143                         tmp = xhci_readl(xhci, addr);
1144                         tmp |= PORT_RWE;
1145                         xhci_writel(xhci, tmp, addr);
1146                 }
1147         }
1148         hcd->state = HC_STATE_SUSPENDED;
1149         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1150         spin_unlock_irqrestore(&xhci->lock, flags);
1151         return 0;
1152 }
1153
1154 int xhci_bus_resume(struct usb_hcd *hcd)
1155 {
1156         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1157         int max_ports, port_index;
1158         __le32 __iomem **port_array;
1159         struct xhci_bus_state *bus_state;
1160         u32 temp;
1161         unsigned long flags;
1162
1163         max_ports = xhci_get_ports(hcd, &port_array);
1164         bus_state = &xhci->bus_state[hcd_index(hcd)];
1165
1166         if (time_before(jiffies, bus_state->next_statechange))
1167                 msleep(5);
1168
1169         spin_lock_irqsave(&xhci->lock, flags);
1170         if (!HCD_HW_ACCESSIBLE(hcd)) {
1171                 spin_unlock_irqrestore(&xhci->lock, flags);
1172                 return -ESHUTDOWN;
1173         }
1174
1175         /* delay the irqs */
1176         temp = xhci_readl(xhci, &xhci->op_regs->command);
1177         temp &= ~CMD_EIE;
1178         xhci_writel(xhci, temp, &xhci->op_regs->command);
1179
1180         port_index = max_ports;
1181         while (port_index--) {
1182                 /* Check whether need resume ports. If needed
1183                    resume port and disable remote wakeup */
1184                 u32 temp;
1185                 int slot_id;
1186
1187                 temp = xhci_readl(xhci, port_array[port_index]);
1188                 if (DEV_SUPERSPEED(temp))
1189                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1190                 else
1191                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1192                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1193                     (temp & PORT_PLS_MASK)) {
1194                         if (DEV_SUPERSPEED(temp)) {
1195                                 xhci_set_link_state(xhci, port_array,
1196                                                         port_index, XDEV_U0);
1197                         } else {
1198                                 xhci_set_link_state(xhci, port_array,
1199                                                 port_index, XDEV_RESUME);
1200
1201                                 spin_unlock_irqrestore(&xhci->lock, flags);
1202                                 msleep(20);
1203                                 spin_lock_irqsave(&xhci->lock, flags);
1204
1205                                 xhci_set_link_state(xhci, port_array,
1206                                                         port_index, XDEV_U0);
1207                         }
1208                         /* wait for the port to enter U0 and report port link
1209                          * state change.
1210                          */
1211                         spin_unlock_irqrestore(&xhci->lock, flags);
1212                         msleep(20);
1213                         spin_lock_irqsave(&xhci->lock, flags);
1214
1215                         /* Clear PLC */
1216                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1217                                                 PORT_PLC);
1218
1219                         slot_id = xhci_find_slot_id_by_port(hcd,
1220                                         xhci, port_index + 1);
1221                         if (slot_id)
1222                                 xhci_ring_device(xhci, slot_id);
1223                 } else
1224                         xhci_writel(xhci, temp, port_array[port_index]);
1225
1226                 if (hcd->speed != HCD_USB3) {
1227                         /* disable remote wake up for USB 2.0 */
1228                         __le32 __iomem *addr;
1229                         u32 tmp;
1230
1231                         /* Add one to the port status register address to get
1232                          * the port power control register address.
1233                          */
1234                         addr = port_array[port_index] + PORTPMSC;
1235                         tmp = xhci_readl(xhci, addr);
1236                         tmp &= ~PORT_RWE;
1237                         xhci_writel(xhci, tmp, addr);
1238                 }
1239         }
1240
1241         (void) xhci_readl(xhci, &xhci->op_regs->command);
1242
1243         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1244         /* re-enable irqs */
1245         temp = xhci_readl(xhci, &xhci->op_regs->command);
1246         temp |= CMD_EIE;
1247         xhci_writel(xhci, temp, &xhci->op_regs->command);
1248         temp = xhci_readl(xhci, &xhci->op_regs->command);
1249
1250         spin_unlock_irqrestore(&xhci->lock, flags);
1251         return 0;
1252 }
1253
1254 #endif  /* CONFIG_PM */