drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  38                                         unsigned int cycle_state, gfp_t flags)
  39 {
  40         struct xhci_segment *seg;
  41         dma_addr_t      dma;
  42         int             i;
  43
  44         seg = kzalloc(sizeof *seg, flags);
  45         if (!seg)
  46                 return NULL;
  47
  48         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  49         if (!seg->trbs) {
  50                 kfree(seg);
  51                 return NULL;
  52         }
  53
  54         memset(seg->trbs, 0, SEGMENT_SIZE);
  55         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
  56         if (cycle_state == 0) {
  57                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
  58                         seg->trbs[i].link.control |= TRB_CYCLE;
  59         }
  60         seg->dma = dma;
  61         seg->next = NULL;
  62
  63         return seg;
  64 }
  65
  66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  67 {
  68         if (seg->trbs) {
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         kfree(seg);
  73 }
  74
  75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
  76                                 struct xhci_segment *first)
  77 {
  78         struct xhci_segment *seg;
  79
  80         seg = first->next;
  81         while (seg != first) {
  82                 struct xhci_segment *next = seg->next;
  83                 xhci_segment_free(xhci, seg);
  84                 seg = next;
  85         }
  86         xhci_segment_free(xhci, first);
  87 }
  88
  89 /*
  90  * Make the prev segment point to the next segment.
  91  *
  92  * Change the last TRB in the prev segment to be a Link TRB which points to the
  93  * DMA address of the next segment.  The caller needs to set any Link TRB
  94  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  95  */
  96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  97                 struct xhci_segment *next, enum xhci_ring_type type)
  98 {
  99         u32 val;
 100
 101         if (!prev || !next)
 102                 return;
 103         prev->next = next;
 104         if (type != TYPE_EVENT) {
 105                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
 106                         cpu_to_le64(next->dma);
 107
 108                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 109                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 110                 val &= ~TRB_TYPE_BITMASK;
 111                 val |= TRB_TYPE(TRB_LINK);
 112                 /* Always set the chain bit with 0.95 hardware */
 113                 /* Set chain bit for isoc rings on AMD 0.96 host */
 114                 if (xhci_link_trb_quirk(xhci) ||
 115                                 (type == TYPE_ISOC &&
 116                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
 117                         val |= TRB_CHAIN;
 118                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 119         }
 120 }
 121
 122 /* XXX: Do we need the hcd structure in all these functions? */
 123 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 124 {
 125         if (!ring)
 126                 return;
 127
 128         if (ring->first_seg)
 129                 xhci_free_segments_for_ring(xhci, ring->first_seg);
 130
 131         kfree(ring);
 132 }
 133
 134 static void xhci_initialize_ring_info(struct xhci_ring *ring,
 135                                         unsigned int cycle_state)
 136 {
 137         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 138         ring->enqueue = ring->first_seg->trbs;
 139         ring->enq_seg = ring->first_seg;
 140         ring->dequeue = ring->enqueue;
 141         ring->deq_seg = ring->first_seg;
 142         /* The ring is initialized to 0. The producer must write 1 to the cycle
 143          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 144          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 145          *
 146          * New rings are initialized with cycle state equal to 1; if we are
 147          * handling ring expansion, set the cycle state equal to the old ring.
 148          */
 149         ring->cycle_state = cycle_state;
 150         /* Not necessary for new rings, but needed for re-initialized rings */
 151         ring->enq_updates = 0;
 152         ring->deq_updates = 0;
 153
 154         /*
 155          * Each segment has a link TRB, and leave an extra TRB for SW
 156          * accounting purpose
 157          */
 158         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 159 }
 160
 161 /* Allocate segments and link them for a ring */
 162 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
 163                 struct xhci_segment **first, struct xhci_segment **last,
 164                 unsigned int num_segs, unsigned int cycle_state,
 165                 enum xhci_ring_type type, gfp_t flags)
 166 {
 167         struct xhci_segment *prev;
 168
 169         prev = xhci_segment_alloc(xhci, cycle_state, flags);
 170         if (!prev)
 171                 return -ENOMEM;
 172         num_segs--;
 173
 174         *first = prev;
 175         while (num_segs > 0) {
 176                 struct xhci_segment     *next;
 177
 178                 next = xhci_segment_alloc(xhci, cycle_state, flags);
 179                 if (!next) {
 180                         xhci_free_segments_for_ring(xhci, *first);
 181                         return -ENOMEM;
 182                 }
 183                 xhci_link_segments(xhci, prev, next, type);
 184
 185                 prev = next;
 186                 num_segs--;
 187         }
 188         xhci_link_segments(xhci, prev, *first, type);
 189         *last = prev;
 190
 191         return 0;
 192 }
 193
 194 /**
 195  * Create a new ring with zero or more segments.
 196  *
 197  * Link each segment together into a ring.
 198  * Set the end flag and the cycle toggle bit on the last segment.
 199  * See section 4.9.1 and figures 15 and 16.
 200  */
 201 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 202                 unsigned int num_segs, unsigned int cycle_state,
 203                 enum xhci_ring_type type, gfp_t flags)
 204 {
 205         struct xhci_ring        *ring;
 206         int ret;
 207
 208         ring = kzalloc(sizeof *(ring), flags);
 209         if (!ring)
 210                 return NULL;
 211
 212         ring->num_segs = num_segs;
 213         INIT_LIST_HEAD(&ring->td_list);
 214         ring->type = type;
 215         if (num_segs == 0)
 216                 return ring;
 217
 218         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
 219                         &ring->last_seg, num_segs, cycle_state, type, flags);
 220         if (ret)
 221                 goto fail;
 222
 223         /* Only event ring does not use link TRB */
 224         if (type != TYPE_EVENT) {
 225                 /* See section 4.9.2.1 and 6.4.4.1 */
 226                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
 227                         cpu_to_le32(LINK_TOGGLE);
 228         }
 229         xhci_initialize_ring_info(ring, cycle_state);
 230         return ring;
 231
 232 fail:
 233         xhci_ring_free(xhci, ring);
 234         return NULL;
 235 }
 236
 237 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 238                 struct xhci_virt_device *virt_dev,
 239                 unsigned int ep_index)
 240 {
 241         int rings_cached;
 242
 243         rings_cached = virt_dev->num_rings_cached;
 244         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 245                 virt_dev->ring_cache[rings_cached] =
 246                         virt_dev->eps[ep_index].ring;
 247                 virt_dev->num_rings_cached++;
 248                 xhci_dbg(xhci, "Cached old ring, "
 249                                 "%d ring%s cached\n",
 250                                 virt_dev->num_rings_cached,
 251                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 252         } else {
 253                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 254                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 255                                 "freeing ring\n",
 256                                 virt_dev->num_rings_cached);
 257         }
 258         virt_dev->eps[ep_index].ring = NULL;
 259 }
 260
 261 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 262  * pointers to the beginning of the ring.
 263  */
 264 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 265                         struct xhci_ring *ring, unsigned int cycle_state,
 266                         enum xhci_ring_type type)
 267 {
 268         struct xhci_segment     *seg = ring->first_seg;
 269         int i;
 270
 271         do {
 272                 memset(seg->trbs, 0,
 273                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 274                 if (cycle_state == 0) {
 275                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
 276                                 seg->trbs[i].link.control |= TRB_CYCLE;
 277                 }
 278                 /* All endpoint rings have link TRBs */
 279                 xhci_link_segments(xhci, seg, seg->next, type);
 280                 seg = seg->next;
 281         } while (seg != ring->first_seg);
 282         ring->type = type;
 283         xhci_initialize_ring_info(ring, cycle_state);
 284         /* td list should be empty since all URBs have been cancelled,
 285          * but just in case...
 286          */
 287         INIT_LIST_HEAD(&ring->td_list);
 288 }
 289
 290 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 291
 292 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 293                                                     int type, gfp_t flags)
 294 {
 295         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 296         if (!ctx)
 297                 return NULL;
 298
 299         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 300         ctx->type = type;
 301         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 302         if (type == XHCI_CTX_TYPE_INPUT)
 303                 ctx->size += CTX_SIZE(xhci->hcc_params);
 304
 305         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 306         memset(ctx->bytes, 0, ctx->size);
 307         return ctx;
 308 }
 309
 310 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 311                              struct xhci_container_ctx *ctx)
 312 {
 313         if (!ctx)
 314                 return;
 315         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 316         kfree(ctx);
 317 }
 318
 319 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 320                                               struct xhci_container_ctx *ctx)
 321 {
 322         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 323         return (struct xhci_input_control_ctx *)ctx->bytes;
 324 }
 325
 326 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 327                                         struct xhci_container_ctx *ctx)
 328 {
 329         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 330                 return (struct xhci_slot_ctx *)ctx->bytes;
 331
 332         return (struct xhci_slot_ctx *)
 333                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 334 }
 335
 336 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 337                                     struct xhci_container_ctx *ctx,
 338                                     unsigned int ep_index)
 339 {
 340         /* increment ep index by offset of start of ep ctx array */
 341         ep_index++;
 342         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 343                 ep_index++;
 344
 345         return (struct xhci_ep_ctx *)
 346                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 347 }
 348
 349
 350 /***************** Streams structures manipulation *************************/
 351
 352 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 353                 unsigned int num_stream_ctxs,
 354                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 355 {
 356         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 357
 358         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 359                 dma_free_coherent(&pdev->dev,
 360                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 361                                 stream_ctx, dma);
 362         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 363                 return dma_pool_free(xhci->small_streams_pool,
 364                                 stream_ctx, dma);
 365         else
 366                 return dma_pool_free(xhci->medium_streams_pool,
 367                                 stream_ctx, dma);
 368 }
 369
 370 /*
 371  * The stream context array for each endpoint with bulk streams enabled can
 372  * vary in size, based on:
 373  *  - how many streams the endpoint supports,
 374  *  - the maximum primary stream array size the host controller supports,
 375  *  - and how many streams the device driver asks for.
 376  *
 377  * The stream context array must be a power of 2, and can be as small as
 378  * 64 bytes or as large as 1MB.
 379  */
 380 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 381                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 382                 gfp_t mem_flags)
 383 {
 384         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 385
 386         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 387                 return dma_alloc_coherent(&pdev->dev,
 388                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 389                                 dma, mem_flags);
 390         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 391                 return dma_pool_alloc(xhci->small_streams_pool,
 392                                 mem_flags, dma);
 393         else
 394                 return dma_pool_alloc(xhci->medium_streams_pool,
 395                                 mem_flags, dma);
 396 }
 397
 398 struct xhci_ring *xhci_dma_to_transfer_ring(
 399                 struct xhci_virt_ep *ep,
 400                 u64 address)
 401 {
 402         if (ep->ep_state & EP_HAS_STREAMS)
 403                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 404                                 address >> SEGMENT_SHIFT);
 405         return ep->ring;
 406 }
 407
 408 /* Only use this when you know stream_info is valid */
 409 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 410 static struct xhci_ring *dma_to_stream_ring(
 411                 struct xhci_stream_info *stream_info,
 412                 u64 address)
 413 {
 414         return radix_tree_lookup(&stream_info->trb_address_map,
 415                         address >> SEGMENT_SHIFT);
 416 }
 417 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 418
 419 struct xhci_ring *xhci_stream_id_to_ring(
 420                 struct xhci_virt_device *dev,
 421                 unsigned int ep_index,
 422                 unsigned int stream_id)
 423 {
 424         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 425
 426         if (stream_id == 0)
 427                 return ep->ring;
 428         if (!ep->stream_info)
 429                 return NULL;
 430
 431         if (stream_id > ep->stream_info->num_streams)
 432                 return NULL;
 433         return ep->stream_info->stream_rings[stream_id];
 434 }
 435
 436 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 437 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 438                 unsigned int num_streams,
 439                 struct xhci_stream_info *stream_info)
 440 {
 441         u32 cur_stream;
 442         struct xhci_ring *cur_ring;
 443         u64 addr;
 444
 445         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 446                 struct xhci_ring *mapped_ring;
 447                 int trb_size = sizeof(union xhci_trb);
 448
 449                 cur_ring = stream_info->stream_rings[cur_stream];
 450                 for (addr = cur_ring->first_seg->dma;
 451                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 452                                 addr += trb_size) {
 453                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 454                         if (cur_ring != mapped_ring) {
 455                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 456                                                 "didn't map to stream ID %u; "
 457                                                 "mapped to ring %p\n",
 458                                                 (unsigned long long) addr,
 459                                                 cur_stream,
 460                                                 mapped_ring);
 461                                 return -EINVAL;
 462                         }
 463                 }
 464                 /* One TRB after the end of the ring segment shouldn't return a
 465                  * pointer to the current ring (although it may be a part of a
 466                  * different ring).
 467                  */
 468                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 469                 if (mapped_ring != cur_ring) {
 470                         /* One TRB before should also fail */
 471                         addr = cur_ring->first_seg->dma - trb_size;
 472                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 473                 }
 474                 if (mapped_ring == cur_ring) {
 475                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 476                                         "mapped to valid stream ID %u; "
 477                                         "mapped ring = %p\n",
 478                                         (unsigned long long) addr,
 479                                         cur_stream,
 480                                         mapped_ring);
 481                         return -EINVAL;
 482                 }
 483         }
 484         return 0;
 485 }
 486 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 487
 488 /*
 489  * Change an endpoint's internal structure so it supports stream IDs.  The
 490  * number of requested streams includes stream 0, which cannot be used by device
 491  * drivers.
 492  *
 493  * The number of stream contexts in the stream context array may be bigger than
 494  * the number of streams the driver wants to use.  This is because the number of
 495  * stream context array entries must be a power of two.
 496  *
 497  * We need a radix tree for mapping physical addresses of TRBs to which stream
 498  * ID they belong to.  We need to do this because the host controller won't tell
 499  * us which stream ring the TRB came from.  We could store the stream ID in an
 500  * event data TRB, but that doesn't help us for the cancellation case, since the
 501  * endpoint may stop before it reaches that event data TRB.
 502  *
 503  * The radix tree maps the upper portion of the TRB DMA address to a ring
 504  * segment that has the same upper portion of DMA addresses.  For example, say I
 505  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 506  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 507  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 508  * pass the radix tree a key to get the right stream ID:
 509  *
 510  *      0x10c90fff >> 10 = 0x43243
 511  *      0x10c912c0 >> 10 = 0x43244
 512  *      0x10c91400 >> 10 = 0x43245
 513  *
 514  * Obviously, only those TRBs with DMA addresses that are within the segment
 515  * will make the radix tree return the stream ID for that ring.
 516  *
 517  * Caveats for the radix tree:
 518  *
 519  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 520  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 521  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 522  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 523  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 524  * extended systems (where the DMA address can be bigger than 32-bits),
 525  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 526  */
 527 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 528                 unsigned int num_stream_ctxs,
 529                 unsigned int num_streams, gfp_t mem_flags)
 530 {
 531         struct xhci_stream_info *stream_info;
 532         u32 cur_stream;
 533         struct xhci_ring *cur_ring;
 534         unsigned long key;
 535         u64 addr;
 536         int ret;
 537
 538         xhci_dbg(xhci, "Allocating %u streams and %u "
 539                         "stream context array entries.\n",
 540                         num_streams, num_stream_ctxs);
 541         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 542                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 543                 return NULL;
 544         }
 545         xhci->cmd_ring_reserved_trbs++;
 546
 547         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 548         if (!stream_info)
 549                 goto cleanup_trbs;
 550
 551         stream_info->num_streams = num_streams;
 552         stream_info->num_stream_ctxs = num_stream_ctxs;
 553
 554         /* Initialize the array of virtual pointers to stream rings. */
 555         stream_info->stream_rings = kzalloc(
 556                         sizeof(struct xhci_ring *)*num_streams,
 557                         mem_flags);
 558         if (!stream_info->stream_rings)
 559                 goto cleanup_info;
 560
 561         /* Initialize the array of DMA addresses for stream rings for the HW. */
 562         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 563                         num_stream_ctxs, &stream_info->ctx_array_dma,
 564                         mem_flags);
 565         if (!stream_info->stream_ctx_array)
 566                 goto cleanup_ctx;
 567         memset(stream_info->stream_ctx_array, 0,
 568                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 569
 570         /* Allocate everything needed to free the stream rings later */
 571         stream_info->free_streams_command =
 572                 xhci_alloc_command(xhci, true, true, mem_flags);
 573         if (!stream_info->free_streams_command)
 574                 goto cleanup_ctx;
 575
 576         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 577
 578         /* Allocate rings for all the streams that the driver will use,
 579          * and add their segment DMA addresses to the radix tree.
 580          * Stream 0 is reserved.
 581          */
 582         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 583                 stream_info->stream_rings[cur_stream] =
 584                         xhci_ring_alloc(xhci, 1, 1, TYPE_STREAM, mem_flags);
 585                 cur_ring = stream_info->stream_rings[cur_stream];
 586                 if (!cur_ring)
 587                         goto cleanup_rings;
 588                 cur_ring->stream_id = cur_stream;
 589                 /* Set deq ptr, cycle bit, and stream context type */
 590                 addr = cur_ring->first_seg->dma |
 591                         SCT_FOR_CTX(SCT_PRI_TR) |
 592                         cur_ring->cycle_state;
 593                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 594                         cpu_to_le64(addr);
 595                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 596                                 cur_stream, (unsigned long long) addr);
 597
 598                 key = (unsigned long)
 599                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 600                 ret = radix_tree_insert(&stream_info->trb_address_map,
 601                                 key, cur_ring);
 602                 if (ret) {
 603                         xhci_ring_free(xhci, cur_ring);
 604                         stream_info->stream_rings[cur_stream] = NULL;
 605                         goto cleanup_rings;
 606                 }
 607         }
 608         /* Leave the other unused stream ring pointers in the stream context
 609          * array initialized to zero.  This will cause the xHC to give us an
 610          * error if the device asks for a stream ID we don't have setup (if it
 611          * was any other way, the host controller would assume the ring is
 612          * "empty" and wait forever for data to be queued to that stream ID).
 613          */
 614 #if XHCI_DEBUG
 615         /* Do a little test on the radix tree to make sure it returns the
 616          * correct values.
 617          */
 618         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 619                 goto cleanup_rings;
 620 #endif
 621
 622         return stream_info;
 623
 624 cleanup_rings:
 625         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 626                 cur_ring = stream_info->stream_rings[cur_stream];
 627                 if (cur_ring) {
 628                         addr = cur_ring->first_seg->dma;
 629                         radix_tree_delete(&stream_info->trb_address_map,
 630                                         addr >> SEGMENT_SHIFT);
 631                         xhci_ring_free(xhci, cur_ring);
 632                         stream_info->stream_rings[cur_stream] = NULL;
 633                 }
 634         }
 635         xhci_free_command(xhci, stream_info->free_streams_command);
 636 cleanup_ctx:
 637         kfree(stream_info->stream_rings);
 638 cleanup_info:
 639         kfree(stream_info);
 640 cleanup_trbs:
 641         xhci->cmd_ring_reserved_trbs--;
 642         return NULL;
 643 }
 644 /*
 645  * Sets the MaxPStreams field and the Linear Stream Array field.
 646  * Sets the dequeue pointer to the stream context array.
 647  */
 648 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 649                 struct xhci_ep_ctx *ep_ctx,
 650                 struct xhci_stream_info *stream_info)
 651 {
 652         u32 max_primary_streams;
 653         /* MaxPStreams is the number of stream context array entries, not the
 654          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 655          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 656          */
 657         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 658         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 659                         1 << (max_primary_streams + 1));
 660         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 661         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 662                                        | EP_HAS_LSA);
 663         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 664 }
 665
 666 /*
 667  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 668  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 669  * not at the beginning of the ring).
 670  */
 671 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 672                 struct xhci_ep_ctx *ep_ctx,
 673                 struct xhci_virt_ep *ep)
 674 {
 675         dma_addr_t addr;
 676         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 677         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 678         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 679 }
 680
 681 /* Frees all stream contexts associated with the endpoint,
 682  *
 683  * Caller should fix the endpoint context streams fields.
 684  */
 685 void xhci_free_stream_info(struct xhci_hcd *xhci,
 686                 struct xhci_stream_info *stream_info)
 687 {
 688         int cur_stream;
 689         struct xhci_ring *cur_ring;
 690         dma_addr_t addr;
 691
 692         if (!stream_info)
 693                 return;
 694
 695         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 696                         cur_stream++) {
 697                 cur_ring = stream_info->stream_rings[cur_stream];
 698                 if (cur_ring) {
 699                         addr = cur_ring->first_seg->dma;
 700                         radix_tree_delete(&stream_info->trb_address_map,
 701                                         addr >> SEGMENT_SHIFT);
 702                         xhci_ring_free(xhci, cur_ring);
 703                         stream_info->stream_rings[cur_stream] = NULL;
 704                 }
 705         }
 706         xhci_free_command(xhci, stream_info->free_streams_command);
 707         xhci->cmd_ring_reserved_trbs--;
 708         if (stream_info->stream_ctx_array)
 709                 xhci_free_stream_ctx(xhci,
 710                                 stream_info->num_stream_ctxs,
 711                                 stream_info->stream_ctx_array,
 712                                 stream_info->ctx_array_dma);
 713
 714         if (stream_info)
 715                 kfree(stream_info->stream_rings);
 716         kfree(stream_info);
 717 }
 718
 719
 720 /***************** Device context manipulation *************************/
 721
 722 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 723                 struct xhci_virt_ep *ep)
 724 {
 725         init_timer(&ep->stop_cmd_timer);
 726         ep->stop_cmd_timer.data = (unsigned long) ep;
 727         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 728         ep->xhci = xhci;
 729 }
 730
 731 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 732                 struct xhci_virt_device *virt_dev,
 733                 int slot_id)
 734 {
 735         struct list_head *tt;
 736         struct list_head *tt_list_head;
 737         struct list_head *tt_next;
 738         struct xhci_tt_bw_info *tt_info;
 739
 740         /* If the device never made it past the Set Address stage,
 741          * it may not have the real_port set correctly.
 742          */
 743         if (virt_dev->real_port == 0 ||
 744                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 745                 xhci_dbg(xhci, "Bad real port.\n");
 746                 return;
 747         }
 748
 749         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 750         if (list_empty(tt_list_head))
 751                 return;
 752
 753         list_for_each(tt, tt_list_head) {
 754                 tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
 755                 if (tt_info->slot_id == slot_id)
 756                         break;
 757         }
 758         /* Cautionary measure in case the hub was disconnected before we
 759          * stored the TT information.
 760          */
 761         if (tt_info->slot_id != slot_id)
 762                 return;
 763
 764         tt_next = tt->next;
 765         tt_info = list_entry(tt, struct xhci_tt_bw_info,
 766                         tt_list);
 767         /* Multi-TT hubs will have more than one entry */
 768         do {
 769                 list_del(tt);
 770                 kfree(tt_info);
 771                 tt = tt_next;
 772                 if (list_empty(tt_list_head))
 773                         break;
 774                 tt_next = tt->next;
 775                 tt_info = list_entry(tt, struct xhci_tt_bw_info,
 776                                 tt_list);
 777         } while (tt_info->slot_id == slot_id);
 778 }
 779
 780 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 781                 struct xhci_virt_device *virt_dev,
 782                 struct usb_device *hdev,
 783                 struct usb_tt *tt, gfp_t mem_flags)
 784 {
 785         struct xhci_tt_bw_info          *tt_info;
 786         unsigned int                    num_ports;
 787         int                             i, j;
 788
 789         if (!tt->multi)
 790                 num_ports = 1;
 791         else
 792                 num_ports = hdev->maxchild;
 793
 794         for (i = 0; i < num_ports; i++, tt_info++) {
 795                 struct xhci_interval_bw_table *bw_table;
 796
 797                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 798                 if (!tt_info)
 799                         goto free_tts;
 800                 INIT_LIST_HEAD(&tt_info->tt_list);
 801                 list_add(&tt_info->tt_list,
 802                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 803                 tt_info->slot_id = virt_dev->udev->slot_id;
 804                 if (tt->multi)
 805                         tt_info->ttport = i+1;
 806                 bw_table = &tt_info->bw_table;
 807                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 808                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 809         }
 810         return 0;
 811
 812 free_tts:
 813         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 814         return -ENOMEM;
 815 }
 816
 817
 818 /* All the xhci_tds in the ring's TD list should be freed at this point.
 819  * Should be called with xhci->lock held if there is any chance the TT lists
 820  * will be manipulated by the configure endpoint, allocate device, or update
 821  * hub functions while this function is removing the TT entries from the list.
 822  */
 823 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 824 {
 825         struct xhci_virt_device *dev;
 826         int i;
 827         int old_active_eps = 0;
 828
 829         /* Slot ID 0 is reserved */
 830         if (slot_id == 0 || !xhci->devs[slot_id])
 831                 return;
 832
 833         dev = xhci->devs[slot_id];
 834         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 835         if (!dev)
 836                 return;
 837
 838         if (dev->tt_info)
 839                 old_active_eps = dev->tt_info->active_eps;
 840
 841         for (i = 0; i < 31; ++i) {
 842                 if (dev->eps[i].ring)
 843                         xhci_ring_free(xhci, dev->eps[i].ring);
 844                 if (dev->eps[i].stream_info)
 845                         xhci_free_stream_info(xhci,
 846                                         dev->eps[i].stream_info);
 847                 /* Endpoints on the TT/root port lists should have been removed
 848                  * when usb_disable_device() was called for the device.
 849                  * We can't drop them anyway, because the udev might have gone
 850                  * away by this point, and we can't tell what speed it was.
 851                  */
 852                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 853                         xhci_warn(xhci, "Slot %u endpoint %u "
 854                                         "not removed from BW list!\n",
 855                                         slot_id, i);
 856         }
 857         /* If this is a hub, free the TT(s) from the TT list */
 858         xhci_free_tt_info(xhci, dev, slot_id);
 859         /* If necessary, update the number of active TTs on this root port */
 860         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 861
 862         if (dev->ring_cache) {
 863                 for (i = 0; i < dev->num_rings_cached; i++)
 864                         xhci_ring_free(xhci, dev->ring_cache[i]);
 865                 kfree(dev->ring_cache);
 866         }
 867
 868         if (dev->in_ctx)
 869                 xhci_free_container_ctx(xhci, dev->in_ctx);
 870         if (dev->out_ctx)
 871                 xhci_free_container_ctx(xhci, dev->out_ctx);
 872
 873         kfree(xhci->devs[slot_id]);
 874         xhci->devs[slot_id] = NULL;
 875 }
 876
 877 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 878                 struct usb_device *udev, gfp_t flags)
 879 {
 880         struct xhci_virt_device *dev;
 881         int i;
 882
 883         /* Slot ID 0 is reserved */
 884         if (slot_id == 0 || xhci->devs[slot_id]) {
 885                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 886                 return 0;
 887         }
 888
 889         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 890         if (!xhci->devs[slot_id])
 891                 return 0;
 892         dev = xhci->devs[slot_id];
 893
 894         /* Allocate the (output) device context that will be used in the HC. */
 895         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 896         if (!dev->out_ctx)
 897                 goto fail;
 898
 899         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 900                         (unsigned long long)dev->out_ctx->dma);
 901
 902         /* Allocate the (input) device context for address device command */
 903         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 904         if (!dev->in_ctx)
 905                 goto fail;
 906
 907         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 908                         (unsigned long long)dev->in_ctx->dma);
 909
 910         /* Initialize the cancellation list and watchdog timers for each ep */
 911         for (i = 0; i < 31; i++) {
 912                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 913                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 914                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 915         }
 916
 917         /* Allocate endpoint 0 ring */
 918         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, 1, TYPE_CTRL, flags);
 919         if (!dev->eps[0].ring)
 920                 goto fail;
 921
 922         /* Allocate pointers to the ring cache */
 923         dev->ring_cache = kzalloc(
 924                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 925                         flags);
 926         if (!dev->ring_cache)
 927                 goto fail;
 928         dev->num_rings_cached = 0;
 929
 930         init_completion(&dev->cmd_completion);
 931         INIT_LIST_HEAD(&dev->cmd_list);
 932         dev->udev = udev;
 933
 934         /* Point to output device context in dcbaa. */
 935         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 936         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 937                  slot_id,
 938                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 939                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 940
 941         return 1;
 942 fail:
 943         xhci_free_virt_device(xhci, slot_id);
 944         return 0;
 945 }
 946
 947 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 948                 struct usb_device *udev)
 949 {
 950         struct xhci_virt_device *virt_dev;
 951         struct xhci_ep_ctx      *ep0_ctx;
 952         struct xhci_ring        *ep_ring;
 953
 954         virt_dev = xhci->devs[udev->slot_id];
 955         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 956         ep_ring = virt_dev->eps[0].ring;
 957         /*
 958          * FIXME we don't keep track of the dequeue pointer very well after a
 959          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 960          * host to our enqueue pointer.  This should only be called after a
 961          * configured device has reset, so all control transfers should have
 962          * been completed or cancelled before the reset.
 963          */
 964         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
 965                                                         ep_ring->enqueue)
 966                                    | ep_ring->cycle_state);
 967 }
 968
 969 /*
 970  * The xHCI roothub may have ports of differing speeds in any order in the port
 971  * status registers.  xhci->port_array provides an array of the port speed for
 972  * each offset into the port status registers.
 973  *
 974  * The xHCI hardware wants to know the roothub port number that the USB device
 975  * is attached to (or the roothub port its ancestor hub is attached to).  All we
 976  * know is the index of that port under either the USB 2.0 or the USB 3.0
 977  * roothub, but that doesn't give us the real index into the HW port status
 978  * registers.  Scan through the xHCI roothub port array, looking for the Nth
 979  * entry of the correct port speed.  Return the port number of that entry.
 980  */
 981 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
 982                 struct usb_device *udev)
 983 {
 984         struct usb_device *top_dev;
 985         unsigned int num_similar_speed_ports;
 986         unsigned int faked_port_num;
 987         int i;
 988
 989         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 990                         top_dev = top_dev->parent)
 991                 /* Found device below root hub */;
 992         faked_port_num = top_dev->portnum;
 993         for (i = 0, num_similar_speed_ports = 0;
 994                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 995                 u8 port_speed = xhci->port_array[i];
 996
 997                 /*
 998                  * Skip ports that don't have known speeds, or have duplicate
 999                  * Extended Capabilities port speed entries.
1000                  */
1001                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1002                         continue;
1003
1004                 /*
1005                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1006                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1007                  * matches the device speed, it's a similar speed port.
1008                  */
1009                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
1010                         num_similar_speed_ports++;
1011                 if (num_similar_speed_ports == faked_port_num)
1012                         /* Roothub ports are numbered from 1 to N */
1013                         return i+1;
1014         }
1015         return 0;
1016 }
1017
1018 /* Setup an xHCI virtual device for a Set Address command */
1019 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1020 {
1021         struct xhci_virt_device *dev;
1022         struct xhci_ep_ctx      *ep0_ctx;
1023         struct xhci_slot_ctx    *slot_ctx;
1024         u32                     port_num;
1025         struct usb_device *top_dev;
1026
1027         dev = xhci->devs[udev->slot_id];
1028         /* Slot ID 0 is reserved */
1029         if (udev->slot_id == 0 || !dev) {
1030                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1031                                 udev->slot_id);
1032                 return -EINVAL;
1033         }
1034         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1035         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1036
1037         /* 3) Only the control endpoint is valid - one endpoint context */
1038         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1039         switch (udev->speed) {
1040         case USB_SPEED_SUPER:
1041                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1042                 break;
1043         case USB_SPEED_HIGH:
1044                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1045                 break;
1046         case USB_SPEED_FULL:
1047                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1048                 break;
1049         case USB_SPEED_LOW:
1050                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1051                 break;
1052         case USB_SPEED_WIRELESS:
1053                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1054                 return -EINVAL;
1055                 break;
1056         default:
1057                 /* Speed was set earlier, this shouldn't happen. */
1058                 BUG();
1059         }
1060         /* Find the root hub port this device is under */
1061         port_num = xhci_find_real_port_number(xhci, udev);
1062         if (!port_num)
1063                 return -EINVAL;
1064         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1065         /* Set the port number in the virtual_device to the faked port number */
1066         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1067                         top_dev = top_dev->parent)
1068                 /* Found device below root hub */;
1069         dev->fake_port = top_dev->portnum;
1070         dev->real_port = port_num;
1071         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1072         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1073
1074         /* Find the right bandwidth table that this device will be a part of.
1075          * If this is a full speed device attached directly to a root port (or a
1076          * decendent of one), it counts as a primary bandwidth domain, not a
1077          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1078          * will never be created for the HS root hub.
1079          */
1080         if (!udev->tt || !udev->tt->hub->parent) {
1081                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1082         } else {
1083                 struct xhci_root_port_bw_info *rh_bw;
1084                 struct xhci_tt_bw_info *tt_bw;
1085
1086                 rh_bw = &xhci->rh_bw[port_num - 1];
1087                 /* Find the right TT. */
1088                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1089                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1090                                 continue;
1091
1092                         if (!dev->udev->tt->multi ||
1093                                         (udev->tt->multi &&
1094                                          tt_bw->ttport == dev->udev->ttport)) {
1095                                 dev->bw_table = &tt_bw->bw_table;
1096                                 dev->tt_info = tt_bw;
1097                                 break;
1098                         }
1099                 }
1100                 if (!dev->tt_info)
1101                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1102         }
1103
1104         /* Is this a LS/FS device under an external HS hub? */
1105         if (udev->tt && udev->tt->hub->parent) {
1106                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1107                                                 (udev->ttport << 8));
1108                 if (udev->tt->multi)
1109                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1110         }
1111         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1112         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1113
1114         /* Step 4 - ring already allocated */
1115         /* Step 5 */
1116         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1117         /*
1118          * XXX: Not sure about wireless USB devices.
1119          */
1120         switch (udev->speed) {
1121         case USB_SPEED_SUPER:
1122                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1123                 break;
1124         case USB_SPEED_HIGH:
1125         /* USB core guesses at a 64-byte max packet first for FS devices */
1126         case USB_SPEED_FULL:
1127                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1128                 break;
1129         case USB_SPEED_LOW:
1130                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1131                 break;
1132         case USB_SPEED_WIRELESS:
1133                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1134                 return -EINVAL;
1135                 break;
1136         default:
1137                 /* New speed? */
1138                 BUG();
1139         }
1140         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1141         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1142
1143         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1144                                    dev->eps[0].ring->cycle_state);
1145
1146         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1147
1148         return 0;
1149 }
1150
1151 /*
1152  * Convert interval expressed as 2^(bInterval - 1) == interval into
1153  * straight exponent value 2^n == interval.
1154  *
1155  */
1156 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1157                 struct usb_host_endpoint *ep)
1158 {
1159         unsigned int interval;
1160
1161         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1162         if (interval != ep->desc.bInterval - 1)
1163                 dev_warn(&udev->dev,
1164                          "ep %#x - rounding interval to %d %sframes\n",
1165                          ep->desc.bEndpointAddress,
1166                          1 << interval,
1167                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1168
1169         if (udev->speed == USB_SPEED_FULL) {
1170                 /*
1171                  * Full speed isoc endpoints specify interval in frames,
1172                  * not microframes. We are using microframes everywhere,
1173                  * so adjust accordingly.
1174                  */
1175                 interval += 3;  /* 1 frame = 2^3 uframes */
1176         }
1177
1178         return interval;
1179 }
1180
1181 /*
1182  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1183  * microframes, rounded down to nearest power of 2.
1184  */
1185 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1186                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1187                 unsigned int min_exponent, unsigned int max_exponent)
1188 {
1189         unsigned int interval;
1190
1191         interval = fls(desc_interval) - 1;
1192         interval = clamp_val(interval, min_exponent, max_exponent);
1193         if ((1 << interval) != desc_interval)
1194                 dev_warn(&udev->dev,
1195                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1196                          ep->desc.bEndpointAddress,
1197                          1 << interval,
1198                          desc_interval);
1199
1200         return interval;
1201 }
1202
1203 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1204                 struct usb_host_endpoint *ep)
1205 {
1206         return xhci_microframes_to_exponent(udev, ep,
1207                         ep->desc.bInterval, 0, 15);
1208 }
1209
1210
1211 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1212                 struct usb_host_endpoint *ep)
1213 {
1214         return xhci_microframes_to_exponent(udev, ep,
1215                         ep->desc.bInterval * 8, 3, 10);
1216 }
1217
1218 /* Return the polling or NAK interval.
1219  *
1220  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1221  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1222  *
1223  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1224  * is set to 0.
1225  */
1226 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1227                 struct usb_host_endpoint *ep)
1228 {
1229         unsigned int interval = 0;
1230
1231         switch (udev->speed) {
1232         case USB_SPEED_HIGH:
1233                 /* Max NAK rate */
1234                 if (usb_endpoint_xfer_control(&ep->desc) ||
1235                     usb_endpoint_xfer_bulk(&ep->desc)) {
1236                         interval = xhci_parse_microframe_interval(udev, ep);
1237                         break;
1238                 }
1239                 /* Fall through - SS and HS isoc/int have same decoding */
1240
1241         case USB_SPEED_SUPER:
1242                 if (usb_endpoint_xfer_int(&ep->desc) ||
1243                     usb_endpoint_xfer_isoc(&ep->desc)) {
1244                         interval = xhci_parse_exponent_interval(udev, ep);
1245                 }
1246                 break;
1247
1248         case USB_SPEED_FULL:
1249                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1250                         interval = xhci_parse_exponent_interval(udev, ep);
1251                         break;
1252                 }
1253                 /*
1254                  * Fall through for interrupt endpoint interval decoding
1255                  * since it uses the same rules as low speed interrupt
1256                  * endpoints.
1257                  */
1258
1259         case USB_SPEED_LOW:
1260                 if (usb_endpoint_xfer_int(&ep->desc) ||
1261                     usb_endpoint_xfer_isoc(&ep->desc)) {
1262
1263                         interval = xhci_parse_frame_interval(udev, ep);
1264                 }
1265                 break;
1266
1267         default:
1268                 BUG();
1269         }
1270         return EP_INTERVAL(interval);
1271 }
1272
1273 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1274  * High speed endpoint descriptors can define "the number of additional
1275  * transaction opportunities per microframe", but that goes in the Max Burst
1276  * endpoint context field.
1277  */
1278 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1279                 struct usb_host_endpoint *ep)
1280 {
1281         if (udev->speed != USB_SPEED_SUPER ||
1282                         !usb_endpoint_xfer_isoc(&ep->desc))
1283                 return 0;
1284         return ep->ss_ep_comp.bmAttributes;
1285 }
1286
1287 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1288                 struct usb_host_endpoint *ep)
1289 {
1290         int in;
1291         u32 type;
1292
1293         in = usb_endpoint_dir_in(&ep->desc);
1294         if (usb_endpoint_xfer_control(&ep->desc)) {
1295                 type = EP_TYPE(CTRL_EP);
1296         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1297                 if (in)
1298                         type = EP_TYPE(BULK_IN_EP);
1299                 else
1300                         type = EP_TYPE(BULK_OUT_EP);
1301         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1302                 if (in)
1303                         type = EP_TYPE(ISOC_IN_EP);
1304                 else
1305                         type = EP_TYPE(ISOC_OUT_EP);
1306         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1307                 if (in)
1308                         type = EP_TYPE(INT_IN_EP);
1309                 else
1310                         type = EP_TYPE(INT_OUT_EP);
1311         } else {
1312                 BUG();
1313         }
1314         return type;
1315 }
1316
1317 /* Return the maximum endpoint service interval time (ESIT) payload.
1318  * Basically, this is the maxpacket size, multiplied by the burst size
1319  * and mult size.
1320  */
1321 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1322                 struct usb_device *udev,
1323                 struct usb_host_endpoint *ep)
1324 {
1325         int max_burst;
1326         int max_packet;
1327
1328         /* Only applies for interrupt or isochronous endpoints */
1329         if (usb_endpoint_xfer_control(&ep->desc) ||
1330                         usb_endpoint_xfer_bulk(&ep->desc))
1331                 return 0;
1332
1333         if (udev->speed == USB_SPEED_SUPER)
1334                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1335
1336         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1337         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1338         /* A 0 in max burst means 1 transfer per ESIT */
1339         return max_packet * (max_burst + 1);
1340 }
1341
1342 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1343  * Drivers will have to call usb_alloc_streams() to do that.
1344  */
1345 int xhci_endpoint_init(struct xhci_hcd *xhci,
1346                 struct xhci_virt_device *virt_dev,
1347                 struct usb_device *udev,
1348                 struct usb_host_endpoint *ep,
1349                 gfp_t mem_flags)
1350 {
1351         unsigned int ep_index;
1352         struct xhci_ep_ctx *ep_ctx;
1353         struct xhci_ring *ep_ring;
1354         unsigned int max_packet;
1355         unsigned int max_burst;
1356         enum xhci_ring_type type;
1357         u32 max_esit_payload;
1358
1359         ep_index = xhci_get_endpoint_index(&ep->desc);
1360         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1361
1362         type = usb_endpoint_type(&ep->desc);
1363         /* Set up the endpoint ring */
1364         /*
1365          * Isochronous endpoint ring needs bigger size because one isoc URB
1366          * carries multiple packets and it will insert multiple tds to the
1367          * ring.
1368          * This should be replaced with dynamic ring resizing in the future.
1369          */
1370         if (usb_endpoint_xfer_isoc(&ep->desc))
1371                 virt_dev->eps[ep_index].new_ring =
1372                         xhci_ring_alloc(xhci, 8, 1, type, mem_flags);
1373         else
1374                 virt_dev->eps[ep_index].new_ring =
1375                         xhci_ring_alloc(xhci, 1, 1, type, mem_flags);
1376         if (!virt_dev->eps[ep_index].new_ring) {
1377                 /* Attempt to use the ring cache */
1378                 if (virt_dev->num_rings_cached == 0)
1379                         return -ENOMEM;
1380                 virt_dev->eps[ep_index].new_ring =
1381                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1382                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1383                 virt_dev->num_rings_cached--;
1384                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1385                                         1, type);
1386         }
1387         virt_dev->eps[ep_index].skip = false;
1388         ep_ring = virt_dev->eps[ep_index].new_ring;
1389         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1390
1391         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1392                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1393
1394         /* FIXME dig Mult and streams info out of ep companion desc */
1395
1396         /* Allow 3 retries for everything but isoc;
1397          * CErr shall be set to 0 for Isoch endpoints.
1398          */
1399         if (!usb_endpoint_xfer_isoc(&ep->desc))
1400                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1401         else
1402                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1403
1404         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1405
1406         /* Set the max packet size and max burst */
1407         switch (udev->speed) {
1408         case USB_SPEED_SUPER:
1409                 max_packet = usb_endpoint_maxp(&ep->desc);
1410                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1411                 /* dig out max burst from ep companion desc */
1412                 max_packet = ep->ss_ep_comp.bMaxBurst;
1413                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1414                 break;
1415         case USB_SPEED_HIGH:
1416                 /* bits 11:12 specify the number of additional transaction
1417                  * opportunities per microframe (USB 2.0, section 9.6.6)
1418                  */
1419                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1420                                 usb_endpoint_xfer_int(&ep->desc)) {
1421                         max_burst = (usb_endpoint_maxp(&ep->desc)
1422                                      & 0x1800) >> 11;
1423                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1424                 }
1425                 /* Fall through */
1426         case USB_SPEED_FULL:
1427         case USB_SPEED_LOW:
1428                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1429                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1430                 break;
1431         default:
1432                 BUG();
1433         }
1434         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1435         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1436
1437         /*
1438          * XXX no idea how to calculate the average TRB buffer length for bulk
1439          * endpoints, as the driver gives us no clue how big each scatter gather
1440          * list entry (or buffer) is going to be.
1441          *
1442          * For isochronous and interrupt endpoints, we set it to the max
1443          * available, until we have new API in the USB core to allow drivers to
1444          * declare how much bandwidth they actually need.
1445          *
1446          * Normally, it would be calculated by taking the total of the buffer
1447          * lengths in the TD and then dividing by the number of TRBs in a TD,
1448          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1449          * use Event Data TRBs, and we don't chain in a link TRB on short
1450          * transfers, we're basically dividing by 1.
1451          *
1452          * xHCI 1.0 specification indicates that the Average TRB Length should
1453          * be set to 8 for control endpoints.
1454          */
1455         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1456                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1457         else
1458                 ep_ctx->tx_info |=
1459                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1460
1461         /* FIXME Debug endpoint context */
1462         return 0;
1463 }
1464
1465 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1466                 struct xhci_virt_device *virt_dev,
1467                 struct usb_host_endpoint *ep)
1468 {
1469         unsigned int ep_index;
1470         struct xhci_ep_ctx *ep_ctx;
1471
1472         ep_index = xhci_get_endpoint_index(&ep->desc);
1473         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1474
1475         ep_ctx->ep_info = 0;
1476         ep_ctx->ep_info2 = 0;
1477         ep_ctx->deq = 0;
1478         ep_ctx->tx_info = 0;
1479         /* Don't free the endpoint ring until the set interface or configuration
1480          * request succeeds.
1481          */
1482 }
1483
1484 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1485 {
1486         bw_info->ep_interval = 0;
1487         bw_info->mult = 0;
1488         bw_info->num_packets = 0;
1489         bw_info->max_packet_size = 0;
1490         bw_info->type = 0;
1491         bw_info->max_esit_payload = 0;
1492 }
1493
1494 void xhci_update_bw_info(struct xhci_hcd *xhci,
1495                 struct xhci_container_ctx *in_ctx,
1496                 struct xhci_input_control_ctx *ctrl_ctx,
1497                 struct xhci_virt_device *virt_dev)
1498 {
1499         struct xhci_bw_info *bw_info;
1500         struct xhci_ep_ctx *ep_ctx;
1501         unsigned int ep_type;
1502         int i;
1503
1504         for (i = 1; i < 31; ++i) {
1505                 bw_info = &virt_dev->eps[i].bw_info;
1506
1507                 /* We can't tell what endpoint type is being dropped, but
1508                  * unconditionally clearing the bandwidth info for non-periodic
1509                  * endpoints should be harmless because the info will never be
1510                  * set in the first place.
1511                  */
1512                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1513                         /* Dropped endpoint */
1514                         xhci_clear_endpoint_bw_info(bw_info);
1515                         continue;
1516                 }
1517
1518                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1519                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1520                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1521
1522                         /* Ignore non-periodic endpoints */
1523                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1524                                         ep_type != ISOC_IN_EP &&
1525                                         ep_type != INT_IN_EP)
1526                                 continue;
1527
1528                         /* Added or changed endpoint */
1529                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1530                                         le32_to_cpu(ep_ctx->ep_info));
1531                         /* Number of packets and mult are zero-based in the
1532                          * input context, but we want one-based for the
1533                          * interval table.
1534                          */
1535                         bw_info->mult = CTX_TO_EP_MULT(
1536                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1537                         bw_info->num_packets = CTX_TO_MAX_BURST(
1538                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1539                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1540                                         le32_to_cpu(ep_ctx->ep_info2));
1541                         bw_info->type = ep_type;
1542                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1543                                         le32_to_cpu(ep_ctx->tx_info));
1544                 }
1545         }
1546 }
1547
1548 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1549  * Useful when you want to change one particular aspect of the endpoint and then
1550  * issue a configure endpoint command.
1551  */
1552 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1553                 struct xhci_container_ctx *in_ctx,
1554                 struct xhci_container_ctx *out_ctx,
1555                 unsigned int ep_index)
1556 {
1557         struct xhci_ep_ctx *out_ep_ctx;
1558         struct xhci_ep_ctx *in_ep_ctx;
1559
1560         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1561         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1562
1563         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1564         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1565         in_ep_ctx->deq = out_ep_ctx->deq;
1566         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1567 }
1568
1569 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1570  * Useful when you want to change one particular aspect of the endpoint and then
1571  * issue a configure endpoint command.  Only the context entries field matters,
1572  * but we'll copy the whole thing anyway.
1573  */
1574 void xhci_slot_copy(struct xhci_hcd *xhci,
1575                 struct xhci_container_ctx *in_ctx,
1576                 struct xhci_container_ctx *out_ctx)
1577 {
1578         struct xhci_slot_ctx *in_slot_ctx;
1579         struct xhci_slot_ctx *out_slot_ctx;
1580
1581         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1582         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1583
1584         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1585         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1586         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1587         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1588 }
1589
1590 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1591 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1592 {
1593         int i;
1594         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1595         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1596
1597         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1598
1599         if (!num_sp)
1600                 return 0;
1601
1602         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1603         if (!xhci->scratchpad)
1604                 goto fail_sp;
1605
1606         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1607                                      num_sp * sizeof(u64),
1608                                      &xhci->scratchpad->sp_dma, flags);
1609         if (!xhci->scratchpad->sp_array)
1610                 goto fail_sp2;
1611
1612         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1613         if (!xhci->scratchpad->sp_buffers)
1614                 goto fail_sp3;
1615
1616         xhci->scratchpad->sp_dma_buffers =
1617                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1618
1619         if (!xhci->scratchpad->sp_dma_buffers)
1620                 goto fail_sp4;
1621
1622         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1623         for (i = 0; i < num_sp; i++) {
1624                 dma_addr_t dma;
1625                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1626                                 flags);
1627                 if (!buf)
1628                         goto fail_sp5;
1629
1630                 xhci->scratchpad->sp_array[i] = dma;
1631                 xhci->scratchpad->sp_buffers[i] = buf;
1632                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1633         }
1634
1635         return 0;
1636
1637  fail_sp5:
1638         for (i = i - 1; i >= 0; i--) {
1639                 dma_free_coherent(dev, xhci->page_size,
1640                                     xhci->scratchpad->sp_buffers[i],
1641                                     xhci->scratchpad->sp_dma_buffers[i]);
1642         }
1643         kfree(xhci->scratchpad->sp_dma_buffers);
1644
1645  fail_sp4:
1646         kfree(xhci->scratchpad->sp_buffers);
1647
1648  fail_sp3:
1649         dma_free_coherent(dev, num_sp * sizeof(u64),
1650                             xhci->scratchpad->sp_array,
1651                             xhci->scratchpad->sp_dma);
1652
1653  fail_sp2:
1654         kfree(xhci->scratchpad);
1655         xhci->scratchpad = NULL;
1656
1657  fail_sp:
1658         return -ENOMEM;
1659 }
1660
1661 static void scratchpad_free(struct xhci_hcd *xhci)
1662 {
1663         int num_sp;
1664         int i;
1665         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1666
1667         if (!xhci->scratchpad)
1668                 return;
1669
1670         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1671
1672         for (i = 0; i < num_sp; i++) {
1673                 dma_free_coherent(&pdev->dev, xhci->page_size,
1674                                     xhci->scratchpad->sp_buffers[i],
1675                                     xhci->scratchpad->sp_dma_buffers[i]);
1676         }
1677         kfree(xhci->scratchpad->sp_dma_buffers);
1678         kfree(xhci->scratchpad->sp_buffers);
1679         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1680                             xhci->scratchpad->sp_array,
1681                             xhci->scratchpad->sp_dma);
1682         kfree(xhci->scratchpad);
1683         xhci->scratchpad = NULL;
1684 }
1685
1686 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1687                 bool allocate_in_ctx, bool allocate_completion,
1688                 gfp_t mem_flags)
1689 {
1690         struct xhci_command *command;
1691
1692         command = kzalloc(sizeof(*command), mem_flags);
1693         if (!command)
1694                 return NULL;
1695
1696         if (allocate_in_ctx) {
1697                 command->in_ctx =
1698                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1699                                         mem_flags);
1700                 if (!command->in_ctx) {
1701                         kfree(command);
1702                         return NULL;
1703                 }
1704         }
1705
1706         if (allocate_completion) {
1707                 command->completion =
1708                         kzalloc(sizeof(struct completion), mem_flags);
1709                 if (!command->completion) {
1710                         xhci_free_container_ctx(xhci, command->in_ctx);
1711                         kfree(command);
1712                         return NULL;
1713                 }
1714                 init_completion(command->completion);
1715         }
1716
1717         command->status = 0;
1718         INIT_LIST_HEAD(&command->cmd_list);
1719         return command;
1720 }
1721
1722 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1723 {
1724         if (urb_priv) {
1725                 kfree(urb_priv->td[0]);
1726                 kfree(urb_priv);
1727         }
1728 }
1729
1730 void xhci_free_command(struct xhci_hcd *xhci,
1731                 struct xhci_command *command)
1732 {
1733         xhci_free_container_ctx(xhci,
1734                         command->in_ctx);
1735         kfree(command->completion);
1736         kfree(command);
1737 }
1738
1739 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1740 {
1741         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1742         struct dev_info *dev_info, *next;
1743         unsigned long   flags;
1744         int size;
1745         int i;
1746
1747         /* Free the Event Ring Segment Table and the actual Event Ring */
1748         if (xhci->ir_set) {
1749                 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
1750                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
1751                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
1752         }
1753         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1754         if (xhci->erst.entries)
1755                 dma_free_coherent(&pdev->dev, size,
1756                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1757         xhci->erst.entries = NULL;
1758         xhci_dbg(xhci, "Freed ERST\n");
1759         if (xhci->event_ring)
1760                 xhci_ring_free(xhci, xhci->event_ring);
1761         xhci->event_ring = NULL;
1762         xhci_dbg(xhci, "Freed event ring\n");
1763
1764         xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
1765         if (xhci->cmd_ring)
1766                 xhci_ring_free(xhci, xhci->cmd_ring);
1767         xhci->cmd_ring = NULL;
1768         xhci_dbg(xhci, "Freed command ring\n");
1769
1770         for (i = 1; i < MAX_HC_SLOTS; ++i)
1771                 xhci_free_virt_device(xhci, i);
1772
1773         if (xhci->segment_pool)
1774                 dma_pool_destroy(xhci->segment_pool);
1775         xhci->segment_pool = NULL;
1776         xhci_dbg(xhci, "Freed segment pool\n");
1777
1778         if (xhci->device_pool)
1779                 dma_pool_destroy(xhci->device_pool);
1780         xhci->device_pool = NULL;
1781         xhci_dbg(xhci, "Freed device context pool\n");
1782
1783         if (xhci->small_streams_pool)
1784                 dma_pool_destroy(xhci->small_streams_pool);
1785         xhci->small_streams_pool = NULL;
1786         xhci_dbg(xhci, "Freed small stream array pool\n");
1787
1788         if (xhci->medium_streams_pool)
1789                 dma_pool_destroy(xhci->medium_streams_pool);
1790         xhci->medium_streams_pool = NULL;
1791         xhci_dbg(xhci, "Freed medium stream array pool\n");
1792
1793         xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
1794         if (xhci->dcbaa)
1795                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1796                                 xhci->dcbaa, xhci->dcbaa->dma);
1797         xhci->dcbaa = NULL;
1798
1799         scratchpad_free(xhci);
1800
1801         spin_lock_irqsave(&xhci->lock, flags);
1802         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1803                 list_del(&dev_info->list);
1804                 kfree(dev_info);
1805         }
1806         spin_unlock_irqrestore(&xhci->lock, flags);
1807
1808         xhci->num_usb2_ports = 0;
1809         xhci->num_usb3_ports = 0;
1810         kfree(xhci->usb2_ports);
1811         kfree(xhci->usb3_ports);
1812         kfree(xhci->port_array);
1813         kfree(xhci->rh_bw);
1814
1815         xhci->page_size = 0;
1816         xhci->page_shift = 0;
1817         xhci->bus_state[0].bus_suspended = 0;
1818         xhci->bus_state[1].bus_suspended = 0;
1819 }
1820
1821 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1822                 struct xhci_segment *input_seg,
1823                 union xhci_trb *start_trb,
1824                 union xhci_trb *end_trb,
1825                 dma_addr_t input_dma,
1826                 struct xhci_segment *result_seg,
1827                 char *test_name, int test_number)
1828 {
1829         unsigned long long start_dma;
1830         unsigned long long end_dma;
1831         struct xhci_segment *seg;
1832
1833         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1834         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1835
1836         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1837         if (seg != result_seg) {
1838                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1839                                 test_name, test_number);
1840                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1841                                 "input DMA 0x%llx\n",
1842                                 input_seg,
1843                                 (unsigned long long) input_dma);
1844                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1845                                 "ending TRB %p (0x%llx DMA)\n",
1846                                 start_trb, start_dma,
1847                                 end_trb, end_dma);
1848                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1849                                 result_seg, seg);
1850                 return -1;
1851         }
1852         return 0;
1853 }
1854
1855 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1856 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1857 {
1858         struct {
1859                 dma_addr_t              input_dma;
1860                 struct xhci_segment     *result_seg;
1861         } simple_test_vector [] = {
1862                 /* A zeroed DMA field should fail */
1863                 { 0, NULL },
1864                 /* One TRB before the ring start should fail */
1865                 { xhci->event_ring->first_seg->dma - 16, NULL },
1866                 /* One byte before the ring start should fail */
1867                 { xhci->event_ring->first_seg->dma - 1, NULL },
1868                 /* Starting TRB should succeed */
1869                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1870                 /* Ending TRB should succeed */
1871                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1872                         xhci->event_ring->first_seg },
1873                 /* One byte after the ring end should fail */
1874                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1875                 /* One TRB after the ring end should fail */
1876                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1877                 /* An address of all ones should fail */
1878                 { (dma_addr_t) (~0), NULL },
1879         };
1880         struct {
1881                 struct xhci_segment     *input_seg;
1882                 union xhci_trb          *start_trb;
1883                 union xhci_trb          *end_trb;
1884                 dma_addr_t              input_dma;
1885                 struct xhci_segment     *result_seg;
1886         } complex_test_vector [] = {
1887                 /* Test feeding a valid DMA address from a different ring */
1888                 {       .input_seg = xhci->event_ring->first_seg,
1889                         .start_trb = xhci->event_ring->first_seg->trbs,
1890                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1891                         .input_dma = xhci->cmd_ring->first_seg->dma,
1892                         .result_seg = NULL,
1893                 },
1894                 /* Test feeding a valid end TRB from a different ring */
1895                 {       .input_seg = xhci->event_ring->first_seg,
1896                         .start_trb = xhci->event_ring->first_seg->trbs,
1897                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1898                         .input_dma = xhci->cmd_ring->first_seg->dma,
1899                         .result_seg = NULL,
1900                 },
1901                 /* Test feeding a valid start and end TRB from a different ring */
1902                 {       .input_seg = xhci->event_ring->first_seg,
1903                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1904                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1905                         .input_dma = xhci->cmd_ring->first_seg->dma,
1906                         .result_seg = NULL,
1907                 },
1908                 /* TRB in this ring, but after this TD */
1909                 {       .input_seg = xhci->event_ring->first_seg,
1910                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1911                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1912                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1913                         .result_seg = NULL,
1914                 },
1915                 /* TRB in this ring, but before this TD */
1916                 {       .input_seg = xhci->event_ring->first_seg,
1917                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1918                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1919                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1920                         .result_seg = NULL,
1921                 },
1922                 /* TRB in this ring, but after this wrapped TD */
1923                 {       .input_seg = xhci->event_ring->first_seg,
1924                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1925                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1926                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1927                         .result_seg = NULL,
1928                 },
1929                 /* TRB in this ring, but before this wrapped TD */
1930                 {       .input_seg = xhci->event_ring->first_seg,
1931                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1932                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1933                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1934                         .result_seg = NULL,
1935                 },
1936                 /* TRB not in this ring, and we have a wrapped TD */
1937                 {       .input_seg = xhci->event_ring->first_seg,
1938                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1939                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1940                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1941                         .result_seg = NULL,
1942                 },
1943         };
1944
1945         unsigned int num_tests;
1946         int i, ret;
1947
1948         num_tests = ARRAY_SIZE(simple_test_vector);
1949         for (i = 0; i < num_tests; i++) {
1950                 ret = xhci_test_trb_in_td(xhci,
1951                                 xhci->event_ring->first_seg,
1952                                 xhci->event_ring->first_seg->trbs,
1953                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1954                                 simple_test_vector[i].input_dma,
1955                                 simple_test_vector[i].result_seg,
1956                                 "Simple", i);
1957                 if (ret < 0)
1958                         return ret;
1959         }
1960
1961         num_tests = ARRAY_SIZE(complex_test_vector);
1962         for (i = 0; i < num_tests; i++) {
1963                 ret = xhci_test_trb_in_td(xhci,
1964                                 complex_test_vector[i].input_seg,
1965                                 complex_test_vector[i].start_trb,
1966                                 complex_test_vector[i].end_trb,
1967                                 complex_test_vector[i].input_dma,
1968                                 complex_test_vector[i].result_seg,
1969                                 "Complex", i);
1970                 if (ret < 0)
1971                         return ret;
1972         }
1973         xhci_dbg(xhci, "TRB math tests passed.\n");
1974         return 0;
1975 }
1976
1977 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1978 {
1979         u64 temp;
1980         dma_addr_t deq;
1981
1982         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1983                         xhci->event_ring->dequeue);
1984         if (deq == 0 && !in_interrupt())
1985                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1986                                 "dequeue ptr.\n");
1987         /* Update HC event ring dequeue pointer */
1988         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1989         temp &= ERST_PTR_MASK;
1990         /* Don't clear the EHB bit (which is RW1C) because
1991          * there might be more events to service.
1992          */
1993         temp &= ~ERST_EHB;
1994         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1995                         "preserving EHB bit\n");
1996         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1997                         &xhci->ir_set->erst_dequeue);
1998 }
1999
2000 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2001                 __le32 __iomem *addr, u8 major_revision)
2002 {
2003         u32 temp, port_offset, port_count;
2004         int i;
2005
2006         if (major_revision > 0x03) {
2007                 xhci_warn(xhci, "Ignoring unknown port speed, "
2008                                 "Ext Cap %p, revision = 0x%x\n",
2009                                 addr, major_revision);
2010                 /* Ignoring port protocol we can't understand. FIXME */
2011                 return;
2012         }
2013
2014         /* Port offset and count in the third dword, see section 7.2 */
2015         temp = xhci_readl(xhci, addr + 2);
2016         port_offset = XHCI_EXT_PORT_OFF(temp);
2017         port_count = XHCI_EXT_PORT_COUNT(temp);
2018         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2019                         "count = %u, revision = 0x%x\n",
2020                         addr, port_offset, port_count, major_revision);
2021         /* Port count includes the current port offset */
2022         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2023                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2024                 return;
2025
2026         /* Check the host's USB2 LPM capability */
2027         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2028                         (temp & XHCI_L1C)) {
2029                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2030                 xhci->sw_lpm_support = 1;
2031         }
2032
2033         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2034                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2035                 xhci->sw_lpm_support = 1;
2036                 if (temp & XHCI_HLC) {
2037                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2038                         xhci->hw_lpm_support = 1;
2039                 }
2040         }
2041
2042         port_offset--;
2043         for (i = port_offset; i < (port_offset + port_count); i++) {
2044                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2045                 if (xhci->port_array[i] != 0) {
2046                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2047                                         " port %u\n", addr, i);
2048                         xhci_warn(xhci, "Port was marked as USB %u, "
2049                                         "duplicated as USB %u\n",
2050                                         xhci->port_array[i], major_revision);
2051                         /* Only adjust the roothub port counts if we haven't
2052                          * found a similar duplicate.
2053                          */
2054                         if (xhci->port_array[i] != major_revision &&
2055                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2056                                 if (xhci->port_array[i] == 0x03)
2057                                         xhci->num_usb3_ports--;
2058                                 else
2059                                         xhci->num_usb2_ports--;
2060                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2061                         }
2062                         /* FIXME: Should we disable the port? */
2063                         continue;
2064                 }
2065                 xhci->port_array[i] = major_revision;
2066                 if (major_revision == 0x03)
2067                         xhci->num_usb3_ports++;
2068                 else
2069                         xhci->num_usb2_ports++;
2070         }
2071         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2072 }
2073
2074 /*
2075  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2076  * specify what speeds each port is supposed to be.  We can't count on the port
2077  * speed bits in the PORTSC register being correct until a device is connected,
2078  * but we need to set up the two fake roothubs with the correct number of USB
2079  * 3.0 and USB 2.0 ports at host controller initialization time.
2080  */
2081 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2082 {
2083         __le32 __iomem *addr;
2084         u32 offset;
2085         unsigned int num_ports;
2086         int i, j, port_index;
2087
2088         addr = &xhci->cap_regs->hcc_params;
2089         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2090         if (offset == 0) {
2091                 xhci_err(xhci, "No Extended Capability registers, "
2092                                 "unable to set up roothub.\n");
2093                 return -ENODEV;
2094         }
2095
2096         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2097         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2098         if (!xhci->port_array)
2099                 return -ENOMEM;
2100
2101         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2102         if (!xhci->rh_bw)
2103                 return -ENOMEM;
2104         for (i = 0; i < num_ports; i++) {
2105                 struct xhci_interval_bw_table *bw_table;
2106
2107                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2108                 bw_table = &xhci->rh_bw[i].bw_table;
2109                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2110                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2111         }
2112
2113         /*
2114          * For whatever reason, the first capability offset is from the
2115          * capability register base, not from the HCCPARAMS register.
2116          * See section 5.3.6 for offset calculation.
2117          */
2118         addr = &xhci->cap_regs->hc_capbase + offset;
2119         while (1) {
2120                 u32 cap_id;
2121
2122                 cap_id = xhci_readl(xhci, addr);
2123                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2124                         xhci_add_in_port(xhci, num_ports, addr,
2125                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2126                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2127                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2128                                 == num_ports)
2129                         break;
2130                 /*
2131                  * Once you're into the Extended Capabilities, the offset is
2132                  * always relative to the register holding the offset.
2133                  */
2134                 addr += offset;
2135         }
2136
2137         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2138                 xhci_warn(xhci, "No ports on the roothubs?\n");
2139                 return -ENODEV;
2140         }
2141         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2142                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2143
2144         /* Place limits on the number of roothub ports so that the hub
2145          * descriptors aren't longer than the USB core will allocate.
2146          */
2147         if (xhci->num_usb3_ports > 15) {
2148                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2149                 xhci->num_usb3_ports = 15;
2150         }
2151         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2152                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2153                                 USB_MAXCHILDREN);
2154                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2155         }
2156
2157         /*
2158          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2159          * Not sure how the USB core will handle a hub with no ports...
2160          */
2161         if (xhci->num_usb2_ports) {
2162                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2163                                 xhci->num_usb2_ports, flags);
2164                 if (!xhci->usb2_ports)
2165                         return -ENOMEM;
2166
2167                 port_index = 0;
2168                 for (i = 0; i < num_ports; i++) {
2169                         if (xhci->port_array[i] == 0x03 ||
2170                                         xhci->port_array[i] == 0 ||
2171                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2172                                 continue;
2173
2174                         xhci->usb2_ports[port_index] =
2175                                 &xhci->op_regs->port_status_base +
2176                                 NUM_PORT_REGS*i;
2177                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2178                                         "addr = %p\n", i,
2179                                         xhci->usb2_ports[port_index]);
2180                         port_index++;
2181                         if (port_index == xhci->num_usb2_ports)
2182                                 break;
2183                 }
2184         }
2185         if (xhci->num_usb3_ports) {
2186                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2187                                 xhci->num_usb3_ports, flags);
2188                 if (!xhci->usb3_ports)
2189                         return -ENOMEM;
2190
2191                 port_index = 0;
2192                 for (i = 0; i < num_ports; i++)
2193                         if (xhci->port_array[i] == 0x03) {
2194                                 xhci->usb3_ports[port_index] =
2195                                         &xhci->op_regs->port_status_base +
2196                                         NUM_PORT_REGS*i;
2197                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2198                                                 "addr = %p\n", i,
2199                                                 xhci->usb3_ports[port_index]);
2200                                 port_index++;
2201                                 if (port_index == xhci->num_usb3_ports)
2202                                         break;
2203                         }
2204         }
2205         return 0;
2206 }
2207
2208 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2209 {
2210         dma_addr_t      dma;
2211         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2212         unsigned int    val, val2;
2213         u64             val_64;
2214         struct xhci_segment     *seg;
2215         u32 page_size, temp;
2216         int i;
2217
2218         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2219         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2220         for (i = 0; i < 16; i++) {
2221                 if ((0x1 & page_size) != 0)
2222                         break;
2223                 page_size = page_size >> 1;
2224         }
2225         if (i < 16)
2226                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2227         else
2228                 xhci_warn(xhci, "WARN: no supported page size\n");
2229         /* Use 4K pages, since that's common and the minimum the HC supports */
2230         xhci->page_shift = 12;
2231         xhci->page_size = 1 << xhci->page_shift;
2232         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2233
2234         /*
2235          * Program the Number of Device Slots Enabled field in the CONFIG
2236          * register with the max value of slots the HC can handle.
2237          */
2238         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2239         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2240                         (unsigned int) val);
2241         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2242         val |= (val2 & ~HCS_SLOTS_MASK);
2243         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2244                         (unsigned int) val);
2245         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2246
2247         /*
2248          * Section 5.4.8 - doorbell array must be
2249          * "physically contiguous and 64-byte (cache line) aligned".
2250          */
2251         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2252                         GFP_KERNEL);
2253         if (!xhci->dcbaa)
2254                 goto fail;
2255         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2256         xhci->dcbaa->dma = dma;
2257         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2258                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2259         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2260
2261         /*
2262          * Initialize the ring segment pool.  The ring must be a contiguous
2263          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2264          * however, the command ring segment needs 64-byte aligned segments,
2265          * so we pick the greater alignment need.
2266          */
2267         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2268                         SEGMENT_SIZE, 64, xhci->page_size);
2269
2270         /* See Table 46 and Note on Figure 55 */
2271         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2272                         2112, 64, xhci->page_size);
2273         if (!xhci->segment_pool || !xhci->device_pool)
2274                 goto fail;
2275
2276         /* Linear stream context arrays don't have any boundary restrictions,
2277          * and only need to be 16-byte aligned.
2278          */
2279         xhci->small_streams_pool =
2280                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2281                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2282         xhci->medium_streams_pool =
2283                 dma_pool_create("xHCI 1KB stream ctx arrays",
2284                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2285         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2286          * will be allocated with dma_alloc_coherent()
2287          */
2288
2289         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2290                 goto fail;
2291
2292         /* Set up the command ring to have one segments for now. */
2293         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2294         if (!xhci->cmd_ring)
2295                 goto fail;
2296         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2297         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2298                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2299
2300         /* Set the address in the Command Ring Control register */
2301         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2302         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2303                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2304                 xhci->cmd_ring->cycle_state;
2305         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2306         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2307         xhci_dbg_cmd_ptrs(xhci);
2308
2309         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2310         val &= DBOFF_MASK;
2311         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2312                         " from cap regs base addr\n", val);
2313         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2314         xhci_dbg_regs(xhci);
2315         xhci_print_run_regs(xhci);
2316         /* Set ir_set to interrupt register set 0 */
2317         xhci->ir_set = &xhci->run_regs->ir_set[0];
2318
2319         /*
2320          * Event ring setup: Allocate a normal ring, but also setup
2321          * the event ring segment table (ERST).  Section 4.9.3.
2322          */
2323         xhci_dbg(xhci, "// Allocating event ring\n");
2324         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2325                                                 flags);
2326         if (!xhci->event_ring)
2327                 goto fail;
2328         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2329                 goto fail;
2330
2331         xhci->erst.entries = dma_alloc_coherent(dev,
2332                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2333                         GFP_KERNEL);
2334         if (!xhci->erst.entries)
2335                 goto fail;
2336         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2337                         (unsigned long long)dma);
2338
2339         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2340         xhci->erst.num_entries = ERST_NUM_SEGS;
2341         xhci->erst.erst_dma_addr = dma;
2342         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2343                         xhci->erst.num_entries,
2344                         xhci->erst.entries,
2345                         (unsigned long long)xhci->erst.erst_dma_addr);
2346
2347         /* set ring base address and size for each segment table entry */
2348         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2349                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2350                 entry->seg_addr = cpu_to_le64(seg->dma);
2351                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2352                 entry->rsvd = 0;
2353                 seg = seg->next;
2354         }
2355
2356         /* set ERST count with the number of entries in the segment table */
2357         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2358         val &= ERST_SIZE_MASK;
2359         val |= ERST_NUM_SEGS;
2360         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2361                         val);
2362         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2363
2364         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2365         /* set the segment table base address */
2366         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2367                         (unsigned long long)xhci->erst.erst_dma_addr);
2368         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2369         val_64 &= ERST_PTR_MASK;
2370         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2371         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2372
2373         /* Set the event ring dequeue address */
2374         xhci_set_hc_event_deq(xhci);
2375         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2376         xhci_print_ir_set(xhci, 0);
2377
2378         /*
2379          * XXX: Might need to set the Interrupter Moderation Register to
2380          * something other than the default (~1ms minimum between interrupts).
2381          * See section 5.5.1.2.
2382          */
2383         init_completion(&xhci->addr_dev);
2384         for (i = 0; i < MAX_HC_SLOTS; ++i)
2385                 xhci->devs[i] = NULL;
2386         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2387                 xhci->bus_state[0].resume_done[i] = 0;
2388                 xhci->bus_state[1].resume_done[i] = 0;
2389         }
2390
2391         if (scratchpad_alloc(xhci, flags))
2392                 goto fail;
2393         if (xhci_setup_port_arrays(xhci, flags))
2394                 goto fail;
2395
2396         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2397
2398         /* Enable USB 3.0 device notifications for function remote wake, which
2399          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2400          * U3 (device suspend).
2401          */
2402         temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2403         temp &= ~DEV_NOTE_MASK;
2404         temp |= DEV_NOTE_FWAKE;
2405         xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2406
2407         return 0;
2408
2409 fail:
2410         xhci_warn(xhci, "Couldn't initialize memory\n");
2411         xhci_mem_cleanup(xhci);
2412         return -ENOMEM;
2413 }