2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
43 #define PCI_VENDOR_ID_ETRON 0x1b6f
44 #define PCI_DEVICE_ID_EJ168 0x7023
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
57 static const char hcd_name[] = "xhci_hcd";
59 static struct hc_driver __read_mostly xhci_pci_hc_driver;
61 static int xhci_pci_setup(struct usb_hcd *hcd);
63 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
64 .reset = xhci_pci_setup,
67 /* called after powerup, by probe or system-pm "wakeup" */
68 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
71 * TODO: Implement finding debug ports later.
72 * TODO: see if there are any quirks that need to be added to handle
73 * new extended capabilities.
76 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
77 if (!pci_set_mwi(pdev))
78 xhci_dbg(xhci, "MWI active\n");
80 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
84 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
86 struct pci_dev *pdev = to_pci_dev(dev);
88 /* Look for vendor-specific quirks */
89 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
90 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
91 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
92 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
93 pdev->revision == 0x0) {
94 xhci->quirks |= XHCI_RESET_EP_QUIRK;
95 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
96 "QUIRK: Fresco Logic xHC needs configure"
97 " endpoint cmd after reset endpoint");
99 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
100 pdev->revision == 0x4) {
101 xhci->quirks |= XHCI_SLOW_SUSPEND;
102 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
103 "QUIRK: Fresco Logic xHC revision %u"
104 "must be suspended extra slowly",
107 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
108 xhci->quirks |= XHCI_BROKEN_STREAMS;
109 /* Fresco Logic confirms: all revisions of this chip do not
110 * support MSI, even though some of them claim to in their PCI
113 xhci->quirks |= XHCI_BROKEN_MSI;
114 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
115 "QUIRK: Fresco Logic revision %u "
116 "has broken MSI implementation",
118 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
121 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
122 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
123 xhci->quirks |= XHCI_BROKEN_STREAMS;
125 if (pdev->vendor == PCI_VENDOR_ID_NEC)
126 xhci->quirks |= XHCI_NEC_HOST;
128 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
129 xhci->quirks |= XHCI_AMD_0x96_HOST;
132 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
133 xhci->quirks |= XHCI_AMD_PLL_FIX;
135 if (pdev->vendor == PCI_VENDOR_ID_AMD)
136 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
138 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
139 xhci->quirks |= XHCI_LPM_SUPPORT;
140 xhci->quirks |= XHCI_INTEL_HOST;
141 xhci->quirks |= XHCI_AVOID_BEI;
143 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
144 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
145 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
146 xhci->limit_active_eps = 64;
147 xhci->quirks |= XHCI_SW_BW_CHECKING;
149 * PPT desktop boards DH77EB and DH77DF will power back on after
150 * a few seconds of being shutdown. The fix for this is to
151 * switch the ports from xHCI to EHCI on shutdown. We can't use
152 * DMI information to find those particular boards (since each
153 * vendor will change the board name), so we have to key off all
156 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
158 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
159 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
160 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
161 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
162 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
164 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
165 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
166 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
167 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
168 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
169 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
170 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
171 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
172 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
174 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
175 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
176 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
178 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
179 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
180 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
181 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
182 xhci->quirks |= XHCI_MISSING_CAS;
184 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
185 pdev->device == PCI_DEVICE_ID_EJ168) {
186 xhci->quirks |= XHCI_RESET_ON_RESUME;
187 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
188 xhci->quirks |= XHCI_BROKEN_STREAMS;
190 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
191 pdev->device == 0x0015)
192 xhci->quirks |= XHCI_RESET_ON_RESUME;
193 if (pdev->vendor == PCI_VENDOR_ID_VIA)
194 xhci->quirks |= XHCI_RESET_ON_RESUME;
196 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
197 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
198 pdev->device == 0x3432)
199 xhci->quirks |= XHCI_BROKEN_STREAMS;
201 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
202 pdev->device == 0x1042)
203 xhci->quirks |= XHCI_BROKEN_STREAMS;
204 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
205 pdev->device == 0x1142)
206 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
208 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
209 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
211 if (xhci->quirks & XHCI_RESET_ON_RESUME)
212 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
213 "QUIRK: Resetting on resume");
217 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
219 static const guid_t intel_dsm_guid =
220 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
221 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
222 union acpi_object *obj;
224 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
229 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
230 #endif /* CONFIG_ACPI */
232 /* called during probe() after chip reset completes */
233 static int xhci_pci_setup(struct usb_hcd *hcd)
235 struct xhci_hcd *xhci;
236 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
239 xhci = hcd_to_xhci(hcd);
241 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
243 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
247 if (!usb_hcd_is_primary_hcd(hcd))
250 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
252 /* Find any debug ports */
253 return xhci_pci_reinit(xhci, pdev);
257 * We need to register our own PCI probe function (instead of the USB core's
258 * function) in order to create a second roothub under xHCI.
260 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
263 struct xhci_hcd *xhci;
264 struct hc_driver *driver;
267 driver = (struct hc_driver *)id->driver_data;
269 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
270 pm_runtime_get_noresume(&dev->dev);
272 /* Register the USB 2.0 roothub.
273 * FIXME: USB core must know to register the USB 2.0 roothub first.
274 * This is sort of silly, because we could just set the HCD driver flags
275 * to say USB 2.0, but I'm not sure what the implications would be in
276 * the other parts of the HCD code.
278 retval = usb_hcd_pci_probe(dev, id);
283 /* USB 2.0 roothub is stored in the PCI device now. */
284 hcd = dev_get_drvdata(&dev->dev);
285 xhci = hcd_to_xhci(hcd);
286 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
288 if (!xhci->shared_hcd) {
290 goto dealloc_usb2_hcd;
293 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
297 /* Roothub already marked as USB 3.0 speed */
299 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
300 HCC_MAX_PSA(xhci->hcc_params) >= 4)
301 xhci->shared_hcd->can_do_streams = 1;
303 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
304 xhci_pme_acpi_rtd3_enable(dev);
306 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
307 pm_runtime_put_noidle(&dev->dev);
312 usb_put_hcd(xhci->shared_hcd);
314 usb_hcd_pci_remove(dev);
316 pm_runtime_put_noidle(&dev->dev);
320 static void xhci_pci_remove(struct pci_dev *dev)
322 struct xhci_hcd *xhci;
324 xhci = hcd_to_xhci(pci_get_drvdata(dev));
325 xhci->xhc_state |= XHCI_STATE_REMOVING;
326 if (xhci->shared_hcd) {
327 usb_remove_hcd(xhci->shared_hcd);
328 usb_put_hcd(xhci->shared_hcd);
331 /* Workaround for spurious wakeups at shutdown with HSW */
332 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
333 pci_set_power_state(dev, PCI_D3hot);
335 usb_hcd_pci_remove(dev);
340 * In some Intel xHCI controllers, in order to get D3 working,
341 * through a vendor specific SSIC CONFIG register at offset 0x883c,
342 * SSIC PORT need to be marked as "unused" before putting xHCI
343 * into D3. After D3 exit, the SSIC port need to be marked as "used".
344 * Without this change, xHCI might not enter D3 state.
346 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
348 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
353 for (i = 0; i < SSIC_PORT_NUM; i++) {
354 reg = (void __iomem *) xhci->cap_regs +
356 i * SSIC_PORT_CFG2_OFFSET;
358 /* Notify SSIC that SSIC profile programming is not done. */
359 val = readl(reg) & ~PROG_DONE;
362 /* Mark SSIC port as unused(suspend) or used(resume) */
365 val |= SSIC_PORT_UNUSED;
367 val &= ~SSIC_PORT_UNUSED;
370 /* Notify SSIC that SSIC profile programming is done */
371 val = readl(reg) | PROG_DONE;
378 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
379 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
381 static void xhci_pme_quirk(struct usb_hcd *hcd)
383 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
387 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
389 writel(val | BIT(28), reg);
393 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
395 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
396 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
400 * Systems with the TI redriver that loses port status change events
401 * need to have the registers polled during D3, so avoid D3cold.
403 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
404 pci_d3cold_disable(pdev);
406 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
409 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
410 xhci_ssic_port_unused_quirk(hcd, true);
412 ret = xhci_suspend(xhci, do_wakeup);
413 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
414 xhci_ssic_port_unused_quirk(hcd, false);
419 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
421 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
422 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
425 /* The BIOS on systems with the Intel Panther Point chipset may or may
426 * not support xHCI natively. That means that during system resume, it
427 * may switch the ports back to EHCI so that users can use their
428 * keyboard to select a kernel from GRUB after resume from hibernate.
430 * The BIOS is supposed to remember whether the OS had xHCI ports
431 * enabled before resume, and switch the ports back to xHCI when the
432 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
435 * Unconditionally switch the ports back to xHCI after a system resume.
436 * It should not matter whether the EHCI or xHCI controller is
437 * resumed first. It's enough to do the switchover in xHCI because
438 * USB core won't notice anything as the hub driver doesn't start
439 * running again until after all the devices (including both EHCI and
440 * xHCI host controllers) have been resumed.
443 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
444 usb_enable_intel_xhci_ports(pdev);
446 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
447 xhci_ssic_port_unused_quirk(hcd, false);
449 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
452 retval = xhci_resume(xhci, hibernated);
455 #endif /* CONFIG_PM */
457 /*-------------------------------------------------------------------------*/
459 /* PCI driver selection metadata; PCI hotplugging uses this */
460 static const struct pci_device_id pci_ids[] = { {
461 /* handle any USB 3.0 xHCI controller */
462 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
463 .driver_data = (unsigned long) &xhci_pci_hc_driver,
465 { /* end: all zeroes */ }
467 MODULE_DEVICE_TABLE(pci, pci_ids);
469 /* pci driver glue; this is a "new style" PCI driver module */
470 static struct pci_driver xhci_pci_driver = {
471 .name = (char *) hcd_name,
474 .probe = xhci_pci_probe,
475 .remove = xhci_pci_remove,
476 /* suspend and resume implemented later */
478 .shutdown = usb_hcd_pci_shutdown,
481 .pm = &usb_hcd_pci_pm_ops
486 static int __init xhci_pci_init(void)
488 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
490 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
491 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
493 return pci_register_driver(&xhci_pci_driver);
495 module_init(xhci_pci_init);
497 static void __exit xhci_pci_exit(void)
499 pci_unregister_driver(&xhci_pci_driver);
501 module_exit(xhci_pci_exit);
503 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
504 MODULE_LICENSE("GPL");