2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
42 #define PCI_VENDOR_ID_ETRON 0x1b6f
43 #define PCI_DEVICE_ID_EJ168 0x7023
45 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
47 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
49 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
51 static const char hcd_name[] = "xhci_hcd";
53 static struct hc_driver __read_mostly xhci_pci_hc_driver;
55 static int xhci_pci_setup(struct usb_hcd *hcd);
57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
58 .reset = xhci_pci_setup,
61 /* called after powerup, by probe or system-pm "wakeup" */
62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
65 * TODO: Implement finding debug ports later.
66 * TODO: see if there are any quirks that need to be added to handle
67 * new extended capabilities.
70 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
71 if (!pci_set_mwi(pdev))
72 xhci_dbg(xhci, "MWI active\n");
74 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
80 struct pci_dev *pdev = to_pci_dev(dev);
82 /* Look for vendor-specific quirks */
83 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
84 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
85 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
86 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
87 pdev->revision == 0x0) {
88 xhci->quirks |= XHCI_RESET_EP_QUIRK;
89 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
90 "QUIRK: Fresco Logic xHC needs configure"
91 " endpoint cmd after reset endpoint");
93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
94 pdev->revision == 0x4) {
95 xhci->quirks |= XHCI_SLOW_SUSPEND;
96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
97 "QUIRK: Fresco Logic xHC revision %u"
98 "must be suspended extra slowly",
101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
102 xhci->quirks |= XHCI_BROKEN_STREAMS;
103 /* Fresco Logic confirms: all revisions of this chip do not
104 * support MSI, even though some of them claim to in their PCI
107 xhci->quirks |= XHCI_BROKEN_MSI;
108 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
109 "QUIRK: Fresco Logic revision %u "
110 "has broken MSI implementation",
112 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
115 if (pdev->vendor == PCI_VENDOR_ID_NEC)
116 xhci->quirks |= XHCI_NEC_HOST;
118 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
119 xhci->quirks |= XHCI_AMD_0x96_HOST;
122 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
123 xhci->quirks |= XHCI_AMD_PLL_FIX;
125 if (pdev->vendor == PCI_VENDOR_ID_AMD)
126 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
128 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
129 xhci->quirks |= XHCI_LPM_SUPPORT;
130 xhci->quirks |= XHCI_INTEL_HOST;
131 xhci->quirks |= XHCI_AVOID_BEI;
133 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
134 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
135 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
136 xhci->limit_active_eps = 64;
137 xhci->quirks |= XHCI_SW_BW_CHECKING;
139 * PPT desktop boards DH77EB and DH77DF will power back on after
140 * a few seconds of being shutdown. The fix for this is to
141 * switch the ports from xHCI to EHCI on shutdown. We can't use
142 * DMI information to find those particular boards (since each
143 * vendor will change the board name), so we have to key off all
146 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
148 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
149 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
150 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
151 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
153 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
154 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
155 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
156 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
157 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
159 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
160 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
161 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
163 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
164 pdev->device == PCI_DEVICE_ID_EJ168) {
165 xhci->quirks |= XHCI_RESET_ON_RESUME;
166 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
167 xhci->quirks |= XHCI_BROKEN_STREAMS;
169 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
170 pdev->device == 0x0015)
171 xhci->quirks |= XHCI_RESET_ON_RESUME;
172 if (pdev->vendor == PCI_VENDOR_ID_VIA)
173 xhci->quirks |= XHCI_RESET_ON_RESUME;
175 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
176 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
177 pdev->device == 0x3432)
178 xhci->quirks |= XHCI_BROKEN_STREAMS;
180 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
181 pdev->device == 0x1042)
182 xhci->quirks |= XHCI_BROKEN_STREAMS;
184 if (xhci->quirks & XHCI_RESET_ON_RESUME)
185 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
186 "QUIRK: Resetting on resume");
190 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
192 static const u8 intel_dsm_uuid[] = {
193 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
194 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
196 union acpi_object *obj;
198 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
203 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
204 #endif /* CONFIG_ACPI */
206 /* called during probe() after chip reset completes */
207 static int xhci_pci_setup(struct usb_hcd *hcd)
209 struct xhci_hcd *xhci;
210 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
213 xhci = hcd_to_xhci(hcd);
215 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
217 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
221 if (!usb_hcd_is_primary_hcd(hcd))
224 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
226 /* Find any debug ports */
227 retval = xhci_pci_reinit(xhci, pdev);
235 * We need to register our own PCI probe function (instead of the USB core's
236 * function) in order to create a second roothub under xHCI.
238 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
241 struct xhci_hcd *xhci;
242 struct hc_driver *driver;
245 driver = (struct hc_driver *)id->driver_data;
247 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
248 pm_runtime_get_noresume(&dev->dev);
250 /* Register the USB 2.0 roothub.
251 * FIXME: USB core must know to register the USB 2.0 roothub first.
252 * This is sort of silly, because we could just set the HCD driver flags
253 * to say USB 2.0, but I'm not sure what the implications would be in
254 * the other parts of the HCD code.
256 retval = usb_hcd_pci_probe(dev, id);
261 /* USB 2.0 roothub is stored in the PCI device now. */
262 hcd = dev_get_drvdata(&dev->dev);
263 xhci = hcd_to_xhci(hcd);
264 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
266 if (!xhci->shared_hcd) {
268 goto dealloc_usb2_hcd;
271 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
275 /* Roothub already marked as USB 3.0 speed */
277 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
278 HCC_MAX_PSA(xhci->hcc_params) >= 4)
279 xhci->shared_hcd->can_do_streams = 1;
281 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
282 xhci_pme_acpi_rtd3_enable(dev);
284 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
285 pm_runtime_put_noidle(&dev->dev);
290 usb_put_hcd(xhci->shared_hcd);
292 usb_hcd_pci_remove(dev);
294 pm_runtime_put_noidle(&dev->dev);
298 static void xhci_pci_remove(struct pci_dev *dev)
300 struct xhci_hcd *xhci;
302 xhci = hcd_to_xhci(pci_get_drvdata(dev));
303 if (xhci->shared_hcd) {
304 usb_remove_hcd(xhci->shared_hcd);
305 usb_put_hcd(xhci->shared_hcd);
307 usb_hcd_pci_remove(dev);
309 /* Workaround for spurious wakeups at shutdown with HSW */
310 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
311 pci_set_power_state(dev, PCI_D3hot);
316 * In some Intel xHCI controllers, in order to get D3 working,
317 * through a vendor specific SSIC CONFIG register at offset 0x883c,
318 * SSIC PORT need to be marked as "unused" before putting xHCI
319 * into D3. After D3 exit, the SSIC port need to be marked as "used".
320 * Without this change, xHCI might not enter D3 state.
322 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
324 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
329 for (i = 0; i < SSIC_PORT_NUM; i++) {
330 reg = (void __iomem *) xhci->cap_regs +
332 i * SSIC_PORT_CFG2_OFFSET;
334 /* Notify SSIC that SSIC profile programming is not done. */
335 val = readl(reg) & ~PROG_DONE;
338 /* Mark SSIC port as unused(suspend) or used(resume) */
341 val |= SSIC_PORT_UNUSED;
343 val &= ~SSIC_PORT_UNUSED;
346 /* Notify SSIC that SSIC profile programming is done */
347 val = readl(reg) | PROG_DONE;
354 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
355 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
357 static void xhci_pme_quirk(struct usb_hcd *hcd)
359 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
363 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
365 writel(val | BIT(28), reg);
369 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
371 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
372 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
376 * Systems with the TI redriver that loses port status change events
377 * need to have the registers polled during D3, so avoid D3cold.
379 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
380 pdev->no_d3cold = true;
382 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
385 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
386 xhci_ssic_port_unused_quirk(hcd, true);
388 ret = xhci_suspend(xhci, do_wakeup);
389 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
390 xhci_ssic_port_unused_quirk(hcd, false);
395 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
397 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
398 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
401 /* The BIOS on systems with the Intel Panther Point chipset may or may
402 * not support xHCI natively. That means that during system resume, it
403 * may switch the ports back to EHCI so that users can use their
404 * keyboard to select a kernel from GRUB after resume from hibernate.
406 * The BIOS is supposed to remember whether the OS had xHCI ports
407 * enabled before resume, and switch the ports back to xHCI when the
408 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
411 * Unconditionally switch the ports back to xHCI after a system resume.
412 * It should not matter whether the EHCI or xHCI controller is
413 * resumed first. It's enough to do the switchover in xHCI because
414 * USB core won't notice anything as the hub driver doesn't start
415 * running again until after all the devices (including both EHCI and
416 * xHCI host controllers) have been resumed.
419 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
420 usb_enable_intel_xhci_ports(pdev);
422 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
423 xhci_ssic_port_unused_quirk(hcd, false);
425 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
428 retval = xhci_resume(xhci, hibernated);
431 #endif /* CONFIG_PM */
433 /*-------------------------------------------------------------------------*/
435 /* PCI driver selection metadata; PCI hotplugging uses this */
436 static const struct pci_device_id pci_ids[] = { {
437 /* handle any USB 3.0 xHCI controller */
438 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
439 .driver_data = (unsigned long) &xhci_pci_hc_driver,
441 { /* end: all zeroes */ }
443 MODULE_DEVICE_TABLE(pci, pci_ids);
445 /* pci driver glue; this is a "new style" PCI driver module */
446 static struct pci_driver xhci_pci_driver = {
447 .name = (char *) hcd_name,
450 .probe = xhci_pci_probe,
451 .remove = xhci_pci_remove,
452 /* suspend and resume implemented later */
454 .shutdown = usb_hcd_pci_shutdown,
457 .pm = &usb_hcd_pci_pm_ops
462 static int __init xhci_pci_init(void)
464 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
466 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
467 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
469 return pci_register_driver(&xhci_pci_driver);
471 module_init(xhci_pci_init);
473 static void __exit xhci_pci_exit(void)
475 pci_unregister_driver(&xhci_pci_driver);
477 module_exit(xhci_pci_exit);
479 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
480 MODULE_LICENSE("GPL");