drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 127  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 128  * effect the ring dequeue or enqueue pointers.
 129  */
 130 static void next_trb(struct xhci_hcd *xhci,
 131                 struct xhci_ring *ring,
 132                 struct xhci_segment **seg,
 133                 union xhci_trb **trb)
 134 {
 135         if (last_trb(xhci, ring, *seg, *trb)) {
 136                 *seg = (*seg)->next;
 137                 *trb = ((*seg)->trbs);
 138         } else {
 139                 (*trb)++;
 140         }
 141 }
 142
 143 /*
 144  * See Cycle bit rules. SW is the consumer for the event ring only.
 145  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 146  */
 147 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 148 {
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152
 153         /*
 154          * If this is not event ring, and the dequeue pointer
 155          * is not on a link TRB, there is one more usable TRB
 156          */
 157         if (ring->type != TYPE_EVENT &&
 158                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 159                 ring->num_trbs_free++;
 160
 161         do {
 162                 /*
 163                  * Update the dequeue pointer further if that was a link TRB or
 164                  * we're at the end of an event ring segment (which doesn't have
 165                  * link TRBS)
 166                  */
 167                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 168                         if (ring->type == TYPE_EVENT &&
 169                                         last_trb_on_last_seg(xhci, ring,
 170                                                 ring->deq_seg, ring->dequeue)) {
 171                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 172                         }
 173                         ring->deq_seg = ring->deq_seg->next;
 174                         ring->dequeue = ring->deq_seg->trbs;
 175                 } else {
 176                         ring->dequeue++;
 177                 }
 178         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 179
 180         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 181 }
 182
 183 /*
 184  * See Cycle bit rules. SW is the consumer for the event ring only.
 185  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 186  *
 187  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 188  * chain bit is set), then set the chain bit in all the following link TRBs.
 189  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 190  * have their chain bit cleared (so that each Link TRB is a separate TD).
 191  *
 192  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 193  * set, but other sections talk about dealing with the chain bit set.  This was
 194  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 195  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 196  *
 197  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 198  *                      prepare_transfer()?
 199  */
 200 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 201                         bool more_trbs_coming)
 202 {
 203         u32 chain;
 204         union xhci_trb *next;
 205         unsigned long long addr;
 206
 207         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 208         /* If this is not event ring, there is one less usable TRB */
 209         if (ring->type != TYPE_EVENT &&
 210                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 211                 ring->num_trbs_free--;
 212         next = ++(ring->enqueue);
 213
 214         ring->enq_updates++;
 215         /* Update the dequeue pointer further if that was a link TRB or we're at
 216          * the end of an event ring segment (which doesn't have link TRBS)
 217          */
 218         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 219                 if (ring->type != TYPE_EVENT) {
 220                         /*
 221                          * If the caller doesn't plan on enqueueing more
 222                          * TDs before ringing the doorbell, then we
 223                          * don't want to give the link TRB to the
 224                          * hardware just yet.  We'll give the link TRB
 225                          * back in prepare_ring() just before we enqueue
 226                          * the TD at the top of the ring.
 227                          */
 228                         if (!chain && !more_trbs_coming)
 229                                 break;
 230
 231                         /* If we're not dealing with 0.95 hardware or
 232                          * isoc rings on AMD 0.96 host,
 233                          * carry over the chain bit of the previous TRB
 234                          * (which may mean the chain bit is cleared).
 235                          */
 236                         if (!(ring->type == TYPE_ISOC &&
 237                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 238                                                 && !xhci_link_trb_quirk(xhci)) {
 239                                 next->link.control &=
 240                                         cpu_to_le32(~TRB_CHAIN);
 241                                 next->link.control |=
 242                                         cpu_to_le32(chain);
 243                         }
 244                         /* Give this link TRB to the hardware */
 245                         wmb();
 246                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 247
 248                         /* Toggle the cycle bit after the last ring segment. */
 249                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 250                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 251                         }
 252                 }
 253                 ring->enq_seg = ring->enq_seg->next;
 254                 ring->enqueue = ring->enq_seg->trbs;
 255                 next = ring->enqueue;
 256         }
 257         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 258 }
 259
 260 /*
 261  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 262  * enqueue pointer will not advance into dequeue segment. See rules above.
 263  */
 264 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 265                 unsigned int num_trbs)
 266 {
 267         int num_trbs_in_deq_seg;
 268
 269         if (ring->num_trbs_free < num_trbs)
 270                 return 0;
 271
 272         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 273                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 274                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 275                         return 0;
 276         }
 277
 278         return 1;
 279 }
 280
 281 /* Ring the host controller doorbell after placing a command on the ring */
 282 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 283 {
 284         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 285                 return;
 286
 287         xhci_dbg(xhci, "// Ding dong!\n");
 288         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 289         /* Flush PCI posted writes */
 290         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 291 }
 292
 293 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 294 {
 295         u64 temp_64;
 296         int ret;
 297
 298         xhci_dbg(xhci, "Abort command ring\n");
 299
 300         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 301                 xhci_dbg(xhci, "The command ring isn't running, "
 302                                 "Have the command ring been stopped?\n");
 303                 return 0;
 304         }
 305
 306         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 307         if (!(temp_64 & CMD_RING_RUNNING)) {
 308                 xhci_dbg(xhci, "Command ring had been stopped\n");
 309                 return 0;
 310         }
 311         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 312         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 313                         &xhci->op_regs->cmd_ring);
 314
 315         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 316          * time the completion od all xHCI commands, including
 317          * the Command Abort operation. If software doesn't see
 318          * CRR negated in a timely manner (e.g. longer than 5
 319          * seconds), then it should assume that the there are
 320          * larger problems with the xHC and assert HCRST.
 321          */
 322         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 323                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 324         if (ret < 0) {
 325                 xhci_err(xhci, "Stopped the command ring failed, "
 326                                 "maybe the host is dead\n");
 327                 xhci->xhc_state |= XHCI_STATE_DYING;
 328                 xhci_quiesce(xhci);
 329                 xhci_halt(xhci);
 330                 return -ESHUTDOWN;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int xhci_queue_cd(struct xhci_hcd *xhci,
 337                 struct xhci_command *command,
 338                 union xhci_trb *cmd_trb)
 339 {
 340         struct xhci_cd *cd;
 341         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 342         if (!cd)
 343                 return -ENOMEM;
 344         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 345
 346         cd->command = command;
 347         cd->cmd_trb = cmd_trb;
 348         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 349
 350         return 0;
 351 }
 352
 353 /*
 354  * Cancel the command which has issue.
 355  *
 356  * Some commands may hang due to waiting for acknowledgement from
 357  * usb device. It is outside of the xHC's ability to control and
 358  * will cause the command ring is blocked. When it occurs software
 359  * should intervene to recover the command ring.
 360  * See Section 4.6.1.1 and 4.6.1.2
 361  */
 362 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 363                 union xhci_trb *cmd_trb)
 364 {
 365         int retval = 0;
 366         unsigned long flags;
 367
 368         spin_lock_irqsave(&xhci->lock, flags);
 369
 370         if (xhci->xhc_state & XHCI_STATE_DYING) {
 371                 xhci_warn(xhci, "Abort the command ring,"
 372                                 " but the xHCI is dead.\n");
 373                 retval = -ESHUTDOWN;
 374                 goto fail;
 375         }
 376
 377         /* queue the cmd desriptor to cancel_cmd_list */
 378         retval = xhci_queue_cd(xhci, command, cmd_trb);
 379         if (retval) {
 380                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 381                 goto fail;
 382         }
 383
 384         /* abort command ring */
 385         retval = xhci_abort_cmd_ring(xhci);
 386         if (retval) {
 387                 xhci_err(xhci, "Abort command ring failed\n");
 388                 if (unlikely(retval == -ESHUTDOWN)) {
 389                         spin_unlock_irqrestore(&xhci->lock, flags);
 390                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 391                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 392                         return retval;
 393                 }
 394         }
 395
 396 fail:
 397         spin_unlock_irqrestore(&xhci->lock, flags);
 398         return retval;
 399 }
 400
 401 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 402                 unsigned int slot_id,
 403                 unsigned int ep_index,
 404                 unsigned int stream_id)
 405 {
 406         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 407         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 408         unsigned int ep_state = ep->ep_state;
 409
 410         /* Don't ring the doorbell for this endpoint if there are pending
 411          * cancellations because we don't want to interrupt processing.
 412          * We don't want to restart any stream rings if there's a set dequeue
 413          * pointer command pending because the device can choose to start any
 414          * stream once the endpoint is on the HW schedule.
 415          * FIXME - check all the stream rings for pending cancellations.
 416          */
 417         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 418             (ep_state & EP_HALTED))
 419                 return;
 420         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 421         /* The CPU has better things to do at this point than wait for a
 422          * write-posting flush.  It'll get there soon enough.
 423          */
 424 }
 425
 426 /* Ring the doorbell for any rings with pending URBs */
 427 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 428                 unsigned int slot_id,
 429                 unsigned int ep_index)
 430 {
 431         unsigned int stream_id;
 432         struct xhci_virt_ep *ep;
 433
 434         ep = &xhci->devs[slot_id]->eps[ep_index];
 435
 436         /* A ring has pending URBs if its TD list is not empty */
 437         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 438                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 439                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 440                 return;
 441         }
 442
 443         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 444                         stream_id++) {
 445                 struct xhci_stream_info *stream_info = ep->stream_info;
 446                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 447                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 448                                                 stream_id);
 449         }
 450 }
 451
 452 /*
 453  * Find the segment that trb is in.  Start searching in start_seg.
 454  * If we must move past a segment that has a link TRB with a toggle cycle state
 455  * bit set, then we will toggle the value pointed at by cycle_state.
 456  */
 457 static struct xhci_segment *find_trb_seg(
 458                 struct xhci_segment *start_seg,
 459                 union xhci_trb  *trb, int *cycle_state)
 460 {
 461         struct xhci_segment *cur_seg = start_seg;
 462         struct xhci_generic_trb *generic_trb;
 463
 464         while (cur_seg->trbs > trb ||
 465                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 466                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 467                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 468                         *cycle_state ^= 0x1;
 469                 cur_seg = cur_seg->next;
 470                 if (cur_seg == start_seg)
 471                         /* Looped over the entire list.  Oops! */
 472                         return NULL;
 473         }
 474         return cur_seg;
 475 }
 476
 477
 478 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 479                 unsigned int slot_id, unsigned int ep_index,
 480                 unsigned int stream_id)
 481 {
 482         struct xhci_virt_ep *ep;
 483
 484         ep = &xhci->devs[slot_id]->eps[ep_index];
 485         /* Common case: no streams */
 486         if (!(ep->ep_state & EP_HAS_STREAMS))
 487                 return ep->ring;
 488
 489         if (stream_id == 0) {
 490                 xhci_warn(xhci,
 491                                 "WARN: Slot ID %u, ep index %u has streams, "
 492                                 "but URB has no stream ID.\n",
 493                                 slot_id, ep_index);
 494                 return NULL;
 495         }
 496
 497         if (stream_id < ep->stream_info->num_streams)
 498                 return ep->stream_info->stream_rings[stream_id];
 499
 500         xhci_warn(xhci,
 501                         "WARN: Slot ID %u, ep index %u has "
 502                         "stream IDs 1 to %u allocated, "
 503                         "but stream ID %u is requested.\n",
 504                         slot_id, ep_index,
 505                         ep->stream_info->num_streams - 1,
 506                         stream_id);
 507         return NULL;
 508 }
 509
 510 /* Get the right ring for the given URB.
 511  * If the endpoint supports streams, boundary check the URB's stream ID.
 512  * If the endpoint doesn't support streams, return the singular endpoint ring.
 513  */
 514 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 515                 struct urb *urb)
 516 {
 517         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 518                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 519 }
 520
 521 /*
 522  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 523  * Record the new state of the xHC's endpoint ring dequeue segment,
 524  * dequeue pointer, and new consumer cycle state in state.
 525  * Update our internal representation of the ring's dequeue pointer.
 526  *
 527  * We do this in three jumps:
 528  *  - First we update our new ring state to be the same as when the xHC stopped.
 529  *  - Then we traverse the ring to find the segment that contains
 530  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 531  *    any link TRBs with the toggle cycle bit set.
 532  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 533  *    if we've moved it past a link TRB with the toggle cycle bit set.
 534  *
 535  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 536  * with correct __le32 accesses they should work fine.  Only users of this are
 537  * in here.
 538  */
 539 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 540                 unsigned int slot_id, unsigned int ep_index,
 541                 unsigned int stream_id, struct xhci_td *cur_td,
 542                 struct xhci_dequeue_state *state)
 543 {
 544         struct xhci_virt_device *dev = xhci->devs[slot_id];
 545         struct xhci_ring *ep_ring;
 546         struct xhci_generic_trb *trb;
 547         struct xhci_ep_ctx *ep_ctx;
 548         dma_addr_t addr;
 549
 550         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 551                         ep_index, stream_id);
 552         if (!ep_ring) {
 553                 xhci_warn(xhci, "WARN can't find new dequeue state "
 554                                 "for invalid stream ID %u.\n",
 555                                 stream_id);
 556                 return;
 557         }
 558         state->new_cycle_state = 0;
 559         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 560                         "Finding segment containing stopped TRB.");
 561         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 562                         dev->eps[ep_index].stopped_trb,
 563                         &state->new_cycle_state);
 564         if (!state->new_deq_seg) {
 565                 WARN_ON(1);
 566                 return;
 567         }
 568
 569         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 570         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 571                         "Finding endpoint context");
 572         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 573         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 574
 575         state->new_deq_ptr = cur_td->last_trb;
 576         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 577                         "Finding segment containing last TRB in TD.");
 578         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 579                         state->new_deq_ptr,
 580                         &state->new_cycle_state);
 581         if (!state->new_deq_seg) {
 582                 WARN_ON(1);
 583                 return;
 584         }
 585
 586         trb = &state->new_deq_ptr->generic;
 587         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 588             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 589                 state->new_cycle_state ^= 0x1;
 590         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 591
 592         /*
 593          * If there is only one segment in a ring, find_trb_seg()'s while loop
 594          * will not run, and it will return before it has a chance to see if it
 595          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 596          * ended just before the link TRB on a one-segment ring, or if the TD
 597          * wrapped around the top of the ring, because it doesn't have the TD in
 598          * question.  Look for the one-segment case where stalled TRB's address
 599          * is greater than the new dequeue pointer address.
 600          */
 601         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 602                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 603                 state->new_cycle_state ^= 0x1;
 604         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 605                         "Cycle state = 0x%x", state->new_cycle_state);
 606
 607         /* Don't update the ring cycle state for the producer (us). */
 608         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 609                         "New dequeue segment = %p (virtual)",
 610                         state->new_deq_seg);
 611         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 612         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 613                         "New dequeue pointer = 0x%llx (DMA)",
 614                         (unsigned long long) addr);
 615 }
 616
 617 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 618  * (The last TRB actually points to the ring enqueue pointer, which is not part
 619  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 620  */
 621 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 622                 struct xhci_td *cur_td, bool flip_cycle)
 623 {
 624         struct xhci_segment *cur_seg;
 625         union xhci_trb *cur_trb;
 626
 627         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 628                         true;
 629                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 630                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 631                         /* Unchain any chained Link TRBs, but
 632                          * leave the pointers intact.
 633                          */
 634                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 635                         /* Flip the cycle bit (link TRBs can't be the first
 636                          * or last TRB).
 637                          */
 638                         if (flip_cycle)
 639                                 cur_trb->generic.field[3] ^=
 640                                         cpu_to_le32(TRB_CYCLE);
 641                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 642                                         "Cancel (unchain) link TRB");
 643                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 644                                         "Address = %p (0x%llx dma); "
 645                                         "in seg %p (0x%llx dma)",
 646                                         cur_trb,
 647                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 648                                         cur_seg,
 649                                         (unsigned long long)cur_seg->dma);
 650                 } else {
 651                         cur_trb->generic.field[0] = 0;
 652                         cur_trb->generic.field[1] = 0;
 653                         cur_trb->generic.field[2] = 0;
 654                         /* Preserve only the cycle bit of this TRB */
 655                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 656                         /* Flip the cycle bit except on the first or last TRB */
 657                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 658                                         cur_trb != cur_td->last_trb)
 659                                 cur_trb->generic.field[3] ^=
 660                                         cpu_to_le32(TRB_CYCLE);
 661                         cur_trb->generic.field[3] |= cpu_to_le32(
 662                                 TRB_TYPE(TRB_TR_NOOP));
 663                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 664                                         "TRB to noop at offset 0x%llx",
 665                                         (unsigned long long)
 666                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 667                 }
 668                 if (cur_trb == cur_td->last_trb)
 669                         break;
 670         }
 671 }
 672
 673 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 674                 unsigned int ep_index, unsigned int stream_id,
 675                 struct xhci_segment *deq_seg,
 676                 union xhci_trb *deq_ptr, u32 cycle_state);
 677
 678 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 679                 unsigned int slot_id, unsigned int ep_index,
 680                 unsigned int stream_id,
 681                 struct xhci_dequeue_state *deq_state)
 682 {
 683         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 684
 685         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 686                         "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 687                         "new deq ptr = %p (0x%llx dma), new cycle = %u",
 688                         deq_state->new_deq_seg,
 689                         (unsigned long long)deq_state->new_deq_seg->dma,
 690                         deq_state->new_deq_ptr,
 691                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 692                         deq_state->new_cycle_state);
 693         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 694                         deq_state->new_deq_seg,
 695                         deq_state->new_deq_ptr,
 696                         (u32) deq_state->new_cycle_state);
 697         /* Stop the TD queueing code from ringing the doorbell until
 698          * this command completes.  The HC won't set the dequeue pointer
 699          * if the ring is running, and ringing the doorbell starts the
 700          * ring running.
 701          */
 702         ep->ep_state |= SET_DEQ_PENDING;
 703 }
 704
 705 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 706                 struct xhci_virt_ep *ep)
 707 {
 708         ep->ep_state &= ~EP_HALT_PENDING;
 709         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 710          * timer is running on another CPU, we don't decrement stop_cmds_pending
 711          * (since we didn't successfully stop the watchdog timer).
 712          */
 713         if (del_timer(&ep->stop_cmd_timer))
 714                 ep->stop_cmds_pending--;
 715 }
 716
 717 /* Must be called with xhci->lock held in interrupt context */
 718 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 719                 struct xhci_td *cur_td, int status, char *adjective)
 720 {
 721         struct usb_hcd *hcd;
 722         struct urb      *urb;
 723         struct urb_priv *urb_priv;
 724
 725         urb = cur_td->urb;
 726         urb_priv = urb->hcpriv;
 727         urb_priv->td_cnt++;
 728         hcd = bus_to_hcd(urb->dev->bus);
 729
 730         /* Only giveback urb when this is the last td in urb */
 731         if (urb_priv->td_cnt == urb_priv->length) {
 732                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 733                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 734                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 735                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 736                                         usb_amd_quirk_pll_enable();
 737                         }
 738                 }
 739                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 740
 741                 spin_unlock(&xhci->lock);
 742                 usb_hcd_giveback_urb(hcd, urb, status);
 743                 xhci_urb_free_priv(xhci, urb_priv);
 744                 spin_lock(&xhci->lock);
 745         }
 746 }
 747
 748 /*
 749  * When we get a command completion for a Stop Endpoint Command, we need to
 750  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 751  *
 752  *  1. If the HW was in the middle of processing the TD that needs to be
 753  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 754  *     in the TD with a Set Dequeue Pointer Command.
 755  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 756  *     bit cleared) so that the HW will skip over them.
 757  */
 758 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 759                 union xhci_trb *trb, struct xhci_event_cmd *event)
 760 {
 761         unsigned int slot_id;
 762         unsigned int ep_index;
 763         struct xhci_virt_device *virt_dev;
 764         struct xhci_ring *ep_ring;
 765         struct xhci_virt_ep *ep;
 766         struct list_head *entry;
 767         struct xhci_td *cur_td = NULL;
 768         struct xhci_td *last_unlinked_td;
 769
 770         struct xhci_dequeue_state deq_state;
 771
 772         if (unlikely(TRB_TO_SUSPEND_PORT(
 773                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 774                 slot_id = TRB_TO_SLOT_ID(
 775                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 776                 virt_dev = xhci->devs[slot_id];
 777                 if (virt_dev)
 778                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 779                                 event);
 780                 else
 781                         xhci_warn(xhci, "Stop endpoint command "
 782                                 "completion for disabled slot %u\n",
 783                                 slot_id);
 784                 return;
 785         }
 786
 787         memset(&deq_state, 0, sizeof(deq_state));
 788         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 789         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 790         ep = &xhci->devs[slot_id]->eps[ep_index];
 791
 792         if (list_empty(&ep->cancelled_td_list)) {
 793                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 794                 ep->stopped_td = NULL;
 795                 ep->stopped_trb = NULL;
 796                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 797                 return;
 798         }
 799
 800         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 801          * We have the xHCI lock, so nothing can modify this list until we drop
 802          * it.  We're also in the event handler, so we can't get re-interrupted
 803          * if another Stop Endpoint command completes
 804          */
 805         list_for_each(entry, &ep->cancelled_td_list) {
 806                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 807                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 808                                 "Removing canceled TD starting at 0x%llx (dma).",
 809                                 (unsigned long long)xhci_trb_virt_to_dma(
 810                                         cur_td->start_seg, cur_td->first_trb));
 811                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 812                 if (!ep_ring) {
 813                         /* This shouldn't happen unless a driver is mucking
 814                          * with the stream ID after submission.  This will
 815                          * leave the TD on the hardware ring, and the hardware
 816                          * will try to execute it, and may access a buffer
 817                          * that has already been freed.  In the best case, the
 818                          * hardware will execute it, and the event handler will
 819                          * ignore the completion event for that TD, since it was
 820                          * removed from the td_list for that endpoint.  In
 821                          * short, don't muck with the stream ID after
 822                          * submission.
 823                          */
 824                         xhci_warn(xhci, "WARN Cancelled URB %p "
 825                                         "has invalid stream ID %u.\n",
 826                                         cur_td->urb,
 827                                         cur_td->urb->stream_id);
 828                         goto remove_finished_td;
 829                 }
 830                 /*
 831                  * If we stopped on the TD we need to cancel, then we have to
 832                  * move the xHC endpoint ring dequeue pointer past this TD.
 833                  */
 834                 if (cur_td == ep->stopped_td)
 835                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 836                                         cur_td->urb->stream_id,
 837                                         cur_td, &deq_state);
 838                 else
 839                         td_to_noop(xhci, ep_ring, cur_td, false);
 840 remove_finished_td:
 841                 /*
 842                  * The event handler won't see a completion for this TD anymore,
 843                  * so remove it from the endpoint ring's TD list.  Keep it in
 844                  * the cancelled TD list for URB completion later.
 845                  */
 846                 list_del_init(&cur_td->td_list);
 847         }
 848         last_unlinked_td = cur_td;
 849         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 850
 851         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 852         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 853                 xhci_queue_new_dequeue_state(xhci,
 854                                 slot_id, ep_index,
 855                                 ep->stopped_td->urb->stream_id,
 856                                 &deq_state);
 857                 xhci_ring_cmd_db(xhci);
 858         } else {
 859                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 860                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 861         }
 862         ep->stopped_td = NULL;
 863         ep->stopped_trb = NULL;
 864
 865         /*
 866          * Drop the lock and complete the URBs in the cancelled TD list.
 867          * New TDs to be cancelled might be added to the end of the list before
 868          * we can complete all the URBs for the TDs we already unlinked.
 869          * So stop when we've completed the URB for the last TD we unlinked.
 870          */
 871         do {
 872                 cur_td = list_entry(ep->cancelled_td_list.next,
 873                                 struct xhci_td, cancelled_td_list);
 874                 list_del_init(&cur_td->cancelled_td_list);
 875
 876                 /* Clean up the cancelled URB */
 877                 /* Doesn't matter what we pass for status, since the core will
 878                  * just overwrite it (because the URB has been unlinked).
 879                  */
 880                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 881
 882                 /* Stop processing the cancelled list if the watchdog timer is
 883                  * running.
 884                  */
 885                 if (xhci->xhc_state & XHCI_STATE_DYING)
 886                         return;
 887         } while (cur_td != last_unlinked_td);
 888
 889         /* Return to the event handler with xhci->lock re-acquired */
 890 }
 891
 892 /* Watchdog timer function for when a stop endpoint command fails to complete.
 893  * In this case, we assume the host controller is broken or dying or dead.  The
 894  * host may still be completing some other events, so we have to be careful to
 895  * let the event ring handler and the URB dequeueing/enqueueing functions know
 896  * through xhci->state.
 897  *
 898  * The timer may also fire if the host takes a very long time to respond to the
 899  * command, and the stop endpoint command completion handler cannot delete the
 900  * timer before the timer function is called.  Another endpoint cancellation may
 901  * sneak in before the timer function can grab the lock, and that may queue
 902  * another stop endpoint command and add the timer back.  So we cannot use a
 903  * simple flag to say whether there is a pending stop endpoint command for a
 904  * particular endpoint.
 905  *
 906  * Instead we use a combination of that flag and a counter for the number of
 907  * pending stop endpoint commands.  If the timer is the tail end of the last
 908  * stop endpoint command, and the endpoint's command is still pending, we assume
 909  * the host is dying.
 910  */
 911 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 912 {
 913         struct xhci_hcd *xhci;
 914         struct xhci_virt_ep *ep;
 915         struct xhci_virt_ep *temp_ep;
 916         struct xhci_ring *ring;
 917         struct xhci_td *cur_td;
 918         int ret, i, j;
 919         unsigned long flags;
 920
 921         ep = (struct xhci_virt_ep *) arg;
 922         xhci = ep->xhci;
 923
 924         spin_lock_irqsave(&xhci->lock, flags);
 925
 926         ep->stop_cmds_pending--;
 927         if (xhci->xhc_state & XHCI_STATE_DYING) {
 928                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 929                                 "Stop EP timer ran, but another timer marked "
 930                                 "xHCI as DYING, exiting.");
 931                 spin_unlock_irqrestore(&xhci->lock, flags);
 932                 return;
 933         }
 934         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 935                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 936                                 "Stop EP timer ran, but no command pending, "
 937                                 "exiting.");
 938                 spin_unlock_irqrestore(&xhci->lock, flags);
 939                 return;
 940         }
 941
 942         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 943         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 944         /* Oops, HC is dead or dying or at least not responding to the stop
 945          * endpoint command.
 946          */
 947         xhci->xhc_state |= XHCI_STATE_DYING;
 948         /* Disable interrupts from the host controller and start halting it */
 949         xhci_quiesce(xhci);
 950         spin_unlock_irqrestore(&xhci->lock, flags);
 951
 952         ret = xhci_halt(xhci);
 953
 954         spin_lock_irqsave(&xhci->lock, flags);
 955         if (ret < 0) {
 956                 /* This is bad; the host is not responding to commands and it's
 957                  * not allowing itself to be halted.  At least interrupts are
 958                  * disabled. If we call usb_hc_died(), it will attempt to
 959                  * disconnect all device drivers under this host.  Those
 960                  * disconnect() methods will wait for all URBs to be unlinked,
 961                  * so we must complete them.
 962                  */
 963                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 964                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 965                 /* We could turn all TDs on the rings to no-ops.  This won't
 966                  * help if the host has cached part of the ring, and is slow if
 967                  * we want to preserve the cycle bit.  Skip it and hope the host
 968                  * doesn't touch the memory.
 969                  */
 970         }
 971         for (i = 0; i < MAX_HC_SLOTS; i++) {
 972                 if (!xhci->devs[i])
 973                         continue;
 974                 for (j = 0; j < 31; j++) {
 975                         temp_ep = &xhci->devs[i]->eps[j];
 976                         ring = temp_ep->ring;
 977                         if (!ring)
 978                                 continue;
 979                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 980                                         "Killing URBs for slot ID %u, "
 981                                         "ep index %u", i, j);
 982                         while (!list_empty(&ring->td_list)) {
 983                                 cur_td = list_first_entry(&ring->td_list,
 984                                                 struct xhci_td,
 985                                                 td_list);
 986                                 list_del_init(&cur_td->td_list);
 987                                 if (!list_empty(&cur_td->cancelled_td_list))
 988                                         list_del_init(&cur_td->cancelled_td_list);
 989                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 990                                                 -ESHUTDOWN, "killed");
 991                         }
 992                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 993                                 cur_td = list_first_entry(
 994                                                 &temp_ep->cancelled_td_list,
 995                                                 struct xhci_td,
 996                                                 cancelled_td_list);
 997                                 list_del_init(&cur_td->cancelled_td_list);
 998                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 999                                                 -ESHUTDOWN, "killed");
1000                         }
1001                 }
1002         }
1003         spin_unlock_irqrestore(&xhci->lock, flags);
1004         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1005                         "Calling usb_hc_died()");
1006         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1007         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1008                         "xHCI host controller is dead.");
1009 }
1010
1011
1012 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1013                 struct xhci_virt_device *dev,
1014                 struct xhci_ring *ep_ring,
1015                 unsigned int ep_index)
1016 {
1017         union xhci_trb *dequeue_temp;
1018         int num_trbs_free_temp;
1019         bool revert = false;
1020
1021         num_trbs_free_temp = ep_ring->num_trbs_free;
1022         dequeue_temp = ep_ring->dequeue;
1023
1024         /* If we get two back-to-back stalls, and the first stalled transfer
1025          * ends just before a link TRB, the dequeue pointer will be left on
1026          * the link TRB by the code in the while loop.  So we have to update
1027          * the dequeue pointer one segment further, or we'll jump off
1028          * the segment into la-la-land.
1029          */
1030         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1031                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1032                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1033         }
1034
1035         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1036                 /* We have more usable TRBs */
1037                 ep_ring->num_trbs_free++;
1038                 ep_ring->dequeue++;
1039                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1040                                 ep_ring->dequeue)) {
1041                         if (ep_ring->dequeue ==
1042                                         dev->eps[ep_index].queued_deq_ptr)
1043                                 break;
1044                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1045                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1046                 }
1047                 if (ep_ring->dequeue == dequeue_temp) {
1048                         revert = true;
1049                         break;
1050                 }
1051         }
1052
1053         if (revert) {
1054                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1055                 ep_ring->num_trbs_free = num_trbs_free_temp;
1056         }
1057 }
1058
1059 /*
1060  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1061  * we need to clear the set deq pending flag in the endpoint ring state, so that
1062  * the TD queueing code can ring the doorbell again.  We also need to ring the
1063  * endpoint doorbell to restart the ring, but only if there aren't more
1064  * cancellations pending.
1065  */
1066 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1067                 struct xhci_event_cmd *event,
1068                 union xhci_trb *trb)
1069 {
1070         unsigned int slot_id;
1071         unsigned int ep_index;
1072         unsigned int stream_id;
1073         struct xhci_ring *ep_ring;
1074         struct xhci_virt_device *dev;
1075         struct xhci_ep_ctx *ep_ctx;
1076         struct xhci_slot_ctx *slot_ctx;
1077
1078         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1079         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1080         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1081         dev = xhci->devs[slot_id];
1082
1083         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1084         if (!ep_ring) {
1085                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1086                                 "freed stream ID %u\n",
1087                                 stream_id);
1088                 /* XXX: Harmless??? */
1089                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1090                 return;
1091         }
1092
1093         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1094         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1095
1096         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1097                 unsigned int ep_state;
1098                 unsigned int slot_state;
1099
1100                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1101                 case COMP_TRB_ERR:
1102                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1103                                         "of stream ID configuration\n");
1104                         break;
1105                 case COMP_CTX_STATE:
1106                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1107                                         "to incorrect slot or ep state.\n");
1108                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1109                         ep_state &= EP_STATE_MASK;
1110                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1111                         slot_state = GET_SLOT_STATE(slot_state);
1112                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1113                                         "Slot state = %u, EP state = %u",
1114                                         slot_state, ep_state);
1115                         break;
1116                 case COMP_EBADSLT:
1117                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1118                                         "slot %u was not enabled.\n", slot_id);
1119                         break;
1120                 default:
1121                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1122                                         "completion code of %u.\n",
1123                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1124                         break;
1125                 }
1126                 /* OK what do we do now?  The endpoint state is hosed, and we
1127                  * should never get to this point if the synchronization between
1128                  * queueing, and endpoint state are correct.  This might happen
1129                  * if the device gets disconnected after we've finished
1130                  * cancelling URBs, which might not be an error...
1131                  */
1132         } else {
1133                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1134                         "Successful Set TR Deq Ptr cmd, deq = @%08llx",
1135                          le64_to_cpu(ep_ctx->deq));
1136                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1137                                          dev->eps[ep_index].queued_deq_ptr) ==
1138                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1139                         /* Update the ring's dequeue segment and dequeue pointer
1140                          * to reflect the new position.
1141                          */
1142                         update_ring_for_set_deq_completion(xhci, dev,
1143                                 ep_ring, ep_index);
1144                 } else {
1145                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1146                                         "Ptr command & xHCI internal state.\n");
1147                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1148                                         dev->eps[ep_index].queued_deq_seg,
1149                                         dev->eps[ep_index].queued_deq_ptr);
1150                 }
1151         }
1152
1153         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1154         dev->eps[ep_index].queued_deq_seg = NULL;
1155         dev->eps[ep_index].queued_deq_ptr = NULL;
1156         /* Restart any rings with pending URBs */
1157         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1158 }
1159
1160 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1161                 struct xhci_event_cmd *event,
1162                 union xhci_trb *trb)
1163 {
1164         int slot_id;
1165         unsigned int ep_index;
1166
1167         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1168         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1169         /* This command will only fail if the endpoint wasn't halted,
1170          * but we don't care.
1171          */
1172         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1173                 "Ignoring reset ep completion code of %u",
1174                  GET_COMP_CODE(le32_to_cpu(event->status)));
1175
1176         /* HW with the reset endpoint quirk needs to have a configure endpoint
1177          * command complete before the endpoint can be used.  Queue that here
1178          * because the HW can't handle two commands being queued in a row.
1179          */
1180         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1181                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1182                                 "Queueing configure endpoint command");
1183                 xhci_queue_configure_endpoint(xhci,
1184                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1185                                 false);
1186                 xhci_ring_cmd_db(xhci);
1187         } else {
1188                 /* Clear our internal halted state and restart the ring(s) */
1189                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1190                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1191         }
1192 }
1193
1194 /* Complete the command and detele it from the devcie's command queue.
1195  */
1196 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1197                 struct xhci_command *command, u32 status)
1198 {
1199         command->status = status;
1200         list_del(&command->cmd_list);
1201         if (command->completion)
1202                 complete(command->completion);
1203         else
1204                 xhci_free_command(xhci, command);
1205 }
1206
1207
1208 /* Check to see if a command in the device's command queue matches this one.
1209  * Signal the completion or free the command, and return 1.  Return 0 if the
1210  * completed command isn't at the head of the command list.
1211  */
1212 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1213                 struct xhci_virt_device *virt_dev,
1214                 struct xhci_event_cmd *event)
1215 {
1216         struct xhci_command *command;
1217
1218         if (list_empty(&virt_dev->cmd_list))
1219                 return 0;
1220
1221         command = list_entry(virt_dev->cmd_list.next,
1222                         struct xhci_command, cmd_list);
1223         if (xhci->cmd_ring->dequeue != command->command_trb)
1224                 return 0;
1225
1226         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1227                         GET_COMP_CODE(le32_to_cpu(event->status)));
1228         return 1;
1229 }
1230
1231 /*
1232  * Finding the command trb need to be cancelled and modifying it to
1233  * NO OP command. And if the command is in device's command wait
1234  * list, finishing and freeing it.
1235  *
1236  * If we can't find the command trb, we think it had already been
1237  * executed.
1238  */
1239 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1240 {
1241         struct xhci_segment *cur_seg;
1242         union xhci_trb *cmd_trb;
1243         u32 cycle_state;
1244
1245         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1246                 return;
1247
1248         /* find the current segment of command ring */
1249         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1250                         xhci->cmd_ring->dequeue, &cycle_state);
1251
1252         if (!cur_seg) {
1253                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1254                                 xhci->cmd_ring->dequeue,
1255                                 (unsigned long long)
1256                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1257                                         xhci->cmd_ring->dequeue));
1258                 xhci_debug_ring(xhci, xhci->cmd_ring);
1259                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1260                 return;
1261         }
1262
1263         /* find the command trb matched by cd from command ring */
1264         for (cmd_trb = xhci->cmd_ring->dequeue;
1265                         cmd_trb != xhci->cmd_ring->enqueue;
1266                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1267                 /* If the trb is link trb, continue */
1268                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1269                         continue;
1270
1271                 if (cur_cd->cmd_trb == cmd_trb) {
1272
1273                         /* If the command in device's command list, we should
1274                          * finish it and free the command structure.
1275                          */
1276                         if (cur_cd->command)
1277                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1278                                         cur_cd->command, COMP_CMD_STOP);
1279
1280                         /* get cycle state from the origin command trb */
1281                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1282                                 & TRB_CYCLE;
1283
1284                         /* modify the command trb to NO OP command */
1285                         cmd_trb->generic.field[0] = 0;
1286                         cmd_trb->generic.field[1] = 0;
1287                         cmd_trb->generic.field[2] = 0;
1288                         cmd_trb->generic.field[3] = cpu_to_le32(
1289                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1290                         break;
1291                 }
1292         }
1293 }
1294
1295 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1296 {
1297         struct xhci_cd *cur_cd, *next_cd;
1298
1299         if (list_empty(&xhci->cancel_cmd_list))
1300                 return;
1301
1302         list_for_each_entry_safe(cur_cd, next_cd,
1303                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1304                 xhci_cmd_to_noop(xhci, cur_cd);
1305                 list_del(&cur_cd->cancel_cmd_list);
1306                 kfree(cur_cd);
1307         }
1308 }
1309
1310 /*
1311  * traversing the cancel_cmd_list. If the command descriptor according
1312  * to cmd_trb is found, the function free it and return 1, otherwise
1313  * return 0.
1314  */
1315 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1316                 union xhci_trb *cmd_trb)
1317 {
1318         struct xhci_cd *cur_cd, *next_cd;
1319
1320         if (list_empty(&xhci->cancel_cmd_list))
1321                 return 0;
1322
1323         list_for_each_entry_safe(cur_cd, next_cd,
1324                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1325                 if (cur_cd->cmd_trb == cmd_trb) {
1326                         if (cur_cd->command)
1327                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1328                                         cur_cd->command, COMP_CMD_STOP);
1329                         list_del(&cur_cd->cancel_cmd_list);
1330                         kfree(cur_cd);
1331                         return 1;
1332                 }
1333         }
1334
1335         return 0;
1336 }
1337
1338 /*
1339  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1340  * trb pointed by the command ring dequeue pointer is the trb we want to
1341  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1342  * traverse the cancel_cmd_list to trun the all of the commands according
1343  * to command descriptor to NO-OP trb.
1344  */
1345 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1346                 int cmd_trb_comp_code)
1347 {
1348         int cur_trb_is_good = 0;
1349
1350         /* Searching the cmd trb pointed by the command ring dequeue
1351          * pointer in command descriptor list. If it is found, free it.
1352          */
1353         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1354                         xhci->cmd_ring->dequeue);
1355
1356         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1357                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1358         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1359                 /* traversing the cancel_cmd_list and canceling
1360                  * the command according to command descriptor
1361                  */
1362                 xhci_cancel_cmd_in_cd_list(xhci);
1363
1364                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1365                 /*
1366                  * ring command ring doorbell again to restart the
1367                  * command ring
1368                  */
1369                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1370                         xhci_ring_cmd_db(xhci);
1371         }
1372         return cur_trb_is_good;
1373 }
1374
1375 static void handle_cmd_completion(struct xhci_hcd *xhci,
1376                 struct xhci_event_cmd *event)
1377 {
1378         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1379         u64 cmd_dma;
1380         dma_addr_t cmd_dequeue_dma;
1381         struct xhci_input_control_ctx *ctrl_ctx;
1382         struct xhci_virt_device *virt_dev;
1383         unsigned int ep_index;
1384         struct xhci_ring *ep_ring;
1385         unsigned int ep_state;
1386
1387         cmd_dma = le64_to_cpu(event->cmd_trb);
1388         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1389                         xhci->cmd_ring->dequeue);
1390         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1391         if (cmd_dequeue_dma == 0) {
1392                 xhci->error_bitmask |= 1 << 4;
1393                 return;
1394         }
1395         /* Does the DMA address match our internal dequeue pointer address? */
1396         if (cmd_dma != (u64) cmd_dequeue_dma) {
1397                 xhci->error_bitmask |= 1 << 5;
1398                 return;
1399         }
1400
1401         trace_xhci_cmd_completion(&xhci->cmd_ring->dequeue->generic,
1402                                         (struct xhci_generic_trb *) event);
1403
1404         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1405                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1406                 /* If the return value is 0, we think the trb pointed by
1407                  * command ring dequeue pointer is a good trb. The good
1408                  * trb means we don't want to cancel the trb, but it have
1409                  * been stopped by host. So we should handle it normally.
1410                  * Otherwise, driver should invoke inc_deq() and return.
1411                  */
1412                 if (handle_stopped_cmd_ring(xhci,
1413                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1414                         inc_deq(xhci, xhci->cmd_ring);
1415                         return;
1416                 }
1417         }
1418
1419         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1420                 & TRB_TYPE_BITMASK) {
1421         case TRB_TYPE(TRB_ENABLE_SLOT):
1422                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1423                         xhci->slot_id = slot_id;
1424                 else
1425                         xhci->slot_id = 0;
1426                 complete(&xhci->addr_dev);
1427                 break;
1428         case TRB_TYPE(TRB_DISABLE_SLOT):
1429                 if (xhci->devs[slot_id]) {
1430                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1431                                 /* Delete default control endpoint resources */
1432                                 xhci_free_device_endpoint_resources(xhci,
1433                                                 xhci->devs[slot_id], true);
1434                         xhci_free_virt_device(xhci, slot_id);
1435                 }
1436                 break;
1437         case TRB_TYPE(TRB_CONFIG_EP):
1438                 virt_dev = xhci->devs[slot_id];
1439                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1440                         break;
1441                 /*
1442                  * Configure endpoint commands can come from the USB core
1443                  * configuration or alt setting changes, or because the HW
1444                  * needed an extra configure endpoint command after a reset
1445                  * endpoint command or streams were being configured.
1446                  * If the command was for a halted endpoint, the xHCI driver
1447                  * is not waiting on the configure endpoint command.
1448                  */
1449                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1450                                 virt_dev->in_ctx);
1451                 if (!ctrl_ctx) {
1452                         xhci_warn(xhci, "Could not get input context, bad type.\n");
1453                         break;
1454                 }
1455                 /* Input ctx add_flags are the endpoint index plus one */
1456                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1457                 /* A usb_set_interface() call directly after clearing a halted
1458                  * condition may race on this quirky hardware.  Not worth
1459                  * worrying about, since this is prototype hardware.  Not sure
1460                  * if this will work for streams, but streams support was
1461                  * untested on this prototype.
1462                  */
1463                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1464                                 ep_index != (unsigned int) -1 &&
1465                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1466                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1467                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1468                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1469                         if (!(ep_state & EP_HALTED))
1470                                 goto bandwidth_change;
1471                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1472                                         "Completed config ep cmd - "
1473                                         "last ep index = %d, state = %d",
1474                                         ep_index, ep_state);
1475                         /* Clear internal halted state and restart ring(s) */
1476                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1477                                 ~EP_HALTED;
1478                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1479                         break;
1480                 }
1481 bandwidth_change:
1482                 xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1483                                 "Completed config ep cmd");
1484                 xhci->devs[slot_id]->cmd_status =
1485                         GET_COMP_CODE(le32_to_cpu(event->status));
1486                 complete(&xhci->devs[slot_id]->cmd_completion);
1487                 break;
1488         case TRB_TYPE(TRB_EVAL_CONTEXT):
1489                 virt_dev = xhci->devs[slot_id];
1490                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1491                         break;
1492                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1493                 complete(&xhci->devs[slot_id]->cmd_completion);
1494                 break;
1495         case TRB_TYPE(TRB_ADDR_DEV):
1496                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1497                 complete(&xhci->addr_dev);
1498                 break;
1499         case TRB_TYPE(TRB_STOP_RING):
1500                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1501                 break;
1502         case TRB_TYPE(TRB_SET_DEQ):
1503                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1504                 break;
1505         case TRB_TYPE(TRB_CMD_NOOP):
1506                 break;
1507         case TRB_TYPE(TRB_RESET_EP):
1508                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1509                 break;
1510         case TRB_TYPE(TRB_RESET_DEV):
1511                 xhci_dbg(xhci, "Completed reset device command.\n");
1512                 slot_id = TRB_TO_SLOT_ID(
1513                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1514                 virt_dev = xhci->devs[slot_id];
1515                 if (virt_dev)
1516                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1517                 else
1518                         xhci_warn(xhci, "Reset device command completion "
1519                                         "for disabled slot %u\n", slot_id);
1520                 break;
1521         case TRB_TYPE(TRB_NEC_GET_FW):
1522                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1523                         xhci->error_bitmask |= 1 << 6;
1524                         break;
1525                 }
1526                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1527                         "NEC firmware version %2x.%02x",
1528                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1529                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1530                 break;
1531         default:
1532                 /* Skip over unknown commands on the event ring */
1533                 xhci->error_bitmask |= 1 << 6;
1534                 break;
1535         }
1536         inc_deq(xhci, xhci->cmd_ring);
1537 }
1538
1539 static void handle_vendor_event(struct xhci_hcd *xhci,
1540                 union xhci_trb *event)
1541 {
1542         u32 trb_type;
1543
1544         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1545         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1546         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1547                 handle_cmd_completion(xhci, &event->event_cmd);
1548 }
1549
1550 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1551  * port registers -- USB 3.0 and USB 2.0).
1552  *
1553  * Returns a zero-based port number, which is suitable for indexing into each of
1554  * the split roothubs' port arrays and bus state arrays.
1555  * Add one to it in order to call xhci_find_slot_id_by_port.
1556  */
1557 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1558                 struct xhci_hcd *xhci, u32 port_id)
1559 {
1560         unsigned int i;
1561         unsigned int num_similar_speed_ports = 0;
1562
1563         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1564          * and usb2_ports are 0-based indexes.  Count the number of similar
1565          * speed ports, up to 1 port before this port.
1566          */
1567         for (i = 0; i < (port_id - 1); i++) {
1568                 u8 port_speed = xhci->port_array[i];
1569
1570                 /*
1571                  * Skip ports that don't have known speeds, or have duplicate
1572                  * Extended Capabilities port speed entries.
1573                  */
1574                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1575                         continue;
1576
1577                 /*
1578                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1579                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1580                  * matches the device speed, it's a similar speed port.
1581                  */
1582                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1583                         num_similar_speed_ports++;
1584         }
1585         return num_similar_speed_ports;
1586 }
1587
1588 static void handle_device_notification(struct xhci_hcd *xhci,
1589                 union xhci_trb *event)
1590 {
1591         u32 slot_id;
1592         struct usb_device *udev;
1593
1594         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1595         if (!xhci->devs[slot_id]) {
1596                 xhci_warn(xhci, "Device Notification event for "
1597                                 "unused slot %u\n", slot_id);
1598                 return;
1599         }
1600
1601         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1602                         slot_id);
1603         udev = xhci->devs[slot_id]->udev;
1604         if (udev && udev->parent)
1605                 usb_wakeup_notification(udev->parent, udev->portnum);
1606 }
1607
1608 static void handle_port_status(struct xhci_hcd *xhci,
1609                 union xhci_trb *event)
1610 {
1611         struct usb_hcd *hcd;
1612         u32 port_id;
1613         u32 temp, temp1;
1614         int max_ports;
1615         int slot_id;
1616         unsigned int faked_port_index;
1617         u8 major_revision;
1618         struct xhci_bus_state *bus_state;
1619         __le32 __iomem **port_array;
1620         bool bogus_port_status = false;
1621
1622         /* Port status change events always have a successful completion code */
1623         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1624                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1625                 xhci->error_bitmask |= 1 << 8;
1626         }
1627         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1628         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1629
1630         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1631         if ((port_id <= 0) || (port_id > max_ports)) {
1632                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1633                 inc_deq(xhci, xhci->event_ring);
1634                 return;
1635         }
1636
1637         /* Figure out which usb_hcd this port is attached to:
1638          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1639          */
1640         major_revision = xhci->port_array[port_id - 1];
1641
1642         /* Find the right roothub. */
1643         hcd = xhci_to_hcd(xhci);
1644         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1645                 hcd = xhci->shared_hcd;
1646
1647         if (major_revision == 0) {
1648                 xhci_warn(xhci, "Event for port %u not in "
1649                                 "Extended Capabilities, ignoring.\n",
1650                                 port_id);
1651                 bogus_port_status = true;
1652                 goto cleanup;
1653         }
1654         if (major_revision == DUPLICATE_ENTRY) {
1655                 xhci_warn(xhci, "Event for port %u duplicated in"
1656                                 "Extended Capabilities, ignoring.\n",
1657                                 port_id);
1658                 bogus_port_status = true;
1659                 goto cleanup;
1660         }
1661
1662         /*
1663          * Hardware port IDs reported by a Port Status Change Event include USB
1664          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1665          * resume event, but we first need to translate the hardware port ID
1666          * into the index into the ports on the correct split roothub, and the
1667          * correct bus_state structure.
1668          */
1669         bus_state = &xhci->bus_state[hcd_index(hcd)];
1670         if (hcd->speed == HCD_USB3)
1671                 port_array = xhci->usb3_ports;
1672         else
1673                 port_array = xhci->usb2_ports;
1674         /* Find the faked port hub number */
1675         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1676                         port_id);
1677
1678         temp = xhci_readl(xhci, port_array[faked_port_index]);
1679         if (hcd->state == HC_STATE_SUSPENDED) {
1680                 xhci_dbg(xhci, "resume root hub\n");
1681                 usb_hcd_resume_root_hub(hcd);
1682         }
1683
1684         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1685                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1686
1687                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1688                 if (!(temp1 & CMD_RUN)) {
1689                         xhci_warn(xhci, "xHC is not running.\n");
1690                         goto cleanup;
1691                 }
1692
1693                 if (DEV_SUPERSPEED(temp)) {
1694                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1695                         /* Set a flag to say the port signaled remote wakeup,
1696                          * so we can tell the difference between the end of
1697                          * device and host initiated resume.
1698                          */
1699                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1700                         xhci_test_and_clear_bit(xhci, port_array,
1701                                         faked_port_index, PORT_PLC);
1702                         xhci_set_link_state(xhci, port_array, faked_port_index,
1703                                                 XDEV_U0);
1704                         /* Need to wait until the next link state change
1705                          * indicates the device is actually in U0.
1706                          */
1707                         bogus_port_status = true;
1708                         goto cleanup;
1709                 } else {
1710                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1711                         bus_state->resume_done[faked_port_index] = jiffies +
1712                                 msecs_to_jiffies(20);
1713                         set_bit(faked_port_index, &bus_state->resuming_ports);
1714                         mod_timer(&hcd->rh_timer,
1715                                   bus_state->resume_done[faked_port_index]);
1716                         /* Do the rest in GetPortStatus */
1717                 }
1718         }
1719
1720         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1721                         DEV_SUPERSPEED(temp)) {
1722                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1723                 /* We've just brought the device into U0 through either the
1724                  * Resume state after a device remote wakeup, or through the
1725                  * U3Exit state after a host-initiated resume.  If it's a device
1726                  * initiated remote wake, don't pass up the link state change,
1727                  * so the roothub behavior is consistent with external
1728                  * USB 3.0 hub behavior.
1729                  */
1730                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1731                                 faked_port_index + 1);
1732                 if (slot_id && xhci->devs[slot_id])
1733                         xhci_ring_device(xhci, slot_id);
1734                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1735                         bus_state->port_remote_wakeup &=
1736                                 ~(1 << faked_port_index);
1737                         xhci_test_and_clear_bit(xhci, port_array,
1738                                         faked_port_index, PORT_PLC);
1739                         usb_wakeup_notification(hcd->self.root_hub,
1740                                         faked_port_index + 1);
1741                         bogus_port_status = true;
1742                         goto cleanup;
1743                 }
1744         }
1745
1746         if (hcd->speed != HCD_USB3)
1747                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1748                                         PORT_PLC);
1749
1750 cleanup:
1751         /* Update event ring dequeue pointer before dropping the lock */
1752         inc_deq(xhci, xhci->event_ring);
1753
1754         /* Don't make the USB core poll the roothub if we got a bad port status
1755          * change event.  Besides, at that point we can't tell which roothub
1756          * (USB 2.0 or USB 3.0) to kick.
1757          */
1758         if (bogus_port_status)
1759                 return;
1760
1761         /*
1762          * xHCI port-status-change events occur when the "or" of all the
1763          * status-change bits in the portsc register changes from 0 to 1.
1764          * New status changes won't cause an event if any other change
1765          * bits are still set.  When an event occurs, switch over to
1766          * polling to avoid losing status changes.
1767          */
1768         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1769         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1770         spin_unlock(&xhci->lock);
1771         /* Pass this up to the core */
1772         usb_hcd_poll_rh_status(hcd);
1773         spin_lock(&xhci->lock);
1774 }
1775
1776 /*
1777  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1778  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1779  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1780  * returns 0.
1781  */
1782 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1783                 union xhci_trb  *start_trb,
1784                 union xhci_trb  *end_trb,
1785                 dma_addr_t      suspect_dma)
1786 {
1787         dma_addr_t start_dma;
1788         dma_addr_t end_seg_dma;
1789         dma_addr_t end_trb_dma;
1790         struct xhci_segment *cur_seg;
1791
1792         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1793         cur_seg = start_seg;
1794
1795         do {
1796                 if (start_dma == 0)
1797                         return NULL;
1798                 /* We may get an event for a Link TRB in the middle of a TD */
1799                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1800                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1801                 /* If the end TRB isn't in this segment, this is set to 0 */
1802                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1803
1804                 if (end_trb_dma > 0) {
1805                         /* The end TRB is in this segment, so suspect should be here */
1806                         if (start_dma <= end_trb_dma) {
1807                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1808                                         return cur_seg;
1809                         } else {
1810                                 /* Case for one segment with
1811                                  * a TD wrapped around to the top
1812                                  */
1813                                 if ((suspect_dma >= start_dma &&
1814                                                         suspect_dma <= end_seg_dma) ||
1815                                                 (suspect_dma >= cur_seg->dma &&
1816                                                  suspect_dma <= end_trb_dma))
1817                                         return cur_seg;
1818                         }
1819                         return NULL;
1820                 } else {
1821                         /* Might still be somewhere in this segment */
1822                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1823                                 return cur_seg;
1824                 }
1825                 cur_seg = cur_seg->next;
1826                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1827         } while (cur_seg != start_seg);
1828
1829         return NULL;
1830 }
1831
1832 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1833                 unsigned int slot_id, unsigned int ep_index,
1834                 unsigned int stream_id,
1835                 struct xhci_td *td, union xhci_trb *event_trb)
1836 {
1837         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1838         ep->ep_state |= EP_HALTED;
1839         ep->stopped_td = td;
1840         ep->stopped_trb = event_trb;
1841         ep->stopped_stream = stream_id;
1842
1843         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1844         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1845
1846         ep->stopped_td = NULL;
1847         ep->stopped_trb = NULL;
1848         ep->stopped_stream = 0;
1849
1850         xhci_ring_cmd_db(xhci);
1851 }
1852
1853 /* Check if an error has halted the endpoint ring.  The class driver will
1854  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1855  * However, a babble and other errors also halt the endpoint ring, and the class
1856  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1857  * Ring Dequeue Pointer command manually.
1858  */
1859 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1860                 struct xhci_ep_ctx *ep_ctx,
1861                 unsigned int trb_comp_code)
1862 {
1863         /* TRB completion codes that may require a manual halt cleanup */
1864         if (trb_comp_code == COMP_TX_ERR ||
1865                         trb_comp_code == COMP_BABBLE ||
1866                         trb_comp_code == COMP_SPLIT_ERR)
1867                 /* The 0.96 spec says a babbling control endpoint
1868                  * is not halted. The 0.96 spec says it is.  Some HW
1869                  * claims to be 0.95 compliant, but it halts the control
1870                  * endpoint anyway.  Check if a babble halted the
1871                  * endpoint.
1872                  */
1873                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1874                     cpu_to_le32(EP_STATE_HALTED))
1875                         return 1;
1876
1877         return 0;
1878 }
1879
1880 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1881 {
1882         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1883                 /* Vendor defined "informational" completion code,
1884                  * treat as not-an-error.
1885                  */
1886                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1887                                 trb_comp_code);
1888                 xhci_dbg(xhci, "Treating code as success.\n");
1889                 return 1;
1890         }
1891         return 0;
1892 }
1893
1894 /*
1895  * Finish the td processing, remove the td from td list;
1896  * Return 1 if the urb can be given back.
1897  */
1898 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1899         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1900         struct xhci_virt_ep *ep, int *status, bool skip)
1901 {
1902         struct xhci_virt_device *xdev;
1903         struct xhci_ring *ep_ring;
1904         unsigned int slot_id;
1905         int ep_index;
1906         struct urb *urb = NULL;
1907         struct xhci_ep_ctx *ep_ctx;
1908         int ret = 0;
1909         struct urb_priv *urb_priv;
1910         u32 trb_comp_code;
1911
1912         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1913         xdev = xhci->devs[slot_id];
1914         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1915         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1916         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1917         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1918
1919         if (skip)
1920                 goto td_cleanup;
1921
1922         if (trb_comp_code == COMP_STOP_INVAL ||
1923                         trb_comp_code == COMP_STOP) {
1924                 /* The Endpoint Stop Command completion will take care of any
1925                  * stopped TDs.  A stopped TD may be restarted, so don't update
1926                  * the ring dequeue pointer or take this TD off any lists yet.
1927                  */
1928                 ep->stopped_td = td;
1929                 ep->stopped_trb = event_trb;
1930                 return 0;
1931         } else {
1932                 if (trb_comp_code == COMP_STALL) {
1933                         /* The transfer is completed from the driver's
1934                          * perspective, but we need to issue a set dequeue
1935                          * command for this stalled endpoint to move the dequeue
1936                          * pointer past the TD.  We can't do that here because
1937                          * the halt condition must be cleared first.  Let the
1938                          * USB class driver clear the stall later.
1939                          */
1940                         ep->stopped_td = td;
1941                         ep->stopped_trb = event_trb;
1942                         ep->stopped_stream = ep_ring->stream_id;
1943                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1944                                         ep_ctx, trb_comp_code)) {
1945                         /* Other types of errors halt the endpoint, but the
1946                          * class driver doesn't call usb_reset_endpoint() unless
1947                          * the error is -EPIPE.  Clear the halted status in the
1948                          * xHCI hardware manually.
1949                          */
1950                         xhci_cleanup_halted_endpoint(xhci,
1951                                         slot_id, ep_index, ep_ring->stream_id,
1952                                         td, event_trb);
1953                 } else {
1954                         /* Update ring dequeue pointer */
1955                         while (ep_ring->dequeue != td->last_trb)
1956                                 inc_deq(xhci, ep_ring);
1957                         inc_deq(xhci, ep_ring);
1958                 }
1959
1960 td_cleanup:
1961                 /* Clean up the endpoint's TD list */
1962                 urb = td->urb;
1963                 urb_priv = urb->hcpriv;
1964
1965                 /* Do one last check of the actual transfer length.
1966                  * If the host controller said we transferred more data than
1967                  * the buffer length, urb->actual_length will be a very big
1968                  * number (since it's unsigned).  Play it safe and say we didn't
1969                  * transfer anything.
1970                  */
1971                 if (urb->actual_length > urb->transfer_buffer_length) {
1972                         xhci_warn(xhci, "URB transfer length is wrong, "
1973                                         "xHC issue? req. len = %u, "
1974                                         "act. len = %u\n",
1975                                         urb->transfer_buffer_length,
1976                                         urb->actual_length);
1977                         urb->actual_length = 0;
1978                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1979                                 *status = -EREMOTEIO;
1980                         else
1981                                 *status = 0;
1982                 }
1983                 list_del_init(&td->td_list);
1984                 /* Was this TD slated to be cancelled but completed anyway? */
1985                 if (!list_empty(&td->cancelled_td_list))
1986                         list_del_init(&td->cancelled_td_list);
1987
1988                 urb_priv->td_cnt++;
1989                 /* Giveback the urb when all the tds are completed */
1990                 if (urb_priv->td_cnt == urb_priv->length) {
1991                         ret = 1;
1992                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1993                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1994                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1995                                         == 0) {
1996                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1997                                                 usb_amd_quirk_pll_enable();
1998                                 }
1999                         }
2000                 }
2001         }
2002
2003         return ret;
2004 }
2005
2006 /*
2007  * Process control tds, update urb status and actual_length.
2008  */
2009 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2010         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2011         struct xhci_virt_ep *ep, int *status)
2012 {
2013         struct xhci_virt_device *xdev;
2014         struct xhci_ring *ep_ring;
2015         unsigned int slot_id;
2016         int ep_index;
2017         struct xhci_ep_ctx *ep_ctx;
2018         u32 trb_comp_code;
2019
2020         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2021         xdev = xhci->devs[slot_id];
2022         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2023         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2024         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2025         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2026
2027         switch (trb_comp_code) {
2028         case COMP_SUCCESS:
2029                 if (event_trb == ep_ring->dequeue) {
2030                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2031                                         "without IOC set??\n");
2032                         *status = -ESHUTDOWN;
2033                 } else if (event_trb != td->last_trb) {
2034                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2035                                         "without IOC set??\n");
2036                         *status = -ESHUTDOWN;
2037                 } else {
2038                         *status = 0;
2039                 }
2040                 break;
2041         case COMP_SHORT_TX:
2042                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2043                         *status = -EREMOTEIO;
2044                 else
2045                         *status = 0;
2046                 break;
2047         case COMP_STOP_INVAL:
2048         case COMP_STOP:
2049                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2050         default:
2051                 if (!xhci_requires_manual_halt_cleanup(xhci,
2052                                         ep_ctx, trb_comp_code))
2053                         break;
2054                 xhci_dbg(xhci, "TRB error code %u, "
2055                                 "halted endpoint index = %u\n",
2056                                 trb_comp_code, ep_index);
2057                 /* else fall through */
2058         case COMP_STALL:
2059                 /* Did we transfer part of the data (middle) phase? */
2060                 if (event_trb != ep_ring->dequeue &&
2061                                 event_trb != td->last_trb)
2062                         td->urb->actual_length =
2063                                 td->urb->transfer_buffer_length -
2064                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2065                 else
2066                         td->urb->actual_length = 0;
2067
2068                 xhci_cleanup_halted_endpoint(xhci,
2069                         slot_id, ep_index, 0, td, event_trb);
2070                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2071         }
2072         /*
2073          * Did we transfer any data, despite the errors that might have
2074          * happened?  I.e. did we get past the setup stage?
2075          */
2076         if (event_trb != ep_ring->dequeue) {
2077                 /* The event was for the status stage */
2078                 if (event_trb == td->last_trb) {
2079                         if (td->urb->actual_length != 0) {
2080                                 /* Don't overwrite a previously set error code
2081                                  */
2082                                 if ((*status == -EINPROGRESS || *status == 0) &&
2083                                                 (td->urb->transfer_flags
2084                                                  & URB_SHORT_NOT_OK))
2085                                         /* Did we already see a short data
2086                                          * stage? */
2087                                         *status = -EREMOTEIO;
2088                         } else {
2089                                 td->urb->actual_length =
2090                                         td->urb->transfer_buffer_length;
2091                         }
2092                 } else {
2093                 /* Maybe the event was for the data stage? */
2094                         td->urb->actual_length =
2095                                 td->urb->transfer_buffer_length -
2096                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2097                         xhci_dbg(xhci, "Waiting for status "
2098                                         "stage event\n");
2099                         return 0;
2100                 }
2101         }
2102
2103         return finish_td(xhci, td, event_trb, event, ep, status, false);
2104 }
2105
2106 /*
2107  * Process isochronous tds, update urb packet status and actual_length.
2108  */
2109 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2110         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2111         struct xhci_virt_ep *ep, int *status)
2112 {
2113         struct xhci_ring *ep_ring;
2114         struct urb_priv *urb_priv;
2115         int idx;
2116         int len = 0;
2117         union xhci_trb *cur_trb;
2118         struct xhci_segment *cur_seg;
2119         struct usb_iso_packet_descriptor *frame;
2120         u32 trb_comp_code;
2121         bool skip_td = false;
2122
2123         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2124         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2125         urb_priv = td->urb->hcpriv;
2126         idx = urb_priv->td_cnt;
2127         frame = &td->urb->iso_frame_desc[idx];
2128
2129         /* handle completion code */
2130         switch (trb_comp_code) {
2131         case COMP_SUCCESS:
2132                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2133                         frame->status = 0;
2134                         break;
2135                 }
2136                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2137                         trb_comp_code = COMP_SHORT_TX;
2138         case COMP_SHORT_TX:
2139                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2140                                 -EREMOTEIO : 0;
2141                 break;
2142         case COMP_BW_OVER:
2143                 frame->status = -ECOMM;
2144                 skip_td = true;
2145                 break;
2146         case COMP_BUFF_OVER:
2147         case COMP_BABBLE:
2148                 frame->status = -EOVERFLOW;
2149                 skip_td = true;
2150                 break;
2151         case COMP_DEV_ERR:
2152         case COMP_STALL:
2153         case COMP_TX_ERR:
2154                 frame->status = -EPROTO;
2155                 skip_td = true;
2156                 break;
2157         case COMP_STOP:
2158         case COMP_STOP_INVAL:
2159                 break;
2160         default:
2161                 frame->status = -1;
2162                 break;
2163         }
2164
2165         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2166                 frame->actual_length = frame->length;
2167                 td->urb->actual_length += frame->length;
2168         } else {
2169                 for (cur_trb = ep_ring->dequeue,
2170                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2171                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2172                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2173                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2174                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2175                 }
2176                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2177                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2178
2179                 if (trb_comp_code != COMP_STOP_INVAL) {
2180                         frame->actual_length = len;
2181                         td->urb->actual_length += len;
2182                 }
2183         }
2184
2185         return finish_td(xhci, td, event_trb, event, ep, status, false);
2186 }
2187
2188 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2189                         struct xhci_transfer_event *event,
2190                         struct xhci_virt_ep *ep, int *status)
2191 {
2192         struct xhci_ring *ep_ring;
2193         struct urb_priv *urb_priv;
2194         struct usb_iso_packet_descriptor *frame;
2195         int idx;
2196
2197         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2198         urb_priv = td->urb->hcpriv;
2199         idx = urb_priv->td_cnt;
2200         frame = &td->urb->iso_frame_desc[idx];
2201
2202         /* The transfer is partly done. */
2203         frame->status = -EXDEV;
2204
2205         /* calc actual length */
2206         frame->actual_length = 0;
2207
2208         /* Update ring dequeue pointer */
2209         while (ep_ring->dequeue != td->last_trb)
2210                 inc_deq(xhci, ep_ring);
2211         inc_deq(xhci, ep_ring);
2212
2213         return finish_td(xhci, td, NULL, event, ep, status, true);
2214 }
2215
2216 /*
2217  * Process bulk and interrupt tds, update urb status and actual_length.
2218  */
2219 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2220         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2221         struct xhci_virt_ep *ep, int *status)
2222 {
2223         struct xhci_ring *ep_ring;
2224         union xhci_trb *cur_trb;
2225         struct xhci_segment *cur_seg;
2226         u32 trb_comp_code;
2227
2228         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2229         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2230
2231         switch (trb_comp_code) {
2232         case COMP_SUCCESS:
2233                 /* Double check that the HW transferred everything. */
2234                 if (event_trb != td->last_trb ||
2235                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2236                         xhci_warn(xhci, "WARN Successful completion "
2237                                         "on short TX\n");
2238                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2239                                 *status = -EREMOTEIO;
2240                         else
2241                                 *status = 0;
2242                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2243                                 trb_comp_code = COMP_SHORT_TX;
2244                 } else {
2245                         *status = 0;
2246                 }
2247                 break;
2248         case COMP_SHORT_TX:
2249                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2250                         *status = -EREMOTEIO;
2251                 else
2252                         *status = 0;
2253                 break;
2254         default:
2255                 /* Others already handled above */
2256                 break;
2257         }
2258         if (trb_comp_code == COMP_SHORT_TX)
2259                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2260                                 "%d bytes untransferred\n",
2261                                 td->urb->ep->desc.bEndpointAddress,
2262                                 td->urb->transfer_buffer_length,
2263                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2264         /* Fast path - was this the last TRB in the TD for this URB? */
2265         if (event_trb == td->last_trb) {
2266                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2267                         td->urb->actual_length =
2268                                 td->urb->transfer_buffer_length -
2269                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2270                         if (td->urb->transfer_buffer_length <
2271                                         td->urb->actual_length) {
2272                                 xhci_warn(xhci, "HC gave bad length "
2273                                                 "of %d bytes left\n",
2274                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2275                                 td->urb->actual_length = 0;
2276                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2277                                         *status = -EREMOTEIO;
2278                                 else
2279                                         *status = 0;
2280                         }
2281                         /* Don't overwrite a previously set error code */
2282                         if (*status == -EINPROGRESS) {
2283                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2284                                         *status = -EREMOTEIO;
2285                                 else
2286                                         *status = 0;
2287                         }
2288                 } else {
2289                         td->urb->actual_length =
2290                                 td->urb->transfer_buffer_length;
2291                         /* Ignore a short packet completion if the
2292                          * untransferred length was zero.
2293                          */
2294                         if (*status == -EREMOTEIO)
2295                                 *status = 0;
2296                 }
2297         } else {
2298                 /* Slow path - walk the list, starting from the dequeue
2299                  * pointer, to get the actual length transferred.
2300                  */
2301                 td->urb->actual_length = 0;
2302                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2303                                 cur_trb != event_trb;
2304                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2305                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2306                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2307                                 td->urb->actual_length +=
2308                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2309                 }
2310                 /* If the ring didn't stop on a Link or No-op TRB, add
2311                  * in the actual bytes transferred from the Normal TRB
2312                  */
2313                 if (trb_comp_code != COMP_STOP_INVAL)
2314                         td->urb->actual_length +=
2315                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2316                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2317         }
2318
2319         return finish_td(xhci, td, event_trb, event, ep, status, false);
2320 }
2321
2322 /*
2323  * If this function returns an error condition, it means it got a Transfer
2324  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2325  * At this point, the host controller is probably hosed and should be reset.
2326  */
2327 static int handle_tx_event(struct xhci_hcd *xhci,
2328                 struct xhci_transfer_event *event)
2329         __releases(&xhci->lock)
2330         __acquires(&xhci->lock)
2331 {
2332         struct xhci_virt_device *xdev;
2333         struct xhci_virt_ep *ep;
2334         struct xhci_ring *ep_ring;
2335         unsigned int slot_id;
2336         int ep_index;
2337         struct xhci_td *td = NULL;
2338         dma_addr_t event_dma;
2339         struct xhci_segment *event_seg;
2340         union xhci_trb *event_trb;
2341         struct urb *urb = NULL;
2342         int status = -EINPROGRESS;
2343         struct urb_priv *urb_priv;
2344         struct xhci_ep_ctx *ep_ctx;
2345         struct list_head *tmp;
2346         u32 trb_comp_code;
2347         int ret = 0;
2348         int td_num = 0;
2349
2350         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2351         xdev = xhci->devs[slot_id];
2352         if (!xdev) {
2353                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2354                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2355                          (unsigned long long) xhci_trb_virt_to_dma(
2356                                  xhci->event_ring->deq_seg,
2357                                  xhci->event_ring->dequeue),
2358                          lower_32_bits(le64_to_cpu(event->buffer)),
2359                          upper_32_bits(le64_to_cpu(event->buffer)),
2360                          le32_to_cpu(event->transfer_len),
2361                          le32_to_cpu(event->flags));
2362                 xhci_dbg(xhci, "Event ring:\n");
2363                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2364                 return -ENODEV;
2365         }
2366
2367         /* Endpoint ID is 1 based, our index is zero based */
2368         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2369         ep = &xdev->eps[ep_index];
2370         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2371         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2372         if (!ep_ring ||
2373             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2374             EP_STATE_DISABLED) {
2375                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2376                                 "or incorrect stream ring\n");
2377                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2378                          (unsigned long long) xhci_trb_virt_to_dma(
2379                                  xhci->event_ring->deq_seg,
2380                                  xhci->event_ring->dequeue),
2381                          lower_32_bits(le64_to_cpu(event->buffer)),
2382                          upper_32_bits(le64_to_cpu(event->buffer)),
2383                          le32_to_cpu(event->transfer_len),
2384                          le32_to_cpu(event->flags));
2385                 xhci_dbg(xhci, "Event ring:\n");
2386                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2387                 return -ENODEV;
2388         }
2389
2390         /* Count current td numbers if ep->skip is set */
2391         if (ep->skip) {
2392                 list_for_each(tmp, &ep_ring->td_list)
2393                         td_num++;
2394         }
2395
2396         event_dma = le64_to_cpu(event->buffer);
2397         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2398         /* Look for common error cases */
2399         switch (trb_comp_code) {
2400         /* Skip codes that require special handling depending on
2401          * transfer type
2402          */
2403         case COMP_SUCCESS:
2404                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2405                         break;
2406                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2407                         trb_comp_code = COMP_SHORT_TX;
2408                 else
2409                         xhci_warn_ratelimited(xhci,
2410                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2411         case COMP_SHORT_TX:
2412                 break;
2413         case COMP_STOP:
2414                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2415                 break;
2416         case COMP_STOP_INVAL:
2417                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2418                 break;
2419         case COMP_STALL:
2420                 xhci_dbg(xhci, "Stalled endpoint\n");
2421                 ep->ep_state |= EP_HALTED;
2422                 status = -EPIPE;
2423                 break;
2424         case COMP_TRB_ERR:
2425                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2426                 status = -EILSEQ;
2427                 break;
2428         case COMP_SPLIT_ERR:
2429         case COMP_TX_ERR:
2430                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2431                 status = -EPROTO;
2432                 break;
2433         case COMP_BABBLE:
2434                 xhci_dbg(xhci, "Babble error on endpoint\n");
2435                 status = -EOVERFLOW;
2436                 break;
2437         case COMP_DB_ERR:
2438                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2439                 status = -ENOSR;
2440                 break;
2441         case COMP_BW_OVER:
2442                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2443                 break;
2444         case COMP_BUFF_OVER:
2445                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2446                 break;
2447         case COMP_UNDERRUN:
2448                 /*
2449                  * When the Isoch ring is empty, the xHC will generate
2450                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2451                  * Underrun Event for OUT Isoch endpoint.
2452                  */
2453                 xhci_dbg(xhci, "underrun event on endpoint\n");
2454                 if (!list_empty(&ep_ring->td_list))
2455                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2456                                         "still with TDs queued?\n",
2457                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2458                                  ep_index);
2459                 goto cleanup;
2460         case COMP_OVERRUN:
2461                 xhci_dbg(xhci, "overrun event on endpoint\n");
2462                 if (!list_empty(&ep_ring->td_list))
2463                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2464                                         "still with TDs queued?\n",
2465                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2466                                  ep_index);
2467                 goto cleanup;
2468         case COMP_DEV_ERR:
2469                 xhci_warn(xhci, "WARN: detect an incompatible device");
2470                 status = -EPROTO;
2471                 break;
2472         case COMP_MISSED_INT:
2473                 /*
2474                  * When encounter missed service error, one or more isoc tds
2475                  * may be missed by xHC.
2476                  * Set skip flag of the ep_ring; Complete the missed tds as
2477                  * short transfer when process the ep_ring next time.
2478                  */
2479                 ep->skip = true;
2480                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2481                 goto cleanup;
2482         default:
2483                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2484                         status = 0;
2485                         break;
2486                 }
2487                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2488                                 "busted\n");
2489                 goto cleanup;
2490         }
2491
2492         do {
2493                 /* This TRB should be in the TD at the head of this ring's
2494                  * TD list.
2495                  */
2496                 if (list_empty(&ep_ring->td_list)) {
2497                         /*
2498                          * A stopped endpoint may generate an extra completion
2499                          * event if the device was suspended.  Don't print
2500                          * warnings.
2501                          */
2502                         if (!(trb_comp_code == COMP_STOP ||
2503                                                 trb_comp_code == COMP_STOP_INVAL)) {
2504                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2505                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2506                                                 ep_index);
2507                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2508                                                 (le32_to_cpu(event->flags) &
2509                                                  TRB_TYPE_BITMASK)>>10);
2510                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2511                         }
2512                         if (ep->skip) {
2513                                 ep->skip = false;
2514                                 xhci_dbg(xhci, "td_list is empty while skip "
2515                                                 "flag set. Clear skip flag.\n");
2516                         }
2517                         ret = 0;
2518                         goto cleanup;
2519                 }
2520
2521                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2522                 if (ep->skip && td_num == 0) {
2523                         ep->skip = false;
2524                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2525                                                 "Clear skip flag.\n");
2526                         ret = 0;
2527                         goto cleanup;
2528                 }
2529
2530                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2531                 if (ep->skip)
2532                         td_num--;
2533
2534                 /* Is this a TRB in the currently executing TD? */
2535                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2536                                 td->last_trb, event_dma);
2537
2538                 /*
2539                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2540                  * is not in the current TD pointed by ep_ring->dequeue because
2541                  * that the hardware dequeue pointer still at the previous TRB
2542                  * of the current TD. The previous TRB maybe a Link TD or the
2543                  * last TRB of the previous TD. The command completion handle
2544                  * will take care the rest.
2545                  */
2546                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2547                         ret = 0;
2548                         goto cleanup;
2549                 }
2550
2551                 if (!event_seg) {
2552                         if (!ep->skip ||
2553                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2554                                 /* Some host controllers give a spurious
2555                                  * successful event after a short transfer.
2556                                  * Ignore it.
2557                                  */
2558                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2559                                                 ep_ring->last_td_was_short) {
2560                                         ep_ring->last_td_was_short = false;
2561                                         ret = 0;
2562                                         goto cleanup;
2563                                 }
2564                                 /* HC is busted, give up! */
2565                                 xhci_err(xhci,
2566                                         "ERROR Transfer event TRB DMA ptr not "
2567                                         "part of current TD\n");
2568                                 return -ESHUTDOWN;
2569                         }
2570
2571                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2572                         goto cleanup;
2573                 }
2574                 if (trb_comp_code == COMP_SHORT_TX)
2575                         ep_ring->last_td_was_short = true;
2576                 else
2577                         ep_ring->last_td_was_short = false;
2578
2579                 if (ep->skip) {
2580                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2581                         ep->skip = false;
2582                 }
2583
2584                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2585                                                 sizeof(*event_trb)];
2586                 /*
2587                  * No-op TRB should not trigger interrupts.
2588                  * If event_trb is a no-op TRB, it means the
2589                  * corresponding TD has been cancelled. Just ignore
2590                  * the TD.
2591                  */
2592                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2593                         xhci_dbg(xhci,
2594                                  "event_trb is a no-op TRB. Skip it\n");
2595                         goto cleanup;
2596                 }
2597
2598                 /* Now update the urb's actual_length and give back to
2599                  * the core
2600                  */
2601                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2602                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2603                                                  &status);
2604                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2605                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2606                                                  &status);
2607                 else
2608                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2609                                                  ep, &status);
2610
2611 cleanup:
2612                 /*
2613                  * Do not update event ring dequeue pointer if ep->skip is set.
2614                  * Will roll back to continue process missed tds.
2615                  */
2616                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2617                         inc_deq(xhci, xhci->event_ring);
2618                 }
2619
2620                 if (ret) {
2621                         urb = td->urb;
2622                         urb_priv = urb->hcpriv;
2623                         /* Leave the TD around for the reset endpoint function
2624                          * to use(but only if it's not a control endpoint,
2625                          * since we already queued the Set TR dequeue pointer
2626                          * command for stalled control endpoints).
2627                          */
2628                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2629                                 (trb_comp_code != COMP_STALL &&
2630                                         trb_comp_code != COMP_BABBLE))
2631                                 xhci_urb_free_priv(xhci, urb_priv);
2632                         else
2633                                 kfree(urb_priv);
2634
2635                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2636                         if ((urb->actual_length != urb->transfer_buffer_length &&
2637                                                 (urb->transfer_flags &
2638                                                  URB_SHORT_NOT_OK)) ||
2639                                         (status != 0 &&
2640                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2641                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2642                                                 "expected = %d, status = %d\n",
2643                                                 urb, urb->actual_length,
2644                                                 urb->transfer_buffer_length,
2645                                                 status);
2646                         spin_unlock(&xhci->lock);
2647                         /* EHCI, UHCI, and OHCI always unconditionally set the
2648                          * urb->status of an isochronous endpoint to 0.
2649                          */
2650                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2651                                 status = 0;
2652                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2653                         spin_lock(&xhci->lock);
2654                 }
2655
2656         /*
2657          * If ep->skip is set, it means there are missed tds on the
2658          * endpoint ring need to take care of.
2659          * Process them as short transfer until reach the td pointed by
2660          * the event.
2661          */
2662         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2663
2664         return 0;
2665 }
2666
2667 /*
2668  * This function handles all OS-owned events on the event ring.  It may drop
2669  * xhci->lock between event processing (e.g. to pass up port status changes).
2670  * Returns >0 for "possibly more events to process" (caller should call again),
2671  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2672  */
2673 static int xhci_handle_event(struct xhci_hcd *xhci)
2674 {
2675         union xhci_trb *event;
2676         int update_ptrs = 1;
2677         int ret;
2678
2679         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2680                 xhci->error_bitmask |= 1 << 1;
2681                 return 0;
2682         }
2683
2684         event = xhci->event_ring->dequeue;
2685         /* Does the HC or OS own the TRB? */
2686         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2687             xhci->event_ring->cycle_state) {
2688                 xhci->error_bitmask |= 1 << 2;
2689                 return 0;
2690         }
2691
2692         /*
2693          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2694          * speculative reads of the event's flags/data below.
2695          */
2696         rmb();
2697         /* FIXME: Handle more event types. */
2698         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2699         case TRB_TYPE(TRB_COMPLETION):
2700                 handle_cmd_completion(xhci, &event->event_cmd);
2701                 break;
2702         case TRB_TYPE(TRB_PORT_STATUS):
2703                 handle_port_status(xhci, event);
2704                 update_ptrs = 0;
2705                 break;
2706         case TRB_TYPE(TRB_TRANSFER):
2707                 ret = handle_tx_event(xhci, &event->trans_event);
2708                 if (ret < 0)
2709                         xhci->error_bitmask |= 1 << 9;
2710                 else
2711                         update_ptrs = 0;
2712                 break;
2713         case TRB_TYPE(TRB_DEV_NOTE):
2714                 handle_device_notification(xhci, event);
2715                 break;
2716         default:
2717                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2718                     TRB_TYPE(48))
2719                         handle_vendor_event(xhci, event);
2720                 else
2721                         xhci->error_bitmask |= 1 << 3;
2722         }
2723         /* Any of the above functions may drop and re-acquire the lock, so check
2724          * to make sure a watchdog timer didn't mark the host as non-responsive.
2725          */
2726         if (xhci->xhc_state & XHCI_STATE_DYING) {
2727                 xhci_dbg(xhci, "xHCI host dying, returning from "
2728                                 "event handler.\n");
2729                 return 0;
2730         }
2731
2732         if (update_ptrs)
2733                 /* Update SW event ring dequeue pointer */
2734                 inc_deq(xhci, xhci->event_ring);
2735
2736         /* Are there more items on the event ring?  Caller will call us again to
2737          * check.
2738          */
2739         return 1;
2740 }
2741
2742 /*
2743  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2744  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2745  * indicators of an event TRB error, but we check the status *first* to be safe.
2746  */
2747 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2748 {
2749         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2750         u32 status;
2751         u64 temp_64;
2752         union xhci_trb *event_ring_deq;
2753         dma_addr_t deq;
2754
2755         spin_lock(&xhci->lock);
2756         /* Check if the xHC generated the interrupt, or the irq is shared */
2757         status = xhci_readl(xhci, &xhci->op_regs->status);
2758         if (status == 0xffffffff)
2759                 goto hw_died;
2760
2761         if (!(status & STS_EINT)) {
2762                 spin_unlock(&xhci->lock);
2763                 return IRQ_NONE;
2764         }
2765         if (status & STS_FATAL) {
2766                 xhci_warn(xhci, "WARNING: Host System Error\n");
2767                 xhci_halt(xhci);
2768 hw_died:
2769                 spin_unlock(&xhci->lock);
2770                 return -ESHUTDOWN;
2771         }
2772
2773         /*
2774          * Clear the op reg interrupt status first,
2775          * so we can receive interrupts from other MSI-X interrupters.
2776          * Write 1 to clear the interrupt status.
2777          */
2778         status |= STS_EINT;
2779         xhci_writel(xhci, status, &xhci->op_regs->status);
2780         /* FIXME when MSI-X is supported and there are multiple vectors */
2781         /* Clear the MSI-X event interrupt status */
2782
2783         if (hcd->irq) {
2784                 u32 irq_pending;
2785                 /* Acknowledge the PCI interrupt */
2786                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2787                 irq_pending |= IMAN_IP;
2788                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2789         }
2790
2791         if (xhci->xhc_state & XHCI_STATE_DYING) {
2792                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2793                                 "Shouldn't IRQs be disabled?\n");
2794                 /* Clear the event handler busy flag (RW1C);
2795                  * the event ring should be empty.
2796                  */
2797                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2798                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2799                                 &xhci->ir_set->erst_dequeue);
2800                 spin_unlock(&xhci->lock);
2801
2802                 return IRQ_HANDLED;
2803         }
2804
2805         event_ring_deq = xhci->event_ring->dequeue;
2806         /* FIXME this should be a delayed service routine
2807          * that clears the EHB.
2808          */
2809         while (xhci_handle_event(xhci) > 0) {}
2810
2811         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2812         /* If necessary, update the HW's version of the event ring deq ptr. */
2813         if (event_ring_deq != xhci->event_ring->dequeue) {
2814                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2815                                 xhci->event_ring->dequeue);
2816                 if (deq == 0)
2817                         xhci_warn(xhci, "WARN something wrong with SW event "
2818                                         "ring dequeue ptr.\n");
2819                 /* Update HC event ring dequeue pointer */
2820                 temp_64 &= ERST_PTR_MASK;
2821                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2822         }
2823
2824         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2825         temp_64 |= ERST_EHB;
2826         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2827
2828         spin_unlock(&xhci->lock);
2829
2830         return IRQ_HANDLED;
2831 }
2832
2833 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2834 {
2835         return xhci_irq(hcd);
2836 }
2837
2838 /****           Endpoint Ring Operations        ****/
2839
2840 /*
2841  * Generic function for queueing a TRB on a ring.
2842  * The caller must have checked to make sure there's room on the ring.
2843  *
2844  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2845  *                      prepare_transfer()?
2846  */
2847 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2848                 bool more_trbs_coming,
2849                 u32 field1, u32 field2, u32 field3, u32 field4)
2850 {
2851         struct xhci_generic_trb *trb;
2852
2853         trb = &ring->enqueue->generic;
2854         trb->field[0] = cpu_to_le32(field1);
2855         trb->field[1] = cpu_to_le32(field2);
2856         trb->field[2] = cpu_to_le32(field3);
2857         trb->field[3] = cpu_to_le32(field4);
2858         inc_enq(xhci, ring, more_trbs_coming);
2859 }
2860
2861 /*
2862  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2863  * FIXME allocate segments if the ring is full.
2864  */
2865 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2866                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2867 {
2868         unsigned int num_trbs_needed;
2869
2870         /* Make sure the endpoint has been added to xHC schedule */
2871         switch (ep_state) {
2872         case EP_STATE_DISABLED:
2873                 /*
2874                  * USB core changed config/interfaces without notifying us,
2875                  * or hardware is reporting the wrong state.
2876                  */
2877                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2878                 return -ENOENT;
2879         case EP_STATE_ERROR:
2880                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2881                 /* FIXME event handling code for error needs to clear it */
2882                 /* XXX not sure if this should be -ENOENT or not */
2883                 return -EINVAL;
2884         case EP_STATE_HALTED:
2885                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2886         case EP_STATE_STOPPED:
2887         case EP_STATE_RUNNING:
2888                 break;
2889         default:
2890                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2891                 /*
2892                  * FIXME issue Configure Endpoint command to try to get the HC
2893                  * back into a known state.
2894                  */
2895                 return -EINVAL;
2896         }
2897
2898         while (1) {
2899                 if (room_on_ring(xhci, ep_ring, num_trbs))
2900                         break;
2901
2902                 if (ep_ring == xhci->cmd_ring) {
2903                         xhci_err(xhci, "Do not support expand command ring\n");
2904                         return -ENOMEM;
2905                 }
2906
2907                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2908                                 "ERROR no room on ep ring, try ring expansion");
2909                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2910                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2911                                         mem_flags)) {
2912                         xhci_err(xhci, "Ring expansion failed\n");
2913                         return -ENOMEM;
2914                 }
2915         }
2916
2917         if (enqueue_is_link_trb(ep_ring)) {
2918                 struct xhci_ring *ring = ep_ring;
2919                 union xhci_trb *next;
2920
2921                 next = ring->enqueue;
2922
2923                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2924                         /* If we're not dealing with 0.95 hardware or isoc rings
2925                          * on AMD 0.96 host, clear the chain bit.
2926                          */
2927                         if (!xhci_link_trb_quirk(xhci) &&
2928                                         !(ring->type == TYPE_ISOC &&
2929                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2930                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2931                         else
2932                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2933
2934                         wmb();
2935                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2936
2937                         /* Toggle the cycle bit after the last ring segment. */
2938                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2939                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2940                         }
2941                         ring->enq_seg = ring->enq_seg->next;
2942                         ring->enqueue = ring->enq_seg->trbs;
2943                         next = ring->enqueue;
2944                 }
2945         }
2946
2947         return 0;
2948 }
2949
2950 static int prepare_transfer(struct xhci_hcd *xhci,
2951                 struct xhci_virt_device *xdev,
2952                 unsigned int ep_index,
2953                 unsigned int stream_id,
2954                 unsigned int num_trbs,
2955                 struct urb *urb,
2956                 unsigned int td_index,
2957                 gfp_t mem_flags)
2958 {
2959         int ret;
2960         struct urb_priv *urb_priv;
2961         struct xhci_td  *td;
2962         struct xhci_ring *ep_ring;
2963         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2964
2965         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2966         if (!ep_ring) {
2967                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2968                                 stream_id);
2969                 return -EINVAL;
2970         }
2971
2972         ret = prepare_ring(xhci, ep_ring,
2973                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2974                            num_trbs, mem_flags);
2975         if (ret)
2976                 return ret;
2977
2978         urb_priv = urb->hcpriv;
2979         td = urb_priv->td[td_index];
2980
2981         INIT_LIST_HEAD(&td->td_list);
2982         INIT_LIST_HEAD(&td->cancelled_td_list);
2983
2984         if (td_index == 0) {
2985                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2986                 if (unlikely(ret))
2987                         return ret;
2988         }
2989
2990         td->urb = urb;
2991         /* Add this TD to the tail of the endpoint ring's TD list */
2992         list_add_tail(&td->td_list, &ep_ring->td_list);
2993         td->start_seg = ep_ring->enq_seg;
2994         td->first_trb = ep_ring->enqueue;
2995
2996         urb_priv->td[td_index] = td;
2997
2998         return 0;
2999 }
3000
3001 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3002 {
3003         int num_sgs, num_trbs, running_total, temp, i;
3004         struct scatterlist *sg;
3005
3006         sg = NULL;
3007         num_sgs = urb->num_mapped_sgs;
3008         temp = urb->transfer_buffer_length;
3009
3010         num_trbs = 0;
3011         for_each_sg(urb->sg, sg, num_sgs, i) {
3012                 unsigned int len = sg_dma_len(sg);
3013
3014                 /* Scatter gather list entries may cross 64KB boundaries */
3015                 running_total = TRB_MAX_BUFF_SIZE -
3016                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3017                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3018                 if (running_total != 0)
3019                         num_trbs++;
3020
3021                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3022                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3023                         num_trbs++;
3024                         running_total += TRB_MAX_BUFF_SIZE;
3025                 }
3026                 len = min_t(int, len, temp);
3027                 temp -= len;
3028                 if (temp == 0)
3029                         break;
3030         }
3031         return num_trbs;
3032 }
3033
3034 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3035 {
3036         if (num_trbs != 0)
3037                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3038                                 "TRBs, %d left\n", __func__,
3039                                 urb->ep->desc.bEndpointAddress, num_trbs);
3040         if (running_total != urb->transfer_buffer_length)
3041                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3042                                 "queued %#x (%d), asked for %#x (%d)\n",
3043                                 __func__,
3044                                 urb->ep->desc.bEndpointAddress,
3045                                 running_total, running_total,
3046                                 urb->transfer_buffer_length,
3047                                 urb->transfer_buffer_length);
3048 }
3049
3050 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3051                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3052                 struct xhci_generic_trb *start_trb)
3053 {
3054         /*
3055          * Pass all the TRBs to the hardware at once and make sure this write
3056          * isn't reordered.
3057          */
3058         wmb();
3059         if (start_cycle)
3060                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3061         else
3062                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3063         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3064 }
3065
3066 /*
3067  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3068  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3069  * (comprised of sg list entries) can take several service intervals to
3070  * transmit.
3071  */
3072 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3073                 struct urb *urb, int slot_id, unsigned int ep_index)
3074 {
3075         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3076                         xhci->devs[slot_id]->out_ctx, ep_index);
3077         int xhci_interval;
3078         int ep_interval;
3079
3080         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3081         ep_interval = urb->interval;
3082         /* Convert to microframes */
3083         if (urb->dev->speed == USB_SPEED_LOW ||
3084                         urb->dev->speed == USB_SPEED_FULL)
3085                 ep_interval *= 8;
3086         /* FIXME change this to a warning and a suggestion to use the new API
3087          * to set the polling interval (once the API is added).
3088          */
3089         if (xhci_interval != ep_interval) {
3090                 dev_dbg_ratelimited(&urb->dev->dev,
3091                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3092                                 ep_interval, ep_interval == 1 ? "" : "s",
3093                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3094                 urb->interval = xhci_interval;
3095                 /* Convert back to frames for LS/FS devices */
3096                 if (urb->dev->speed == USB_SPEED_LOW ||
3097                                 urb->dev->speed == USB_SPEED_FULL)
3098                         urb->interval /= 8;
3099         }
3100         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3101 }
3102
3103 /*
3104  * The TD size is the number of bytes remaining in the TD (including this TRB),
3105  * right shifted by 10.
3106  * It must fit in bits 21:17, so it can't be bigger than 31.
3107  */
3108 static u32 xhci_td_remainder(unsigned int remainder)
3109 {
3110         u32 max = (1 << (21 - 17 + 1)) - 1;
3111
3112         if ((remainder >> 10) >= max)
3113                 return max << 17;
3114         else
3115                 return (remainder >> 10) << 17;
3116 }
3117
3118 /*
3119  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3120  * packets remaining in the TD (*not* including this TRB).
3121  *
3122  * Total TD packet count = total_packet_count =
3123  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3124  *
3125  * Packets transferred up to and including this TRB = packets_transferred =
3126  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3127  *
3128  * TD size = total_packet_count - packets_transferred
3129  *
3130  * It must fit in bits 21:17, so it can't be bigger than 31.
3131  * The last TRB in a TD must have the TD size set to zero.
3132  */
3133 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3134                 unsigned int total_packet_count, struct urb *urb,
3135                 unsigned int num_trbs_left)
3136 {
3137         int packets_transferred;
3138
3139         /* One TRB with a zero-length data packet. */
3140         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3141                 return 0;
3142
3143         /* All the TRB queueing functions don't count the current TRB in
3144          * running_total.
3145          */
3146         packets_transferred = (running_total + trb_buff_len) /
3147                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3148
3149         if ((total_packet_count - packets_transferred) > 31)
3150                 return 31 << 17;
3151         return (total_packet_count - packets_transferred) << 17;
3152 }
3153
3154 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3155                 struct urb *urb, int slot_id, unsigned int ep_index)
3156 {
3157         struct xhci_ring *ep_ring;
3158         unsigned int num_trbs;
3159         struct urb_priv *urb_priv;
3160         struct xhci_td *td;
3161         struct scatterlist *sg;
3162         int num_sgs;
3163         int trb_buff_len, this_sg_len, running_total;
3164         unsigned int total_packet_count;
3165         bool first_trb;
3166         u64 addr;
3167         bool more_trbs_coming;
3168
3169         struct xhci_generic_trb *start_trb;
3170         int start_cycle;
3171
3172         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3173         if (!ep_ring)
3174                 return -EINVAL;
3175
3176         num_trbs = count_sg_trbs_needed(xhci, urb);
3177         num_sgs = urb->num_mapped_sgs;
3178         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3179                         usb_endpoint_maxp(&urb->ep->desc));
3180
3181         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3182                         ep_index, urb->stream_id,
3183                         num_trbs, urb, 0, mem_flags);
3184         if (trb_buff_len < 0)
3185                 return trb_buff_len;
3186
3187         urb_priv = urb->hcpriv;
3188         td = urb_priv->td[0];
3189
3190         /*
3191          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3192          * until we've finished creating all the other TRBs.  The ring's cycle
3193          * state may change as we enqueue the other TRBs, so save it too.
3194          */
3195         start_trb = &ep_ring->enqueue->generic;
3196         start_cycle = ep_ring->cycle_state;
3197
3198         running_total = 0;
3199         /*
3200          * How much data is in the first TRB?
3201          *
3202          * There are three forces at work for TRB buffer pointers and lengths:
3203          * 1. We don't want to walk off the end of this sg-list entry buffer.
3204          * 2. The transfer length that the driver requested may be smaller than
3205          *    the amount of memory allocated for this scatter-gather list.
3206          * 3. TRBs buffers can't cross 64KB boundaries.
3207          */
3208         sg = urb->sg;
3209         addr = (u64) sg_dma_address(sg);
3210         this_sg_len = sg_dma_len(sg);
3211         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3212         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3213         if (trb_buff_len > urb->transfer_buffer_length)
3214                 trb_buff_len = urb->transfer_buffer_length;
3215
3216         first_trb = true;
3217         /* Queue the first TRB, even if it's zero-length */
3218         do {
3219                 u32 field = 0;
3220                 u32 length_field = 0;
3221                 u32 remainder = 0;
3222
3223                 /* Don't change the cycle bit of the first TRB until later */
3224                 if (first_trb) {
3225                         first_trb = false;
3226                         if (start_cycle == 0)
3227                                 field |= 0x1;
3228                 } else
3229                         field |= ep_ring->cycle_state;
3230
3231                 /* Chain all the TRBs together; clear the chain bit in the last
3232                  * TRB to indicate it's the last TRB in the chain.
3233                  */
3234                 if (num_trbs > 1) {
3235                         field |= TRB_CHAIN;
3236                 } else {
3237                         /* FIXME - add check for ZERO_PACKET flag before this */
3238                         td->last_trb = ep_ring->enqueue;
3239                         field |= TRB_IOC;
3240                 }
3241
3242                 /* Only set interrupt on short packet for IN endpoints */
3243                 if (usb_urb_dir_in(urb))
3244                         field |= TRB_ISP;
3245
3246                 if (TRB_MAX_BUFF_SIZE -
3247                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3248                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3249                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3250                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3251                                         (unsigned int) addr + trb_buff_len);
3252                 }
3253
3254                 /* Set the TRB length, TD size, and interrupter fields. */
3255                 if (xhci->hci_version < 0x100) {
3256                         remainder = xhci_td_remainder(
3257                                         urb->transfer_buffer_length -
3258                                         running_total);
3259                 } else {
3260                         remainder = xhci_v1_0_td_remainder(running_total,
3261                                         trb_buff_len, total_packet_count, urb,
3262                                         num_trbs - 1);
3263                 }
3264                 length_field = TRB_LEN(trb_buff_len) |
3265                         remainder |
3266                         TRB_INTR_TARGET(0);
3267
3268                 if (num_trbs > 1)
3269                         more_trbs_coming = true;
3270                 else
3271                         more_trbs_coming = false;
3272                 queue_trb(xhci, ep_ring, more_trbs_coming,
3273                                 lower_32_bits(addr),
3274                                 upper_32_bits(addr),
3275                                 length_field,
3276                                 field | TRB_TYPE(TRB_NORMAL));
3277                 --num_trbs;
3278                 running_total += trb_buff_len;
3279
3280                 /* Calculate length for next transfer --
3281                  * Are we done queueing all the TRBs for this sg entry?
3282                  */
3283                 this_sg_len -= trb_buff_len;
3284                 if (this_sg_len == 0) {
3285                         --num_sgs;
3286                         if (num_sgs == 0)
3287                                 break;
3288                         sg = sg_next(sg);
3289                         addr = (u64) sg_dma_address(sg);
3290                         this_sg_len = sg_dma_len(sg);
3291                 } else {
3292                         addr += trb_buff_len;
3293                 }
3294
3295                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3296                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3297                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3298                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3299                         trb_buff_len =
3300                                 urb->transfer_buffer_length - running_total;
3301         } while (running_total < urb->transfer_buffer_length);
3302
3303         check_trb_math(urb, num_trbs, running_total);
3304         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3305                         start_cycle, start_trb);
3306         return 0;
3307 }
3308
3309 /* This is very similar to what ehci-q.c qtd_fill() does */
3310 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3311                 struct urb *urb, int slot_id, unsigned int ep_index)
3312 {
3313         struct xhci_ring *ep_ring;
3314         struct urb_priv *urb_priv;
3315         struct xhci_td *td;
3316         int num_trbs;
3317         struct xhci_generic_trb *start_trb;
3318         bool first_trb;
3319         bool more_trbs_coming;
3320         int start_cycle;
3321         u32 field, length_field;
3322
3323         int running_total, trb_buff_len, ret;
3324         unsigned int total_packet_count;
3325         u64 addr;
3326
3327         if (urb->num_sgs)
3328                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3329
3330         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3331         if (!ep_ring)
3332                 return -EINVAL;
3333
3334         num_trbs = 0;
3335         /* How much data is (potentially) left before the 64KB boundary? */
3336         running_total = TRB_MAX_BUFF_SIZE -
3337                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3338         running_total &= TRB_MAX_BUFF_SIZE - 1;
3339
3340         /* If there's some data on this 64KB chunk, or we have to send a
3341          * zero-length transfer, we need at least one TRB
3342          */
3343         if (running_total != 0 || urb->transfer_buffer_length == 0)
3344                 num_trbs++;
3345         /* How many more 64KB chunks to transfer, how many more TRBs? */
3346         while (running_total < urb->transfer_buffer_length) {
3347                 num_trbs++;
3348                 running_total += TRB_MAX_BUFF_SIZE;
3349         }
3350         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3351
3352         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3353                         ep_index, urb->stream_id,
3354                         num_trbs, urb, 0, mem_flags);
3355         if (ret < 0)
3356                 return ret;
3357
3358         urb_priv = urb->hcpriv;
3359         td = urb_priv->td[0];
3360
3361         /*
3362          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3363          * until we've finished creating all the other TRBs.  The ring's cycle
3364          * state may change as we enqueue the other TRBs, so save it too.
3365          */
3366         start_trb = &ep_ring->enqueue->generic;
3367         start_cycle = ep_ring->cycle_state;
3368
3369         running_total = 0;
3370         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3371                         usb_endpoint_maxp(&urb->ep->desc));
3372         /* How much data is in the first TRB? */
3373         addr = (u64) urb->transfer_dma;
3374         trb_buff_len = TRB_MAX_BUFF_SIZE -
3375                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3376         if (trb_buff_len > urb->transfer_buffer_length)
3377                 trb_buff_len = urb->transfer_buffer_length;
3378
3379         first_trb = true;
3380
3381         /* Queue the first TRB, even if it's zero-length */
3382         do {
3383                 u32 remainder = 0;
3384                 field = 0;
3385
3386                 /* Don't change the cycle bit of the first TRB until later */
3387                 if (first_trb) {
3388                         first_trb = false;
3389                         if (start_cycle == 0)
3390                                 field |= 0x1;
3391                 } else
3392                         field |= ep_ring->cycle_state;
3393
3394                 /* Chain all the TRBs together; clear the chain bit in the last
3395                  * TRB to indicate it's the last TRB in the chain.
3396                  */
3397                 if (num_trbs > 1) {
3398                         field |= TRB_CHAIN;
3399                 } else {
3400                         /* FIXME - add check for ZERO_PACKET flag before this */
3401                         td->last_trb = ep_ring->enqueue;
3402                         field |= TRB_IOC;
3403                 }
3404
3405                 /* Only set interrupt on short packet for IN endpoints */
3406                 if (usb_urb_dir_in(urb))
3407                         field |= TRB_ISP;
3408
3409                 /* Set the TRB length, TD size, and interrupter fields. */
3410                 if (xhci->hci_version < 0x100) {
3411                         remainder = xhci_td_remainder(
3412                                         urb->transfer_buffer_length -
3413                                         running_total);
3414                 } else {
3415                         remainder = xhci_v1_0_td_remainder(running_total,
3416                                         trb_buff_len, total_packet_count, urb,
3417                                         num_trbs - 1);
3418                 }
3419                 length_field = TRB_LEN(trb_buff_len) |
3420                         remainder |
3421                         TRB_INTR_TARGET(0);
3422
3423                 if (num_trbs > 1)
3424                         more_trbs_coming = true;
3425                 else
3426                         more_trbs_coming = false;
3427                 queue_trb(xhci, ep_ring, more_trbs_coming,
3428                                 lower_32_bits(addr),
3429                                 upper_32_bits(addr),
3430                                 length_field,
3431                                 field | TRB_TYPE(TRB_NORMAL));
3432                 --num_trbs;
3433                 running_total += trb_buff_len;
3434
3435                 /* Calculate length for next transfer */
3436                 addr += trb_buff_len;
3437                 trb_buff_len = urb->transfer_buffer_length - running_total;
3438                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3439                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3440         } while (running_total < urb->transfer_buffer_length);
3441
3442         check_trb_math(urb, num_trbs, running_total);
3443         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3444                         start_cycle, start_trb);
3445         return 0;
3446 }
3447
3448 /* Caller must have locked xhci->lock */
3449 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3450                 struct urb *urb, int slot_id, unsigned int ep_index)
3451 {
3452         struct xhci_ring *ep_ring;
3453         int num_trbs;
3454         int ret;
3455         struct usb_ctrlrequest *setup;
3456         struct xhci_generic_trb *start_trb;
3457         int start_cycle;
3458         u32 field, length_field;
3459         struct urb_priv *urb_priv;
3460         struct xhci_td *td;
3461
3462         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3463         if (!ep_ring)
3464                 return -EINVAL;
3465
3466         /*
3467          * Need to copy setup packet into setup TRB, so we can't use the setup
3468          * DMA address.
3469          */
3470         if (!urb->setup_packet)
3471                 return -EINVAL;
3472
3473         /* 1 TRB for setup, 1 for status */
3474         num_trbs = 2;
3475         /*
3476          * Don't need to check if we need additional event data and normal TRBs,
3477          * since data in control transfers will never get bigger than 16MB
3478          * XXX: can we get a buffer that crosses 64KB boundaries?
3479          */
3480         if (urb->transfer_buffer_length > 0)
3481                 num_trbs++;
3482         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3483                         ep_index, urb->stream_id,
3484                         num_trbs, urb, 0, mem_flags);
3485         if (ret < 0)
3486                 return ret;
3487
3488         urb_priv = urb->hcpriv;
3489         td = urb_priv->td[0];
3490
3491         /*
3492          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3493          * until we've finished creating all the other TRBs.  The ring's cycle
3494          * state may change as we enqueue the other TRBs, so save it too.
3495          */
3496         start_trb = &ep_ring->enqueue->generic;
3497         start_cycle = ep_ring->cycle_state;
3498
3499         /* Queue setup TRB - see section 6.4.1.2.1 */
3500         /* FIXME better way to translate setup_packet into two u32 fields? */
3501         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3502         field = 0;
3503         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3504         if (start_cycle == 0)
3505                 field |= 0x1;
3506
3507         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3508         if (xhci->hci_version == 0x100) {
3509                 if (urb->transfer_buffer_length > 0) {
3510                         if (setup->bRequestType & USB_DIR_IN)
3511                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3512                         else
3513                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3514                 }
3515         }
3516
3517         queue_trb(xhci, ep_ring, true,
3518                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3519                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3520                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3521                   /* Immediate data in pointer */
3522                   field);
3523
3524         /* If there's data, queue data TRBs */
3525         /* Only set interrupt on short packet for IN endpoints */
3526         if (usb_urb_dir_in(urb))
3527                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3528         else
3529                 field = TRB_TYPE(TRB_DATA);
3530
3531         length_field = TRB_LEN(urb->transfer_buffer_length) |
3532                 xhci_td_remainder(urb->transfer_buffer_length) |
3533                 TRB_INTR_TARGET(0);
3534         if (urb->transfer_buffer_length > 0) {
3535                 if (setup->bRequestType & USB_DIR_IN)
3536                         field |= TRB_DIR_IN;
3537                 queue_trb(xhci, ep_ring, true,
3538                                 lower_32_bits(urb->transfer_dma),
3539                                 upper_32_bits(urb->transfer_dma),
3540                                 length_field,
3541                                 field | ep_ring->cycle_state);
3542         }
3543
3544         /* Save the DMA address of the last TRB in the TD */
3545         td->last_trb = ep_ring->enqueue;
3546
3547         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3548         /* If the device sent data, the status stage is an OUT transfer */
3549         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3550                 field = 0;
3551         else
3552                 field = TRB_DIR_IN;
3553         queue_trb(xhci, ep_ring, false,
3554                         0,
3555                         0,
3556                         TRB_INTR_TARGET(0),
3557                         /* Event on completion */
3558                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3559
3560         giveback_first_trb(xhci, slot_id, ep_index, 0,
3561                         start_cycle, start_trb);
3562         return 0;
3563 }
3564
3565 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3566                 struct urb *urb, int i)
3567 {
3568         int num_trbs = 0;
3569         u64 addr, td_len;
3570
3571         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3572         td_len = urb->iso_frame_desc[i].length;
3573
3574         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3575                         TRB_MAX_BUFF_SIZE);
3576         if (num_trbs == 0)
3577                 num_trbs++;
3578
3579         return num_trbs;
3580 }
3581
3582 /*
3583  * The transfer burst count field of the isochronous TRB defines the number of
3584  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3585  * devices can burst up to bMaxBurst number of packets per service interval.
3586  * This field is zero based, meaning a value of zero in the field means one
3587  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3588  * zero.  Only xHCI 1.0 host controllers support this field.
3589  */
3590 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3591                 struct usb_device *udev,
3592                 struct urb *urb, unsigned int total_packet_count)
3593 {
3594         unsigned int max_burst;
3595
3596         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3597                 return 0;
3598
3599         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3600         return roundup(total_packet_count, max_burst + 1) - 1;
3601 }
3602
3603 /*
3604  * Returns the number of packets in the last "burst" of packets.  This field is
3605  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3606  * the last burst packet count is equal to the total number of packets in the
3607  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3608  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3609  * contain 1 to (bMaxBurst + 1) packets.
3610  */
3611 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3612                 struct usb_device *udev,
3613                 struct urb *urb, unsigned int total_packet_count)
3614 {
3615         unsigned int max_burst;
3616         unsigned int residue;
3617
3618         if (xhci->hci_version < 0x100)
3619                 return 0;
3620
3621         switch (udev->speed) {
3622         case USB_SPEED_SUPER:
3623                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3624                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3625                 residue = total_packet_count % (max_burst + 1);
3626                 /* If residue is zero, the last burst contains (max_burst + 1)
3627                  * number of packets, but the TLBPC field is zero-based.
3628                  */
3629                 if (residue == 0)
3630                         return max_burst;
3631                 return residue - 1;
3632         default:
3633                 if (total_packet_count == 0)
3634                         return 0;
3635                 return total_packet_count - 1;
3636         }
3637 }
3638
3639 /* This is for isoc transfer */
3640 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3641                 struct urb *urb, int slot_id, unsigned int ep_index)
3642 {
3643         struct xhci_ring *ep_ring;
3644         struct urb_priv *urb_priv;
3645         struct xhci_td *td;
3646         int num_tds, trbs_per_td;
3647         struct xhci_generic_trb *start_trb;
3648         bool first_trb;
3649         int start_cycle;
3650         u32 field, length_field;
3651         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3652         u64 start_addr, addr;
3653         int i, j;
3654         bool more_trbs_coming;
3655
3656         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3657
3658         num_tds = urb->number_of_packets;
3659         if (num_tds < 1) {
3660                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3661                 return -EINVAL;
3662         }
3663
3664         start_addr = (u64) urb->transfer_dma;
3665         start_trb = &ep_ring->enqueue->generic;
3666         start_cycle = ep_ring->cycle_state;
3667
3668         urb_priv = urb->hcpriv;
3669         /* Queue the first TRB, even if it's zero-length */
3670         for (i = 0; i < num_tds; i++) {
3671                 unsigned int total_packet_count;
3672                 unsigned int burst_count;
3673                 unsigned int residue;
3674
3675                 first_trb = true;
3676                 running_total = 0;
3677                 addr = start_addr + urb->iso_frame_desc[i].offset;
3678                 td_len = urb->iso_frame_desc[i].length;
3679                 td_remain_len = td_len;
3680                 total_packet_count = DIV_ROUND_UP(td_len,
3681                                 GET_MAX_PACKET(
3682                                         usb_endpoint_maxp(&urb->ep->desc)));
3683                 /* A zero-length transfer still involves at least one packet. */
3684                 if (total_packet_count == 0)
3685                         total_packet_count++;
3686                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3687                                 total_packet_count);
3688                 residue = xhci_get_last_burst_packet_count(xhci,
3689                                 urb->dev, urb, total_packet_count);
3690
3691                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3692
3693                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3694                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3695                 if (ret < 0) {
3696                         if (i == 0)
3697                                 return ret;
3698                         goto cleanup;
3699                 }
3700
3701                 td = urb_priv->td[i];
3702                 for (j = 0; j < trbs_per_td; j++) {
3703                         u32 remainder = 0;
3704                         field = 0;
3705
3706                         if (first_trb) {
3707                                 field = TRB_TBC(burst_count) |
3708                                         TRB_TLBPC(residue);
3709                                 /* Queue the isoc TRB */
3710                                 field |= TRB_TYPE(TRB_ISOC);
3711                                 /* Assume URB_ISO_ASAP is set */
3712                                 field |= TRB_SIA;
3713                                 if (i == 0) {
3714                                         if (start_cycle == 0)
3715                                                 field |= 0x1;
3716                                 } else
3717                                         field |= ep_ring->cycle_state;
3718                                 first_trb = false;
3719                         } else {
3720                                 /* Queue other normal TRBs */
3721                                 field |= TRB_TYPE(TRB_NORMAL);
3722                                 field |= ep_ring->cycle_state;
3723                         }
3724
3725                         /* Only set interrupt on short packet for IN EPs */
3726                         if (usb_urb_dir_in(urb))
3727                                 field |= TRB_ISP;
3728
3729                         /* Chain all the TRBs together; clear the chain bit in
3730                          * the last TRB to indicate it's the last TRB in the
3731                          * chain.
3732                          */
3733                         if (j < trbs_per_td - 1) {
3734                                 field |= TRB_CHAIN;
3735                                 more_trbs_coming = true;
3736                         } else {
3737                                 td->last_trb = ep_ring->enqueue;
3738                                 field |= TRB_IOC;
3739                                 if (xhci->hci_version == 0x100 &&
3740                                                 !(xhci->quirks &
3741                                                         XHCI_AVOID_BEI)) {
3742                                         /* Set BEI bit except for the last td */
3743                                         if (i < num_tds - 1)
3744                                                 field |= TRB_BEI;
3745                                 }
3746                                 more_trbs_coming = false;
3747                         }
3748
3749                         /* Calculate TRB length */
3750                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3751                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3752                         if (trb_buff_len > td_remain_len)
3753                                 trb_buff_len = td_remain_len;
3754
3755                         /* Set the TRB length, TD size, & interrupter fields. */
3756                         if (xhci->hci_version < 0x100) {
3757                                 remainder = xhci_td_remainder(
3758                                                 td_len - running_total);
3759                         } else {
3760                                 remainder = xhci_v1_0_td_remainder(
3761                                                 running_total, trb_buff_len,
3762                                                 total_packet_count, urb,
3763                                                 (trbs_per_td - j - 1));
3764                         }
3765                         length_field = TRB_LEN(trb_buff_len) |
3766                                 remainder |
3767                                 TRB_INTR_TARGET(0);
3768
3769                         queue_trb(xhci, ep_ring, more_trbs_coming,
3770                                 lower_32_bits(addr),
3771                                 upper_32_bits(addr),
3772                                 length_field,
3773                                 field);
3774                         running_total += trb_buff_len;
3775
3776                         addr += trb_buff_len;
3777                         td_remain_len -= trb_buff_len;
3778                 }
3779
3780                 /* Check TD length */
3781                 if (running_total != td_len) {
3782                         xhci_err(xhci, "ISOC TD length unmatch\n");
3783                         ret = -EINVAL;
3784                         goto cleanup;
3785                 }
3786         }
3787
3788         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3789                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3790                         usb_amd_quirk_pll_disable();
3791         }
3792         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3793
3794         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3795                         start_cycle, start_trb);
3796         return 0;
3797 cleanup:
3798         /* Clean up a partially enqueued isoc transfer. */
3799
3800         for (i--; i >= 0; i--)
3801                 list_del_init(&urb_priv->td[i]->td_list);
3802
3803         /* Use the first TD as a temporary variable to turn the TDs we've queued
3804          * into No-ops with a software-owned cycle bit. That way the hardware
3805          * won't accidentally start executing bogus TDs when we partially
3806          * overwrite them.  td->first_trb and td->start_seg are already set.
3807          */
3808         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3809         /* Every TRB except the first & last will have its cycle bit flipped. */
3810         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3811
3812         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3813         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3814         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3815         ep_ring->cycle_state = start_cycle;
3816         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3817         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3818         return ret;
3819 }
3820
3821 /*
3822  * Check transfer ring to guarantee there is enough room for the urb.
3823  * Update ISO URB start_frame and interval.
3824  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3825  * update the urb->start_frame by now.
3826  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3827  */
3828 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3829                 struct urb *urb, int slot_id, unsigned int ep_index)
3830 {
3831         struct xhci_virt_device *xdev;
3832         struct xhci_ring *ep_ring;
3833         struct xhci_ep_ctx *ep_ctx;
3834         int start_frame;
3835         int xhci_interval;
3836         int ep_interval;
3837         int num_tds, num_trbs, i;
3838         int ret;
3839
3840         xdev = xhci->devs[slot_id];
3841         ep_ring = xdev->eps[ep_index].ring;
3842         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3843
3844         num_trbs = 0;
3845         num_tds = urb->number_of_packets;
3846         for (i = 0; i < num_tds; i++)
3847                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3848
3849         /* Check the ring to guarantee there is enough room for the whole urb.
3850          * Do not insert any td of the urb to the ring if the check failed.
3851          */
3852         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3853                            num_trbs, mem_flags);
3854         if (ret)
3855                 return ret;
3856
3857         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3858         start_frame &= 0x3fff;
3859
3860         urb->start_frame = start_frame;
3861         if (urb->dev->speed == USB_SPEED_LOW ||
3862                         urb->dev->speed == USB_SPEED_FULL)
3863                 urb->start_frame >>= 3;
3864
3865         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3866         ep_interval = urb->interval;
3867         /* Convert to microframes */
3868         if (urb->dev->speed == USB_SPEED_LOW ||
3869                         urb->dev->speed == USB_SPEED_FULL)
3870                 ep_interval *= 8;
3871         /* FIXME change this to a warning and a suggestion to use the new API
3872          * to set the polling interval (once the API is added).
3873          */
3874         if (xhci_interval != ep_interval) {
3875                 dev_dbg_ratelimited(&urb->dev->dev,
3876                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3877                                 ep_interval, ep_interval == 1 ? "" : "s",
3878                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3879                 urb->interval = xhci_interval;
3880                 /* Convert back to frames for LS/FS devices */
3881                 if (urb->dev->speed == USB_SPEED_LOW ||
3882                                 urb->dev->speed == USB_SPEED_FULL)
3883                         urb->interval /= 8;
3884         }
3885         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3886
3887         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3888 }
3889
3890 /****           Command Ring Operations         ****/
3891
3892 /* Generic function for queueing a command TRB on the command ring.
3893  * Check to make sure there's room on the command ring for one command TRB.
3894  * Also check that there's room reserved for commands that must not fail.
3895  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3896  * then only check for the number of reserved spots.
3897  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3898  * because the command event handler may want to resubmit a failed command.
3899  */
3900 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3901                 u32 field3, u32 field4, bool command_must_succeed)
3902 {
3903         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3904         int ret;
3905
3906         if (!command_must_succeed)
3907                 reserved_trbs++;
3908
3909         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3910                         reserved_trbs, GFP_ATOMIC);
3911         if (ret < 0) {
3912                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3913                 if (command_must_succeed)
3914                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3915                                         "unfailable commands failed.\n");
3916                 return ret;
3917         }
3918         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3919                         field4 | xhci->cmd_ring->cycle_state);
3920         return 0;
3921 }
3922
3923 /* Queue a slot enable or disable request on the command ring */
3924 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3925 {
3926         return queue_command(xhci, 0, 0, 0,
3927                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3928 }
3929
3930 /* Queue an address device command TRB */
3931 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3932                 u32 slot_id)
3933 {
3934         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3935                         upper_32_bits(in_ctx_ptr), 0,
3936                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3937                         false);
3938 }
3939
3940 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3941                 u32 field1, u32 field2, u32 field3, u32 field4)
3942 {
3943         return queue_command(xhci, field1, field2, field3, field4, false);
3944 }
3945
3946 /* Queue a reset device command TRB */
3947 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3948 {
3949         return queue_command(xhci, 0, 0, 0,
3950                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3951                         false);
3952 }
3953
3954 /* Queue a configure endpoint command TRB */
3955 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3956                 u32 slot_id, bool command_must_succeed)
3957 {
3958         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3959                         upper_32_bits(in_ctx_ptr), 0,
3960                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3961                         command_must_succeed);
3962 }
3963
3964 /* Queue an evaluate context command TRB */
3965 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3966                 u32 slot_id, bool command_must_succeed)
3967 {
3968         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3969                         upper_32_bits(in_ctx_ptr), 0,
3970                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3971                         command_must_succeed);
3972 }
3973
3974 /*
3975  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3976  * activity on an endpoint that is about to be suspended.
3977  */
3978 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3979                 unsigned int ep_index, int suspend)
3980 {
3981         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3982         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3983         u32 type = TRB_TYPE(TRB_STOP_RING);
3984         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3985
3986         return queue_command(xhci, 0, 0, 0,
3987                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3988 }
3989
3990 /* Set Transfer Ring Dequeue Pointer command.
3991  * This should not be used for endpoints that have streams enabled.
3992  */
3993 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3994                 unsigned int ep_index, unsigned int stream_id,
3995                 struct xhci_segment *deq_seg,
3996                 union xhci_trb *deq_ptr, u32 cycle_state)
3997 {
3998         dma_addr_t addr;
3999         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4000         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4001         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4002         u32 type = TRB_TYPE(TRB_SET_DEQ);
4003         struct xhci_virt_ep *ep;
4004
4005         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4006         if (addr == 0) {
4007                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4008                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4009                                 deq_seg, deq_ptr);
4010                 return 0;
4011         }
4012         ep = &xhci->devs[slot_id]->eps[ep_index];
4013         if ((ep->ep_state & SET_DEQ_PENDING)) {
4014                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4015                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4016                 return 0;
4017         }
4018         ep->queued_deq_seg = deq_seg;
4019         ep->queued_deq_ptr = deq_ptr;
4020         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4021                         upper_32_bits(addr), trb_stream_id,
4022                         trb_slot_id | trb_ep_index | type, false);
4023 }
4024
4025 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4026                 unsigned int ep_index)
4027 {
4028         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4029         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4030         u32 type = TRB_TYPE(TRB_RESET_EP);
4031
4032         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4033                         false);
4034 }