2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
77 unsigned long segment_offset;
79 if (!seg || !trb || trb < seg->trbs)
82 segment_offset = trb - seg->trbs;
83 if (segment_offset > TRBS_PER_SEGMENT)
85 return seg->dma + (segment_offset * sizeof(*trb));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
92 struct xhci_segment *seg, union xhci_trb *trb)
94 if (ring == xhci->event_ring)
95 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
96 (seg->next == xhci->event_ring->first_seg);
98 return trb->link.control & LINK_TOGGLE;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
106 struct xhci_segment *seg, union xhci_trb *trb)
108 if (ring == xhci->event_ring)
109 return trb == &seg->trbs[TRBS_PER_SEGMENT];
111 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd *xhci,
119 struct xhci_ring *ring,
120 struct xhci_segment **seg,
121 union xhci_trb **trb)
123 if (last_trb(xhci, ring, *seg, *trb)) {
125 *trb = ((*seg)->trbs);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
137 union xhci_trb *next = ++(ring->dequeue);
138 unsigned long long addr;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci, ring, ring->deq_seg, next)) {
145 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
146 ring->cycle_state = (ring->cycle_state ? 0 : 1);
148 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring->cycle_state);
152 ring->deq_seg = ring->deq_seg->next;
153 ring->dequeue = ring->deq_seg->trbs;
154 next = ring->dequeue;
156 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
157 if (ring == xhci->event_ring)
158 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
159 else if (ring == xhci->cmd_ring)
160 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
162 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
182 union xhci_trb *next;
183 unsigned long long addr;
185 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
186 next = ++(ring->enqueue);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci, ring, ring->enq_seg, next)) {
194 if (ring != xhci->event_ring) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci)) {
200 next->link.control &= ~TRB_CHAIN;
201 next->link.control |= chain;
203 /* Give this link TRB to the hardware */
205 if (next->link.control & TRB_CYCLE)
206 next->link.control &= (u32) ~TRB_CYCLE;
208 next->link.control |= (u32) TRB_CYCLE;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
212 ring->cycle_state = (ring->cycle_state ? 0 : 1);
214 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring->cycle_state);
219 ring->enq_seg = ring->enq_seg->next;
220 ring->enqueue = ring->enq_seg->trbs;
221 next = ring->enqueue;
223 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
224 if (ring == xhci->event_ring)
225 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
226 else if (ring == xhci->cmd_ring)
227 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
229 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
239 unsigned int num_trbs)
242 union xhci_trb *enq = ring->enqueue;
243 struct xhci_segment *enq_seg = ring->enq_seg;
245 /* Check if ring is empty */
246 if (enq == ring->dequeue)
248 /* Make sure there's an extra empty TRB available */
249 for (i = 0; i <= num_trbs; ++i) {
250 if (enq == ring->dequeue)
253 while (last_trb(xhci, ring, enq_seg, enq)) {
254 enq_seg = enq_seg->next;
261 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
266 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
267 xhci->event_ring->dequeue);
268 if (deq == 0 && !in_interrupt())
269 xhci_warn(xhci, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
273 temp &= ERST_PTR_MASK;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
280 &xhci->ir_set->erst_dequeue);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "// Ding dong!\n");
289 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
290 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci, &xhci->dba->doorbell[0]);
295 static void ring_ep_doorbell(struct xhci_hcd *xhci,
296 unsigned int slot_id,
297 unsigned int ep_index)
299 struct xhci_virt_ep *ep;
300 unsigned int ep_state;
302 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
304 ep = &xhci->devs[slot_id]->eps[ep_index];
305 ep_state = ep->ep_state;
306 /* Don't ring the doorbell for this endpoint if there are pending
307 * cancellations because the we don't want to interrupt processing.
309 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
310 && !(ep_state & EP_HALTED)) {
311 field = xhci_readl(xhci, db_addr) & DB_MASK;
312 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
313 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
314 * isn't time-critical and we shouldn't make the CPU wait for
317 xhci_readl(xhci, db_addr);
322 * Find the segment that trb is in. Start searching in start_seg.
323 * If we must move past a segment that has a link TRB with a toggle cycle state
324 * bit set, then we will toggle the value pointed at by cycle_state.
326 static struct xhci_segment *find_trb_seg(
327 struct xhci_segment *start_seg,
328 union xhci_trb *trb, int *cycle_state)
330 struct xhci_segment *cur_seg = start_seg;
331 struct xhci_generic_trb *generic_trb;
333 while (cur_seg->trbs > trb ||
334 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
335 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
336 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
337 (generic_trb->field[3] & LINK_TOGGLE))
338 *cycle_state = ~(*cycle_state) & 0x1;
339 cur_seg = cur_seg->next;
340 if (cur_seg == start_seg)
341 /* Looped over the entire list. Oops! */
348 * Move the xHC's endpoint ring dequeue pointer past cur_td.
349 * Record the new state of the xHC's endpoint ring dequeue segment,
350 * dequeue pointer, and new consumer cycle state in state.
351 * Update our internal representation of the ring's dequeue pointer.
353 * We do this in three jumps:
354 * - First we update our new ring state to be the same as when the xHC stopped.
355 * - Then we traverse the ring to find the segment that contains
356 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
357 * any link TRBs with the toggle cycle bit set.
358 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
359 * if we've moved it past a link TRB with the toggle cycle bit set.
361 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
362 unsigned int slot_id, unsigned int ep_index,
363 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
365 struct xhci_virt_device *dev = xhci->devs[slot_id];
366 struct xhci_ring *ep_ring = dev->eps[ep_index].ring;
367 struct xhci_generic_trb *trb;
368 struct xhci_ep_ctx *ep_ctx;
371 state->new_cycle_state = 0;
372 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
373 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
374 dev->eps[ep_index].stopped_trb,
375 &state->new_cycle_state);
376 if (!state->new_deq_seg)
378 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
379 xhci_dbg(xhci, "Finding endpoint context\n");
380 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
381 state->new_cycle_state = 0x1 & ep_ctx->deq;
383 state->new_deq_ptr = cur_td->last_trb;
384 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
385 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
387 &state->new_cycle_state);
388 if (!state->new_deq_seg)
391 trb = &state->new_deq_ptr->generic;
392 if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
393 (trb->field[3] & LINK_TOGGLE))
394 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
395 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
397 /* Don't update the ring cycle state for the producer (us). */
398 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
400 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
401 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
402 (unsigned long long) addr);
403 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
404 ep_ring->dequeue = state->new_deq_ptr;
405 ep_ring->deq_seg = state->new_deq_seg;
408 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
409 struct xhci_td *cur_td)
411 struct xhci_segment *cur_seg;
412 union xhci_trb *cur_trb;
414 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
416 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
417 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
418 TRB_TYPE(TRB_LINK)) {
419 /* Unchain any chained Link TRBs, but
420 * leave the pointers intact.
422 cur_trb->generic.field[3] &= ~TRB_CHAIN;
423 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
424 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
425 "in seg %p (0x%llx dma)\n",
427 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
429 (unsigned long long)cur_seg->dma);
431 cur_trb->generic.field[0] = 0;
432 cur_trb->generic.field[1] = 0;
433 cur_trb->generic.field[2] = 0;
434 /* Preserve only the cycle bit of this TRB */
435 cur_trb->generic.field[3] &= TRB_CYCLE;
436 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
437 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
438 "in seg %p (0x%llx dma)\n",
440 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
442 (unsigned long long)cur_seg->dma);
444 if (cur_trb == cur_td->last_trb)
449 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
450 unsigned int ep_index, struct xhci_segment *deq_seg,
451 union xhci_trb *deq_ptr, u32 cycle_state);
453 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
454 unsigned int slot_id, unsigned int ep_index,
455 struct xhci_dequeue_state *deq_state)
457 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
459 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
460 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
461 deq_state->new_deq_seg,
462 (unsigned long long)deq_state->new_deq_seg->dma,
463 deq_state->new_deq_ptr,
464 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
465 deq_state->new_cycle_state);
466 queue_set_tr_deq(xhci, slot_id, ep_index,
467 deq_state->new_deq_seg,
468 deq_state->new_deq_ptr,
469 (u32) deq_state->new_cycle_state);
470 /* Stop the TD queueing code from ringing the doorbell until
471 * this command completes. The HC won't set the dequeue pointer
472 * if the ring is running, and ringing the doorbell starts the
475 ep->ep_state |= SET_DEQ_PENDING;
478 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
479 struct xhci_virt_ep *ep)
481 ep->ep_state &= ~EP_HALT_PENDING;
482 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
483 * timer is running on another CPU, we don't decrement stop_cmds_pending
484 * (since we didn't successfully stop the watchdog timer).
486 if (del_timer(&ep->stop_cmd_timer))
487 ep->stop_cmds_pending--;
490 /* Must be called with xhci->lock held in interrupt context */
491 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
492 struct xhci_td *cur_td, int status, char *adjective)
494 struct usb_hcd *hcd = xhci_to_hcd(xhci);
496 cur_td->urb->hcpriv = NULL;
497 usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb);
498 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb);
500 spin_unlock(&xhci->lock);
501 usb_hcd_giveback_urb(hcd, cur_td->urb, status);
503 spin_lock(&xhci->lock);
504 xhci_dbg(xhci, "%s URB given back\n", adjective);
508 * When we get a command completion for a Stop Endpoint Command, we need to
509 * unlink any cancelled TDs from the ring. There are two ways to do that:
511 * 1. If the HW was in the middle of processing the TD that needs to be
512 * cancelled, then we must move the ring's dequeue pointer past the last TRB
513 * in the TD with a Set Dequeue Pointer Command.
514 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
515 * bit cleared) so that the HW will skip over them.
517 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
520 unsigned int slot_id;
521 unsigned int ep_index;
522 struct xhci_ring *ep_ring;
523 struct xhci_virt_ep *ep;
524 struct list_head *entry;
525 struct xhci_td *cur_td = 0;
526 struct xhci_td *last_unlinked_td;
528 struct xhci_dequeue_state deq_state;
530 memset(&deq_state, 0, sizeof(deq_state));
531 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
532 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
533 ep = &xhci->devs[slot_id]->eps[ep_index];
536 if (list_empty(&ep->cancelled_td_list)) {
537 xhci_stop_watchdog_timer_in_irq(xhci, ep);
538 ring_ep_doorbell(xhci, slot_id, ep_index);
542 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
543 * We have the xHCI lock, so nothing can modify this list until we drop
544 * it. We're also in the event handler, so we can't get re-interrupted
545 * if another Stop Endpoint command completes
547 list_for_each(entry, &ep->cancelled_td_list) {
548 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
549 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
551 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
553 * If we stopped on the TD we need to cancel, then we have to
554 * move the xHC endpoint ring dequeue pointer past this TD.
556 if (cur_td == ep->stopped_td)
557 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
560 td_to_noop(xhci, ep_ring, cur_td);
562 * The event handler won't see a completion for this TD anymore,
563 * so remove it from the endpoint ring's TD list. Keep it in
564 * the cancelled TD list for URB completion later.
566 list_del(&cur_td->td_list);
568 last_unlinked_td = cur_td;
569 xhci_stop_watchdog_timer_in_irq(xhci, ep);
571 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
572 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
573 xhci_queue_new_dequeue_state(xhci,
574 slot_id, ep_index, &deq_state);
575 xhci_ring_cmd_db(xhci);
577 /* Otherwise just ring the doorbell to restart the ring */
578 ring_ep_doorbell(xhci, slot_id, ep_index);
582 * Drop the lock and complete the URBs in the cancelled TD list.
583 * New TDs to be cancelled might be added to the end of the list before
584 * we can complete all the URBs for the TDs we already unlinked.
585 * So stop when we've completed the URB for the last TD we unlinked.
588 cur_td = list_entry(ep->cancelled_td_list.next,
589 struct xhci_td, cancelled_td_list);
590 list_del(&cur_td->cancelled_td_list);
592 /* Clean up the cancelled URB */
593 /* Doesn't matter what we pass for status, since the core will
594 * just overwrite it (because the URB has been unlinked).
596 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
598 /* Stop processing the cancelled list if the watchdog timer is
601 if (xhci->xhc_state & XHCI_STATE_DYING)
603 } while (cur_td != last_unlinked_td);
605 /* Return to the event handler with xhci->lock re-acquired */
608 /* Watchdog timer function for when a stop endpoint command fails to complete.
609 * In this case, we assume the host controller is broken or dying or dead. The
610 * host may still be completing some other events, so we have to be careful to
611 * let the event ring handler and the URB dequeueing/enqueueing functions know
612 * through xhci->state.
614 * The timer may also fire if the host takes a very long time to respond to the
615 * command, and the stop endpoint command completion handler cannot delete the
616 * timer before the timer function is called. Another endpoint cancellation may
617 * sneak in before the timer function can grab the lock, and that may queue
618 * another stop endpoint command and add the timer back. So we cannot use a
619 * simple flag to say whether there is a pending stop endpoint command for a
620 * particular endpoint.
622 * Instead we use a combination of that flag and a counter for the number of
623 * pending stop endpoint commands. If the timer is the tail end of the last
624 * stop endpoint command, and the endpoint's command is still pending, we assume
627 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
629 struct xhci_hcd *xhci;
630 struct xhci_virt_ep *ep;
631 struct xhci_virt_ep *temp_ep;
632 struct xhci_ring *ring;
633 struct xhci_td *cur_td;
636 ep = (struct xhci_virt_ep *) arg;
639 spin_lock(&xhci->lock);
641 ep->stop_cmds_pending--;
642 if (xhci->xhc_state & XHCI_STATE_DYING) {
643 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
644 "xHCI as DYING, exiting.\n");
645 spin_unlock(&xhci->lock);
648 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
649 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
651 spin_unlock(&xhci->lock);
655 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
656 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
657 /* Oops, HC is dead or dying or at least not responding to the stop
660 xhci->xhc_state |= XHCI_STATE_DYING;
661 /* Disable interrupts from the host controller and start halting it */
663 spin_unlock(&xhci->lock);
665 ret = xhci_halt(xhci);
667 spin_lock(&xhci->lock);
669 /* This is bad; the host is not responding to commands and it's
670 * not allowing itself to be halted. At least interrupts are
671 * disabled, so we can set HC_STATE_HALT and notify the
672 * USB core. But if we call usb_hc_died(), it will attempt to
673 * disconnect all device drivers under this host. Those
674 * disconnect() methods will wait for all URBs to be unlinked,
675 * so we must complete them.
677 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
678 xhci_warn(xhci, "Completing active URBs anyway.\n");
679 /* We could turn all TDs on the rings to no-ops. This won't
680 * help if the host has cached part of the ring, and is slow if
681 * we want to preserve the cycle bit. Skip it and hope the host
682 * doesn't touch the memory.
685 for (i = 0; i < MAX_HC_SLOTS; i++) {
688 for (j = 0; j < 31; j++) {
689 temp_ep = &xhci->devs[i]->eps[j];
690 ring = temp_ep->ring;
693 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
694 "ep index %u\n", i, j);
695 while (!list_empty(&ring->td_list)) {
696 cur_td = list_first_entry(&ring->td_list,
699 list_del(&cur_td->td_list);
700 if (!list_empty(&cur_td->cancelled_td_list))
701 list_del(&cur_td->cancelled_td_list);
702 xhci_giveback_urb_in_irq(xhci, cur_td,
703 -ESHUTDOWN, "killed");
705 while (!list_empty(&temp_ep->cancelled_td_list)) {
706 cur_td = list_first_entry(
707 &temp_ep->cancelled_td_list,
710 list_del(&cur_td->cancelled_td_list);
711 xhci_giveback_urb_in_irq(xhci, cur_td,
712 -ESHUTDOWN, "killed");
716 spin_unlock(&xhci->lock);
717 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
718 xhci_dbg(xhci, "Calling usb_hc_died()\n");
719 usb_hc_died(xhci_to_hcd(xhci));
720 xhci_dbg(xhci, "xHCI host controller is dead.\n");
724 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
725 * we need to clear the set deq pending flag in the endpoint ring state, so that
726 * the TD queueing code can ring the doorbell again. We also need to ring the
727 * endpoint doorbell to restart the ring, but only if there aren't more
728 * cancellations pending.
730 static void handle_set_deq_completion(struct xhci_hcd *xhci,
731 struct xhci_event_cmd *event,
734 unsigned int slot_id;
735 unsigned int ep_index;
736 struct xhci_ring *ep_ring;
737 struct xhci_virt_device *dev;
738 struct xhci_ep_ctx *ep_ctx;
739 struct xhci_slot_ctx *slot_ctx;
741 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
742 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
743 dev = xhci->devs[slot_id];
744 ep_ring = dev->eps[ep_index].ring;
745 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
746 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
748 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
749 unsigned int ep_state;
750 unsigned int slot_state;
752 switch (GET_COMP_CODE(event->status)) {
754 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
755 "of stream ID configuration\n");
758 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
759 "to incorrect slot or ep state.\n");
760 ep_state = ep_ctx->ep_info;
761 ep_state &= EP_STATE_MASK;
762 slot_state = slot_ctx->dev_state;
763 slot_state = GET_SLOT_STATE(slot_state);
764 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
765 slot_state, ep_state);
768 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
769 "slot %u was not enabled.\n", slot_id);
772 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
773 "completion code of %u.\n",
774 GET_COMP_CODE(event->status));
777 /* OK what do we do now? The endpoint state is hosed, and we
778 * should never get to this point if the synchronization between
779 * queueing, and endpoint state are correct. This might happen
780 * if the device gets disconnected after we've finished
781 * cancelling URBs, which might not be an error...
784 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
788 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
789 ring_ep_doorbell(xhci, slot_id, ep_index);
792 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
793 struct xhci_event_cmd *event,
797 unsigned int ep_index;
798 struct xhci_ring *ep_ring;
800 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
801 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
802 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
803 /* This command will only fail if the endpoint wasn't halted,
806 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
807 (unsigned int) GET_COMP_CODE(event->status));
809 /* HW with the reset endpoint quirk needs to have a configure endpoint
810 * command complete before the endpoint can be used. Queue that here
811 * because the HW can't handle two commands being queued in a row.
813 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
814 xhci_dbg(xhci, "Queueing configure endpoint command\n");
815 xhci_queue_configure_endpoint(xhci,
816 xhci->devs[slot_id]->in_ctx->dma, slot_id,
818 xhci_ring_cmd_db(xhci);
820 /* Clear our internal halted state and restart the ring */
821 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
822 ring_ep_doorbell(xhci, slot_id, ep_index);
826 /* Check to see if a command in the device's command queue matches this one.
827 * Signal the completion or free the command, and return 1. Return 0 if the
828 * completed command isn't at the head of the command list.
830 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
831 struct xhci_virt_device *virt_dev,
832 struct xhci_event_cmd *event)
834 struct xhci_command *command;
836 if (list_empty(&virt_dev->cmd_list))
839 command = list_entry(virt_dev->cmd_list.next,
840 struct xhci_command, cmd_list);
841 if (xhci->cmd_ring->dequeue != command->command_trb)
845 GET_COMP_CODE(event->status);
846 list_del(&command->cmd_list);
847 if (command->completion)
848 complete(command->completion);
850 xhci_free_command(xhci, command);
854 static void handle_cmd_completion(struct xhci_hcd *xhci,
855 struct xhci_event_cmd *event)
857 int slot_id = TRB_TO_SLOT_ID(event->flags);
859 dma_addr_t cmd_dequeue_dma;
860 struct xhci_input_control_ctx *ctrl_ctx;
861 struct xhci_virt_device *virt_dev;
862 unsigned int ep_index;
863 struct xhci_ring *ep_ring;
864 unsigned int ep_state;
866 cmd_dma = event->cmd_trb;
867 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
868 xhci->cmd_ring->dequeue);
869 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
870 if (cmd_dequeue_dma == 0) {
871 xhci->error_bitmask |= 1 << 4;
874 /* Does the DMA address match our internal dequeue pointer address? */
875 if (cmd_dma != (u64) cmd_dequeue_dma) {
876 xhci->error_bitmask |= 1 << 5;
879 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
880 case TRB_TYPE(TRB_ENABLE_SLOT):
881 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
882 xhci->slot_id = slot_id;
885 complete(&xhci->addr_dev);
887 case TRB_TYPE(TRB_DISABLE_SLOT):
888 if (xhci->devs[slot_id])
889 xhci_free_virt_device(xhci, slot_id);
891 case TRB_TYPE(TRB_CONFIG_EP):
892 virt_dev = xhci->devs[slot_id];
893 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
896 * Configure endpoint commands can come from the USB core
897 * configuration or alt setting changes, or because the HW
898 * needed an extra configure endpoint command after a reset
899 * endpoint command. In the latter case, the xHCI driver is
900 * not waiting on the configure endpoint command.
902 ctrl_ctx = xhci_get_input_control_ctx(xhci,
904 /* Input ctx add_flags are the endpoint index plus one */
905 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
906 /* A usb_set_interface() call directly after clearing a halted
907 * condition may race on this quirky hardware.
908 * Not worth worrying about, since this is prototype hardware.
910 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
911 ep_index != (unsigned int) -1 &&
912 ctrl_ctx->add_flags - SLOT_FLAG ==
913 ctrl_ctx->drop_flags) {
914 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
915 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
916 if (!(ep_state & EP_HALTED))
917 goto bandwidth_change;
918 xhci_dbg(xhci, "Completed config ep cmd - "
919 "last ep index = %d, state = %d\n",
921 /* Clear our internal halted state and restart ring */
922 xhci->devs[slot_id]->eps[ep_index].ep_state &=
924 ring_ep_doorbell(xhci, slot_id, ep_index);
928 xhci_dbg(xhci, "Completed config ep cmd\n");
929 xhci->devs[slot_id]->cmd_status =
930 GET_COMP_CODE(event->status);
931 complete(&xhci->devs[slot_id]->cmd_completion);
933 case TRB_TYPE(TRB_EVAL_CONTEXT):
934 virt_dev = xhci->devs[slot_id];
935 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
937 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
938 complete(&xhci->devs[slot_id]->cmd_completion);
940 case TRB_TYPE(TRB_ADDR_DEV):
941 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
942 complete(&xhci->addr_dev);
944 case TRB_TYPE(TRB_STOP_RING):
945 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
947 case TRB_TYPE(TRB_SET_DEQ):
948 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
950 case TRB_TYPE(TRB_CMD_NOOP):
951 ++xhci->noops_handled;
953 case TRB_TYPE(TRB_RESET_EP):
954 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
956 case TRB_TYPE(TRB_RESET_DEV):
957 xhci_dbg(xhci, "Completed reset device command.\n");
958 slot_id = TRB_TO_SLOT_ID(
959 xhci->cmd_ring->dequeue->generic.field[3]);
960 virt_dev = xhci->devs[slot_id];
962 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
964 xhci_warn(xhci, "Reset device command completion "
965 "for disabled slot %u\n", slot_id);
968 /* Skip over unknown commands on the event ring */
969 xhci->error_bitmask |= 1 << 6;
972 inc_deq(xhci, xhci->cmd_ring, false);
975 static void handle_port_status(struct xhci_hcd *xhci,
976 union xhci_trb *event)
980 /* Port status change events always have a successful completion code */
981 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
982 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
983 xhci->error_bitmask |= 1 << 8;
985 /* FIXME: core doesn't care about all port link state changes yet */
986 port_id = GET_PORT_ID(event->generic.field[0]);
987 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
989 /* Update event ring dequeue pointer before dropping the lock */
990 inc_deq(xhci, xhci->event_ring, true);
991 xhci_set_hc_event_deq(xhci);
993 spin_unlock(&xhci->lock);
994 /* Pass this up to the core */
995 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
996 spin_lock(&xhci->lock);
1000 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1001 * at end_trb, which may be in another segment. If the suspect DMA address is a
1002 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1005 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1006 union xhci_trb *start_trb,
1007 union xhci_trb *end_trb,
1008 dma_addr_t suspect_dma)
1010 dma_addr_t start_dma;
1011 dma_addr_t end_seg_dma;
1012 dma_addr_t end_trb_dma;
1013 struct xhci_segment *cur_seg;
1015 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1016 cur_seg = start_seg;
1021 /* We may get an event for a Link TRB in the middle of a TD */
1022 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1023 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1024 /* If the end TRB isn't in this segment, this is set to 0 */
1025 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1027 if (end_trb_dma > 0) {
1028 /* The end TRB is in this segment, so suspect should be here */
1029 if (start_dma <= end_trb_dma) {
1030 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1033 /* Case for one segment with
1034 * a TD wrapped around to the top
1036 if ((suspect_dma >= start_dma &&
1037 suspect_dma <= end_seg_dma) ||
1038 (suspect_dma >= cur_seg->dma &&
1039 suspect_dma <= end_trb_dma))
1044 /* Might still be somewhere in this segment */
1045 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1048 cur_seg = cur_seg->next;
1049 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1050 } while (cur_seg != start_seg);
1055 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1056 unsigned int slot_id, unsigned int ep_index,
1057 struct xhci_td *td, union xhci_trb *event_trb)
1059 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1060 ep->ep_state |= EP_HALTED;
1061 ep->stopped_td = td;
1062 ep->stopped_trb = event_trb;
1063 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1064 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1065 xhci_ring_cmd_db(xhci);
1068 /* Check if an error has halted the endpoint ring. The class driver will
1069 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1070 * However, a babble and other errors also halt the endpoint ring, and the class
1071 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1072 * Ring Dequeue Pointer command manually.
1074 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1075 struct xhci_ep_ctx *ep_ctx,
1076 unsigned int trb_comp_code)
1078 /* TRB completion codes that may require a manual halt cleanup */
1079 if (trb_comp_code == COMP_TX_ERR ||
1080 trb_comp_code == COMP_BABBLE ||
1081 trb_comp_code == COMP_SPLIT_ERR)
1082 /* The 0.96 spec says a babbling control endpoint
1083 * is not halted. The 0.96 spec says it is. Some HW
1084 * claims to be 0.95 compliant, but it halts the control
1085 * endpoint anyway. Check if a babble halted the
1088 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1094 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1096 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1097 /* Vendor defined "informational" completion code,
1098 * treat as not-an-error.
1100 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1102 xhci_dbg(xhci, "Treating code as success.\n");
1109 * If this function returns an error condition, it means it got a Transfer
1110 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1111 * At this point, the host controller is probably hosed and should be reset.
1113 static int handle_tx_event(struct xhci_hcd *xhci,
1114 struct xhci_transfer_event *event)
1116 struct xhci_virt_device *xdev;
1117 struct xhci_virt_ep *ep;
1118 struct xhci_ring *ep_ring;
1119 unsigned int slot_id;
1121 struct xhci_td *td = 0;
1122 dma_addr_t event_dma;
1123 struct xhci_segment *event_seg;
1124 union xhci_trb *event_trb;
1125 struct urb *urb = 0;
1126 int status = -EINPROGRESS;
1127 struct xhci_ep_ctx *ep_ctx;
1130 xhci_dbg(xhci, "In %s\n", __func__);
1131 slot_id = TRB_TO_SLOT_ID(event->flags);
1132 xdev = xhci->devs[slot_id];
1134 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1138 /* Endpoint ID is 1 based, our index is zero based */
1139 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1140 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1141 ep = &xdev->eps[ep_index];
1143 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1144 if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1145 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
1149 event_dma = event->buffer;
1150 /* This TRB should be in the TD at the head of this ring's TD list */
1151 xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
1152 if (list_empty(&ep_ring->td_list)) {
1153 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1154 TRB_TO_SLOT_ID(event->flags), ep_index);
1155 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1156 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1157 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1161 xhci_dbg(xhci, "%s - getting list entry\n", __func__);
1162 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1164 /* Is this a TRB in the currently executing TD? */
1165 xhci_dbg(xhci, "%s - looking for TD\n", __func__);
1166 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1167 td->last_trb, event_dma);
1168 xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
1170 /* HC is busted, give up! */
1171 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1174 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
1175 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1176 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1177 xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
1178 lower_32_bits(event->buffer));
1179 xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1180 upper_32_bits(event->buffer));
1181 xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1182 (unsigned int) event->transfer_len);
1183 xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1184 (unsigned int) event->flags);
1186 /* Look for common error cases */
1187 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1188 switch (trb_comp_code) {
1189 /* Skip codes that require special handling depending on
1196 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1198 case COMP_STOP_INVAL:
1199 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1202 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1203 ep->ep_state |= EP_HALTED;
1207 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1210 case COMP_SPLIT_ERR:
1212 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1216 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1217 status = -EOVERFLOW;
1220 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1224 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1228 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1232 /* Now update the urb's actual_length and give back to the core */
1233 /* Was this a control transfer? */
1234 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1235 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1236 switch (trb_comp_code) {
1238 if (event_trb == ep_ring->dequeue) {
1239 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1240 status = -ESHUTDOWN;
1241 } else if (event_trb != td->last_trb) {
1242 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1243 status = -ESHUTDOWN;
1245 xhci_dbg(xhci, "Successful control transfer!\n");
1250 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1251 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1252 status = -EREMOTEIO;
1258 if (!xhci_requires_manual_halt_cleanup(xhci,
1259 ep_ctx, trb_comp_code))
1261 xhci_dbg(xhci, "TRB error code %u, "
1262 "halted endpoint index = %u\n",
1263 trb_comp_code, ep_index);
1264 /* else fall through */
1266 /* Did we transfer part of the data (middle) phase? */
1267 if (event_trb != ep_ring->dequeue &&
1268 event_trb != td->last_trb)
1269 td->urb->actual_length =
1270 td->urb->transfer_buffer_length
1271 - TRB_LEN(event->transfer_len);
1273 td->urb->actual_length = 0;
1275 xhci_cleanup_halted_endpoint(xhci,
1276 slot_id, ep_index, td, event_trb);
1280 * Did we transfer any data, despite the errors that might have
1281 * happened? I.e. did we get past the setup stage?
1283 if (event_trb != ep_ring->dequeue) {
1284 /* The event was for the status stage */
1285 if (event_trb == td->last_trb) {
1286 if (td->urb->actual_length != 0) {
1287 /* Don't overwrite a previously set error code */
1288 if ((status == -EINPROGRESS ||
1290 (td->urb->transfer_flags
1291 & URB_SHORT_NOT_OK))
1292 /* Did we already see a short data stage? */
1293 status = -EREMOTEIO;
1295 td->urb->actual_length =
1296 td->urb->transfer_buffer_length;
1299 /* Maybe the event was for the data stage? */
1300 if (trb_comp_code != COMP_STOP_INVAL) {
1301 /* We didn't stop on a link TRB in the middle */
1302 td->urb->actual_length =
1303 td->urb->transfer_buffer_length -
1304 TRB_LEN(event->transfer_len);
1305 xhci_dbg(xhci, "Waiting for status stage event\n");
1312 switch (trb_comp_code) {
1314 /* Double check that the HW transferred everything. */
1315 if (event_trb != td->last_trb) {
1316 xhci_warn(xhci, "WARN Successful completion "
1318 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1319 status = -EREMOTEIO;
1323 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1324 xhci_dbg(xhci, "Successful bulk "
1327 xhci_dbg(xhci, "Successful interrupt "
1333 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1334 status = -EREMOTEIO;
1339 /* Others already handled above */
1342 dev_dbg(&td->urb->dev->dev,
1343 "ep %#x - asked for %d bytes, "
1344 "%d bytes untransferred\n",
1345 td->urb->ep->desc.bEndpointAddress,
1346 td->urb->transfer_buffer_length,
1347 TRB_LEN(event->transfer_len));
1348 /* Fast path - was this the last TRB in the TD for this URB? */
1349 if (event_trb == td->last_trb) {
1350 if (TRB_LEN(event->transfer_len) != 0) {
1351 td->urb->actual_length =
1352 td->urb->transfer_buffer_length -
1353 TRB_LEN(event->transfer_len);
1354 if (td->urb->transfer_buffer_length <
1355 td->urb->actual_length) {
1356 xhci_warn(xhci, "HC gave bad length "
1357 "of %d bytes left\n",
1358 TRB_LEN(event->transfer_len));
1359 td->urb->actual_length = 0;
1360 if (td->urb->transfer_flags &
1362 status = -EREMOTEIO;
1366 /* Don't overwrite a previously set error code */
1367 if (status == -EINPROGRESS) {
1368 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1369 status = -EREMOTEIO;
1374 td->urb->actual_length = td->urb->transfer_buffer_length;
1375 /* Ignore a short packet completion if the
1376 * untransferred length was zero.
1378 if (status == -EREMOTEIO)
1382 /* Slow path - walk the list, starting from the dequeue
1383 * pointer, to get the actual length transferred.
1385 union xhci_trb *cur_trb;
1386 struct xhci_segment *cur_seg;
1388 td->urb->actual_length = 0;
1389 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1390 cur_trb != event_trb;
1391 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1392 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1393 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1394 td->urb->actual_length +=
1395 TRB_LEN(cur_trb->generic.field[2]);
1397 /* If the ring didn't stop on a Link or No-op TRB, add
1398 * in the actual bytes transferred from the Normal TRB
1400 if (trb_comp_code != COMP_STOP_INVAL)
1401 td->urb->actual_length +=
1402 TRB_LEN(cur_trb->generic.field[2]) -
1403 TRB_LEN(event->transfer_len);
1406 if (trb_comp_code == COMP_STOP_INVAL ||
1407 trb_comp_code == COMP_STOP) {
1408 /* The Endpoint Stop Command completion will take care of any
1409 * stopped TDs. A stopped TD may be restarted, so don't update
1410 * the ring dequeue pointer or take this TD off any lists yet.
1412 ep->stopped_td = td;
1413 ep->stopped_trb = event_trb;
1415 if (trb_comp_code == COMP_STALL) {
1416 /* The transfer is completed from the driver's
1417 * perspective, but we need to issue a set dequeue
1418 * command for this stalled endpoint to move the dequeue
1419 * pointer past the TD. We can't do that here because
1420 * the halt condition must be cleared first. Let the
1421 * USB class driver clear the stall later.
1423 ep->stopped_td = td;
1424 ep->stopped_trb = event_trb;
1425 } else if (xhci_requires_manual_halt_cleanup(xhci,
1426 ep_ctx, trb_comp_code)) {
1427 /* Other types of errors halt the endpoint, but the
1428 * class driver doesn't call usb_reset_endpoint() unless
1429 * the error is -EPIPE. Clear the halted status in the
1430 * xHCI hardware manually.
1432 xhci_cleanup_halted_endpoint(xhci,
1433 slot_id, ep_index, td, event_trb);
1435 /* Update ring dequeue pointer */
1436 while (ep_ring->dequeue != td->last_trb)
1437 inc_deq(xhci, ep_ring, false);
1438 inc_deq(xhci, ep_ring, false);
1442 /* Clean up the endpoint's TD list */
1444 /* Do one last check of the actual transfer length.
1445 * If the host controller said we transferred more data than
1446 * the buffer length, urb->actual_length will be a very big
1447 * number (since it's unsigned). Play it safe and say we didn't
1448 * transfer anything.
1450 if (urb->actual_length > urb->transfer_buffer_length) {
1451 xhci_warn(xhci, "URB transfer length is wrong, "
1452 "xHC issue? req. len = %u, "
1454 urb->transfer_buffer_length,
1455 urb->actual_length);
1456 urb->actual_length = 0;
1457 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1458 status = -EREMOTEIO;
1462 list_del(&td->td_list);
1463 /* Was this TD slated to be cancelled but completed anyway? */
1464 if (!list_empty(&td->cancelled_td_list))
1465 list_del(&td->cancelled_td_list);
1467 /* Leave the TD around for the reset endpoint function to use
1468 * (but only if it's not a control endpoint, since we already
1469 * queued the Set TR dequeue pointer command for stalled
1470 * control endpoints).
1472 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1473 (trb_comp_code != COMP_STALL &&
1474 trb_comp_code != COMP_BABBLE)) {
1480 inc_deq(xhci, xhci->event_ring, true);
1481 xhci_set_hc_event_deq(xhci);
1483 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1485 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1486 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1487 urb, urb->actual_length, status);
1488 spin_unlock(&xhci->lock);
1489 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1490 spin_lock(&xhci->lock);
1496 * This function handles all OS-owned events on the event ring. It may drop
1497 * xhci->lock between event processing (e.g. to pass up port status changes).
1499 void xhci_handle_event(struct xhci_hcd *xhci)
1501 union xhci_trb *event;
1502 int update_ptrs = 1;
1505 xhci_dbg(xhci, "In %s\n", __func__);
1506 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1507 xhci->error_bitmask |= 1 << 1;
1511 event = xhci->event_ring->dequeue;
1512 /* Does the HC or OS own the TRB? */
1513 if ((event->event_cmd.flags & TRB_CYCLE) !=
1514 xhci->event_ring->cycle_state) {
1515 xhci->error_bitmask |= 1 << 2;
1518 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1520 /* FIXME: Handle more event types. */
1521 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1522 case TRB_TYPE(TRB_COMPLETION):
1523 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1524 handle_cmd_completion(xhci, &event->event_cmd);
1525 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1527 case TRB_TYPE(TRB_PORT_STATUS):
1528 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1529 handle_port_status(xhci, event);
1530 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1533 case TRB_TYPE(TRB_TRANSFER):
1534 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1535 ret = handle_tx_event(xhci, &event->trans_event);
1536 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1538 xhci->error_bitmask |= 1 << 9;
1543 xhci->error_bitmask |= 1 << 3;
1545 /* Any of the above functions may drop and re-acquire the lock, so check
1546 * to make sure a watchdog timer didn't mark the host as non-responsive.
1548 if (xhci->xhc_state & XHCI_STATE_DYING) {
1549 xhci_dbg(xhci, "xHCI host dying, returning from "
1550 "event handler.\n");
1555 /* Update SW and HC event ring dequeue pointer */
1556 inc_deq(xhci, xhci->event_ring, true);
1557 xhci_set_hc_event_deq(xhci);
1559 /* Are there more items on the event ring? */
1560 xhci_handle_event(xhci);
1563 /**** Endpoint Ring Operations ****/
1566 * Generic function for queueing a TRB on a ring.
1567 * The caller must have checked to make sure there's room on the ring.
1569 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1571 u32 field1, u32 field2, u32 field3, u32 field4)
1573 struct xhci_generic_trb *trb;
1575 trb = &ring->enqueue->generic;
1576 trb->field[0] = field1;
1577 trb->field[1] = field2;
1578 trb->field[2] = field3;
1579 trb->field[3] = field4;
1580 inc_enq(xhci, ring, consumer);
1584 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1585 * FIXME allocate segments if the ring is full.
1587 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1588 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1590 /* Make sure the endpoint has been added to xHC schedule */
1591 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1593 case EP_STATE_DISABLED:
1595 * USB core changed config/interfaces without notifying us,
1596 * or hardware is reporting the wrong state.
1598 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1600 case EP_STATE_ERROR:
1601 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1602 /* FIXME event handling code for error needs to clear it */
1603 /* XXX not sure if this should be -ENOENT or not */
1605 case EP_STATE_HALTED:
1606 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1607 case EP_STATE_STOPPED:
1608 case EP_STATE_RUNNING:
1611 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1613 * FIXME issue Configure Endpoint command to try to get the HC
1614 * back into a known state.
1618 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1619 /* FIXME allocate more room */
1620 xhci_err(xhci, "ERROR no room on ep ring\n");
1626 static int prepare_transfer(struct xhci_hcd *xhci,
1627 struct xhci_virt_device *xdev,
1628 unsigned int ep_index,
1629 unsigned int num_trbs,
1631 struct xhci_td **td,
1635 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1636 ret = prepare_ring(xhci, xdev->eps[ep_index].ring,
1637 ep_ctx->ep_info & EP_STATE_MASK,
1638 num_trbs, mem_flags);
1641 *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1644 INIT_LIST_HEAD(&(*td)->td_list);
1645 INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1647 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1648 if (unlikely(ret)) {
1654 urb->hcpriv = (void *) (*td);
1655 /* Add this TD to the tail of the endpoint ring's TD list */
1656 list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list);
1657 (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg;
1658 (*td)->first_trb = xdev->eps[ep_index].ring->enqueue;
1663 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1665 int num_sgs, num_trbs, running_total, temp, i;
1666 struct scatterlist *sg;
1669 num_sgs = urb->num_sgs;
1670 temp = urb->transfer_buffer_length;
1672 xhci_dbg(xhci, "count sg list trbs: \n");
1674 for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1675 unsigned int previous_total_trbs = num_trbs;
1676 unsigned int len = sg_dma_len(sg);
1678 /* Scatter gather list entries may cross 64KB boundaries */
1679 running_total = TRB_MAX_BUFF_SIZE -
1680 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1681 if (running_total != 0)
1684 /* How many more 64KB chunks to transfer, how many more TRBs? */
1685 while (running_total < sg_dma_len(sg)) {
1687 running_total += TRB_MAX_BUFF_SIZE;
1689 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1690 i, (unsigned long long)sg_dma_address(sg),
1691 len, len, num_trbs - previous_total_trbs);
1693 len = min_t(int, len, temp);
1698 xhci_dbg(xhci, "\n");
1699 if (!in_interrupt())
1700 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1701 urb->ep->desc.bEndpointAddress,
1702 urb->transfer_buffer_length,
1707 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1710 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1711 "TRBs, %d left\n", __func__,
1712 urb->ep->desc.bEndpointAddress, num_trbs);
1713 if (running_total != urb->transfer_buffer_length)
1714 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1715 "queued %#x (%d), asked for %#x (%d)\n",
1717 urb->ep->desc.bEndpointAddress,
1718 running_total, running_total,
1719 urb->transfer_buffer_length,
1720 urb->transfer_buffer_length);
1723 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1724 unsigned int ep_index, int start_cycle,
1725 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1728 * Pass all the TRBs to the hardware at once and make sure this write
1732 start_trb->field[3] |= start_cycle;
1733 ring_ep_doorbell(xhci, slot_id, ep_index);
1737 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1738 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1739 * (comprised of sg list entries) can take several service intervals to
1742 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1743 struct urb *urb, int slot_id, unsigned int ep_index)
1745 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1746 xhci->devs[slot_id]->out_ctx, ep_index);
1750 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1751 ep_interval = urb->interval;
1752 /* Convert to microframes */
1753 if (urb->dev->speed == USB_SPEED_LOW ||
1754 urb->dev->speed == USB_SPEED_FULL)
1756 /* FIXME change this to a warning and a suggestion to use the new API
1757 * to set the polling interval (once the API is added).
1759 if (xhci_interval != ep_interval) {
1760 if (!printk_ratelimit())
1761 dev_dbg(&urb->dev->dev, "Driver uses different interval"
1762 " (%d microframe%s) than xHCI "
1763 "(%d microframe%s)\n",
1765 ep_interval == 1 ? "" : "s",
1767 xhci_interval == 1 ? "" : "s");
1768 urb->interval = xhci_interval;
1769 /* Convert back to frames for LS/FS devices */
1770 if (urb->dev->speed == USB_SPEED_LOW ||
1771 urb->dev->speed == USB_SPEED_FULL)
1774 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1778 * The TD size is the number of bytes remaining in the TD (including this TRB),
1779 * right shifted by 10.
1780 * It must fit in bits 21:17, so it can't be bigger than 31.
1782 static u32 xhci_td_remainder(unsigned int remainder)
1784 u32 max = (1 << (21 - 17 + 1)) - 1;
1786 if ((remainder >> 10) >= max)
1789 return (remainder >> 10) << 17;
1792 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1793 struct urb *urb, int slot_id, unsigned int ep_index)
1795 struct xhci_ring *ep_ring;
1796 unsigned int num_trbs;
1798 struct scatterlist *sg;
1800 int trb_buff_len, this_sg_len, running_total;
1804 struct xhci_generic_trb *start_trb;
1807 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1808 num_trbs = count_sg_trbs_needed(xhci, urb);
1809 num_sgs = urb->num_sgs;
1811 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1812 ep_index, num_trbs, urb, &td, mem_flags);
1813 if (trb_buff_len < 0)
1814 return trb_buff_len;
1816 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1817 * until we've finished creating all the other TRBs. The ring's cycle
1818 * state may change as we enqueue the other TRBs, so save it too.
1820 start_trb = &ep_ring->enqueue->generic;
1821 start_cycle = ep_ring->cycle_state;
1825 * How much data is in the first TRB?
1827 * There are three forces at work for TRB buffer pointers and lengths:
1828 * 1. We don't want to walk off the end of this sg-list entry buffer.
1829 * 2. The transfer length that the driver requested may be smaller than
1830 * the amount of memory allocated for this scatter-gather list.
1831 * 3. TRBs buffers can't cross 64KB boundaries.
1834 addr = (u64) sg_dma_address(sg);
1835 this_sg_len = sg_dma_len(sg);
1836 trb_buff_len = TRB_MAX_BUFF_SIZE -
1837 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1838 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1839 if (trb_buff_len > urb->transfer_buffer_length)
1840 trb_buff_len = urb->transfer_buffer_length;
1841 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1845 /* Queue the first TRB, even if it's zero-length */
1848 u32 length_field = 0;
1851 /* Don't change the cycle bit of the first TRB until later */
1855 field |= ep_ring->cycle_state;
1857 /* Chain all the TRBs together; clear the chain bit in the last
1858 * TRB to indicate it's the last TRB in the chain.
1863 /* FIXME - add check for ZERO_PACKET flag before this */
1864 td->last_trb = ep_ring->enqueue;
1867 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1868 "64KB boundary at %#x, end dma = %#x\n",
1869 (unsigned int) addr, trb_buff_len, trb_buff_len,
1870 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1871 (unsigned int) addr + trb_buff_len);
1872 if (TRB_MAX_BUFF_SIZE -
1873 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1874 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1875 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1876 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1877 (unsigned int) addr + trb_buff_len);
1879 remainder = xhci_td_remainder(urb->transfer_buffer_length -
1881 length_field = TRB_LEN(trb_buff_len) |
1884 queue_trb(xhci, ep_ring, false,
1885 lower_32_bits(addr),
1886 upper_32_bits(addr),
1888 /* We always want to know if the TRB was short,
1889 * or we won't get an event when it completes.
1890 * (Unless we use event data TRBs, which are a
1891 * waste of space and HC resources.)
1893 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1895 running_total += trb_buff_len;
1897 /* Calculate length for next transfer --
1898 * Are we done queueing all the TRBs for this sg entry?
1900 this_sg_len -= trb_buff_len;
1901 if (this_sg_len == 0) {
1906 addr = (u64) sg_dma_address(sg);
1907 this_sg_len = sg_dma_len(sg);
1909 addr += trb_buff_len;
1912 trb_buff_len = TRB_MAX_BUFF_SIZE -
1913 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1914 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1915 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1917 urb->transfer_buffer_length - running_total;
1918 } while (running_total < urb->transfer_buffer_length);
1920 check_trb_math(urb, num_trbs, running_total);
1921 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1925 /* This is very similar to what ehci-q.c qtd_fill() does */
1926 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1927 struct urb *urb, int slot_id, unsigned int ep_index)
1929 struct xhci_ring *ep_ring;
1932 struct xhci_generic_trb *start_trb;
1935 u32 field, length_field;
1937 int running_total, trb_buff_len, ret;
1941 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1943 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1946 /* How much data is (potentially) left before the 64KB boundary? */
1947 running_total = TRB_MAX_BUFF_SIZE -
1948 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1950 /* If there's some data on this 64KB chunk, or we have to send a
1951 * zero-length transfer, we need at least one TRB
1953 if (running_total != 0 || urb->transfer_buffer_length == 0)
1955 /* How many more 64KB chunks to transfer, how many more TRBs? */
1956 while (running_total < urb->transfer_buffer_length) {
1958 running_total += TRB_MAX_BUFF_SIZE;
1960 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1962 if (!in_interrupt())
1963 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1964 urb->ep->desc.bEndpointAddress,
1965 urb->transfer_buffer_length,
1966 urb->transfer_buffer_length,
1967 (unsigned long long)urb->transfer_dma,
1970 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1971 num_trbs, urb, &td, mem_flags);
1976 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1977 * until we've finished creating all the other TRBs. The ring's cycle
1978 * state may change as we enqueue the other TRBs, so save it too.
1980 start_trb = &ep_ring->enqueue->generic;
1981 start_cycle = ep_ring->cycle_state;
1984 /* How much data is in the first TRB? */
1985 addr = (u64) urb->transfer_dma;
1986 trb_buff_len = TRB_MAX_BUFF_SIZE -
1987 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1988 if (urb->transfer_buffer_length < trb_buff_len)
1989 trb_buff_len = urb->transfer_buffer_length;
1993 /* Queue the first TRB, even if it's zero-length */
1998 /* Don't change the cycle bit of the first TRB until later */
2002 field |= ep_ring->cycle_state;
2004 /* Chain all the TRBs together; clear the chain bit in the last
2005 * TRB to indicate it's the last TRB in the chain.
2010 /* FIXME - add check for ZERO_PACKET flag before this */
2011 td->last_trb = ep_ring->enqueue;
2014 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2016 length_field = TRB_LEN(trb_buff_len) |
2019 queue_trb(xhci, ep_ring, false,
2020 lower_32_bits(addr),
2021 upper_32_bits(addr),
2023 /* We always want to know if the TRB was short,
2024 * or we won't get an event when it completes.
2025 * (Unless we use event data TRBs, which are a
2026 * waste of space and HC resources.)
2028 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2030 running_total += trb_buff_len;
2032 /* Calculate length for next transfer */
2033 addr += trb_buff_len;
2034 trb_buff_len = urb->transfer_buffer_length - running_total;
2035 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2036 trb_buff_len = TRB_MAX_BUFF_SIZE;
2037 } while (running_total < urb->transfer_buffer_length);
2039 check_trb_math(urb, num_trbs, running_total);
2040 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2044 /* Caller must have locked xhci->lock */
2045 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2046 struct urb *urb, int slot_id, unsigned int ep_index)
2048 struct xhci_ring *ep_ring;
2051 struct usb_ctrlrequest *setup;
2052 struct xhci_generic_trb *start_trb;
2054 u32 field, length_field;
2057 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2060 * Need to copy setup packet into setup TRB, so we can't use the setup
2063 if (!urb->setup_packet)
2066 if (!in_interrupt())
2067 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2069 /* 1 TRB for setup, 1 for status */
2072 * Don't need to check if we need additional event data and normal TRBs,
2073 * since data in control transfers will never get bigger than 16MB
2074 * XXX: can we get a buffer that crosses 64KB boundaries?
2076 if (urb->transfer_buffer_length > 0)
2078 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
2079 urb, &td, mem_flags);
2084 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2085 * until we've finished creating all the other TRBs. The ring's cycle
2086 * state may change as we enqueue the other TRBs, so save it too.
2088 start_trb = &ep_ring->enqueue->generic;
2089 start_cycle = ep_ring->cycle_state;
2091 /* Queue setup TRB - see section 6.4.1.2.1 */
2092 /* FIXME better way to translate setup_packet into two u32 fields? */
2093 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2094 queue_trb(xhci, ep_ring, false,
2095 /* FIXME endianness is probably going to bite my ass here. */
2096 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2097 setup->wIndex | setup->wLength << 16,
2098 TRB_LEN(8) | TRB_INTR_TARGET(0),
2099 /* Immediate data in pointer */
2100 TRB_IDT | TRB_TYPE(TRB_SETUP));
2102 /* If there's data, queue data TRBs */
2104 length_field = TRB_LEN(urb->transfer_buffer_length) |
2105 xhci_td_remainder(urb->transfer_buffer_length) |
2107 if (urb->transfer_buffer_length > 0) {
2108 if (setup->bRequestType & USB_DIR_IN)
2109 field |= TRB_DIR_IN;
2110 queue_trb(xhci, ep_ring, false,
2111 lower_32_bits(urb->transfer_dma),
2112 upper_32_bits(urb->transfer_dma),
2114 /* Event on short tx */
2115 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2118 /* Save the DMA address of the last TRB in the TD */
2119 td->last_trb = ep_ring->enqueue;
2121 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2122 /* If the device sent data, the status stage is an OUT transfer */
2123 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2127 queue_trb(xhci, ep_ring, false,
2131 /* Event on completion */
2132 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2134 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2138 /**** Command Ring Operations ****/
2140 /* Generic function for queueing a command TRB on the command ring.
2141 * Check to make sure there's room on the command ring for one command TRB.
2142 * Also check that there's room reserved for commands that must not fail.
2143 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2144 * then only check for the number of reserved spots.
2145 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2146 * because the command event handler may want to resubmit a failed command.
2148 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2149 u32 field3, u32 field4, bool command_must_succeed)
2151 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2152 if (!command_must_succeed)
2155 if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
2156 if (!in_interrupt())
2157 xhci_err(xhci, "ERR: No room for command on command ring\n");
2158 if (command_must_succeed)
2159 xhci_err(xhci, "ERR: Reserved TRB counting for "
2160 "unfailable commands failed.\n");
2163 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
2164 field4 | xhci->cmd_ring->cycle_state);
2168 /* Queue a no-op command on the command ring */
2169 static int queue_cmd_noop(struct xhci_hcd *xhci)
2171 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2175 * Place a no-op command on the command ring to test the command and
2178 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2180 if (queue_cmd_noop(xhci) < 0)
2182 xhci->noops_submitted++;
2183 return xhci_ring_cmd_db;
2186 /* Queue a slot enable or disable request on the command ring */
2187 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2189 return queue_command(xhci, 0, 0, 0,
2190 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2193 /* Queue an address device command TRB */
2194 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2197 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2198 upper_32_bits(in_ctx_ptr), 0,
2199 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2203 /* Queue a reset device command TRB */
2204 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2206 return queue_command(xhci, 0, 0, 0,
2207 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2211 /* Queue a configure endpoint command TRB */
2212 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2213 u32 slot_id, bool command_must_succeed)
2215 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2216 upper_32_bits(in_ctx_ptr), 0,
2217 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2218 command_must_succeed);
2221 /* Queue an evaluate context command TRB */
2222 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2225 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2226 upper_32_bits(in_ctx_ptr), 0,
2227 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2231 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2232 unsigned int ep_index)
2234 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2235 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2236 u32 type = TRB_TYPE(TRB_STOP_RING);
2238 return queue_command(xhci, 0, 0, 0,
2239 trb_slot_id | trb_ep_index | type, false);
2242 /* Set Transfer Ring Dequeue Pointer command.
2243 * This should not be used for endpoints that have streams enabled.
2245 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2246 unsigned int ep_index, struct xhci_segment *deq_seg,
2247 union xhci_trb *deq_ptr, u32 cycle_state)
2250 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2251 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2252 u32 type = TRB_TYPE(TRB_SET_DEQ);
2254 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2256 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2257 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2261 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2262 upper_32_bits(addr), 0,
2263 trb_slot_id | trb_ep_index | type, false);
2266 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2267 unsigned int ep_index)
2269 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2270 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2271 u32 type = TRB_TYPE(TRB_RESET_EP);
2273 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,