drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include "xhci.h"
  69
  70 /*
  71  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  72  * address of the TRB.
  73  */
  74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  75                 union xhci_trb *trb)
  76 {
  77         unsigned long segment_offset;
  78
  79         if (!seg || !trb || trb < seg->trbs)
  80                 return 0;
  81         /* offset in TRBs */
  82         segment_offset = trb - seg->trbs;
  83         if (segment_offset > TRBS_PER_SEGMENT)
  84                 return 0;
  85         return seg->dma + (segment_offset * sizeof(*trb));
  86 }
  87
  88 /* Does this link TRB point to the first segment in a ring,
  89  * or was the previous TRB the last TRB on the last segment in the ERST?
  90  */
  91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  92                 struct xhci_segment *seg, union xhci_trb *trb)
  93 {
  94         if (ring == xhci->event_ring)
  95                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  96                         (seg->next == xhci->event_ring->first_seg);
  97         else
  98                 return trb->link.control & LINK_TOGGLE;
  99 }
 100
 101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 102  * segment?  I.e. would the updated event TRB pointer step off the end of the
 103  * event seg?
 104  */
 105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 106                 struct xhci_segment *seg, union xhci_trb *trb)
 107 {
 108         if (ring == xhci->event_ring)
 109                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 110         else
 111                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 112 }
 113
 114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 115  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 116  * effect the ring dequeue or enqueue pointers.
 117  */
 118 static void next_trb(struct xhci_hcd *xhci,
 119                 struct xhci_ring *ring,
 120                 struct xhci_segment **seg,
 121                 union xhci_trb **trb)
 122 {
 123         if (last_trb(xhci, ring, *seg, *trb)) {
 124                 *seg = (*seg)->next;
 125                 *trb = ((*seg)->trbs);
 126         } else {
 127                 *trb = (*trb)++;
 128         }
 129 }
 130
 131 /*
 132  * See Cycle bit rules. SW is the consumer for the event ring only.
 133  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 134  */
 135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 136 {
 137         union xhci_trb *next = ++(ring->dequeue);
 138         unsigned long long addr;
 139
 140         ring->deq_updates++;
 141         /* Update the dequeue pointer further if that was a link TRB or we're at
 142          * the end of an event ring segment (which doesn't have link TRBS)
 143          */
 144         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 145                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 146                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 147                         if (!in_interrupt())
 148                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 149                                                 ring,
 150                                                 (unsigned int) ring->cycle_state);
 151                 }
 152                 ring->deq_seg = ring->deq_seg->next;
 153                 ring->dequeue = ring->deq_seg->trbs;
 154                 next = ring->dequeue;
 155         }
 156         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 157         if (ring == xhci->event_ring)
 158                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 159         else if (ring == xhci->cmd_ring)
 160                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 161         else
 162                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 163 }
 164
 165 /*
 166  * See Cycle bit rules. SW is the consumer for the event ring only.
 167  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 168  *
 169  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 170  * chain bit is set), then set the chain bit in all the following link TRBs.
 171  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 172  * have their chain bit cleared (so that each Link TRB is a separate TD).
 173  *
 174  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 175  * set, but other sections talk about dealing with the chain bit set.
 176  * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
 177  */
 178 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 179 {
 180         u32 chain;
 181         union xhci_trb *next;
 182         unsigned long long addr;
 183
 184         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 185         next = ++(ring->enqueue);
 186
 187         ring->enq_updates++;
 188         /* Update the dequeue pointer further if that was a link TRB or we're at
 189          * the end of an event ring segment (which doesn't have link TRBS)
 190          */
 191         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 192                 if (!consumer) {
 193                         if (ring != xhci->event_ring) {
 194                                 next->link.control &= ~TRB_CHAIN;
 195                                 next->link.control |= chain;
 196                                 /* Give this link TRB to the hardware */
 197                                 wmb();
 198                                 if (next->link.control & TRB_CYCLE)
 199                                         next->link.control &= (u32) ~TRB_CYCLE;
 200                                 else
 201                                         next->link.control |= (u32) TRB_CYCLE;
 202                         }
 203                         /* Toggle the cycle bit after the last ring segment. */
 204                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 205                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 206                                 if (!in_interrupt())
 207                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 208                                                         ring,
 209                                                         (unsigned int) ring->cycle_state);
 210                         }
 211                 }
 212                 ring->enq_seg = ring->enq_seg->next;
 213                 ring->enqueue = ring->enq_seg->trbs;
 214                 next = ring->enqueue;
 215         }
 216         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 217         if (ring == xhci->event_ring)
 218                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 219         else if (ring == xhci->cmd_ring)
 220                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 221         else
 222                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 223 }
 224
 225 /*
 226  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 227  * above.
 228  * FIXME: this would be simpler and faster if we just kept track of the number
 229  * of free TRBs in a ring.
 230  */
 231 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 232                 unsigned int num_trbs)
 233 {
 234         int i;
 235         union xhci_trb *enq = ring->enqueue;
 236         struct xhci_segment *enq_seg = ring->enq_seg;
 237
 238         /* Check if ring is empty */
 239         if (enq == ring->dequeue)
 240                 return 1;
 241         /* Make sure there's an extra empty TRB available */
 242         for (i = 0; i <= num_trbs; ++i) {
 243                 if (enq == ring->dequeue)
 244                         return 0;
 245                 enq++;
 246                 while (last_trb(xhci, ring, enq_seg, enq)) {
 247                         enq_seg = enq_seg->next;
 248                         enq = enq_seg->trbs;
 249                 }
 250         }
 251         return 1;
 252 }
 253
 254 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 255 {
 256         u64 temp;
 257         dma_addr_t deq;
 258
 259         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 260                         xhci->event_ring->dequeue);
 261         if (deq == 0 && !in_interrupt())
 262                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 263                                 "dequeue ptr.\n");
 264         /* Update HC event ring dequeue pointer */
 265         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 266         temp &= ERST_PTR_MASK;
 267         /* Don't clear the EHB bit (which is RW1C) because
 268          * there might be more events to service.
 269          */
 270         temp &= ~ERST_EHB;
 271         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 272         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 273                         &xhci->ir_set->erst_dequeue);
 274 }
 275
 276 /* Ring the host controller doorbell after placing a command on the ring */
 277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 278 {
 279         u32 temp;
 280
 281         xhci_dbg(xhci, "// Ding dong!\n");
 282         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 283         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 284         /* Flush PCI posted writes */
 285         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 286 }
 287
 288 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 289                 unsigned int slot_id,
 290                 unsigned int ep_index)
 291 {
 292         struct xhci_ring *ep_ring;
 293         u32 field;
 294         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 295
 296         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 297         /* Don't ring the doorbell for this endpoint if there are pending
 298          * cancellations because the we don't want to interrupt processing.
 299          */
 300         if (!ep_ring->cancels_pending && !(ep_ring->state & SET_DEQ_PENDING)
 301                         && !(ep_ring->state & EP_HALTED)) {
 302                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 303                 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
 304                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 305                  * isn't time-critical and we shouldn't make the CPU wait for
 306                  * the flush.
 307                  */
 308                 xhci_readl(xhci, db_addr);
 309         }
 310 }
 311
 312 /*
 313  * Find the segment that trb is in.  Start searching in start_seg.
 314  * If we must move past a segment that has a link TRB with a toggle cycle state
 315  * bit set, then we will toggle the value pointed at by cycle_state.
 316  */
 317 static struct xhci_segment *find_trb_seg(
 318                 struct xhci_segment *start_seg,
 319                 union xhci_trb  *trb, int *cycle_state)
 320 {
 321         struct xhci_segment *cur_seg = start_seg;
 322         struct xhci_generic_trb *generic_trb;
 323
 324         while (cur_seg->trbs > trb ||
 325                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 326                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 327                 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
 328                                 (generic_trb->field[3] & LINK_TOGGLE))
 329                         *cycle_state = ~(*cycle_state) & 0x1;
 330                 cur_seg = cur_seg->next;
 331                 if (cur_seg == start_seg)
 332                         /* Looped over the entire list.  Oops! */
 333                         return 0;
 334         }
 335         return cur_seg;
 336 }
 337
 338 /*
 339  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 340  * Record the new state of the xHC's endpoint ring dequeue segment,
 341  * dequeue pointer, and new consumer cycle state in state.
 342  * Update our internal representation of the ring's dequeue pointer.
 343  *
 344  * We do this in three jumps:
 345  *  - First we update our new ring state to be the same as when the xHC stopped.
 346  *  - Then we traverse the ring to find the segment that contains
 347  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 348  *    any link TRBs with the toggle cycle bit set.
 349  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 350  *    if we've moved it past a link TRB with the toggle cycle bit set.
 351  */
 352 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 353                 unsigned int slot_id, unsigned int ep_index,
 354                 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
 355 {
 356         struct xhci_virt_device *dev = xhci->devs[slot_id];
 357         struct xhci_ring *ep_ring = dev->ep_rings[ep_index];
 358         struct xhci_generic_trb *trb;
 359         struct xhci_ep_ctx *ep_ctx;
 360         dma_addr_t addr;
 361
 362         state->new_cycle_state = 0;
 363         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 364         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 365                         ep_ring->stopped_trb,
 366                         &state->new_cycle_state);
 367         if (!state->new_deq_seg)
 368                 BUG();
 369         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 370         xhci_dbg(xhci, "Finding endpoint context\n");
 371         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 372         state->new_cycle_state = 0x1 & ep_ctx->deq;
 373
 374         state->new_deq_ptr = cur_td->last_trb;
 375         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 376         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 377                         state->new_deq_ptr,
 378                         &state->new_cycle_state);
 379         if (!state->new_deq_seg)
 380                 BUG();
 381
 382         trb = &state->new_deq_ptr->generic;
 383         if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
 384                                 (trb->field[3] & LINK_TOGGLE))
 385                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 386         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 387
 388         /* Don't update the ring cycle state for the producer (us). */
 389         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 390                         state->new_deq_seg);
 391         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 392         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 393                         (unsigned long long) addr);
 394         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 395         ep_ring->dequeue = state->new_deq_ptr;
 396         ep_ring->deq_seg = state->new_deq_seg;
 397 }
 398
 399 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 400                 struct xhci_td *cur_td)
 401 {
 402         struct xhci_segment *cur_seg;
 403         union xhci_trb *cur_trb;
 404
 405         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 406                         true;
 407                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 408                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 409                                 TRB_TYPE(TRB_LINK)) {
 410                         /* Unchain any chained Link TRBs, but
 411                          * leave the pointers intact.
 412                          */
 413                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 414                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 415                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 416                                         "in seg %p (0x%llx dma)\n",
 417                                         cur_trb,
 418                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 419                                         cur_seg,
 420                                         (unsigned long long)cur_seg->dma);
 421                 } else {
 422                         cur_trb->generic.field[0] = 0;
 423                         cur_trb->generic.field[1] = 0;
 424                         cur_trb->generic.field[2] = 0;
 425                         /* Preserve only the cycle bit of this TRB */
 426                         cur_trb->generic.field[3] &= TRB_CYCLE;
 427                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 428                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 429                                         "in seg %p (0x%llx dma)\n",
 430                                         cur_trb,
 431                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 432                                         cur_seg,
 433                                         (unsigned long long)cur_seg->dma);
 434                 }
 435                 if (cur_trb == cur_td->last_trb)
 436                         break;
 437         }
 438 }
 439
 440 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 441                 unsigned int ep_index, struct xhci_segment *deq_seg,
 442                 union xhci_trb *deq_ptr, u32 cycle_state);
 443
 444 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 445                 struct xhci_ring *ep_ring, unsigned int slot_id,
 446                 unsigned int ep_index, struct xhci_dequeue_state *deq_state)
 447 {
 448         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 449                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 450                         deq_state->new_deq_seg,
 451                         (unsigned long long)deq_state->new_deq_seg->dma,
 452                         deq_state->new_deq_ptr,
 453                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 454                         deq_state->new_cycle_state);
 455         queue_set_tr_deq(xhci, slot_id, ep_index,
 456                         deq_state->new_deq_seg,
 457                         deq_state->new_deq_ptr,
 458                         (u32) deq_state->new_cycle_state);
 459         /* Stop the TD queueing code from ringing the doorbell until
 460          * this command completes.  The HC won't set the dequeue pointer
 461          * if the ring is running, and ringing the doorbell starts the
 462          * ring running.
 463          */
 464         ep_ring->state |= SET_DEQ_PENDING;
 465         xhci_ring_cmd_db(xhci);
 466 }
 467
 468 /*
 469  * When we get a command completion for a Stop Endpoint Command, we need to
 470  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 471  *
 472  *  1. If the HW was in the middle of processing the TD that needs to be
 473  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 474  *     in the TD with a Set Dequeue Pointer Command.
 475  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 476  *     bit cleared) so that the HW will skip over them.
 477  */
 478 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 479                 union xhci_trb *trb)
 480 {
 481         unsigned int slot_id;
 482         unsigned int ep_index;
 483         struct xhci_ring *ep_ring;
 484         struct list_head *entry;
 485         struct xhci_td *cur_td = 0;
 486         struct xhci_td *last_unlinked_td;
 487
 488         struct xhci_dequeue_state deq_state;
 489 #ifdef CONFIG_USB_HCD_STAT
 490         ktime_t stop_time = ktime_get();
 491 #endif
 492
 493         memset(&deq_state, 0, sizeof(deq_state));
 494         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 495         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 496         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 497
 498         if (list_empty(&ep_ring->cancelled_td_list))
 499                 return;
 500
 501         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 502          * We have the xHCI lock, so nothing can modify this list until we drop
 503          * it.  We're also in the event handler, so we can't get re-interrupted
 504          * if another Stop Endpoint command completes
 505          */
 506         list_for_each(entry, &ep_ring->cancelled_td_list) {
 507                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 508                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 509                                 cur_td->first_trb,
 510                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 511                 /*
 512                  * If we stopped on the TD we need to cancel, then we have to
 513                  * move the xHC endpoint ring dequeue pointer past this TD.
 514                  */
 515                 if (cur_td == ep_ring->stopped_td)
 516                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
 517                                         &deq_state);
 518                 else
 519                         td_to_noop(xhci, ep_ring, cur_td);
 520                 /*
 521                  * The event handler won't see a completion for this TD anymore,
 522                  * so remove it from the endpoint ring's TD list.  Keep it in
 523                  * the cancelled TD list for URB completion later.
 524                  */
 525                 list_del(&cur_td->td_list);
 526                 ep_ring->cancels_pending--;
 527         }
 528         last_unlinked_td = cur_td;
 529
 530         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 531         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 532                 xhci_queue_new_dequeue_state(xhci, ep_ring,
 533                                 slot_id, ep_index, &deq_state);
 534         } else {
 535                 /* Otherwise just ring the doorbell to restart the ring */
 536                 ring_ep_doorbell(xhci, slot_id, ep_index);
 537         }
 538
 539         /*
 540          * Drop the lock and complete the URBs in the cancelled TD list.
 541          * New TDs to be cancelled might be added to the end of the list before
 542          * we can complete all the URBs for the TDs we already unlinked.
 543          * So stop when we've completed the URB for the last TD we unlinked.
 544          */
 545         do {
 546                 cur_td = list_entry(ep_ring->cancelled_td_list.next,
 547                                 struct xhci_td, cancelled_td_list);
 548                 list_del(&cur_td->cancelled_td_list);
 549
 550                 /* Clean up the cancelled URB */
 551 #ifdef CONFIG_USB_HCD_STAT
 552                 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
 553                                 ktime_sub(stop_time, cur_td->start_time));
 554 #endif
 555                 cur_td->urb->hcpriv = NULL;
 556                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
 557
 558                 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
 559                 spin_unlock(&xhci->lock);
 560                 /* Doesn't matter what we pass for status, since the core will
 561                  * just overwrite it (because the URB has been unlinked).
 562                  */
 563                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
 564                 kfree(cur_td);
 565
 566                 spin_lock(&xhci->lock);
 567         } while (cur_td != last_unlinked_td);
 568
 569         /* Return to the event handler with xhci->lock re-acquired */
 570 }
 571
 572 /*
 573  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 574  * we need to clear the set deq pending flag in the endpoint ring state, so that
 575  * the TD queueing code can ring the doorbell again.  We also need to ring the
 576  * endpoint doorbell to restart the ring, but only if there aren't more
 577  * cancellations pending.
 578  */
 579 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 580                 struct xhci_event_cmd *event,
 581                 union xhci_trb *trb)
 582 {
 583         unsigned int slot_id;
 584         unsigned int ep_index;
 585         struct xhci_ring *ep_ring;
 586         struct xhci_virt_device *dev;
 587         struct xhci_ep_ctx *ep_ctx;
 588         struct xhci_slot_ctx *slot_ctx;
 589
 590         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 591         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 592         dev = xhci->devs[slot_id];
 593         ep_ring = dev->ep_rings[ep_index];
 594         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 595         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 596
 597         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 598                 unsigned int ep_state;
 599                 unsigned int slot_state;
 600
 601                 switch (GET_COMP_CODE(event->status)) {
 602                 case COMP_TRB_ERR:
 603                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 604                                         "of stream ID configuration\n");
 605                         break;
 606                 case COMP_CTX_STATE:
 607                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 608                                         "to incorrect slot or ep state.\n");
 609                         ep_state = ep_ctx->ep_info;
 610                         ep_state &= EP_STATE_MASK;
 611                         slot_state = slot_ctx->dev_state;
 612                         slot_state = GET_SLOT_STATE(slot_state);
 613                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 614                                         slot_state, ep_state);
 615                         break;
 616                 case COMP_EBADSLT:
 617                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 618                                         "slot %u was not enabled.\n", slot_id);
 619                         break;
 620                 default:
 621                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 622                                         "completion code of %u.\n",
 623                                         GET_COMP_CODE(event->status));
 624                         break;
 625                 }
 626                 /* OK what do we do now?  The endpoint state is hosed, and we
 627                  * should never get to this point if the synchronization between
 628                  * queueing, and endpoint state are correct.  This might happen
 629                  * if the device gets disconnected after we've finished
 630                  * cancelling URBs, which might not be an error...
 631                  */
 632         } else {
 633                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 634                                 ep_ctx->deq);
 635         }
 636
 637         ep_ring->state &= ~SET_DEQ_PENDING;
 638         ring_ep_doorbell(xhci, slot_id, ep_index);
 639 }
 640
 641 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 642                 struct xhci_event_cmd *event,
 643                 union xhci_trb *trb)
 644 {
 645         int slot_id;
 646         unsigned int ep_index;
 647
 648         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 649         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 650         /* This command will only fail if the endpoint wasn't halted,
 651          * but we don't care.
 652          */
 653         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 654                         (unsigned int) GET_COMP_CODE(event->status));
 655
 656         /* Clear our internal halted state and restart the ring */
 657         xhci->devs[slot_id]->ep_rings[ep_index]->state &= ~EP_HALTED;
 658         ring_ep_doorbell(xhci, slot_id, ep_index);
 659 }
 660
 661 static void handle_cmd_completion(struct xhci_hcd *xhci,
 662                 struct xhci_event_cmd *event)
 663 {
 664         int slot_id = TRB_TO_SLOT_ID(event->flags);
 665         u64 cmd_dma;
 666         dma_addr_t cmd_dequeue_dma;
 667
 668         cmd_dma = event->cmd_trb;
 669         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 670                         xhci->cmd_ring->dequeue);
 671         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 672         if (cmd_dequeue_dma == 0) {
 673                 xhci->error_bitmask |= 1 << 4;
 674                 return;
 675         }
 676         /* Does the DMA address match our internal dequeue pointer address? */
 677         if (cmd_dma != (u64) cmd_dequeue_dma) {
 678                 xhci->error_bitmask |= 1 << 5;
 679                 return;
 680         }
 681         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 682         case TRB_TYPE(TRB_ENABLE_SLOT):
 683                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 684                         xhci->slot_id = slot_id;
 685                 else
 686                         xhci->slot_id = 0;
 687                 complete(&xhci->addr_dev);
 688                 break;
 689         case TRB_TYPE(TRB_DISABLE_SLOT):
 690                 if (xhci->devs[slot_id])
 691                         xhci_free_virt_device(xhci, slot_id);
 692                 break;
 693         case TRB_TYPE(TRB_CONFIG_EP):
 694                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 695                 complete(&xhci->devs[slot_id]->cmd_completion);
 696                 break;
 697         case TRB_TYPE(TRB_ADDR_DEV):
 698                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 699                 complete(&xhci->addr_dev);
 700                 break;
 701         case TRB_TYPE(TRB_STOP_RING):
 702                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
 703                 break;
 704         case TRB_TYPE(TRB_SET_DEQ):
 705                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
 706                 break;
 707         case TRB_TYPE(TRB_CMD_NOOP):
 708                 ++xhci->noops_handled;
 709                 break;
 710         case TRB_TYPE(TRB_RESET_EP):
 711                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
 712                 break;
 713         default:
 714                 /* Skip over unknown commands on the event ring */
 715                 xhci->error_bitmask |= 1 << 6;
 716                 break;
 717         }
 718         inc_deq(xhci, xhci->cmd_ring, false);
 719 }
 720
 721 static void handle_port_status(struct xhci_hcd *xhci,
 722                 union xhci_trb *event)
 723 {
 724         u32 port_id;
 725
 726         /* Port status change events always have a successful completion code */
 727         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
 728                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
 729                 xhci->error_bitmask |= 1 << 8;
 730         }
 731         /* FIXME: core doesn't care about all port link state changes yet */
 732         port_id = GET_PORT_ID(event->generic.field[0]);
 733         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
 734
 735         /* Update event ring dequeue pointer before dropping the lock */
 736         inc_deq(xhci, xhci->event_ring, true);
 737         xhci_set_hc_event_deq(xhci);
 738
 739         spin_unlock(&xhci->lock);
 740         /* Pass this up to the core */
 741         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
 742         spin_lock(&xhci->lock);
 743 }
 744
 745 /*
 746  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
 747  * at end_trb, which may be in another segment.  If the suspect DMA address is a
 748  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
 749  * returns 0.
 750  */
 751 static struct xhci_segment *trb_in_td(
 752                 struct xhci_segment *start_seg,
 753                 union xhci_trb  *start_trb,
 754                 union xhci_trb  *end_trb,
 755                 dma_addr_t      suspect_dma)
 756 {
 757         dma_addr_t start_dma;
 758         dma_addr_t end_seg_dma;
 759         dma_addr_t end_trb_dma;
 760         struct xhci_segment *cur_seg;
 761
 762         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
 763         cur_seg = start_seg;
 764
 765         do {
 766                 /* We may get an event for a Link TRB in the middle of a TD */
 767                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
 768                                 &start_seg->trbs[TRBS_PER_SEGMENT - 1]);
 769                 /* If the end TRB isn't in this segment, this is set to 0 */
 770                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
 771
 772                 if (end_trb_dma > 0) {
 773                         /* The end TRB is in this segment, so suspect should be here */
 774                         if (start_dma <= end_trb_dma) {
 775                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
 776                                         return cur_seg;
 777                         } else {
 778                                 /* Case for one segment with
 779                                  * a TD wrapped around to the top
 780                                  */
 781                                 if ((suspect_dma >= start_dma &&
 782                                                         suspect_dma <= end_seg_dma) ||
 783                                                 (suspect_dma >= cur_seg->dma &&
 784                                                  suspect_dma <= end_trb_dma))
 785                                         return cur_seg;
 786                         }
 787                         return 0;
 788                 } else {
 789                         /* Might still be somewhere in this segment */
 790                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
 791                                 return cur_seg;
 792                 }
 793                 cur_seg = cur_seg->next;
 794                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
 795         } while (1);
 796
 797 }
 798
 799 /*
 800  * If this function returns an error condition, it means it got a Transfer
 801  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
 802  * At this point, the host controller is probably hosed and should be reset.
 803  */
 804 static int handle_tx_event(struct xhci_hcd *xhci,
 805                 struct xhci_transfer_event *event)
 806 {
 807         struct xhci_virt_device *xdev;
 808         struct xhci_ring *ep_ring;
 809         int ep_index;
 810         struct xhci_td *td = 0;
 811         dma_addr_t event_dma;
 812         struct xhci_segment *event_seg;
 813         union xhci_trb *event_trb;
 814         struct urb *urb = 0;
 815         int status = -EINPROGRESS;
 816         struct xhci_ep_ctx *ep_ctx;
 817
 818         xhci_dbg(xhci, "In %s\n", __func__);
 819         xdev = xhci->devs[TRB_TO_SLOT_ID(event->flags)];
 820         if (!xdev) {
 821                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
 822                 return -ENODEV;
 823         }
 824
 825         /* Endpoint ID is 1 based, our index is zero based */
 826         ep_index = TRB_TO_EP_ID(event->flags) - 1;
 827         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
 828         ep_ring = xdev->ep_rings[ep_index];
 829         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
 830         if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
 831                 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
 832                 return -ENODEV;
 833         }
 834
 835         event_dma = event->buffer;
 836         /* This TRB should be in the TD at the head of this ring's TD list */
 837         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
 838         if (list_empty(&ep_ring->td_list)) {
 839                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
 840                                 TRB_TO_SLOT_ID(event->flags), ep_index);
 841                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 842                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 843                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
 844                 urb = NULL;
 845                 goto cleanup;
 846         }
 847         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
 848         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
 849
 850         /* Is this a TRB in the currently executing TD? */
 851         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
 852         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
 853                         td->last_trb, event_dma);
 854         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
 855         if (!event_seg) {
 856                 /* HC is busted, give up! */
 857                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
 858                 return -ESHUTDOWN;
 859         }
 860         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
 861         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 862                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 863         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
 864                         lower_32_bits(event->buffer));
 865         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
 866                         upper_32_bits(event->buffer));
 867         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
 868                         (unsigned int) event->transfer_len);
 869         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
 870                         (unsigned int) event->flags);
 871
 872         /* Look for common error cases */
 873         switch (GET_COMP_CODE(event->transfer_len)) {
 874         /* Skip codes that require special handling depending on
 875          * transfer type
 876          */
 877         case COMP_SUCCESS:
 878         case COMP_SHORT_TX:
 879                 break;
 880         case COMP_STOP:
 881                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
 882                 break;
 883         case COMP_STOP_INVAL:
 884                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
 885                 break;
 886         case COMP_STALL:
 887                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
 888                 ep_ring->state |= EP_HALTED;
 889                 status = -EPIPE;
 890                 break;
 891         case COMP_TRB_ERR:
 892                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
 893                 status = -EILSEQ;
 894                 break;
 895         case COMP_TX_ERR:
 896                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
 897                 status = -EPROTO;
 898                 break;
 899         case COMP_BABBLE:
 900                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
 901                 status = -EOVERFLOW;
 902                 break;
 903         case COMP_DB_ERR:
 904                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
 905                 status = -ENOSR;
 906                 break;
 907         default:
 908                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
 909                 urb = NULL;
 910                 goto cleanup;
 911         }
 912         /* Now update the urb's actual_length and give back to the core */
 913         /* Was this a control transfer? */
 914         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
 915                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
 916                 switch (GET_COMP_CODE(event->transfer_len)) {
 917                 case COMP_SUCCESS:
 918                         if (event_trb == ep_ring->dequeue) {
 919                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
 920                                 status = -ESHUTDOWN;
 921                         } else if (event_trb != td->last_trb) {
 922                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
 923                                 status = -ESHUTDOWN;
 924                         } else {
 925                                 xhci_dbg(xhci, "Successful control transfer!\n");
 926                                 status = 0;
 927                         }
 928                         break;
 929                 case COMP_SHORT_TX:
 930                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
 931                         status = -EREMOTEIO;
 932                         break;
 933                 default:
 934                         /* Others already handled above */
 935                         break;
 936                 }
 937                 /*
 938                  * Did we transfer any data, despite the errors that might have
 939                  * happened?  I.e. did we get past the setup stage?
 940                  */
 941                 if (event_trb != ep_ring->dequeue) {
 942                         /* The event was for the status stage */
 943                         if (event_trb == td->last_trb) {
 944                                 if (td->urb->actual_length != 0) {
 945                                         /* Don't overwrite a previously set error code */
 946                                         if (status == -EINPROGRESS || status == 0)
 947                                                 /* Did we already see a short data stage? */
 948                                                 status = -EREMOTEIO;
 949                                 } else {
 950                                         td->urb->actual_length =
 951                                                 td->urb->transfer_buffer_length;
 952                                 }
 953                         } else {
 954                         /* Maybe the event was for the data stage? */
 955                                 if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL) {
 956                                         /* We didn't stop on a link TRB in the middle */
 957                                         td->urb->actual_length =
 958                                                 td->urb->transfer_buffer_length -
 959                                                 TRB_LEN(event->transfer_len);
 960                                         xhci_dbg(xhci, "Waiting for status stage event\n");
 961                                         urb = NULL;
 962                                         goto cleanup;
 963                                 }
 964                         }
 965                 }
 966         } else {
 967                 switch (GET_COMP_CODE(event->transfer_len)) {
 968                 case COMP_SUCCESS:
 969                         /* Double check that the HW transferred everything. */
 970                         if (event_trb != td->last_trb) {
 971                                 xhci_warn(xhci, "WARN Successful completion "
 972                                                 "on short TX\n");
 973                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
 974                                         status = -EREMOTEIO;
 975                                 else
 976                                         status = 0;
 977                         } else {
 978                                 xhci_dbg(xhci, "Successful bulk transfer!\n");
 979                                 status = 0;
 980                         }
 981                         break;
 982                 case COMP_SHORT_TX:
 983                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
 984                                 status = -EREMOTEIO;
 985                         else
 986                                 status = 0;
 987                         break;
 988                 default:
 989                         /* Others already handled above */
 990                         break;
 991                 }
 992                 dev_dbg(&td->urb->dev->dev,
 993                                 "ep %#x - asked for %d bytes, "
 994                                 "%d bytes untransferred\n",
 995                                 td->urb->ep->desc.bEndpointAddress,
 996                                 td->urb->transfer_buffer_length,
 997                                 TRB_LEN(event->transfer_len));
 998                 /* Fast path - was this the last TRB in the TD for this URB? */
 999                 if (event_trb == td->last_trb) {
1000                         if (TRB_LEN(event->transfer_len) != 0) {
1001                                 td->urb->actual_length =
1002                                         td->urb->transfer_buffer_length -
1003                                         TRB_LEN(event->transfer_len);
1004                                 if (td->urb->actual_length < 0) {
1005                                         xhci_warn(xhci, "HC gave bad length "
1006                                                         "of %d bytes left\n",
1007                                                         TRB_LEN(event->transfer_len));
1008                                         td->urb->actual_length = 0;
1009                                 }
1010                                 /* Don't overwrite a previously set error code */
1011                                 if (status == -EINPROGRESS) {
1012                                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1013                                                 status = -EREMOTEIO;
1014                                         else
1015                                                 status = 0;
1016                                 }
1017                         } else {
1018                                 td->urb->actual_length = td->urb->transfer_buffer_length;
1019                                 /* Ignore a short packet completion if the
1020                                  * untransferred length was zero.
1021                                  */
1022                                 if (status == -EREMOTEIO)
1023                                         status = 0;
1024                         }
1025                 } else {
1026                         /* Slow path - walk the list, starting from the dequeue
1027                          * pointer, to get the actual length transferred.
1028                          */
1029                         union xhci_trb *cur_trb;
1030                         struct xhci_segment *cur_seg;
1031
1032                         td->urb->actual_length = 0;
1033                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1034                                         cur_trb != event_trb;
1035                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1036                                 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1037                                                 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1038                                         td->urb->actual_length +=
1039                                                 TRB_LEN(cur_trb->generic.field[2]);
1040                         }
1041                         /* If the ring didn't stop on a Link or No-op TRB, add
1042                          * in the actual bytes transferred from the Normal TRB
1043                          */
1044                         if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL)
1045                                 td->urb->actual_length +=
1046                                         TRB_LEN(cur_trb->generic.field[2]) -
1047                                         TRB_LEN(event->transfer_len);
1048                 }
1049         }
1050         if (GET_COMP_CODE(event->transfer_len) == COMP_STOP_INVAL ||
1051                         GET_COMP_CODE(event->transfer_len) == COMP_STOP) {
1052                 /* The Endpoint Stop Command completion will take care of any
1053                  * stopped TDs.  A stopped TD may be restarted, so don't update
1054                  * the ring dequeue pointer or take this TD off any lists yet.
1055                  */
1056                 ep_ring->stopped_td = td;
1057                 ep_ring->stopped_trb = event_trb;
1058         } else {
1059                 if (GET_COMP_CODE(event->transfer_len) == COMP_STALL) {
1060                         /* The transfer is completed from the driver's
1061                          * perspective, but we need to issue a set dequeue
1062                          * command for this stalled endpoint to move the dequeue
1063                          * pointer past the TD.  We can't do that here because
1064                          * the halt condition must be cleared first.
1065                          */
1066                         ep_ring->stopped_td = td;
1067                         ep_ring->stopped_trb = event_trb;
1068                 } else {
1069                         /* Update ring dequeue pointer */
1070                         while (ep_ring->dequeue != td->last_trb)
1071                                 inc_deq(xhci, ep_ring, false);
1072                         inc_deq(xhci, ep_ring, false);
1073                 }
1074
1075                 /* Clean up the endpoint's TD list */
1076                 urb = td->urb;
1077                 list_del(&td->td_list);
1078                 /* Was this TD slated to be cancelled but completed anyway? */
1079                 if (!list_empty(&td->cancelled_td_list)) {
1080                         list_del(&td->cancelled_td_list);
1081                         ep_ring->cancels_pending--;
1082                 }
1083                 /* Leave the TD around for the reset endpoint function to use */
1084                 if (GET_COMP_CODE(event->transfer_len) != COMP_STALL) {
1085                         kfree(td);
1086                 }
1087                 urb->hcpriv = NULL;
1088         }
1089 cleanup:
1090         inc_deq(xhci, xhci->event_ring, true);
1091         xhci_set_hc_event_deq(xhci);
1092
1093         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1094         if (urb) {
1095                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1096                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1097                                 urb, td->urb->actual_length, status);
1098                 spin_unlock(&xhci->lock);
1099                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1100                 spin_lock(&xhci->lock);
1101         }
1102         return 0;
1103 }
1104
1105 /*
1106  * This function handles all OS-owned events on the event ring.  It may drop
1107  * xhci->lock between event processing (e.g. to pass up port status changes).
1108  */
1109 void xhci_handle_event(struct xhci_hcd *xhci)
1110 {
1111         union xhci_trb *event;
1112         int update_ptrs = 1;
1113         int ret;
1114
1115         xhci_dbg(xhci, "In %s\n", __func__);
1116         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1117                 xhci->error_bitmask |= 1 << 1;
1118                 return;
1119         }
1120
1121         event = xhci->event_ring->dequeue;
1122         /* Does the HC or OS own the TRB? */
1123         if ((event->event_cmd.flags & TRB_CYCLE) !=
1124                         xhci->event_ring->cycle_state) {
1125                 xhci->error_bitmask |= 1 << 2;
1126                 return;
1127         }
1128         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1129
1130         /* FIXME: Handle more event types. */
1131         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1132         case TRB_TYPE(TRB_COMPLETION):
1133                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1134                 handle_cmd_completion(xhci, &event->event_cmd);
1135                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1136                 break;
1137         case TRB_TYPE(TRB_PORT_STATUS):
1138                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1139                 handle_port_status(xhci, event);
1140                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1141                 update_ptrs = 0;
1142                 break;
1143         case TRB_TYPE(TRB_TRANSFER):
1144                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1145                 ret = handle_tx_event(xhci, &event->trans_event);
1146                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1147                 if (ret < 0)
1148                         xhci->error_bitmask |= 1 << 9;
1149                 else
1150                         update_ptrs = 0;
1151                 break;
1152         default:
1153                 xhci->error_bitmask |= 1 << 3;
1154         }
1155
1156         if (update_ptrs) {
1157                 /* Update SW and HC event ring dequeue pointer */
1158                 inc_deq(xhci, xhci->event_ring, true);
1159                 xhci_set_hc_event_deq(xhci);
1160         }
1161         /* Are there more items on the event ring? */
1162         xhci_handle_event(xhci);
1163 }
1164
1165 /****           Endpoint Ring Operations        ****/
1166
1167 /*
1168  * Generic function for queueing a TRB on a ring.
1169  * The caller must have checked to make sure there's room on the ring.
1170  */
1171 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1172                 bool consumer,
1173                 u32 field1, u32 field2, u32 field3, u32 field4)
1174 {
1175         struct xhci_generic_trb *trb;
1176
1177         trb = &ring->enqueue->generic;
1178         trb->field[0] = field1;
1179         trb->field[1] = field2;
1180         trb->field[2] = field3;
1181         trb->field[3] = field4;
1182         inc_enq(xhci, ring, consumer);
1183 }
1184
1185 /*
1186  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1187  * FIXME allocate segments if the ring is full.
1188  */
1189 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1190                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1191 {
1192         /* Make sure the endpoint has been added to xHC schedule */
1193         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1194         switch (ep_state) {
1195         case EP_STATE_DISABLED:
1196                 /*
1197                  * USB core changed config/interfaces without notifying us,
1198                  * or hardware is reporting the wrong state.
1199                  */
1200                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1201                 return -ENOENT;
1202         case EP_STATE_ERROR:
1203                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1204                 /* FIXME event handling code for error needs to clear it */
1205                 /* XXX not sure if this should be -ENOENT or not */
1206                 return -EINVAL;
1207         case EP_STATE_HALTED:
1208                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1209         case EP_STATE_STOPPED:
1210         case EP_STATE_RUNNING:
1211                 break;
1212         default:
1213                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1214                 /*
1215                  * FIXME issue Configure Endpoint command to try to get the HC
1216                  * back into a known state.
1217                  */
1218                 return -EINVAL;
1219         }
1220         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1221                 /* FIXME allocate more room */
1222                 xhci_err(xhci, "ERROR no room on ep ring\n");
1223                 return -ENOMEM;
1224         }
1225         return 0;
1226 }
1227
1228 static int prepare_transfer(struct xhci_hcd *xhci,
1229                 struct xhci_virt_device *xdev,
1230                 unsigned int ep_index,
1231                 unsigned int num_trbs,
1232                 struct urb *urb,
1233                 struct xhci_td **td,
1234                 gfp_t mem_flags)
1235 {
1236         int ret;
1237         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1238         ret = prepare_ring(xhci, xdev->ep_rings[ep_index],
1239                         ep_ctx->ep_info & EP_STATE_MASK,
1240                         num_trbs, mem_flags);
1241         if (ret)
1242                 return ret;
1243         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1244         if (!*td)
1245                 return -ENOMEM;
1246         INIT_LIST_HEAD(&(*td)->td_list);
1247         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1248
1249         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1250         if (unlikely(ret)) {
1251                 kfree(*td);
1252                 return ret;
1253         }
1254
1255         (*td)->urb = urb;
1256         urb->hcpriv = (void *) (*td);
1257         /* Add this TD to the tail of the endpoint ring's TD list */
1258         list_add_tail(&(*td)->td_list, &xdev->ep_rings[ep_index]->td_list);
1259         (*td)->start_seg = xdev->ep_rings[ep_index]->enq_seg;
1260         (*td)->first_trb = xdev->ep_rings[ep_index]->enqueue;
1261
1262         return 0;
1263 }
1264
1265 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1266 {
1267         int num_sgs, num_trbs, running_total, temp, i;
1268         struct scatterlist *sg;
1269
1270         sg = NULL;
1271         num_sgs = urb->num_sgs;
1272         temp = urb->transfer_buffer_length;
1273
1274         xhci_dbg(xhci, "count sg list trbs: \n");
1275         num_trbs = 0;
1276         for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1277                 unsigned int previous_total_trbs = num_trbs;
1278                 unsigned int len = sg_dma_len(sg);
1279
1280                 /* Scatter gather list entries may cross 64KB boundaries */
1281                 running_total = TRB_MAX_BUFF_SIZE -
1282                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1283                 if (running_total != 0)
1284                         num_trbs++;
1285
1286                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1287                 while (running_total < sg_dma_len(sg)) {
1288                         num_trbs++;
1289                         running_total += TRB_MAX_BUFF_SIZE;
1290                 }
1291                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1292                                 i, (unsigned long long)sg_dma_address(sg),
1293                                 len, len, num_trbs - previous_total_trbs);
1294
1295                 len = min_t(int, len, temp);
1296                 temp -= len;
1297                 if (temp == 0)
1298                         break;
1299         }
1300         xhci_dbg(xhci, "\n");
1301         if (!in_interrupt())
1302                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1303                                 urb->ep->desc.bEndpointAddress,
1304                                 urb->transfer_buffer_length,
1305                                 num_trbs);
1306         return num_trbs;
1307 }
1308
1309 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1310 {
1311         if (num_trbs != 0)
1312                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1313                                 "TRBs, %d left\n", __func__,
1314                                 urb->ep->desc.bEndpointAddress, num_trbs);
1315         if (running_total != urb->transfer_buffer_length)
1316                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1317                                 "queued %#x (%d), asked for %#x (%d)\n",
1318                                 __func__,
1319                                 urb->ep->desc.bEndpointAddress,
1320                                 running_total, running_total,
1321                                 urb->transfer_buffer_length,
1322                                 urb->transfer_buffer_length);
1323 }
1324
1325 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1326                 unsigned int ep_index, int start_cycle,
1327                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1328 {
1329         /*
1330          * Pass all the TRBs to the hardware at once and make sure this write
1331          * isn't reordered.
1332          */
1333         wmb();
1334         start_trb->field[3] |= start_cycle;
1335         ring_ep_doorbell(xhci, slot_id, ep_index);
1336 }
1337
1338 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1339                 struct urb *urb, int slot_id, unsigned int ep_index)
1340 {
1341         struct xhci_ring *ep_ring;
1342         unsigned int num_trbs;
1343         struct xhci_td *td;
1344         struct scatterlist *sg;
1345         int num_sgs;
1346         int trb_buff_len, this_sg_len, running_total;
1347         bool first_trb;
1348         u64 addr;
1349
1350         struct xhci_generic_trb *start_trb;
1351         int start_cycle;
1352
1353         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1354         num_trbs = count_sg_trbs_needed(xhci, urb);
1355         num_sgs = urb->num_sgs;
1356
1357         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1358                         ep_index, num_trbs, urb, &td, mem_flags);
1359         if (trb_buff_len < 0)
1360                 return trb_buff_len;
1361         /*
1362          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1363          * until we've finished creating all the other TRBs.  The ring's cycle
1364          * state may change as we enqueue the other TRBs, so save it too.
1365          */
1366         start_trb = &ep_ring->enqueue->generic;
1367         start_cycle = ep_ring->cycle_state;
1368
1369         running_total = 0;
1370         /*
1371          * How much data is in the first TRB?
1372          *
1373          * There are three forces at work for TRB buffer pointers and lengths:
1374          * 1. We don't want to walk off the end of this sg-list entry buffer.
1375          * 2. The transfer length that the driver requested may be smaller than
1376          *    the amount of memory allocated for this scatter-gather list.
1377          * 3. TRBs buffers can't cross 64KB boundaries.
1378          */
1379         sg = urb->sg->sg;
1380         addr = (u64) sg_dma_address(sg);
1381         this_sg_len = sg_dma_len(sg);
1382         trb_buff_len = TRB_MAX_BUFF_SIZE -
1383                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1384         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1385         if (trb_buff_len > urb->transfer_buffer_length)
1386                 trb_buff_len = urb->transfer_buffer_length;
1387         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1388                         trb_buff_len);
1389
1390         first_trb = true;
1391         /* Queue the first TRB, even if it's zero-length */
1392         do {
1393                 u32 field = 0;
1394                 u32 length_field = 0;
1395
1396                 /* Don't change the cycle bit of the first TRB until later */
1397                 if (first_trb)
1398                         first_trb = false;
1399                 else
1400                         field |= ep_ring->cycle_state;
1401
1402                 /* Chain all the TRBs together; clear the chain bit in the last
1403                  * TRB to indicate it's the last TRB in the chain.
1404                  */
1405                 if (num_trbs > 1) {
1406                         field |= TRB_CHAIN;
1407                 } else {
1408                         /* FIXME - add check for ZERO_PACKET flag before this */
1409                         td->last_trb = ep_ring->enqueue;
1410                         field |= TRB_IOC;
1411                 }
1412                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1413                                 "64KB boundary at %#x, end dma = %#x\n",
1414                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
1415                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1416                                 (unsigned int) addr + trb_buff_len);
1417                 if (TRB_MAX_BUFF_SIZE -
1418                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1419                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1420                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1421                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1422                                         (unsigned int) addr + trb_buff_len);
1423                 }
1424                 length_field = TRB_LEN(trb_buff_len) |
1425                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1426                         TRB_INTR_TARGET(0);
1427                 queue_trb(xhci, ep_ring, false,
1428                                 lower_32_bits(addr),
1429                                 upper_32_bits(addr),
1430                                 length_field,
1431                                 /* We always want to know if the TRB was short,
1432                                  * or we won't get an event when it completes.
1433                                  * (Unless we use event data TRBs, which are a
1434                                  * waste of space and HC resources.)
1435                                  */
1436                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1437                 --num_trbs;
1438                 running_total += trb_buff_len;
1439
1440                 /* Calculate length for next transfer --
1441                  * Are we done queueing all the TRBs for this sg entry?
1442                  */
1443                 this_sg_len -= trb_buff_len;
1444                 if (this_sg_len == 0) {
1445                         --num_sgs;
1446                         if (num_sgs == 0)
1447                                 break;
1448                         sg = sg_next(sg);
1449                         addr = (u64) sg_dma_address(sg);
1450                         this_sg_len = sg_dma_len(sg);
1451                 } else {
1452                         addr += trb_buff_len;
1453                 }
1454
1455                 trb_buff_len = TRB_MAX_BUFF_SIZE -
1456                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1457                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1458                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1459                         trb_buff_len =
1460                                 urb->transfer_buffer_length - running_total;
1461         } while (running_total < urb->transfer_buffer_length);
1462
1463         check_trb_math(urb, num_trbs, running_total);
1464         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1465         return 0;
1466 }
1467
1468 /* This is very similar to what ehci-q.c qtd_fill() does */
1469 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1470                 struct urb *urb, int slot_id, unsigned int ep_index)
1471 {
1472         struct xhci_ring *ep_ring;
1473         struct xhci_td *td;
1474         int num_trbs;
1475         struct xhci_generic_trb *start_trb;
1476         bool first_trb;
1477         int start_cycle;
1478         u32 field, length_field;
1479
1480         int running_total, trb_buff_len, ret;
1481         u64 addr;
1482
1483         if (urb->sg)
1484                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1485
1486         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1487
1488         num_trbs = 0;
1489         /* How much data is (potentially) left before the 64KB boundary? */
1490         running_total = TRB_MAX_BUFF_SIZE -
1491                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1492
1493         /* If there's some data on this 64KB chunk, or we have to send a
1494          * zero-length transfer, we need at least one TRB
1495          */
1496         if (running_total != 0 || urb->transfer_buffer_length == 0)
1497                 num_trbs++;
1498         /* How many more 64KB chunks to transfer, how many more TRBs? */
1499         while (running_total < urb->transfer_buffer_length) {
1500                 num_trbs++;
1501                 running_total += TRB_MAX_BUFF_SIZE;
1502         }
1503         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1504
1505         if (!in_interrupt())
1506                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1507                                 urb->ep->desc.bEndpointAddress,
1508                                 urb->transfer_buffer_length,
1509                                 urb->transfer_buffer_length,
1510                                 (unsigned long long)urb->transfer_dma,
1511                                 num_trbs);
1512
1513         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1514                         num_trbs, urb, &td, mem_flags);
1515         if (ret < 0)
1516                 return ret;
1517
1518         /*
1519          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1520          * until we've finished creating all the other TRBs.  The ring's cycle
1521          * state may change as we enqueue the other TRBs, so save it too.
1522          */
1523         start_trb = &ep_ring->enqueue->generic;
1524         start_cycle = ep_ring->cycle_state;
1525
1526         running_total = 0;
1527         /* How much data is in the first TRB? */
1528         addr = (u64) urb->transfer_dma;
1529         trb_buff_len = TRB_MAX_BUFF_SIZE -
1530                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1531         if (urb->transfer_buffer_length < trb_buff_len)
1532                 trb_buff_len = urb->transfer_buffer_length;
1533
1534         first_trb = true;
1535
1536         /* Queue the first TRB, even if it's zero-length */
1537         do {
1538                 field = 0;
1539
1540                 /* Don't change the cycle bit of the first TRB until later */
1541                 if (first_trb)
1542                         first_trb = false;
1543                 else
1544                         field |= ep_ring->cycle_state;
1545
1546                 /* Chain all the TRBs together; clear the chain bit in the last
1547                  * TRB to indicate it's the last TRB in the chain.
1548                  */
1549                 if (num_trbs > 1) {
1550                         field |= TRB_CHAIN;
1551                 } else {
1552                         /* FIXME - add check for ZERO_PACKET flag before this */
1553                         td->last_trb = ep_ring->enqueue;
1554                         field |= TRB_IOC;
1555                 }
1556                 length_field = TRB_LEN(trb_buff_len) |
1557                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1558                         TRB_INTR_TARGET(0);
1559                 queue_trb(xhci, ep_ring, false,
1560                                 lower_32_bits(addr),
1561                                 upper_32_bits(addr),
1562                                 length_field,
1563                                 /* We always want to know if the TRB was short,
1564                                  * or we won't get an event when it completes.
1565                                  * (Unless we use event data TRBs, which are a
1566                                  * waste of space and HC resources.)
1567                                  */
1568                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1569                 --num_trbs;
1570                 running_total += trb_buff_len;
1571
1572                 /* Calculate length for next transfer */
1573                 addr += trb_buff_len;
1574                 trb_buff_len = urb->transfer_buffer_length - running_total;
1575                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1576                         trb_buff_len = TRB_MAX_BUFF_SIZE;
1577         } while (running_total < urb->transfer_buffer_length);
1578
1579         check_trb_math(urb, num_trbs, running_total);
1580         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1581         return 0;
1582 }
1583
1584 /* Caller must have locked xhci->lock */
1585 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1586                 struct urb *urb, int slot_id, unsigned int ep_index)
1587 {
1588         struct xhci_ring *ep_ring;
1589         int num_trbs;
1590         int ret;
1591         struct usb_ctrlrequest *setup;
1592         struct xhci_generic_trb *start_trb;
1593         int start_cycle;
1594         u32 field, length_field;
1595         struct xhci_td *td;
1596
1597         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1598
1599         /*
1600          * Need to copy setup packet into setup TRB, so we can't use the setup
1601          * DMA address.
1602          */
1603         if (!urb->setup_packet)
1604                 return -EINVAL;
1605
1606         if (!in_interrupt())
1607                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1608                                 slot_id, ep_index);
1609         /* 1 TRB for setup, 1 for status */
1610         num_trbs = 2;
1611         /*
1612          * Don't need to check if we need additional event data and normal TRBs,
1613          * since data in control transfers will never get bigger than 16MB
1614          * XXX: can we get a buffer that crosses 64KB boundaries?
1615          */
1616         if (urb->transfer_buffer_length > 0)
1617                 num_trbs++;
1618         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1619                         urb, &td, mem_flags);
1620         if (ret < 0)
1621                 return ret;
1622
1623         /*
1624          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1625          * until we've finished creating all the other TRBs.  The ring's cycle
1626          * state may change as we enqueue the other TRBs, so save it too.
1627          */
1628         start_trb = &ep_ring->enqueue->generic;
1629         start_cycle = ep_ring->cycle_state;
1630
1631         /* Queue setup TRB - see section 6.4.1.2.1 */
1632         /* FIXME better way to translate setup_packet into two u32 fields? */
1633         setup = (struct usb_ctrlrequest *) urb->setup_packet;
1634         queue_trb(xhci, ep_ring, false,
1635                         /* FIXME endianness is probably going to bite my ass here. */
1636                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1637                         setup->wIndex | setup->wLength << 16,
1638                         TRB_LEN(8) | TRB_INTR_TARGET(0),
1639                         /* Immediate data in pointer */
1640                         TRB_IDT | TRB_TYPE(TRB_SETUP));
1641
1642         /* If there's data, queue data TRBs */
1643         field = 0;
1644         length_field = TRB_LEN(urb->transfer_buffer_length) |
1645                 TD_REMAINDER(urb->transfer_buffer_length) |
1646                 TRB_INTR_TARGET(0);
1647         if (urb->transfer_buffer_length > 0) {
1648                 if (setup->bRequestType & USB_DIR_IN)
1649                         field |= TRB_DIR_IN;
1650                 queue_trb(xhci, ep_ring, false,
1651                                 lower_32_bits(urb->transfer_dma),
1652                                 upper_32_bits(urb->transfer_dma),
1653                                 length_field,
1654                                 /* Event on short tx */
1655                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1656         }
1657
1658         /* Save the DMA address of the last TRB in the TD */
1659         td->last_trb = ep_ring->enqueue;
1660
1661         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1662         /* If the device sent data, the status stage is an OUT transfer */
1663         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1664                 field = 0;
1665         else
1666                 field = TRB_DIR_IN;
1667         queue_trb(xhci, ep_ring, false,
1668                         0,
1669                         0,
1670                         TRB_INTR_TARGET(0),
1671                         /* Event on completion */
1672                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1673
1674         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1675         return 0;
1676 }
1677
1678 /****           Command Ring Operations         ****/
1679
1680 /* Generic function for queueing a command TRB on the command ring */
1681 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4)
1682 {
1683         if (!room_on_ring(xhci, xhci->cmd_ring, 1)) {
1684                 if (!in_interrupt())
1685                         xhci_err(xhci, "ERR: No room for command on command ring\n");
1686                 return -ENOMEM;
1687         }
1688         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1689                         field4 | xhci->cmd_ring->cycle_state);
1690         return 0;
1691 }
1692
1693 /* Queue a no-op command on the command ring */
1694 static int queue_cmd_noop(struct xhci_hcd *xhci)
1695 {
1696         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP));
1697 }
1698
1699 /*
1700  * Place a no-op command on the command ring to test the command and
1701  * event ring.
1702  */
1703 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1704 {
1705         if (queue_cmd_noop(xhci) < 0)
1706                 return NULL;
1707         xhci->noops_submitted++;
1708         return xhci_ring_cmd_db;
1709 }
1710
1711 /* Queue a slot enable or disable request on the command ring */
1712 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1713 {
1714         return queue_command(xhci, 0, 0, 0,
1715                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id));
1716 }
1717
1718 /* Queue an address device command TRB */
1719 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1720                 u32 slot_id)
1721 {
1722         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1723                         upper_32_bits(in_ctx_ptr), 0,
1724                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id));
1725 }
1726
1727 /* Queue a configure endpoint command TRB */
1728 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1729                 u32 slot_id)
1730 {
1731         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1732                         upper_32_bits(in_ctx_ptr), 0,
1733                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
1734 }
1735
1736 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1737                 unsigned int ep_index)
1738 {
1739         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1740         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1741         u32 type = TRB_TYPE(TRB_STOP_RING);
1742
1743         return queue_command(xhci, 0, 0, 0,
1744                         trb_slot_id | trb_ep_index | type);
1745 }
1746
1747 /* Set Transfer Ring Dequeue Pointer command.
1748  * This should not be used for endpoints that have streams enabled.
1749  */
1750 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
1751                 unsigned int ep_index, struct xhci_segment *deq_seg,
1752                 union xhci_trb *deq_ptr, u32 cycle_state)
1753 {
1754         dma_addr_t addr;
1755         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1756         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1757         u32 type = TRB_TYPE(TRB_SET_DEQ);
1758
1759         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
1760         if (addr == 0) {
1761                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
1762                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
1763                                 deq_seg, deq_ptr);
1764                 return 0;
1765         }
1766         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
1767                         upper_32_bits(addr), 0,
1768                         trb_slot_id | trb_ep_index | type);
1769 }
1770
1771 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1772                 unsigned int ep_index)
1773 {
1774         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1775         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1776         u32 type = TRB_TYPE(TRB_RESET_EP);
1777
1778         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type);
1779 }