drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include "xhci.h"
  69
  70 /*
  71  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  72  * address of the TRB.
  73  */
  74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  75                 union xhci_trb *trb)
  76 {
  77         unsigned long segment_offset;
  78
  79         if (!seg || !trb || trb < seg->trbs)
  80                 return 0;
  81         /* offset in TRBs */
  82         segment_offset = trb - seg->trbs;
  83         if (segment_offset > TRBS_PER_SEGMENT)
  84                 return 0;
  85         return seg->dma + (segment_offset * sizeof(*trb));
  86 }
  87
  88 /* Does this link TRB point to the first segment in a ring,
  89  * or was the previous TRB the last TRB on the last segment in the ERST?
  90  */
  91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  92                 struct xhci_segment *seg, union xhci_trb *trb)
  93 {
  94         if (ring == xhci->event_ring)
  95                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  96                         (seg->next == xhci->event_ring->first_seg);
  97         else
  98                 return trb->link.control & LINK_TOGGLE;
  99 }
 100
 101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 102  * segment?  I.e. would the updated event TRB pointer step off the end of the
 103  * event seg?
 104  */
 105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 106                 struct xhci_segment *seg, union xhci_trb *trb)
 107 {
 108         if (ring == xhci->event_ring)
 109                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 110         else
 111                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 112 }
 113
 114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 115  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 116  * effect the ring dequeue or enqueue pointers.
 117  */
 118 static void next_trb(struct xhci_hcd *xhci,
 119                 struct xhci_ring *ring,
 120                 struct xhci_segment **seg,
 121                 union xhci_trb **trb)
 122 {
 123         if (last_trb(xhci, ring, *seg, *trb)) {
 124                 *seg = (*seg)->next;
 125                 *trb = ((*seg)->trbs);
 126         } else {
 127                 *trb = (*trb)++;
 128         }
 129 }
 130
 131 /*
 132  * See Cycle bit rules. SW is the consumer for the event ring only.
 133  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 134  */
 135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 136 {
 137         union xhci_trb *next = ++(ring->dequeue);
 138         unsigned long long addr;
 139
 140         ring->deq_updates++;
 141         /* Update the dequeue pointer further if that was a link TRB or we're at
 142          * the end of an event ring segment (which doesn't have link TRBS)
 143          */
 144         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 145                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 146                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 147                         if (!in_interrupt())
 148                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 149                                                 ring,
 150                                                 (unsigned int) ring->cycle_state);
 151                 }
 152                 ring->deq_seg = ring->deq_seg->next;
 153                 ring->dequeue = ring->deq_seg->trbs;
 154                 next = ring->dequeue;
 155         }
 156         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 157         if (ring == xhci->event_ring)
 158                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 159         else if (ring == xhci->cmd_ring)
 160                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 161         else
 162                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 163 }
 164
 165 /*
 166  * See Cycle bit rules. SW is the consumer for the event ring only.
 167  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 168  *
 169  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 170  * chain bit is set), then set the chain bit in all the following link TRBs.
 171  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 172  * have their chain bit cleared (so that each Link TRB is a separate TD).
 173  *
 174  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 175  * set, but other sections talk about dealing with the chain bit set.  This was
 176  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 177  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 178  */
 179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 180 {
 181         u32 chain;
 182         union xhci_trb *next;
 183         unsigned long long addr;
 184
 185         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 186         next = ++(ring->enqueue);
 187
 188         ring->enq_updates++;
 189         /* Update the dequeue pointer further if that was a link TRB or we're at
 190          * the end of an event ring segment (which doesn't have link TRBS)
 191          */
 192         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 193                 if (!consumer) {
 194                         if (ring != xhci->event_ring) {
 195                                 /* If we're not dealing with 0.95 hardware,
 196                                  * carry over the chain bit of the previous TRB
 197                                  * (which may mean the chain bit is cleared).
 198                                  */
 199                                 if (!xhci_link_trb_quirk(xhci)) {
 200                                         next->link.control &= ~TRB_CHAIN;
 201                                         next->link.control |= chain;
 202                                 }
 203                                 /* Give this link TRB to the hardware */
 204                                 wmb();
 205                                 if (next->link.control & TRB_CYCLE)
 206                                         next->link.control &= (u32) ~TRB_CYCLE;
 207                                 else
 208                                         next->link.control |= (u32) TRB_CYCLE;
 209                         }
 210                         /* Toggle the cycle bit after the last ring segment. */
 211                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 212                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 213                                 if (!in_interrupt())
 214                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 215                                                         ring,
 216                                                         (unsigned int) ring->cycle_state);
 217                         }
 218                 }
 219                 ring->enq_seg = ring->enq_seg->next;
 220                 ring->enqueue = ring->enq_seg->trbs;
 221                 next = ring->enqueue;
 222         }
 223         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 224         if (ring == xhci->event_ring)
 225                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 226         else if (ring == xhci->cmd_ring)
 227                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 228         else
 229                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 230 }
 231
 232 /*
 233  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 234  * above.
 235  * FIXME: this would be simpler and faster if we just kept track of the number
 236  * of free TRBs in a ring.
 237  */
 238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 239                 unsigned int num_trbs)
 240 {
 241         int i;
 242         union xhci_trb *enq = ring->enqueue;
 243         struct xhci_segment *enq_seg = ring->enq_seg;
 244
 245         /* Check if ring is empty */
 246         if (enq == ring->dequeue)
 247                 return 1;
 248         /* Make sure there's an extra empty TRB available */
 249         for (i = 0; i <= num_trbs; ++i) {
 250                 if (enq == ring->dequeue)
 251                         return 0;
 252                 enq++;
 253                 while (last_trb(xhci, ring, enq_seg, enq)) {
 254                         enq_seg = enq_seg->next;
 255                         enq = enq_seg->trbs;
 256                 }
 257         }
 258         return 1;
 259 }
 260
 261 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 262 {
 263         u64 temp;
 264         dma_addr_t deq;
 265
 266         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 267                         xhci->event_ring->dequeue);
 268         if (deq == 0 && !in_interrupt())
 269                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 270                                 "dequeue ptr.\n");
 271         /* Update HC event ring dequeue pointer */
 272         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 273         temp &= ERST_PTR_MASK;
 274         /* Don't clear the EHB bit (which is RW1C) because
 275          * there might be more events to service.
 276          */
 277         temp &= ~ERST_EHB;
 278         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 279         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 280                         &xhci->ir_set->erst_dequeue);
 281 }
 282
 283 /* Ring the host controller doorbell after placing a command on the ring */
 284 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 285 {
 286         u32 temp;
 287
 288         xhci_dbg(xhci, "// Ding dong!\n");
 289         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 290         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 291         /* Flush PCI posted writes */
 292         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 293 }
 294
 295 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 296                 unsigned int slot_id,
 297                 unsigned int ep_index)
 298 {
 299         struct xhci_virt_ep *ep;
 300         unsigned int ep_state;
 301         u32 field;
 302         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 303
 304         ep = &xhci->devs[slot_id]->eps[ep_index];
 305         ep_state = ep->ep_state;
 306         /* Don't ring the doorbell for this endpoint if there are pending
 307          * cancellations because the we don't want to interrupt processing.
 308          */
 309         if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
 310                         && !(ep_state & EP_HALTED)) {
 311                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 312                 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
 313                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 314                  * isn't time-critical and we shouldn't make the CPU wait for
 315                  * the flush.
 316                  */
 317                 xhci_readl(xhci, db_addr);
 318         }
 319 }
 320
 321 /*
 322  * Find the segment that trb is in.  Start searching in start_seg.
 323  * If we must move past a segment that has a link TRB with a toggle cycle state
 324  * bit set, then we will toggle the value pointed at by cycle_state.
 325  */
 326 static struct xhci_segment *find_trb_seg(
 327                 struct xhci_segment *start_seg,
 328                 union xhci_trb  *trb, int *cycle_state)
 329 {
 330         struct xhci_segment *cur_seg = start_seg;
 331         struct xhci_generic_trb *generic_trb;
 332
 333         while (cur_seg->trbs > trb ||
 334                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 335                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 336                 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
 337                                 (generic_trb->field[3] & LINK_TOGGLE))
 338                         *cycle_state = ~(*cycle_state) & 0x1;
 339                 cur_seg = cur_seg->next;
 340                 if (cur_seg == start_seg)
 341                         /* Looped over the entire list.  Oops! */
 342                         return 0;
 343         }
 344         return cur_seg;
 345 }
 346
 347 /*
 348  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 349  * Record the new state of the xHC's endpoint ring dequeue segment,
 350  * dequeue pointer, and new consumer cycle state in state.
 351  * Update our internal representation of the ring's dequeue pointer.
 352  *
 353  * We do this in three jumps:
 354  *  - First we update our new ring state to be the same as when the xHC stopped.
 355  *  - Then we traverse the ring to find the segment that contains
 356  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 357  *    any link TRBs with the toggle cycle bit set.
 358  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 359  *    if we've moved it past a link TRB with the toggle cycle bit set.
 360  */
 361 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 362                 unsigned int slot_id, unsigned int ep_index,
 363                 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
 364 {
 365         struct xhci_virt_device *dev = xhci->devs[slot_id];
 366         struct xhci_ring *ep_ring = dev->eps[ep_index].ring;
 367         struct xhci_generic_trb *trb;
 368         struct xhci_ep_ctx *ep_ctx;
 369         dma_addr_t addr;
 370
 371         state->new_cycle_state = 0;
 372         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 373         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 374                         dev->eps[ep_index].stopped_trb,
 375                         &state->new_cycle_state);
 376         if (!state->new_deq_seg)
 377                 BUG();
 378         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 379         xhci_dbg(xhci, "Finding endpoint context\n");
 380         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 381         state->new_cycle_state = 0x1 & ep_ctx->deq;
 382
 383         state->new_deq_ptr = cur_td->last_trb;
 384         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 385         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 386                         state->new_deq_ptr,
 387                         &state->new_cycle_state);
 388         if (!state->new_deq_seg)
 389                 BUG();
 390
 391         trb = &state->new_deq_ptr->generic;
 392         if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
 393                                 (trb->field[3] & LINK_TOGGLE))
 394                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 395         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 396
 397         /* Don't update the ring cycle state for the producer (us). */
 398         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 399                         state->new_deq_seg);
 400         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 401         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 402                         (unsigned long long) addr);
 403         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 404         ep_ring->dequeue = state->new_deq_ptr;
 405         ep_ring->deq_seg = state->new_deq_seg;
 406 }
 407
 408 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 409                 struct xhci_td *cur_td)
 410 {
 411         struct xhci_segment *cur_seg;
 412         union xhci_trb *cur_trb;
 413
 414         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 415                         true;
 416                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 417                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 418                                 TRB_TYPE(TRB_LINK)) {
 419                         /* Unchain any chained Link TRBs, but
 420                          * leave the pointers intact.
 421                          */
 422                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 423                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 424                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 425                                         "in seg %p (0x%llx dma)\n",
 426                                         cur_trb,
 427                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 428                                         cur_seg,
 429                                         (unsigned long long)cur_seg->dma);
 430                 } else {
 431                         cur_trb->generic.field[0] = 0;
 432                         cur_trb->generic.field[1] = 0;
 433                         cur_trb->generic.field[2] = 0;
 434                         /* Preserve only the cycle bit of this TRB */
 435                         cur_trb->generic.field[3] &= TRB_CYCLE;
 436                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 437                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 438                                         "in seg %p (0x%llx dma)\n",
 439                                         cur_trb,
 440                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 441                                         cur_seg,
 442                                         (unsigned long long)cur_seg->dma);
 443                 }
 444                 if (cur_trb == cur_td->last_trb)
 445                         break;
 446         }
 447 }
 448
 449 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 450                 unsigned int ep_index, struct xhci_segment *deq_seg,
 451                 union xhci_trb *deq_ptr, u32 cycle_state);
 452
 453 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 454                 unsigned int slot_id, unsigned int ep_index,
 455                 struct xhci_dequeue_state *deq_state)
 456 {
 457         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 458
 459         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 460                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 461                         deq_state->new_deq_seg,
 462                         (unsigned long long)deq_state->new_deq_seg->dma,
 463                         deq_state->new_deq_ptr,
 464                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 465                         deq_state->new_cycle_state);
 466         queue_set_tr_deq(xhci, slot_id, ep_index,
 467                         deq_state->new_deq_seg,
 468                         deq_state->new_deq_ptr,
 469                         (u32) deq_state->new_cycle_state);
 470         /* Stop the TD queueing code from ringing the doorbell until
 471          * this command completes.  The HC won't set the dequeue pointer
 472          * if the ring is running, and ringing the doorbell starts the
 473          * ring running.
 474          */
 475         ep->ep_state |= SET_DEQ_PENDING;
 476 }
 477
 478 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 479                 struct xhci_virt_ep *ep)
 480 {
 481         ep->ep_state &= ~EP_HALT_PENDING;
 482         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 483          * timer is running on another CPU, we don't decrement stop_cmds_pending
 484          * (since we didn't successfully stop the watchdog timer).
 485          */
 486         if (del_timer(&ep->stop_cmd_timer))
 487                 ep->stop_cmds_pending--;
 488 }
 489
 490 /* Must be called with xhci->lock held in interrupt context */
 491 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 492                 struct xhci_td *cur_td, int status, char *adjective)
 493 {
 494         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 495
 496         cur_td->urb->hcpriv = NULL;
 497         usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb);
 498         xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb);
 499
 500         spin_unlock(&xhci->lock);
 501         usb_hcd_giveback_urb(hcd, cur_td->urb, status);
 502         kfree(cur_td);
 503         spin_lock(&xhci->lock);
 504         xhci_dbg(xhci, "%s URB given back\n", adjective);
 505 }
 506
 507 /*
 508  * When we get a command completion for a Stop Endpoint Command, we need to
 509  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 510  *
 511  *  1. If the HW was in the middle of processing the TD that needs to be
 512  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 513  *     in the TD with a Set Dequeue Pointer Command.
 514  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 515  *     bit cleared) so that the HW will skip over them.
 516  */
 517 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 518                 union xhci_trb *trb)
 519 {
 520         unsigned int slot_id;
 521         unsigned int ep_index;
 522         struct xhci_ring *ep_ring;
 523         struct xhci_virt_ep *ep;
 524         struct list_head *entry;
 525         struct xhci_td *cur_td = 0;
 526         struct xhci_td *last_unlinked_td;
 527
 528         struct xhci_dequeue_state deq_state;
 529
 530         memset(&deq_state, 0, sizeof(deq_state));
 531         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 532         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 533         ep = &xhci->devs[slot_id]->eps[ep_index];
 534         ep_ring = ep->ring;
 535
 536         if (list_empty(&ep->cancelled_td_list)) {
 537                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 538                 ring_ep_doorbell(xhci, slot_id, ep_index);
 539                 return;
 540         }
 541
 542         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 543          * We have the xHCI lock, so nothing can modify this list until we drop
 544          * it.  We're also in the event handler, so we can't get re-interrupted
 545          * if another Stop Endpoint command completes
 546          */
 547         list_for_each(entry, &ep->cancelled_td_list) {
 548                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 549                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 550                                 cur_td->first_trb,
 551                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 552                 /*
 553                  * If we stopped on the TD we need to cancel, then we have to
 554                  * move the xHC endpoint ring dequeue pointer past this TD.
 555                  */
 556                 if (cur_td == ep->stopped_td)
 557                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
 558                                         &deq_state);
 559                 else
 560                         td_to_noop(xhci, ep_ring, cur_td);
 561                 /*
 562                  * The event handler won't see a completion for this TD anymore,
 563                  * so remove it from the endpoint ring's TD list.  Keep it in
 564                  * the cancelled TD list for URB completion later.
 565                  */
 566                 list_del(&cur_td->td_list);
 567         }
 568         last_unlinked_td = cur_td;
 569         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 570
 571         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 572         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 573                 xhci_queue_new_dequeue_state(xhci,
 574                                 slot_id, ep_index, &deq_state);
 575                 xhci_ring_cmd_db(xhci);
 576         } else {
 577                 /* Otherwise just ring the doorbell to restart the ring */
 578                 ring_ep_doorbell(xhci, slot_id, ep_index);
 579         }
 580
 581         /*
 582          * Drop the lock and complete the URBs in the cancelled TD list.
 583          * New TDs to be cancelled might be added to the end of the list before
 584          * we can complete all the URBs for the TDs we already unlinked.
 585          * So stop when we've completed the URB for the last TD we unlinked.
 586          */
 587         do {
 588                 cur_td = list_entry(ep->cancelled_td_list.next,
 589                                 struct xhci_td, cancelled_td_list);
 590                 list_del(&cur_td->cancelled_td_list);
 591
 592                 /* Clean up the cancelled URB */
 593                 /* Doesn't matter what we pass for status, since the core will
 594                  * just overwrite it (because the URB has been unlinked).
 595                  */
 596                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 597
 598                 /* Stop processing the cancelled list if the watchdog timer is
 599                  * running.
 600                  */
 601                 if (xhci->xhc_state & XHCI_STATE_DYING)
 602                         return;
 603         } while (cur_td != last_unlinked_td);
 604
 605         /* Return to the event handler with xhci->lock re-acquired */
 606 }
 607
 608 /* Watchdog timer function for when a stop endpoint command fails to complete.
 609  * In this case, we assume the host controller is broken or dying or dead.  The
 610  * host may still be completing some other events, so we have to be careful to
 611  * let the event ring handler and the URB dequeueing/enqueueing functions know
 612  * through xhci->state.
 613  *
 614  * The timer may also fire if the host takes a very long time to respond to the
 615  * command, and the stop endpoint command completion handler cannot delete the
 616  * timer before the timer function is called.  Another endpoint cancellation may
 617  * sneak in before the timer function can grab the lock, and that may queue
 618  * another stop endpoint command and add the timer back.  So we cannot use a
 619  * simple flag to say whether there is a pending stop endpoint command for a
 620  * particular endpoint.
 621  *
 622  * Instead we use a combination of that flag and a counter for the number of
 623  * pending stop endpoint commands.  If the timer is the tail end of the last
 624  * stop endpoint command, and the endpoint's command is still pending, we assume
 625  * the host is dying.
 626  */
 627 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 628 {
 629         struct xhci_hcd *xhci;
 630         struct xhci_virt_ep *ep;
 631         struct xhci_virt_ep *temp_ep;
 632         struct xhci_ring *ring;
 633         struct xhci_td *cur_td;
 634         int ret, i, j;
 635
 636         ep = (struct xhci_virt_ep *) arg;
 637         xhci = ep->xhci;
 638
 639         spin_lock(&xhci->lock);
 640
 641         ep->stop_cmds_pending--;
 642         if (xhci->xhc_state & XHCI_STATE_DYING) {
 643                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 644                                 "xHCI as DYING, exiting.\n");
 645                 spin_unlock(&xhci->lock);
 646                 return;
 647         }
 648         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 649                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 650                                 "exiting.\n");
 651                 spin_unlock(&xhci->lock);
 652                 return;
 653         }
 654
 655         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 656         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 657         /* Oops, HC is dead or dying or at least not responding to the stop
 658          * endpoint command.
 659          */
 660         xhci->xhc_state |= XHCI_STATE_DYING;
 661         /* Disable interrupts from the host controller and start halting it */
 662         xhci_quiesce(xhci);
 663         spin_unlock(&xhci->lock);
 664
 665         ret = xhci_halt(xhci);
 666
 667         spin_lock(&xhci->lock);
 668         if (ret < 0) {
 669                 /* This is bad; the host is not responding to commands and it's
 670                  * not allowing itself to be halted.  At least interrupts are
 671                  * disabled, so we can set HC_STATE_HALT and notify the
 672                  * USB core.  But if we call usb_hc_died(), it will attempt to
 673                  * disconnect all device drivers under this host.  Those
 674                  * disconnect() methods will wait for all URBs to be unlinked,
 675                  * so we must complete them.
 676                  */
 677                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 678                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 679                 /* We could turn all TDs on the rings to no-ops.  This won't
 680                  * help if the host has cached part of the ring, and is slow if
 681                  * we want to preserve the cycle bit.  Skip it and hope the host
 682                  * doesn't touch the memory.
 683                  */
 684         }
 685         for (i = 0; i < MAX_HC_SLOTS; i++) {
 686                 if (!xhci->devs[i])
 687                         continue;
 688                 for (j = 0; j < 31; j++) {
 689                         temp_ep = &xhci->devs[i]->eps[j];
 690                         ring = temp_ep->ring;
 691                         if (!ring)
 692                                 continue;
 693                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 694                                         "ep index %u\n", i, j);
 695                         while (!list_empty(&ring->td_list)) {
 696                                 cur_td = list_first_entry(&ring->td_list,
 697                                                 struct xhci_td,
 698                                                 td_list);
 699                                 list_del(&cur_td->td_list);
 700                                 if (!list_empty(&cur_td->cancelled_td_list))
 701                                         list_del(&cur_td->cancelled_td_list);
 702                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 703                                                 -ESHUTDOWN, "killed");
 704                         }
 705                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 706                                 cur_td = list_first_entry(
 707                                                 &temp_ep->cancelled_td_list,
 708                                                 struct xhci_td,
 709                                                 cancelled_td_list);
 710                                 list_del(&cur_td->cancelled_td_list);
 711                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 712                                                 -ESHUTDOWN, "killed");
 713                         }
 714                 }
 715         }
 716         spin_unlock(&xhci->lock);
 717         xhci_to_hcd(xhci)->state = HC_STATE_HALT;
 718         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 719         usb_hc_died(xhci_to_hcd(xhci));
 720         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 721 }
 722
 723 /*
 724  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 725  * we need to clear the set deq pending flag in the endpoint ring state, so that
 726  * the TD queueing code can ring the doorbell again.  We also need to ring the
 727  * endpoint doorbell to restart the ring, but only if there aren't more
 728  * cancellations pending.
 729  */
 730 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 731                 struct xhci_event_cmd *event,
 732                 union xhci_trb *trb)
 733 {
 734         unsigned int slot_id;
 735         unsigned int ep_index;
 736         struct xhci_ring *ep_ring;
 737         struct xhci_virt_device *dev;
 738         struct xhci_ep_ctx *ep_ctx;
 739         struct xhci_slot_ctx *slot_ctx;
 740
 741         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 742         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 743         dev = xhci->devs[slot_id];
 744         ep_ring = dev->eps[ep_index].ring;
 745         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 746         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 747
 748         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 749                 unsigned int ep_state;
 750                 unsigned int slot_state;
 751
 752                 switch (GET_COMP_CODE(event->status)) {
 753                 case COMP_TRB_ERR:
 754                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 755                                         "of stream ID configuration\n");
 756                         break;
 757                 case COMP_CTX_STATE:
 758                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 759                                         "to incorrect slot or ep state.\n");
 760                         ep_state = ep_ctx->ep_info;
 761                         ep_state &= EP_STATE_MASK;
 762                         slot_state = slot_ctx->dev_state;
 763                         slot_state = GET_SLOT_STATE(slot_state);
 764                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 765                                         slot_state, ep_state);
 766                         break;
 767                 case COMP_EBADSLT:
 768                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 769                                         "slot %u was not enabled.\n", slot_id);
 770                         break;
 771                 default:
 772                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 773                                         "completion code of %u.\n",
 774                                         GET_COMP_CODE(event->status));
 775                         break;
 776                 }
 777                 /* OK what do we do now?  The endpoint state is hosed, and we
 778                  * should never get to this point if the synchronization between
 779                  * queueing, and endpoint state are correct.  This might happen
 780                  * if the device gets disconnected after we've finished
 781                  * cancelling URBs, which might not be an error...
 782                  */
 783         } else {
 784                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 785                                 ep_ctx->deq);
 786         }
 787
 788         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 789         ring_ep_doorbell(xhci, slot_id, ep_index);
 790 }
 791
 792 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 793                 struct xhci_event_cmd *event,
 794                 union xhci_trb *trb)
 795 {
 796         int slot_id;
 797         unsigned int ep_index;
 798         struct xhci_ring *ep_ring;
 799
 800         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 801         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 802         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
 803         /* This command will only fail if the endpoint wasn't halted,
 804          * but we don't care.
 805          */
 806         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 807                         (unsigned int) GET_COMP_CODE(event->status));
 808
 809         /* HW with the reset endpoint quirk needs to have a configure endpoint
 810          * command complete before the endpoint can be used.  Queue that here
 811          * because the HW can't handle two commands being queued in a row.
 812          */
 813         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 814                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 815                 xhci_queue_configure_endpoint(xhci,
 816                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 817                                 false);
 818                 xhci_ring_cmd_db(xhci);
 819         } else {
 820                 /* Clear our internal halted state and restart the ring */
 821                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 822                 ring_ep_doorbell(xhci, slot_id, ep_index);
 823         }
 824 }
 825
 826 /* Check to see if a command in the device's command queue matches this one.
 827  * Signal the completion or free the command, and return 1.  Return 0 if the
 828  * completed command isn't at the head of the command list.
 829  */
 830 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
 831                 struct xhci_virt_device *virt_dev,
 832                 struct xhci_event_cmd *event)
 833 {
 834         struct xhci_command *command;
 835
 836         if (list_empty(&virt_dev->cmd_list))
 837                 return 0;
 838
 839         command = list_entry(virt_dev->cmd_list.next,
 840                         struct xhci_command, cmd_list);
 841         if (xhci->cmd_ring->dequeue != command->command_trb)
 842                 return 0;
 843
 844         command->status =
 845                 GET_COMP_CODE(event->status);
 846         list_del(&command->cmd_list);
 847         if (command->completion)
 848                 complete(command->completion);
 849         else
 850                 xhci_free_command(xhci, command);
 851         return 1;
 852 }
 853
 854 static void handle_cmd_completion(struct xhci_hcd *xhci,
 855                 struct xhci_event_cmd *event)
 856 {
 857         int slot_id = TRB_TO_SLOT_ID(event->flags);
 858         u64 cmd_dma;
 859         dma_addr_t cmd_dequeue_dma;
 860         struct xhci_input_control_ctx *ctrl_ctx;
 861         struct xhci_virt_device *virt_dev;
 862         unsigned int ep_index;
 863         struct xhci_ring *ep_ring;
 864         unsigned int ep_state;
 865
 866         cmd_dma = event->cmd_trb;
 867         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 868                         xhci->cmd_ring->dequeue);
 869         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 870         if (cmd_dequeue_dma == 0) {
 871                 xhci->error_bitmask |= 1 << 4;
 872                 return;
 873         }
 874         /* Does the DMA address match our internal dequeue pointer address? */
 875         if (cmd_dma != (u64) cmd_dequeue_dma) {
 876                 xhci->error_bitmask |= 1 << 5;
 877                 return;
 878         }
 879         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 880         case TRB_TYPE(TRB_ENABLE_SLOT):
 881                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 882                         xhci->slot_id = slot_id;
 883                 else
 884                         xhci->slot_id = 0;
 885                 complete(&xhci->addr_dev);
 886                 break;
 887         case TRB_TYPE(TRB_DISABLE_SLOT):
 888                 if (xhci->devs[slot_id])
 889                         xhci_free_virt_device(xhci, slot_id);
 890                 break;
 891         case TRB_TYPE(TRB_CONFIG_EP):
 892                 virt_dev = xhci->devs[slot_id];
 893                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 894                         break;
 895                 /*
 896                  * Configure endpoint commands can come from the USB core
 897                  * configuration or alt setting changes, or because the HW
 898                  * needed an extra configure endpoint command after a reset
 899                  * endpoint command.  In the latter case, the xHCI driver is
 900                  * not waiting on the configure endpoint command.
 901                  */
 902                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
 903                                 virt_dev->in_ctx);
 904                 /* Input ctx add_flags are the endpoint index plus one */
 905                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
 906                 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
 907                 if (!ep_ring) {
 908                         /* This must have been an initial configure endpoint */
 909                         xhci->devs[slot_id]->cmd_status =
 910                                 GET_COMP_CODE(event->status);
 911                         complete(&xhci->devs[slot_id]->cmd_completion);
 912                         break;
 913                 }
 914                 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
 915                 xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
 916                                 "state = %d\n", ep_index, ep_state);
 917                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
 918                                 ep_state & EP_HALTED) {
 919                         /* Clear our internal halted state and restart ring */
 920                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
 921                                 ~EP_HALTED;
 922                         ring_ep_doorbell(xhci, slot_id, ep_index);
 923                 } else {
 924                         xhci->devs[slot_id]->cmd_status =
 925                                 GET_COMP_CODE(event->status);
 926                         complete(&xhci->devs[slot_id]->cmd_completion);
 927                 }
 928                 break;
 929         case TRB_TYPE(TRB_EVAL_CONTEXT):
 930                 virt_dev = xhci->devs[slot_id];
 931                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 932                         break;
 933                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 934                 complete(&xhci->devs[slot_id]->cmd_completion);
 935                 break;
 936         case TRB_TYPE(TRB_ADDR_DEV):
 937                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 938                 complete(&xhci->addr_dev);
 939                 break;
 940         case TRB_TYPE(TRB_STOP_RING):
 941                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
 942                 break;
 943         case TRB_TYPE(TRB_SET_DEQ):
 944                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
 945                 break;
 946         case TRB_TYPE(TRB_CMD_NOOP):
 947                 ++xhci->noops_handled;
 948                 break;
 949         case TRB_TYPE(TRB_RESET_EP):
 950                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
 951                 break;
 952         default:
 953                 /* Skip over unknown commands on the event ring */
 954                 xhci->error_bitmask |= 1 << 6;
 955                 break;
 956         }
 957         inc_deq(xhci, xhci->cmd_ring, false);
 958 }
 959
 960 static void handle_port_status(struct xhci_hcd *xhci,
 961                 union xhci_trb *event)
 962 {
 963         u32 port_id;
 964
 965         /* Port status change events always have a successful completion code */
 966         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
 967                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
 968                 xhci->error_bitmask |= 1 << 8;
 969         }
 970         /* FIXME: core doesn't care about all port link state changes yet */
 971         port_id = GET_PORT_ID(event->generic.field[0]);
 972         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
 973
 974         /* Update event ring dequeue pointer before dropping the lock */
 975         inc_deq(xhci, xhci->event_ring, true);
 976         xhci_set_hc_event_deq(xhci);
 977
 978         spin_unlock(&xhci->lock);
 979         /* Pass this up to the core */
 980         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
 981         spin_lock(&xhci->lock);
 982 }
 983
 984 /*
 985  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
 986  * at end_trb, which may be in another segment.  If the suspect DMA address is a
 987  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
 988  * returns 0.
 989  */
 990 static struct xhci_segment *trb_in_td(
 991                 struct xhci_segment *start_seg,
 992                 union xhci_trb  *start_trb,
 993                 union xhci_trb  *end_trb,
 994                 dma_addr_t      suspect_dma)
 995 {
 996         dma_addr_t start_dma;
 997         dma_addr_t end_seg_dma;
 998         dma_addr_t end_trb_dma;
 999         struct xhci_segment *cur_seg;
1000
1001         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1002         cur_seg = start_seg;
1003
1004         do {
1005                 if (start_dma == 0)
1006                         return 0;
1007                 /* We may get an event for a Link TRB in the middle of a TD */
1008                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1009                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1010                 /* If the end TRB isn't in this segment, this is set to 0 */
1011                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1012
1013                 if (end_trb_dma > 0) {
1014                         /* The end TRB is in this segment, so suspect should be here */
1015                         if (start_dma <= end_trb_dma) {
1016                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1017                                         return cur_seg;
1018                         } else {
1019                                 /* Case for one segment with
1020                                  * a TD wrapped around to the top
1021                                  */
1022                                 if ((suspect_dma >= start_dma &&
1023                                                         suspect_dma <= end_seg_dma) ||
1024                                                 (suspect_dma >= cur_seg->dma &&
1025                                                  suspect_dma <= end_trb_dma))
1026                                         return cur_seg;
1027                         }
1028                         return 0;
1029                 } else {
1030                         /* Might still be somewhere in this segment */
1031                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1032                                 return cur_seg;
1033                 }
1034                 cur_seg = cur_seg->next;
1035                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1036         } while (cur_seg != start_seg);
1037
1038         return 0;
1039 }
1040
1041 /*
1042  * If this function returns an error condition, it means it got a Transfer
1043  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1044  * At this point, the host controller is probably hosed and should be reset.
1045  */
1046 static int handle_tx_event(struct xhci_hcd *xhci,
1047                 struct xhci_transfer_event *event)
1048 {
1049         struct xhci_virt_device *xdev;
1050         struct xhci_virt_ep *ep;
1051         struct xhci_ring *ep_ring;
1052         unsigned int slot_id;
1053         int ep_index;
1054         struct xhci_td *td = 0;
1055         dma_addr_t event_dma;
1056         struct xhci_segment *event_seg;
1057         union xhci_trb *event_trb;
1058         struct urb *urb = 0;
1059         int status = -EINPROGRESS;
1060         struct xhci_ep_ctx *ep_ctx;
1061         u32 trb_comp_code;
1062
1063         xhci_dbg(xhci, "In %s\n", __func__);
1064         slot_id = TRB_TO_SLOT_ID(event->flags);
1065         xdev = xhci->devs[slot_id];
1066         if (!xdev) {
1067                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1068                 return -ENODEV;
1069         }
1070
1071         /* Endpoint ID is 1 based, our index is zero based */
1072         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1073         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1074         ep = &xdev->eps[ep_index];
1075         ep_ring = ep->ring;
1076         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1077         if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1078                 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
1079                 return -ENODEV;
1080         }
1081
1082         event_dma = event->buffer;
1083         /* This TRB should be in the TD at the head of this ring's TD list */
1084         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
1085         if (list_empty(&ep_ring->td_list)) {
1086                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1087                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1088                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1089                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1090                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1091                 urb = NULL;
1092                 goto cleanup;
1093         }
1094         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
1095         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1096
1097         /* Is this a TRB in the currently executing TD? */
1098         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
1099         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1100                         td->last_trb, event_dma);
1101         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
1102         if (!event_seg) {
1103                 /* HC is busted, give up! */
1104                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1105                 return -ESHUTDOWN;
1106         }
1107         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
1108         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1109                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1110         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
1111                         lower_32_bits(event->buffer));
1112         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1113                         upper_32_bits(event->buffer));
1114         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1115                         (unsigned int) event->transfer_len);
1116         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1117                         (unsigned int) event->flags);
1118
1119         /* Look for common error cases */
1120         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1121         switch (trb_comp_code) {
1122         /* Skip codes that require special handling depending on
1123          * transfer type
1124          */
1125         case COMP_SUCCESS:
1126         case COMP_SHORT_TX:
1127                 break;
1128         case COMP_STOP:
1129                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1130                 break;
1131         case COMP_STOP_INVAL:
1132                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1133                 break;
1134         case COMP_STALL:
1135                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1136                 ep->ep_state |= EP_HALTED;
1137                 status = -EPIPE;
1138                 break;
1139         case COMP_TRB_ERR:
1140                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1141                 status = -EILSEQ;
1142                 break;
1143         case COMP_TX_ERR:
1144                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1145                 status = -EPROTO;
1146                 break;
1147         case COMP_BABBLE:
1148                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1149                 status = -EOVERFLOW;
1150                 break;
1151         case COMP_DB_ERR:
1152                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1153                 status = -ENOSR;
1154                 break;
1155         default:
1156                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1157                 urb = NULL;
1158                 goto cleanup;
1159         }
1160         /* Now update the urb's actual_length and give back to the core */
1161         /* Was this a control transfer? */
1162         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1163                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1164                 switch (trb_comp_code) {
1165                 case COMP_SUCCESS:
1166                         if (event_trb == ep_ring->dequeue) {
1167                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1168                                 status = -ESHUTDOWN;
1169                         } else if (event_trb != td->last_trb) {
1170                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1171                                 status = -ESHUTDOWN;
1172                         } else {
1173                                 xhci_dbg(xhci, "Successful control transfer!\n");
1174                                 status = 0;
1175                         }
1176                         break;
1177                 case COMP_SHORT_TX:
1178                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
1179                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1180                                 status = -EREMOTEIO;
1181                         else
1182                                 status = 0;
1183                         break;
1184                 case COMP_BABBLE:
1185                         /* The 0.96 spec says a babbling control endpoint
1186                          * is not halted. The 0.96 spec says it is.  Some HW
1187                          * claims to be 0.95 compliant, but it halts the control
1188                          * endpoint anyway.  Check if a babble halted the
1189                          * endpoint.
1190                          */
1191                         if (ep_ctx->ep_info != EP_STATE_HALTED)
1192                                 break;
1193                         /* else fall through */
1194                 case COMP_STALL:
1195                         /* Did we transfer part of the data (middle) phase? */
1196                         if (event_trb != ep_ring->dequeue &&
1197                                         event_trb != td->last_trb)
1198                                 td->urb->actual_length =
1199                                         td->urb->transfer_buffer_length
1200                                         - TRB_LEN(event->transfer_len);
1201                         else
1202                                 td->urb->actual_length = 0;
1203
1204                         ep->stopped_td = td;
1205                         ep->stopped_trb = event_trb;
1206                         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1207                         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1208                         xhci_ring_cmd_db(xhci);
1209                         goto td_cleanup;
1210                 default:
1211                         /* Others already handled above */
1212                         break;
1213                 }
1214                 /*
1215                  * Did we transfer any data, despite the errors that might have
1216                  * happened?  I.e. did we get past the setup stage?
1217                  */
1218                 if (event_trb != ep_ring->dequeue) {
1219                         /* The event was for the status stage */
1220                         if (event_trb == td->last_trb) {
1221                                 if (td->urb->actual_length != 0) {
1222                                         /* Don't overwrite a previously set error code */
1223                                         if ((status == -EINPROGRESS ||
1224                                                                 status == 0) &&
1225                                                         (td->urb->transfer_flags
1226                                                          & URB_SHORT_NOT_OK))
1227                                                 /* Did we already see a short data stage? */
1228                                                 status = -EREMOTEIO;
1229                                 } else {
1230                                         td->urb->actual_length =
1231                                                 td->urb->transfer_buffer_length;
1232                                 }
1233                         } else {
1234                         /* Maybe the event was for the data stage? */
1235                                 if (trb_comp_code != COMP_STOP_INVAL) {
1236                                         /* We didn't stop on a link TRB in the middle */
1237                                         td->urb->actual_length =
1238                                                 td->urb->transfer_buffer_length -
1239                                                 TRB_LEN(event->transfer_len);
1240                                         xhci_dbg(xhci, "Waiting for status stage event\n");
1241                                         urb = NULL;
1242                                         goto cleanup;
1243                                 }
1244                         }
1245                 }
1246         } else {
1247                 switch (trb_comp_code) {
1248                 case COMP_SUCCESS:
1249                         /* Double check that the HW transferred everything. */
1250                         if (event_trb != td->last_trb) {
1251                                 xhci_warn(xhci, "WARN Successful completion "
1252                                                 "on short TX\n");
1253                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1254                                         status = -EREMOTEIO;
1255                                 else
1256                                         status = 0;
1257                         } else {
1258                                 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1259                                         xhci_dbg(xhci, "Successful bulk "
1260                                                         "transfer!\n");
1261                                 else
1262                                         xhci_dbg(xhci, "Successful interrupt "
1263                                                         "transfer!\n");
1264                                 status = 0;
1265                         }
1266                         break;
1267                 case COMP_SHORT_TX:
1268                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1269                                 status = -EREMOTEIO;
1270                         else
1271                                 status = 0;
1272                         break;
1273                 default:
1274                         /* Others already handled above */
1275                         break;
1276                 }
1277                 dev_dbg(&td->urb->dev->dev,
1278                                 "ep %#x - asked for %d bytes, "
1279                                 "%d bytes untransferred\n",
1280                                 td->urb->ep->desc.bEndpointAddress,
1281                                 td->urb->transfer_buffer_length,
1282                                 TRB_LEN(event->transfer_len));
1283                 /* Fast path - was this the last TRB in the TD for this URB? */
1284                 if (event_trb == td->last_trb) {
1285                         if (TRB_LEN(event->transfer_len) != 0) {
1286                                 td->urb->actual_length =
1287                                         td->urb->transfer_buffer_length -
1288                                         TRB_LEN(event->transfer_len);
1289                                 if (td->urb->transfer_buffer_length <
1290                                                 td->urb->actual_length) {
1291                                         xhci_warn(xhci, "HC gave bad length "
1292                                                         "of %d bytes left\n",
1293                                                         TRB_LEN(event->transfer_len));
1294                                         td->urb->actual_length = 0;
1295                                         if (td->urb->transfer_flags &
1296                                                         URB_SHORT_NOT_OK)
1297                                                 status = -EREMOTEIO;
1298                                         else
1299                                                 status = 0;
1300                                 }
1301                                 /* Don't overwrite a previously set error code */
1302                                 if (status == -EINPROGRESS) {
1303                                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1304                                                 status = -EREMOTEIO;
1305                                         else
1306                                                 status = 0;
1307                                 }
1308                         } else {
1309                                 td->urb->actual_length = td->urb->transfer_buffer_length;
1310                                 /* Ignore a short packet completion if the
1311                                  * untransferred length was zero.
1312                                  */
1313                                 if (status == -EREMOTEIO)
1314                                         status = 0;
1315                         }
1316                 } else {
1317                         /* Slow path - walk the list, starting from the dequeue
1318                          * pointer, to get the actual length transferred.
1319                          */
1320                         union xhci_trb *cur_trb;
1321                         struct xhci_segment *cur_seg;
1322
1323                         td->urb->actual_length = 0;
1324                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1325                                         cur_trb != event_trb;
1326                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1327                                 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1328                                                 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1329                                         td->urb->actual_length +=
1330                                                 TRB_LEN(cur_trb->generic.field[2]);
1331                         }
1332                         /* If the ring didn't stop on a Link or No-op TRB, add
1333                          * in the actual bytes transferred from the Normal TRB
1334                          */
1335                         if (trb_comp_code != COMP_STOP_INVAL)
1336                                 td->urb->actual_length +=
1337                                         TRB_LEN(cur_trb->generic.field[2]) -
1338                                         TRB_LEN(event->transfer_len);
1339                 }
1340         }
1341         if (trb_comp_code == COMP_STOP_INVAL ||
1342                         trb_comp_code == COMP_STOP) {
1343                 /* The Endpoint Stop Command completion will take care of any
1344                  * stopped TDs.  A stopped TD may be restarted, so don't update
1345                  * the ring dequeue pointer or take this TD off any lists yet.
1346                  */
1347                 ep->stopped_td = td;
1348                 ep->stopped_trb = event_trb;
1349         } else {
1350                 if (trb_comp_code == COMP_STALL ||
1351                                 trb_comp_code == COMP_BABBLE) {
1352                         /* The transfer is completed from the driver's
1353                          * perspective, but we need to issue a set dequeue
1354                          * command for this stalled endpoint to move the dequeue
1355                          * pointer past the TD.  We can't do that here because
1356                          * the halt condition must be cleared first.
1357                          */
1358                         ep->stopped_td = td;
1359                         ep->stopped_trb = event_trb;
1360                 } else {
1361                         /* Update ring dequeue pointer */
1362                         while (ep_ring->dequeue != td->last_trb)
1363                                 inc_deq(xhci, ep_ring, false);
1364                         inc_deq(xhci, ep_ring, false);
1365                 }
1366
1367 td_cleanup:
1368                 /* Clean up the endpoint's TD list */
1369                 urb = td->urb;
1370                 /* Do one last check of the actual transfer length.
1371                  * If the host controller said we transferred more data than
1372                  * the buffer length, urb->actual_length will be a very big
1373                  * number (since it's unsigned).  Play it safe and say we didn't
1374                  * transfer anything.
1375                  */
1376                 if (urb->actual_length > urb->transfer_buffer_length) {
1377                         xhci_warn(xhci, "URB transfer length is wrong, "
1378                                         "xHC issue? req. len = %u, "
1379                                         "act. len = %u\n",
1380                                         urb->transfer_buffer_length,
1381                                         urb->actual_length);
1382                         urb->actual_length = 0;
1383                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1384                                 status = -EREMOTEIO;
1385                         else
1386                                 status = 0;
1387                 }
1388                 list_del(&td->td_list);
1389                 /* Was this TD slated to be cancelled but completed anyway? */
1390                 if (!list_empty(&td->cancelled_td_list))
1391                         list_del(&td->cancelled_td_list);
1392
1393                 /* Leave the TD around for the reset endpoint function to use
1394                  * (but only if it's not a control endpoint, since we already
1395                  * queued the Set TR dequeue pointer command for stalled
1396                  * control endpoints).
1397                  */
1398                 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1399                         (trb_comp_code != COMP_STALL &&
1400                                 trb_comp_code != COMP_BABBLE)) {
1401                         kfree(td);
1402                 }
1403                 urb->hcpriv = NULL;
1404         }
1405 cleanup:
1406         inc_deq(xhci, xhci->event_ring, true);
1407         xhci_set_hc_event_deq(xhci);
1408
1409         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1410         if (urb) {
1411                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1412                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1413                                 urb, urb->actual_length, status);
1414                 spin_unlock(&xhci->lock);
1415                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1416                 spin_lock(&xhci->lock);
1417         }
1418         return 0;
1419 }
1420
1421 /*
1422  * This function handles all OS-owned events on the event ring.  It may drop
1423  * xhci->lock between event processing (e.g. to pass up port status changes).
1424  */
1425 void xhci_handle_event(struct xhci_hcd *xhci)
1426 {
1427         union xhci_trb *event;
1428         int update_ptrs = 1;
1429         int ret;
1430
1431         xhci_dbg(xhci, "In %s\n", __func__);
1432         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1433                 xhci->error_bitmask |= 1 << 1;
1434                 return;
1435         }
1436
1437         event = xhci->event_ring->dequeue;
1438         /* Does the HC or OS own the TRB? */
1439         if ((event->event_cmd.flags & TRB_CYCLE) !=
1440                         xhci->event_ring->cycle_state) {
1441                 xhci->error_bitmask |= 1 << 2;
1442                 return;
1443         }
1444         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1445
1446         /* FIXME: Handle more event types. */
1447         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1448         case TRB_TYPE(TRB_COMPLETION):
1449                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1450                 handle_cmd_completion(xhci, &event->event_cmd);
1451                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1452                 break;
1453         case TRB_TYPE(TRB_PORT_STATUS):
1454                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1455                 handle_port_status(xhci, event);
1456                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1457                 update_ptrs = 0;
1458                 break;
1459         case TRB_TYPE(TRB_TRANSFER):
1460                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1461                 ret = handle_tx_event(xhci, &event->trans_event);
1462                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1463                 if (ret < 0)
1464                         xhci->error_bitmask |= 1 << 9;
1465                 else
1466                         update_ptrs = 0;
1467                 break;
1468         default:
1469                 xhci->error_bitmask |= 1 << 3;
1470         }
1471         /* Any of the above functions may drop and re-acquire the lock, so check
1472          * to make sure a watchdog timer didn't mark the host as non-responsive.
1473          */
1474         if (xhci->xhc_state & XHCI_STATE_DYING) {
1475                 xhci_dbg(xhci, "xHCI host dying, returning from "
1476                                 "event handler.\n");
1477                 return;
1478         }
1479
1480         if (update_ptrs) {
1481                 /* Update SW and HC event ring dequeue pointer */
1482                 inc_deq(xhci, xhci->event_ring, true);
1483                 xhci_set_hc_event_deq(xhci);
1484         }
1485         /* Are there more items on the event ring? */
1486         xhci_handle_event(xhci);
1487 }
1488
1489 /****           Endpoint Ring Operations        ****/
1490
1491 /*
1492  * Generic function for queueing a TRB on a ring.
1493  * The caller must have checked to make sure there's room on the ring.
1494  */
1495 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1496                 bool consumer,
1497                 u32 field1, u32 field2, u32 field3, u32 field4)
1498 {
1499         struct xhci_generic_trb *trb;
1500
1501         trb = &ring->enqueue->generic;
1502         trb->field[0] = field1;
1503         trb->field[1] = field2;
1504         trb->field[2] = field3;
1505         trb->field[3] = field4;
1506         inc_enq(xhci, ring, consumer);
1507 }
1508
1509 /*
1510  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1511  * FIXME allocate segments if the ring is full.
1512  */
1513 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1514                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1515 {
1516         /* Make sure the endpoint has been added to xHC schedule */
1517         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1518         switch (ep_state) {
1519         case EP_STATE_DISABLED:
1520                 /*
1521                  * USB core changed config/interfaces without notifying us,
1522                  * or hardware is reporting the wrong state.
1523                  */
1524                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1525                 return -ENOENT;
1526         case EP_STATE_ERROR:
1527                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1528                 /* FIXME event handling code for error needs to clear it */
1529                 /* XXX not sure if this should be -ENOENT or not */
1530                 return -EINVAL;
1531         case EP_STATE_HALTED:
1532                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1533         case EP_STATE_STOPPED:
1534         case EP_STATE_RUNNING:
1535                 break;
1536         default:
1537                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1538                 /*
1539                  * FIXME issue Configure Endpoint command to try to get the HC
1540                  * back into a known state.
1541                  */
1542                 return -EINVAL;
1543         }
1544         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1545                 /* FIXME allocate more room */
1546                 xhci_err(xhci, "ERROR no room on ep ring\n");
1547                 return -ENOMEM;
1548         }
1549         return 0;
1550 }
1551
1552 static int prepare_transfer(struct xhci_hcd *xhci,
1553                 struct xhci_virt_device *xdev,
1554                 unsigned int ep_index,
1555                 unsigned int num_trbs,
1556                 struct urb *urb,
1557                 struct xhci_td **td,
1558                 gfp_t mem_flags)
1559 {
1560         int ret;
1561         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1562         ret = prepare_ring(xhci, xdev->eps[ep_index].ring,
1563                         ep_ctx->ep_info & EP_STATE_MASK,
1564                         num_trbs, mem_flags);
1565         if (ret)
1566                 return ret;
1567         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1568         if (!*td)
1569                 return -ENOMEM;
1570         INIT_LIST_HEAD(&(*td)->td_list);
1571         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1572
1573         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1574         if (unlikely(ret)) {
1575                 kfree(*td);
1576                 return ret;
1577         }
1578
1579         (*td)->urb = urb;
1580         urb->hcpriv = (void *) (*td);
1581         /* Add this TD to the tail of the endpoint ring's TD list */
1582         list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list);
1583         (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg;
1584         (*td)->first_trb = xdev->eps[ep_index].ring->enqueue;
1585
1586         return 0;
1587 }
1588
1589 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1590 {
1591         int num_sgs, num_trbs, running_total, temp, i;
1592         struct scatterlist *sg;
1593
1594         sg = NULL;
1595         num_sgs = urb->num_sgs;
1596         temp = urb->transfer_buffer_length;
1597
1598         xhci_dbg(xhci, "count sg list trbs: \n");
1599         num_trbs = 0;
1600         for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1601                 unsigned int previous_total_trbs = num_trbs;
1602                 unsigned int len = sg_dma_len(sg);
1603
1604                 /* Scatter gather list entries may cross 64KB boundaries */
1605                 running_total = TRB_MAX_BUFF_SIZE -
1606                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1607                 if (running_total != 0)
1608                         num_trbs++;
1609
1610                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1611                 while (running_total < sg_dma_len(sg)) {
1612                         num_trbs++;
1613                         running_total += TRB_MAX_BUFF_SIZE;
1614                 }
1615                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1616                                 i, (unsigned long long)sg_dma_address(sg),
1617                                 len, len, num_trbs - previous_total_trbs);
1618
1619                 len = min_t(int, len, temp);
1620                 temp -= len;
1621                 if (temp == 0)
1622                         break;
1623         }
1624         xhci_dbg(xhci, "\n");
1625         if (!in_interrupt())
1626                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1627                                 urb->ep->desc.bEndpointAddress,
1628                                 urb->transfer_buffer_length,
1629                                 num_trbs);
1630         return num_trbs;
1631 }
1632
1633 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1634 {
1635         if (num_trbs != 0)
1636                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1637                                 "TRBs, %d left\n", __func__,
1638                                 urb->ep->desc.bEndpointAddress, num_trbs);
1639         if (running_total != urb->transfer_buffer_length)
1640                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1641                                 "queued %#x (%d), asked for %#x (%d)\n",
1642                                 __func__,
1643                                 urb->ep->desc.bEndpointAddress,
1644                                 running_total, running_total,
1645                                 urb->transfer_buffer_length,
1646                                 urb->transfer_buffer_length);
1647 }
1648
1649 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1650                 unsigned int ep_index, int start_cycle,
1651                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1652 {
1653         /*
1654          * Pass all the TRBs to the hardware at once and make sure this write
1655          * isn't reordered.
1656          */
1657         wmb();
1658         start_trb->field[3] |= start_cycle;
1659         ring_ep_doorbell(xhci, slot_id, ep_index);
1660 }
1661
1662 /*
1663  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
1664  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
1665  * (comprised of sg list entries) can take several service intervals to
1666  * transmit.
1667  */
1668 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1669                 struct urb *urb, int slot_id, unsigned int ep_index)
1670 {
1671         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1672                         xhci->devs[slot_id]->out_ctx, ep_index);
1673         int xhci_interval;
1674         int ep_interval;
1675
1676         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1677         ep_interval = urb->interval;
1678         /* Convert to microframes */
1679         if (urb->dev->speed == USB_SPEED_LOW ||
1680                         urb->dev->speed == USB_SPEED_FULL)
1681                 ep_interval *= 8;
1682         /* FIXME change this to a warning and a suggestion to use the new API
1683          * to set the polling interval (once the API is added).
1684          */
1685         if (xhci_interval != ep_interval) {
1686                 if (!printk_ratelimit())
1687                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
1688                                         " (%d microframe%s) than xHCI "
1689                                         "(%d microframe%s)\n",
1690                                         ep_interval,
1691                                         ep_interval == 1 ? "" : "s",
1692                                         xhci_interval,
1693                                         xhci_interval == 1 ? "" : "s");
1694                 urb->interval = xhci_interval;
1695                 /* Convert back to frames for LS/FS devices */
1696                 if (urb->dev->speed == USB_SPEED_LOW ||
1697                                 urb->dev->speed == USB_SPEED_FULL)
1698                         urb->interval /= 8;
1699         }
1700         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1701 }
1702
1703 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1704                 struct urb *urb, int slot_id, unsigned int ep_index)
1705 {
1706         struct xhci_ring *ep_ring;
1707         unsigned int num_trbs;
1708         struct xhci_td *td;
1709         struct scatterlist *sg;
1710         int num_sgs;
1711         int trb_buff_len, this_sg_len, running_total;
1712         bool first_trb;
1713         u64 addr;
1714
1715         struct xhci_generic_trb *start_trb;
1716         int start_cycle;
1717
1718         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1719         num_trbs = count_sg_trbs_needed(xhci, urb);
1720         num_sgs = urb->num_sgs;
1721
1722         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1723                         ep_index, num_trbs, urb, &td, mem_flags);
1724         if (trb_buff_len < 0)
1725                 return trb_buff_len;
1726         /*
1727          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1728          * until we've finished creating all the other TRBs.  The ring's cycle
1729          * state may change as we enqueue the other TRBs, so save it too.
1730          */
1731         start_trb = &ep_ring->enqueue->generic;
1732         start_cycle = ep_ring->cycle_state;
1733
1734         running_total = 0;
1735         /*
1736          * How much data is in the first TRB?
1737          *
1738          * There are three forces at work for TRB buffer pointers and lengths:
1739          * 1. We don't want to walk off the end of this sg-list entry buffer.
1740          * 2. The transfer length that the driver requested may be smaller than
1741          *    the amount of memory allocated for this scatter-gather list.
1742          * 3. TRBs buffers can't cross 64KB boundaries.
1743          */
1744         sg = urb->sg->sg;
1745         addr = (u64) sg_dma_address(sg);
1746         this_sg_len = sg_dma_len(sg);
1747         trb_buff_len = TRB_MAX_BUFF_SIZE -
1748                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1749         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1750         if (trb_buff_len > urb->transfer_buffer_length)
1751                 trb_buff_len = urb->transfer_buffer_length;
1752         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1753                         trb_buff_len);
1754
1755         first_trb = true;
1756         /* Queue the first TRB, even if it's zero-length */
1757         do {
1758                 u32 field = 0;
1759                 u32 length_field = 0;
1760
1761                 /* Don't change the cycle bit of the first TRB until later */
1762                 if (first_trb)
1763                         first_trb = false;
1764                 else
1765                         field |= ep_ring->cycle_state;
1766
1767                 /* Chain all the TRBs together; clear the chain bit in the last
1768                  * TRB to indicate it's the last TRB in the chain.
1769                  */
1770                 if (num_trbs > 1) {
1771                         field |= TRB_CHAIN;
1772                 } else {
1773                         /* FIXME - add check for ZERO_PACKET flag before this */
1774                         td->last_trb = ep_ring->enqueue;
1775                         field |= TRB_IOC;
1776                 }
1777                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1778                                 "64KB boundary at %#x, end dma = %#x\n",
1779                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
1780                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1781                                 (unsigned int) addr + trb_buff_len);
1782                 if (TRB_MAX_BUFF_SIZE -
1783                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1784                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1785                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1786                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1787                                         (unsigned int) addr + trb_buff_len);
1788                 }
1789                 length_field = TRB_LEN(trb_buff_len) |
1790                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1791                         TRB_INTR_TARGET(0);
1792                 queue_trb(xhci, ep_ring, false,
1793                                 lower_32_bits(addr),
1794                                 upper_32_bits(addr),
1795                                 length_field,
1796                                 /* We always want to know if the TRB was short,
1797                                  * or we won't get an event when it completes.
1798                                  * (Unless we use event data TRBs, which are a
1799                                  * waste of space and HC resources.)
1800                                  */
1801                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1802                 --num_trbs;
1803                 running_total += trb_buff_len;
1804
1805                 /* Calculate length for next transfer --
1806                  * Are we done queueing all the TRBs for this sg entry?
1807                  */
1808                 this_sg_len -= trb_buff_len;
1809                 if (this_sg_len == 0) {
1810                         --num_sgs;
1811                         if (num_sgs == 0)
1812                                 break;
1813                         sg = sg_next(sg);
1814                         addr = (u64) sg_dma_address(sg);
1815                         this_sg_len = sg_dma_len(sg);
1816                 } else {
1817                         addr += trb_buff_len;
1818                 }
1819
1820                 trb_buff_len = TRB_MAX_BUFF_SIZE -
1821                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1822                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1823                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1824                         trb_buff_len =
1825                                 urb->transfer_buffer_length - running_total;
1826         } while (running_total < urb->transfer_buffer_length);
1827
1828         check_trb_math(urb, num_trbs, running_total);
1829         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1830         return 0;
1831 }
1832
1833 /* This is very similar to what ehci-q.c qtd_fill() does */
1834 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1835                 struct urb *urb, int slot_id, unsigned int ep_index)
1836 {
1837         struct xhci_ring *ep_ring;
1838         struct xhci_td *td;
1839         int num_trbs;
1840         struct xhci_generic_trb *start_trb;
1841         bool first_trb;
1842         int start_cycle;
1843         u32 field, length_field;
1844
1845         int running_total, trb_buff_len, ret;
1846         u64 addr;
1847
1848         if (urb->sg)
1849                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1850
1851         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1852
1853         num_trbs = 0;
1854         /* How much data is (potentially) left before the 64KB boundary? */
1855         running_total = TRB_MAX_BUFF_SIZE -
1856                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1857
1858         /* If there's some data on this 64KB chunk, or we have to send a
1859          * zero-length transfer, we need at least one TRB
1860          */
1861         if (running_total != 0 || urb->transfer_buffer_length == 0)
1862                 num_trbs++;
1863         /* How many more 64KB chunks to transfer, how many more TRBs? */
1864         while (running_total < urb->transfer_buffer_length) {
1865                 num_trbs++;
1866                 running_total += TRB_MAX_BUFF_SIZE;
1867         }
1868         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1869
1870         if (!in_interrupt())
1871                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1872                                 urb->ep->desc.bEndpointAddress,
1873                                 urb->transfer_buffer_length,
1874                                 urb->transfer_buffer_length,
1875                                 (unsigned long long)urb->transfer_dma,
1876                                 num_trbs);
1877
1878         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1879                         num_trbs, urb, &td, mem_flags);
1880         if (ret < 0)
1881                 return ret;
1882
1883         /*
1884          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1885          * until we've finished creating all the other TRBs.  The ring's cycle
1886          * state may change as we enqueue the other TRBs, so save it too.
1887          */
1888         start_trb = &ep_ring->enqueue->generic;
1889         start_cycle = ep_ring->cycle_state;
1890
1891         running_total = 0;
1892         /* How much data is in the first TRB? */
1893         addr = (u64) urb->transfer_dma;
1894         trb_buff_len = TRB_MAX_BUFF_SIZE -
1895                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1896         if (urb->transfer_buffer_length < trb_buff_len)
1897                 trb_buff_len = urb->transfer_buffer_length;
1898
1899         first_trb = true;
1900
1901         /* Queue the first TRB, even if it's zero-length */
1902         do {
1903                 field = 0;
1904
1905                 /* Don't change the cycle bit of the first TRB until later */
1906                 if (first_trb)
1907                         first_trb = false;
1908                 else
1909                         field |= ep_ring->cycle_state;
1910
1911                 /* Chain all the TRBs together; clear the chain bit in the last
1912                  * TRB to indicate it's the last TRB in the chain.
1913                  */
1914                 if (num_trbs > 1) {
1915                         field |= TRB_CHAIN;
1916                 } else {
1917                         /* FIXME - add check for ZERO_PACKET flag before this */
1918                         td->last_trb = ep_ring->enqueue;
1919                         field |= TRB_IOC;
1920                 }
1921                 length_field = TRB_LEN(trb_buff_len) |
1922                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1923                         TRB_INTR_TARGET(0);
1924                 queue_trb(xhci, ep_ring, false,
1925                                 lower_32_bits(addr),
1926                                 upper_32_bits(addr),
1927                                 length_field,
1928                                 /* We always want to know if the TRB was short,
1929                                  * or we won't get an event when it completes.
1930                                  * (Unless we use event data TRBs, which are a
1931                                  * waste of space and HC resources.)
1932                                  */
1933                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1934                 --num_trbs;
1935                 running_total += trb_buff_len;
1936
1937                 /* Calculate length for next transfer */
1938                 addr += trb_buff_len;
1939                 trb_buff_len = urb->transfer_buffer_length - running_total;
1940                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1941                         trb_buff_len = TRB_MAX_BUFF_SIZE;
1942         } while (running_total < urb->transfer_buffer_length);
1943
1944         check_trb_math(urb, num_trbs, running_total);
1945         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1946         return 0;
1947 }
1948
1949 /* Caller must have locked xhci->lock */
1950 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1951                 struct urb *urb, int slot_id, unsigned int ep_index)
1952 {
1953         struct xhci_ring *ep_ring;
1954         int num_trbs;
1955         int ret;
1956         struct usb_ctrlrequest *setup;
1957         struct xhci_generic_trb *start_trb;
1958         int start_cycle;
1959         u32 field, length_field;
1960         struct xhci_td *td;
1961
1962         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1963
1964         /*
1965          * Need to copy setup packet into setup TRB, so we can't use the setup
1966          * DMA address.
1967          */
1968         if (!urb->setup_packet)
1969                 return -EINVAL;
1970
1971         if (!in_interrupt())
1972                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1973                                 slot_id, ep_index);
1974         /* 1 TRB for setup, 1 for status */
1975         num_trbs = 2;
1976         /*
1977          * Don't need to check if we need additional event data and normal TRBs,
1978          * since data in control transfers will never get bigger than 16MB
1979          * XXX: can we get a buffer that crosses 64KB boundaries?
1980          */
1981         if (urb->transfer_buffer_length > 0)
1982                 num_trbs++;
1983         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1984                         urb, &td, mem_flags);
1985         if (ret < 0)
1986                 return ret;
1987
1988         /*
1989          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1990          * until we've finished creating all the other TRBs.  The ring's cycle
1991          * state may change as we enqueue the other TRBs, so save it too.
1992          */
1993         start_trb = &ep_ring->enqueue->generic;
1994         start_cycle = ep_ring->cycle_state;
1995
1996         /* Queue setup TRB - see section 6.4.1.2.1 */
1997         /* FIXME better way to translate setup_packet into two u32 fields? */
1998         setup = (struct usb_ctrlrequest *) urb->setup_packet;
1999         queue_trb(xhci, ep_ring, false,
2000                         /* FIXME endianness is probably going to bite my ass here. */
2001                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2002                         setup->wIndex | setup->wLength << 16,
2003                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2004                         /* Immediate data in pointer */
2005                         TRB_IDT | TRB_TYPE(TRB_SETUP));
2006
2007         /* If there's data, queue data TRBs */
2008         field = 0;
2009         length_field = TRB_LEN(urb->transfer_buffer_length) |
2010                 TD_REMAINDER(urb->transfer_buffer_length) |
2011                 TRB_INTR_TARGET(0);
2012         if (urb->transfer_buffer_length > 0) {
2013                 if (setup->bRequestType & USB_DIR_IN)
2014                         field |= TRB_DIR_IN;
2015                 queue_trb(xhci, ep_ring, false,
2016                                 lower_32_bits(urb->transfer_dma),
2017                                 upper_32_bits(urb->transfer_dma),
2018                                 length_field,
2019                                 /* Event on short tx */
2020                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2021         }
2022
2023         /* Save the DMA address of the last TRB in the TD */
2024         td->last_trb = ep_ring->enqueue;
2025
2026         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2027         /* If the device sent data, the status stage is an OUT transfer */
2028         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2029                 field = 0;
2030         else
2031                 field = TRB_DIR_IN;
2032         queue_trb(xhci, ep_ring, false,
2033                         0,
2034                         0,
2035                         TRB_INTR_TARGET(0),
2036                         /* Event on completion */
2037                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2038
2039         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2040         return 0;
2041 }
2042
2043 /****           Command Ring Operations         ****/
2044
2045 /* Generic function for queueing a command TRB on the command ring.
2046  * Check to make sure there's room on the command ring for one command TRB.
2047  * Also check that there's room reserved for commands that must not fail.
2048  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2049  * then only check for the number of reserved spots.
2050  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2051  * because the command event handler may want to resubmit a failed command.
2052  */
2053 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2054                 u32 field3, u32 field4, bool command_must_succeed)
2055 {
2056         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2057         if (!command_must_succeed)
2058                 reserved_trbs++;
2059
2060         if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
2061                 if (!in_interrupt())
2062                         xhci_err(xhci, "ERR: No room for command on command ring\n");
2063                 if (command_must_succeed)
2064                         xhci_err(xhci, "ERR: Reserved TRB counting for "
2065                                         "unfailable commands failed.\n");
2066                 return -ENOMEM;
2067         }
2068         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
2069                         field4 | xhci->cmd_ring->cycle_state);
2070         return 0;
2071 }
2072
2073 /* Queue a no-op command on the command ring */
2074 static int queue_cmd_noop(struct xhci_hcd *xhci)
2075 {
2076         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2077 }
2078
2079 /*
2080  * Place a no-op command on the command ring to test the command and
2081  * event ring.
2082  */
2083 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2084 {
2085         if (queue_cmd_noop(xhci) < 0)
2086                 return NULL;
2087         xhci->noops_submitted++;
2088         return xhci_ring_cmd_db;
2089 }
2090
2091 /* Queue a slot enable or disable request on the command ring */
2092 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2093 {
2094         return queue_command(xhci, 0, 0, 0,
2095                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2096 }
2097
2098 /* Queue an address device command TRB */
2099 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2100                 u32 slot_id)
2101 {
2102         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2103                         upper_32_bits(in_ctx_ptr), 0,
2104                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2105                         false);
2106 }
2107
2108 /* Queue a configure endpoint command TRB */
2109 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2110                 u32 slot_id, bool command_must_succeed)
2111 {
2112         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2113                         upper_32_bits(in_ctx_ptr), 0,
2114                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2115                         command_must_succeed);
2116 }
2117
2118 /* Queue an evaluate context command TRB */
2119 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2120                 u32 slot_id)
2121 {
2122         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2123                         upper_32_bits(in_ctx_ptr), 0,
2124                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2125                         false);
2126 }
2127
2128 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2129                 unsigned int ep_index)
2130 {
2131         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2132         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2133         u32 type = TRB_TYPE(TRB_STOP_RING);
2134
2135         return queue_command(xhci, 0, 0, 0,
2136                         trb_slot_id | trb_ep_index | type, false);
2137 }
2138
2139 /* Set Transfer Ring Dequeue Pointer command.
2140  * This should not be used for endpoints that have streams enabled.
2141  */
2142 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2143                 unsigned int ep_index, struct xhci_segment *deq_seg,
2144                 union xhci_trb *deq_ptr, u32 cycle_state)
2145 {
2146         dma_addr_t addr;
2147         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2148         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2149         u32 type = TRB_TYPE(TRB_SET_DEQ);
2150
2151         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2152         if (addr == 0) {
2153                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2154                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2155                                 deq_seg, deq_ptr);
2156                 return 0;
2157         }
2158         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2159                         upper_32_bits(addr), 0,
2160                         trb_slot_id | trb_ep_index | type, false);
2161 }
2162
2163 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2164                 unsigned int ep_index)
2165 {
2166         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2167         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2168         u32 type = TRB_TYPE(TRB_RESET_EP);
2169
2170         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
2171                         false);
2172 }