drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
 127 {
 128         /* Enqueue pointer can be left pointing to the link TRB,
 129          * we must handle that
 130          */
 131         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
 132                 return ring->enq_seg->next->trbs;
 133         return ring->enqueue;
 134 }
 135
 136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 137  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 138  * effect the ring dequeue or enqueue pointers.
 139  */
 140 static void next_trb(struct xhci_hcd *xhci,
 141                 struct xhci_ring *ring,
 142                 struct xhci_segment **seg,
 143                 union xhci_trb **trb)
 144 {
 145         if (last_trb(xhci, ring, *seg, *trb)) {
 146                 *seg = (*seg)->next;
 147                 *trb = ((*seg)->trbs);
 148         } else {
 149                 (*trb)++;
 150         }
 151 }
 152
 153 /*
 154  * See Cycle bit rules. SW is the consumer for the event ring only.
 155  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 156  */
 157 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 158 {
 159         ring->deq_updates++;
 160
 161         /*
 162          * If this is not event ring, and the dequeue pointer
 163          * is not on a link TRB, there is one more usable TRB
 164          */
 165         if (ring->type != TYPE_EVENT &&
 166                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 167                 ring->num_trbs_free++;
 168
 169         do {
 170                 /*
 171                  * Update the dequeue pointer further if that was a link TRB or
 172                  * we're at the end of an event ring segment (which doesn't have
 173                  * link TRBS)
 174                  */
 175                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 176                         if (ring->type == TYPE_EVENT &&
 177                                         last_trb_on_last_seg(xhci, ring,
 178                                                 ring->deq_seg, ring->dequeue)) {
 179                                 ring->cycle_state ^= 1;
 180                         }
 181                         ring->deq_seg = ring->deq_seg->next;
 182                         ring->dequeue = ring->deq_seg->trbs;
 183                 } else {
 184                         ring->dequeue++;
 185                 }
 186         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 187 }
 188
 189 /*
 190  * See Cycle bit rules. SW is the consumer for the event ring only.
 191  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 192  *
 193  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 194  * chain bit is set), then set the chain bit in all the following link TRBs.
 195  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 196  * have their chain bit cleared (so that each Link TRB is a separate TD).
 197  *
 198  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 199  * set, but other sections talk about dealing with the chain bit set.  This was
 200  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 201  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 202  *
 203  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 204  *                      prepare_transfer()?
 205  */
 206 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 207                         bool more_trbs_coming)
 208 {
 209         u32 chain;
 210         union xhci_trb *next;
 211
 212         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 213         /* If this is not event ring, there is one less usable TRB */
 214         if (ring->type != TYPE_EVENT &&
 215                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 216                 ring->num_trbs_free--;
 217         next = ++(ring->enqueue);
 218
 219         ring->enq_updates++;
 220         /* Update the dequeue pointer further if that was a link TRB or we're at
 221          * the end of an event ring segment (which doesn't have link TRBS)
 222          */
 223         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 224                 if (ring->type != TYPE_EVENT) {
 225                         /*
 226                          * If the caller doesn't plan on enqueueing more
 227                          * TDs before ringing the doorbell, then we
 228                          * don't want to give the link TRB to the
 229                          * hardware just yet.  We'll give the link TRB
 230                          * back in prepare_ring() just before we enqueue
 231                          * the TD at the top of the ring.
 232                          */
 233                         if (!chain && !more_trbs_coming)
 234                                 break;
 235
 236                         /* If we're not dealing with 0.95 hardware or
 237                          * isoc rings on AMD 0.96 host,
 238                          * carry over the chain bit of the previous TRB
 239                          * (which may mean the chain bit is cleared).
 240                          */
 241                         if (!(ring->type == TYPE_ISOC &&
 242                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 243                                                 && !xhci_link_trb_quirk(xhci)) {
 244                                 next->link.control &=
 245                                         cpu_to_le32(~TRB_CHAIN);
 246                                 next->link.control |=
 247                                         cpu_to_le32(chain);
 248                         }
 249                         /* Give this link TRB to the hardware */
 250                         wmb();
 251                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 252
 253                         /* Toggle the cycle bit after the last ring segment. */
 254                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 255                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 256                         }
 257                 }
 258                 ring->enq_seg = ring->enq_seg->next;
 259                 ring->enqueue = ring->enq_seg->trbs;
 260                 next = ring->enqueue;
 261         }
 262 }
 263
 264 /*
 265  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 266  * enqueue pointer will not advance into dequeue segment. See rules above.
 267  */
 268 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 269                 unsigned int num_trbs)
 270 {
 271         int num_trbs_in_deq_seg;
 272
 273         if (ring->num_trbs_free < num_trbs)
 274                 return 0;
 275
 276         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 277                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 278                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 279                         return 0;
 280         }
 281
 282         return 1;
 283 }
 284
 285 /* Ring the host controller doorbell after placing a command on the ring */
 286 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 287 {
 288         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 289                 return;
 290
 291         xhci_dbg(xhci, "// Ding dong!\n");
 292         writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 293         /* Flush PCI posted writes */
 294         readl(&xhci->dba->doorbell[0]);
 295 }
 296
 297 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 298 {
 299         u64 temp_64;
 300         int ret;
 301
 302         xhci_dbg(xhci, "Abort command ring\n");
 303
 304         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 305                 xhci_dbg(xhci, "The command ring isn't running, "
 306                                 "Have the command ring been stopped?\n");
 307                 return 0;
 308         }
 309
 310         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 311         if (!(temp_64 & CMD_RING_RUNNING)) {
 312                 xhci_dbg(xhci, "Command ring had been stopped\n");
 313                 return 0;
 314         }
 315         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 316         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 317                         &xhci->op_regs->cmd_ring);
 318
 319         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 320          * time the completion od all xHCI commands, including
 321          * the Command Abort operation. If software doesn't see
 322          * CRR negated in a timely manner (e.g. longer than 5
 323          * seconds), then it should assume that the there are
 324          * larger problems with the xHC and assert HCRST.
 325          */
 326         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 327                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 328         if (ret < 0) {
 329                 xhci_err(xhci, "Stopped the command ring failed, "
 330                                 "maybe the host is dead\n");
 331                 xhci->xhc_state |= XHCI_STATE_DYING;
 332                 xhci_quiesce(xhci);
 333                 xhci_halt(xhci);
 334                 return -ESHUTDOWN;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int xhci_queue_cd(struct xhci_hcd *xhci,
 341                 struct xhci_command *command,
 342                 union xhci_trb *cmd_trb)
 343 {
 344         struct xhci_cd *cd;
 345         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 346         if (!cd)
 347                 return -ENOMEM;
 348         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 349
 350         cd->command = command;
 351         cd->cmd_trb = cmd_trb;
 352         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 353
 354         return 0;
 355 }
 356
 357 /*
 358  * Cancel the command which has issue.
 359  *
 360  * Some commands may hang due to waiting for acknowledgement from
 361  * usb device. It is outside of the xHC's ability to control and
 362  * will cause the command ring is blocked. When it occurs software
 363  * should intervene to recover the command ring.
 364  * See Section 4.6.1.1 and 4.6.1.2
 365  */
 366 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 367                 union xhci_trb *cmd_trb)
 368 {
 369         int retval = 0;
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&xhci->lock, flags);
 373
 374         if (xhci->xhc_state & XHCI_STATE_DYING) {
 375                 xhci_warn(xhci, "Abort the command ring,"
 376                                 " but the xHCI is dead.\n");
 377                 retval = -ESHUTDOWN;
 378                 goto fail;
 379         }
 380
 381         /* queue the cmd desriptor to cancel_cmd_list */
 382         retval = xhci_queue_cd(xhci, command, cmd_trb);
 383         if (retval) {
 384                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 385                 goto fail;
 386         }
 387
 388         /* abort command ring */
 389         retval = xhci_abort_cmd_ring(xhci);
 390         if (retval) {
 391                 xhci_err(xhci, "Abort command ring failed\n");
 392                 if (unlikely(retval == -ESHUTDOWN)) {
 393                         spin_unlock_irqrestore(&xhci->lock, flags);
 394                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 395                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 396                         return retval;
 397                 }
 398         }
 399
 400 fail:
 401         spin_unlock_irqrestore(&xhci->lock, flags);
 402         return retval;
 403 }
 404
 405 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 406                 unsigned int slot_id,
 407                 unsigned int ep_index,
 408                 unsigned int stream_id)
 409 {
 410         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 411         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 412         unsigned int ep_state = ep->ep_state;
 413
 414         /* Don't ring the doorbell for this endpoint if there are pending
 415          * cancellations because we don't want to interrupt processing.
 416          * We don't want to restart any stream rings if there's a set dequeue
 417          * pointer command pending because the device can choose to start any
 418          * stream once the endpoint is on the HW schedule.
 419          * FIXME - check all the stream rings for pending cancellations.
 420          */
 421         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 422             (ep_state & EP_HALTED))
 423                 return;
 424         writel(DB_VALUE(ep_index, stream_id), db_addr);
 425         /* The CPU has better things to do at this point than wait for a
 426          * write-posting flush.  It'll get there soon enough.
 427          */
 428 }
 429
 430 /* Ring the doorbell for any rings with pending URBs */
 431 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 432                 unsigned int slot_id,
 433                 unsigned int ep_index)
 434 {
 435         unsigned int stream_id;
 436         struct xhci_virt_ep *ep;
 437
 438         ep = &xhci->devs[slot_id]->eps[ep_index];
 439
 440         /* A ring has pending URBs if its TD list is not empty */
 441         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 442                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 443                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 444                 return;
 445         }
 446
 447         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 448                         stream_id++) {
 449                 struct xhci_stream_info *stream_info = ep->stream_info;
 450                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 451                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 452                                                 stream_id);
 453         }
 454 }
 455
 456 /*
 457  * Find the segment that trb is in.  Start searching in start_seg.
 458  * If we must move past a segment that has a link TRB with a toggle cycle state
 459  * bit set, then we will toggle the value pointed at by cycle_state.
 460  */
 461 static struct xhci_segment *find_trb_seg(
 462                 struct xhci_segment *start_seg,
 463                 union xhci_trb  *trb, int *cycle_state)
 464 {
 465         struct xhci_segment *cur_seg = start_seg;
 466         struct xhci_generic_trb *generic_trb;
 467
 468         while (cur_seg->trbs > trb ||
 469                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 470                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 471                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 472                         *cycle_state ^= 0x1;
 473                 cur_seg = cur_seg->next;
 474                 if (cur_seg == start_seg)
 475                         /* Looped over the entire list.  Oops! */
 476                         return NULL;
 477         }
 478         return cur_seg;
 479 }
 480
 481
 482 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 483                 unsigned int slot_id, unsigned int ep_index,
 484                 unsigned int stream_id)
 485 {
 486         struct xhci_virt_ep *ep;
 487
 488         ep = &xhci->devs[slot_id]->eps[ep_index];
 489         /* Common case: no streams */
 490         if (!(ep->ep_state & EP_HAS_STREAMS))
 491                 return ep->ring;
 492
 493         if (stream_id == 0) {
 494                 xhci_warn(xhci,
 495                                 "WARN: Slot ID %u, ep index %u has streams, "
 496                                 "but URB has no stream ID.\n",
 497                                 slot_id, ep_index);
 498                 return NULL;
 499         }
 500
 501         if (stream_id < ep->stream_info->num_streams)
 502                 return ep->stream_info->stream_rings[stream_id];
 503
 504         xhci_warn(xhci,
 505                         "WARN: Slot ID %u, ep index %u has "
 506                         "stream IDs 1 to %u allocated, "
 507                         "but stream ID %u is requested.\n",
 508                         slot_id, ep_index,
 509                         ep->stream_info->num_streams - 1,
 510                         stream_id);
 511         return NULL;
 512 }
 513
 514 /* Get the right ring for the given URB.
 515  * If the endpoint supports streams, boundary check the URB's stream ID.
 516  * If the endpoint doesn't support streams, return the singular endpoint ring.
 517  */
 518 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 519                 struct urb *urb)
 520 {
 521         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 522                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 523 }
 524
 525 /*
 526  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 527  * Record the new state of the xHC's endpoint ring dequeue segment,
 528  * dequeue pointer, and new consumer cycle state in state.
 529  * Update our internal representation of the ring's dequeue pointer.
 530  *
 531  * We do this in three jumps:
 532  *  - First we update our new ring state to be the same as when the xHC stopped.
 533  *  - Then we traverse the ring to find the segment that contains
 534  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 535  *    any link TRBs with the toggle cycle bit set.
 536  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 537  *    if we've moved it past a link TRB with the toggle cycle bit set.
 538  *
 539  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 540  * with correct __le32 accesses they should work fine.  Only users of this are
 541  * in here.
 542  */
 543 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 544                 unsigned int slot_id, unsigned int ep_index,
 545                 unsigned int stream_id, struct xhci_td *cur_td,
 546                 struct xhci_dequeue_state *state)
 547 {
 548         struct xhci_virt_device *dev = xhci->devs[slot_id];
 549         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 550         struct xhci_ring *ep_ring;
 551         struct xhci_generic_trb *trb;
 552         dma_addr_t addr;
 553
 554         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 555                         ep_index, stream_id);
 556         if (!ep_ring) {
 557                 xhci_warn(xhci, "WARN can't find new dequeue state "
 558                                 "for invalid stream ID %u.\n",
 559                                 stream_id);
 560                 return;
 561         }
 562         state->new_cycle_state = 0;
 563         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 564                         "Finding segment containing stopped TRB.");
 565         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 566                         dev->eps[ep_index].stopped_trb,
 567                         &state->new_cycle_state);
 568         if (!state->new_deq_seg) {
 569                 WARN_ON(1);
 570                 return;
 571         }
 572
 573         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 574         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 575                         "Finding endpoint context");
 576         /* 4.6.9 the css flag is written to the stream context for streams */
 577         if (ep->ep_state & EP_HAS_STREAMS) {
 578                 struct xhci_stream_ctx *ctx =
 579                         &ep->stream_info->stream_ctx_array[stream_id];
 580                 state->new_cycle_state = 0x1 & le64_to_cpu(ctx->stream_ring);
 581         } else {
 582                 struct xhci_ep_ctx *ep_ctx
 583                         = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 584                 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 585         }
 586
 587         state->new_deq_ptr = cur_td->last_trb;
 588         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 589                         "Finding segment containing last TRB in TD.");
 590         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 591                         state->new_deq_ptr,
 592                         &state->new_cycle_state);
 593         if (!state->new_deq_seg) {
 594                 WARN_ON(1);
 595                 return;
 596         }
 597
 598         trb = &state->new_deq_ptr->generic;
 599         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 600             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 601                 state->new_cycle_state ^= 0x1;
 602         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 603
 604         /*
 605          * If there is only one segment in a ring, find_trb_seg()'s while loop
 606          * will not run, and it will return before it has a chance to see if it
 607          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 608          * ended just before the link TRB on a one-segment ring, or if the TD
 609          * wrapped around the top of the ring, because it doesn't have the TD in
 610          * question.  Look for the one-segment case where stalled TRB's address
 611          * is greater than the new dequeue pointer address.
 612          */
 613         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 614                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 615                 state->new_cycle_state ^= 0x1;
 616         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 617                         "Cycle state = 0x%x", state->new_cycle_state);
 618
 619         /* Don't update the ring cycle state for the producer (us). */
 620         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 621                         "New dequeue segment = %p (virtual)",
 622                         state->new_deq_seg);
 623         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 624         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 625                         "New dequeue pointer = 0x%llx (DMA)",
 626                         (unsigned long long) addr);
 627 }
 628
 629 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 630  * (The last TRB actually points to the ring enqueue pointer, which is not part
 631  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 632  */
 633 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 634                 struct xhci_td *cur_td, bool flip_cycle)
 635 {
 636         struct xhci_segment *cur_seg;
 637         union xhci_trb *cur_trb;
 638
 639         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 640                         true;
 641                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 642                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 643                         /* Unchain any chained Link TRBs, but
 644                          * leave the pointers intact.
 645                          */
 646                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 647                         /* Flip the cycle bit (link TRBs can't be the first
 648                          * or last TRB).
 649                          */
 650                         if (flip_cycle)
 651                                 cur_trb->generic.field[3] ^=
 652                                         cpu_to_le32(TRB_CYCLE);
 653                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 654                                         "Cancel (unchain) link TRB");
 655                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 656                                         "Address = %p (0x%llx dma); "
 657                                         "in seg %p (0x%llx dma)",
 658                                         cur_trb,
 659                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 660                                         cur_seg,
 661                                         (unsigned long long)cur_seg->dma);
 662                 } else {
 663                         cur_trb->generic.field[0] = 0;
 664                         cur_trb->generic.field[1] = 0;
 665                         cur_trb->generic.field[2] = 0;
 666                         /* Preserve only the cycle bit of this TRB */
 667                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 668                         /* Flip the cycle bit except on the first or last TRB */
 669                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 670                                         cur_trb != cur_td->last_trb)
 671                                 cur_trb->generic.field[3] ^=
 672                                         cpu_to_le32(TRB_CYCLE);
 673                         cur_trb->generic.field[3] |= cpu_to_le32(
 674                                 TRB_TYPE(TRB_TR_NOOP));
 675                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 676                                         "TRB to noop at offset 0x%llx",
 677                                         (unsigned long long)
 678                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 679                 }
 680                 if (cur_trb == cur_td->last_trb)
 681                         break;
 682         }
 683 }
 684
 685 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 686                 unsigned int ep_index, unsigned int stream_id,
 687                 struct xhci_segment *deq_seg,
 688                 union xhci_trb *deq_ptr, u32 cycle_state);
 689
 690 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 691                 unsigned int slot_id, unsigned int ep_index,
 692                 unsigned int stream_id,
 693                 struct xhci_dequeue_state *deq_state)
 694 {
 695         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 696
 697         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 698                         "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 699                         "new deq ptr = %p (0x%llx dma), new cycle = %u",
 700                         deq_state->new_deq_seg,
 701                         (unsigned long long)deq_state->new_deq_seg->dma,
 702                         deq_state->new_deq_ptr,
 703                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 704                         deq_state->new_cycle_state);
 705         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 706                         deq_state->new_deq_seg,
 707                         deq_state->new_deq_ptr,
 708                         (u32) deq_state->new_cycle_state);
 709         /* Stop the TD queueing code from ringing the doorbell until
 710          * this command completes.  The HC won't set the dequeue pointer
 711          * if the ring is running, and ringing the doorbell starts the
 712          * ring running.
 713          */
 714         ep->ep_state |= SET_DEQ_PENDING;
 715 }
 716
 717 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 718                 struct xhci_virt_ep *ep)
 719 {
 720         ep->ep_state &= ~EP_HALT_PENDING;
 721         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 722          * timer is running on another CPU, we don't decrement stop_cmds_pending
 723          * (since we didn't successfully stop the watchdog timer).
 724          */
 725         if (del_timer(&ep->stop_cmd_timer))
 726                 ep->stop_cmds_pending--;
 727 }
 728
 729 /* Must be called with xhci->lock held in interrupt context */
 730 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 731                 struct xhci_td *cur_td, int status)
 732 {
 733         struct usb_hcd *hcd;
 734         struct urb      *urb;
 735         struct urb_priv *urb_priv;
 736
 737         urb = cur_td->urb;
 738         urb_priv = urb->hcpriv;
 739         urb_priv->td_cnt++;
 740         hcd = bus_to_hcd(urb->dev->bus);
 741
 742         /* Only giveback urb when this is the last td in urb */
 743         if (urb_priv->td_cnt == urb_priv->length) {
 744                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 745                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 746                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 747                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 748                                         usb_amd_quirk_pll_enable();
 749                         }
 750                 }
 751                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 752
 753                 spin_unlock(&xhci->lock);
 754                 usb_hcd_giveback_urb(hcd, urb, status);
 755                 xhci_urb_free_priv(xhci, urb_priv);
 756                 spin_lock(&xhci->lock);
 757         }
 758 }
 759
 760 /*
 761  * When we get a command completion for a Stop Endpoint Command, we need to
 762  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 763  *
 764  *  1. If the HW was in the middle of processing the TD that needs to be
 765  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 766  *     in the TD with a Set Dequeue Pointer Command.
 767  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 768  *     bit cleared) so that the HW will skip over them.
 769  */
 770 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 771                 union xhci_trb *trb, struct xhci_event_cmd *event)
 772 {
 773         unsigned int ep_index;
 774         struct xhci_virt_device *virt_dev;
 775         struct xhci_ring *ep_ring;
 776         struct xhci_virt_ep *ep;
 777         struct list_head *entry;
 778         struct xhci_td *cur_td = NULL;
 779         struct xhci_td *last_unlinked_td;
 780
 781         struct xhci_dequeue_state deq_state;
 782
 783         if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 784                 virt_dev = xhci->devs[slot_id];
 785                 if (virt_dev)
 786                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 787                                 event);
 788                 else
 789                         xhci_warn(xhci, "Stop endpoint command "
 790                                 "completion for disabled slot %u\n",
 791                                 slot_id);
 792                 return;
 793         }
 794
 795         memset(&deq_state, 0, sizeof(deq_state));
 796         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 797         ep = &xhci->devs[slot_id]->eps[ep_index];
 798
 799         if (list_empty(&ep->cancelled_td_list)) {
 800                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 801                 ep->stopped_td = NULL;
 802                 ep->stopped_trb = NULL;
 803                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 804                 return;
 805         }
 806
 807         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 808          * We have the xHCI lock, so nothing can modify this list until we drop
 809          * it.  We're also in the event handler, so we can't get re-interrupted
 810          * if another Stop Endpoint command completes
 811          */
 812         list_for_each(entry, &ep->cancelled_td_list) {
 813                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 814                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 815                                 "Removing canceled TD starting at 0x%llx (dma).",
 816                                 (unsigned long long)xhci_trb_virt_to_dma(
 817                                         cur_td->start_seg, cur_td->first_trb));
 818                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 819                 if (!ep_ring) {
 820                         /* This shouldn't happen unless a driver is mucking
 821                          * with the stream ID after submission.  This will
 822                          * leave the TD on the hardware ring, and the hardware
 823                          * will try to execute it, and may access a buffer
 824                          * that has already been freed.  In the best case, the
 825                          * hardware will execute it, and the event handler will
 826                          * ignore the completion event for that TD, since it was
 827                          * removed from the td_list for that endpoint.  In
 828                          * short, don't muck with the stream ID after
 829                          * submission.
 830                          */
 831                         xhci_warn(xhci, "WARN Cancelled URB %p "
 832                                         "has invalid stream ID %u.\n",
 833                                         cur_td->urb,
 834                                         cur_td->urb->stream_id);
 835                         goto remove_finished_td;
 836                 }
 837                 /*
 838                  * If we stopped on the TD we need to cancel, then we have to
 839                  * move the xHC endpoint ring dequeue pointer past this TD.
 840                  */
 841                 if (cur_td == ep->stopped_td)
 842                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 843                                         cur_td->urb->stream_id,
 844                                         cur_td, &deq_state);
 845                 else
 846                         td_to_noop(xhci, ep_ring, cur_td, false);
 847 remove_finished_td:
 848                 /*
 849                  * The event handler won't see a completion for this TD anymore,
 850                  * so remove it from the endpoint ring's TD list.  Keep it in
 851                  * the cancelled TD list for URB completion later.
 852                  */
 853                 list_del_init(&cur_td->td_list);
 854         }
 855         last_unlinked_td = cur_td;
 856         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 857
 858         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 859         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 860                 xhci_queue_new_dequeue_state(xhci,
 861                                 slot_id, ep_index,
 862                                 ep->stopped_td->urb->stream_id,
 863                                 &deq_state);
 864                 xhci_ring_cmd_db(xhci);
 865         } else {
 866                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 867                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 868         }
 869
 870         /* Clear stopped_td and stopped_trb if endpoint is not halted */
 871         if (!(ep->ep_state & EP_HALTED)) {
 872                 ep->stopped_td = NULL;
 873                 ep->stopped_trb = NULL;
 874         }
 875
 876         /*
 877          * Drop the lock and complete the URBs in the cancelled TD list.
 878          * New TDs to be cancelled might be added to the end of the list before
 879          * we can complete all the URBs for the TDs we already unlinked.
 880          * So stop when we've completed the URB for the last TD we unlinked.
 881          */
 882         do {
 883                 cur_td = list_entry(ep->cancelled_td_list.next,
 884                                 struct xhci_td, cancelled_td_list);
 885                 list_del_init(&cur_td->cancelled_td_list);
 886
 887                 /* Clean up the cancelled URB */
 888                 /* Doesn't matter what we pass for status, since the core will
 889                  * just overwrite it (because the URB has been unlinked).
 890                  */
 891                 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 892
 893                 /* Stop processing the cancelled list if the watchdog timer is
 894                  * running.
 895                  */
 896                 if (xhci->xhc_state & XHCI_STATE_DYING)
 897                         return;
 898         } while (cur_td != last_unlinked_td);
 899
 900         /* Return to the event handler with xhci->lock re-acquired */
 901 }
 902
 903 /* Watchdog timer function for when a stop endpoint command fails to complete.
 904  * In this case, we assume the host controller is broken or dying or dead.  The
 905  * host may still be completing some other events, so we have to be careful to
 906  * let the event ring handler and the URB dequeueing/enqueueing functions know
 907  * through xhci->state.
 908  *
 909  * The timer may also fire if the host takes a very long time to respond to the
 910  * command, and the stop endpoint command completion handler cannot delete the
 911  * timer before the timer function is called.  Another endpoint cancellation may
 912  * sneak in before the timer function can grab the lock, and that may queue
 913  * another stop endpoint command and add the timer back.  So we cannot use a
 914  * simple flag to say whether there is a pending stop endpoint command for a
 915  * particular endpoint.
 916  *
 917  * Instead we use a combination of that flag and a counter for the number of
 918  * pending stop endpoint commands.  If the timer is the tail end of the last
 919  * stop endpoint command, and the endpoint's command is still pending, we assume
 920  * the host is dying.
 921  */
 922 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 923 {
 924         struct xhci_hcd *xhci;
 925         struct xhci_virt_ep *ep;
 926         struct xhci_virt_ep *temp_ep;
 927         struct xhci_ring *ring;
 928         struct xhci_td *cur_td;
 929         int ret, i, j;
 930         unsigned long flags;
 931
 932         ep = (struct xhci_virt_ep *) arg;
 933         xhci = ep->xhci;
 934
 935         spin_lock_irqsave(&xhci->lock, flags);
 936
 937         ep->stop_cmds_pending--;
 938         if (xhci->xhc_state & XHCI_STATE_DYING) {
 939                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 940                                 "Stop EP timer ran, but another timer marked "
 941                                 "xHCI as DYING, exiting.");
 942                 spin_unlock_irqrestore(&xhci->lock, flags);
 943                 return;
 944         }
 945         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 946                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 947                                 "Stop EP timer ran, but no command pending, "
 948                                 "exiting.");
 949                 spin_unlock_irqrestore(&xhci->lock, flags);
 950                 return;
 951         }
 952
 953         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 954         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 955         /* Oops, HC is dead or dying or at least not responding to the stop
 956          * endpoint command.
 957          */
 958         xhci->xhc_state |= XHCI_STATE_DYING;
 959         /* Disable interrupts from the host controller and start halting it */
 960         xhci_quiesce(xhci);
 961         spin_unlock_irqrestore(&xhci->lock, flags);
 962
 963         ret = xhci_halt(xhci);
 964
 965         spin_lock_irqsave(&xhci->lock, flags);
 966         if (ret < 0) {
 967                 /* This is bad; the host is not responding to commands and it's
 968                  * not allowing itself to be halted.  At least interrupts are
 969                  * disabled. If we call usb_hc_died(), it will attempt to
 970                  * disconnect all device drivers under this host.  Those
 971                  * disconnect() methods will wait for all URBs to be unlinked,
 972                  * so we must complete them.
 973                  */
 974                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 975                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 976                 /* We could turn all TDs on the rings to no-ops.  This won't
 977                  * help if the host has cached part of the ring, and is slow if
 978                  * we want to preserve the cycle bit.  Skip it and hope the host
 979                  * doesn't touch the memory.
 980                  */
 981         }
 982         for (i = 0; i < MAX_HC_SLOTS; i++) {
 983                 if (!xhci->devs[i])
 984                         continue;
 985                 for (j = 0; j < 31; j++) {
 986                         temp_ep = &xhci->devs[i]->eps[j];
 987                         ring = temp_ep->ring;
 988                         if (!ring)
 989                                 continue;
 990                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 991                                         "Killing URBs for slot ID %u, "
 992                                         "ep index %u", i, j);
 993                         while (!list_empty(&ring->td_list)) {
 994                                 cur_td = list_first_entry(&ring->td_list,
 995                                                 struct xhci_td,
 996                                                 td_list);
 997                                 list_del_init(&cur_td->td_list);
 998                                 if (!list_empty(&cur_td->cancelled_td_list))
 999                                         list_del_init(&cur_td->cancelled_td_list);
1000                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1001                                                 -ESHUTDOWN);
1002                         }
1003                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1004                                 cur_td = list_first_entry(
1005                                                 &temp_ep->cancelled_td_list,
1006                                                 struct xhci_td,
1007                                                 cancelled_td_list);
1008                                 list_del_init(&cur_td->cancelled_td_list);
1009                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1010                                                 -ESHUTDOWN);
1011                         }
1012                 }
1013         }
1014         spin_unlock_irqrestore(&xhci->lock, flags);
1015         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1016                         "Calling usb_hc_died()");
1017         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1018         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1019                         "xHCI host controller is dead.");
1020 }
1021
1022
1023 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1024                 struct xhci_virt_device *dev,
1025                 struct xhci_ring *ep_ring,
1026                 unsigned int ep_index)
1027 {
1028         union xhci_trb *dequeue_temp;
1029         int num_trbs_free_temp;
1030         bool revert = false;
1031
1032         num_trbs_free_temp = ep_ring->num_trbs_free;
1033         dequeue_temp = ep_ring->dequeue;
1034
1035         /* If we get two back-to-back stalls, and the first stalled transfer
1036          * ends just before a link TRB, the dequeue pointer will be left on
1037          * the link TRB by the code in the while loop.  So we have to update
1038          * the dequeue pointer one segment further, or we'll jump off
1039          * the segment into la-la-land.
1040          */
1041         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1042                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1043                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1044         }
1045
1046         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1047                 /* We have more usable TRBs */
1048                 ep_ring->num_trbs_free++;
1049                 ep_ring->dequeue++;
1050                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1051                                 ep_ring->dequeue)) {
1052                         if (ep_ring->dequeue ==
1053                                         dev->eps[ep_index].queued_deq_ptr)
1054                                 break;
1055                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1056                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1057                 }
1058                 if (ep_ring->dequeue == dequeue_temp) {
1059                         revert = true;
1060                         break;
1061                 }
1062         }
1063
1064         if (revert) {
1065                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1066                 ep_ring->num_trbs_free = num_trbs_free_temp;
1067         }
1068 }
1069
1070 /*
1071  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1072  * we need to clear the set deq pending flag in the endpoint ring state, so that
1073  * the TD queueing code can ring the doorbell again.  We also need to ring the
1074  * endpoint doorbell to restart the ring, but only if there aren't more
1075  * cancellations pending.
1076  */
1077 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1078                 union xhci_trb *trb, u32 cmd_comp_code)
1079 {
1080         unsigned int ep_index;
1081         unsigned int stream_id;
1082         struct xhci_ring *ep_ring;
1083         struct xhci_virt_device *dev;
1084         struct xhci_virt_ep *ep;
1085         struct xhci_ep_ctx *ep_ctx;
1086         struct xhci_slot_ctx *slot_ctx;
1087
1088         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1089         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1090         dev = xhci->devs[slot_id];
1091         ep = &dev->eps[ep_index];
1092
1093         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1094         if (!ep_ring) {
1095                 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1096                                 stream_id);
1097                 /* XXX: Harmless??? */
1098                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1099                 return;
1100         }
1101
1102         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1103         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1104
1105         if (cmd_comp_code != COMP_SUCCESS) {
1106                 unsigned int ep_state;
1107                 unsigned int slot_state;
1108
1109                 switch (cmd_comp_code) {
1110                 case COMP_TRB_ERR:
1111                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1112                         break;
1113                 case COMP_CTX_STATE:
1114                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1115                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1116                         ep_state &= EP_STATE_MASK;
1117                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1118                         slot_state = GET_SLOT_STATE(slot_state);
1119                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1120                                         "Slot state = %u, EP state = %u",
1121                                         slot_state, ep_state);
1122                         break;
1123                 case COMP_EBADSLT:
1124                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1125                                         slot_id);
1126                         break;
1127                 default:
1128                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1129                                         cmd_comp_code);
1130                         break;
1131                 }
1132                 /* OK what do we do now?  The endpoint state is hosed, and we
1133                  * should never get to this point if the synchronization between
1134                  * queueing, and endpoint state are correct.  This might happen
1135                  * if the device gets disconnected after we've finished
1136                  * cancelling URBs, which might not be an error...
1137                  */
1138         } else {
1139                 u64 deq;
1140                 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1141                 if (ep->ep_state & EP_HAS_STREAMS) {
1142                         struct xhci_stream_ctx *ctx =
1143                                 &ep->stream_info->stream_ctx_array[stream_id];
1144                         deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1145                 } else {
1146                         deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1147                 }
1148                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1149                         "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1150                 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1151                                          ep->queued_deq_ptr) == deq) {
1152                         /* Update the ring's dequeue segment and dequeue pointer
1153                          * to reflect the new position.
1154                          */
1155                         update_ring_for_set_deq_completion(xhci, dev,
1156                                 ep_ring, ep_index);
1157                 } else {
1158                         xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1159                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1160                                   ep->queued_deq_seg, ep->queued_deq_ptr);
1161                 }
1162         }
1163
1164         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1165         dev->eps[ep_index].queued_deq_seg = NULL;
1166         dev->eps[ep_index].queued_deq_ptr = NULL;
1167         /* Restart any rings with pending URBs */
1168         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1169 }
1170
1171 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1172                 union xhci_trb *trb, u32 cmd_comp_code)
1173 {
1174         unsigned int ep_index;
1175
1176         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1177         /* This command will only fail if the endpoint wasn't halted,
1178          * but we don't care.
1179          */
1180         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1181                 "Ignoring reset ep completion code of %u", cmd_comp_code);
1182
1183         /* HW with the reset endpoint quirk needs to have a configure endpoint
1184          * command complete before the endpoint can be used.  Queue that here
1185          * because the HW can't handle two commands being queued in a row.
1186          */
1187         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1188                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1189                                 "Queueing configure endpoint command");
1190                 xhci_queue_configure_endpoint(xhci,
1191                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1192                                 false);
1193                 xhci_ring_cmd_db(xhci);
1194         } else {
1195                 /* Clear our internal halted state and restart the ring(s) */
1196                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1197                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1198         }
1199 }
1200
1201 /* Complete the command and detele it from the devcie's command queue.
1202  */
1203 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1204                 struct xhci_command *command, u32 status)
1205 {
1206         command->status = status;
1207         list_del(&command->cmd_list);
1208         if (command->completion)
1209                 complete(command->completion);
1210         else
1211                 xhci_free_command(xhci, command);
1212 }
1213
1214
1215 /* Check to see if a command in the device's command queue matches this one.
1216  * Signal the completion or free the command, and return 1.  Return 0 if the
1217  * completed command isn't at the head of the command list.
1218  */
1219 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1220                 struct xhci_virt_device *virt_dev,
1221                 struct xhci_event_cmd *event)
1222 {
1223         struct xhci_command *command;
1224
1225         if (list_empty(&virt_dev->cmd_list))
1226                 return 0;
1227
1228         command = list_entry(virt_dev->cmd_list.next,
1229                         struct xhci_command, cmd_list);
1230         if (xhci->cmd_ring->dequeue != command->command_trb)
1231                 return 0;
1232
1233         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1234                         GET_COMP_CODE(le32_to_cpu(event->status)));
1235         return 1;
1236 }
1237
1238 /*
1239  * Finding the command trb need to be cancelled and modifying it to
1240  * NO OP command. And if the command is in device's command wait
1241  * list, finishing and freeing it.
1242  *
1243  * If we can't find the command trb, we think it had already been
1244  * executed.
1245  */
1246 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1247 {
1248         struct xhci_segment *cur_seg;
1249         union xhci_trb *cmd_trb;
1250         u32 cycle_state;
1251
1252         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1253                 return;
1254
1255         /* find the current segment of command ring */
1256         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1257                         xhci->cmd_ring->dequeue, &cycle_state);
1258
1259         if (!cur_seg) {
1260                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1261                                 xhci->cmd_ring->dequeue,
1262                                 (unsigned long long)
1263                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1264                                         xhci->cmd_ring->dequeue));
1265                 xhci_debug_ring(xhci, xhci->cmd_ring);
1266                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1267                 return;
1268         }
1269
1270         /* find the command trb matched by cd from command ring */
1271         for (cmd_trb = xhci->cmd_ring->dequeue;
1272                         cmd_trb != xhci->cmd_ring->enqueue;
1273                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1274                 /* If the trb is link trb, continue */
1275                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1276                         continue;
1277
1278                 if (cur_cd->cmd_trb == cmd_trb) {
1279
1280                         /* If the command in device's command list, we should
1281                          * finish it and free the command structure.
1282                          */
1283                         if (cur_cd->command)
1284                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1285                                         cur_cd->command, COMP_CMD_STOP);
1286
1287                         /* get cycle state from the origin command trb */
1288                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1289                                 & TRB_CYCLE;
1290
1291                         /* modify the command trb to NO OP command */
1292                         cmd_trb->generic.field[0] = 0;
1293                         cmd_trb->generic.field[1] = 0;
1294                         cmd_trb->generic.field[2] = 0;
1295                         cmd_trb->generic.field[3] = cpu_to_le32(
1296                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1297                         break;
1298                 }
1299         }
1300 }
1301
1302 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1303 {
1304         struct xhci_cd *cur_cd, *next_cd;
1305
1306         if (list_empty(&xhci->cancel_cmd_list))
1307                 return;
1308
1309         list_for_each_entry_safe(cur_cd, next_cd,
1310                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1311                 xhci_cmd_to_noop(xhci, cur_cd);
1312                 list_del(&cur_cd->cancel_cmd_list);
1313                 kfree(cur_cd);
1314         }
1315 }
1316
1317 /*
1318  * traversing the cancel_cmd_list. If the command descriptor according
1319  * to cmd_trb is found, the function free it and return 1, otherwise
1320  * return 0.
1321  */
1322 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1323                 union xhci_trb *cmd_trb)
1324 {
1325         struct xhci_cd *cur_cd, *next_cd;
1326
1327         if (list_empty(&xhci->cancel_cmd_list))
1328                 return 0;
1329
1330         list_for_each_entry_safe(cur_cd, next_cd,
1331                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1332                 if (cur_cd->cmd_trb == cmd_trb) {
1333                         if (cur_cd->command)
1334                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1335                                         cur_cd->command, COMP_CMD_STOP);
1336                         list_del(&cur_cd->cancel_cmd_list);
1337                         kfree(cur_cd);
1338                         return 1;
1339                 }
1340         }
1341
1342         return 0;
1343 }
1344
1345 /*
1346  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1347  * trb pointed by the command ring dequeue pointer is the trb we want to
1348  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1349  * traverse the cancel_cmd_list to trun the all of the commands according
1350  * to command descriptor to NO-OP trb.
1351  */
1352 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1353                 int cmd_trb_comp_code)
1354 {
1355         int cur_trb_is_good = 0;
1356
1357         /* Searching the cmd trb pointed by the command ring dequeue
1358          * pointer in command descriptor list. If it is found, free it.
1359          */
1360         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1361                         xhci->cmd_ring->dequeue);
1362
1363         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1364                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1365         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1366                 /* traversing the cancel_cmd_list and canceling
1367                  * the command according to command descriptor
1368                  */
1369                 xhci_cancel_cmd_in_cd_list(xhci);
1370
1371                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1372                 /*
1373                  * ring command ring doorbell again to restart the
1374                  * command ring
1375                  */
1376                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1377                         xhci_ring_cmd_db(xhci);
1378         }
1379         return cur_trb_is_good;
1380 }
1381
1382 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1383                 u32 cmd_comp_code)
1384 {
1385         if (cmd_comp_code == COMP_SUCCESS)
1386                 xhci->slot_id = slot_id;
1387         else
1388                 xhci->slot_id = 0;
1389         complete(&xhci->addr_dev);
1390 }
1391
1392 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1393 {
1394         struct xhci_virt_device *virt_dev;
1395
1396         virt_dev = xhci->devs[slot_id];
1397         if (!virt_dev)
1398                 return;
1399         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1400                 /* Delete default control endpoint resources */
1401                 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1402         xhci_free_virt_device(xhci, slot_id);
1403 }
1404
1405 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1406                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1407 {
1408         struct xhci_virt_device *virt_dev;
1409         struct xhci_input_control_ctx *ctrl_ctx;
1410         unsigned int ep_index;
1411         unsigned int ep_state;
1412         u32 add_flags, drop_flags;
1413
1414         virt_dev = xhci->devs[slot_id];
1415         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1416                 return;
1417         /*
1418          * Configure endpoint commands can come from the USB core
1419          * configuration or alt setting changes, or because the HW
1420          * needed an extra configure endpoint command after a reset
1421          * endpoint command or streams were being configured.
1422          * If the command was for a halted endpoint, the xHCI driver
1423          * is not waiting on the configure endpoint command.
1424          */
1425         ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1426         if (!ctrl_ctx) {
1427                 xhci_warn(xhci, "Could not get input context, bad type.\n");
1428                 return;
1429         }
1430
1431         add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1432         drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1433         /* Input ctx add_flags are the endpoint index plus one */
1434         ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1435
1436         /* A usb_set_interface() call directly after clearing a halted
1437          * condition may race on this quirky hardware.  Not worth
1438          * worrying about, since this is prototype hardware.  Not sure
1439          * if this will work for streams, but streams support was
1440          * untested on this prototype.
1441          */
1442         if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1443                         ep_index != (unsigned int) -1 &&
1444                         add_flags - SLOT_FLAG == drop_flags) {
1445                 ep_state = virt_dev->eps[ep_index].ep_state;
1446                 if (!(ep_state & EP_HALTED))
1447                         goto bandwidth_change;
1448                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1449                                 "Completed config ep cmd - "
1450                                 "last ep index = %d, state = %d",
1451                                 ep_index, ep_state);
1452                 /* Clear internal halted state and restart ring(s) */
1453                 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1454                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1455                 return;
1456         }
1457 bandwidth_change:
1458         xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1459                         "Completed config ep cmd");
1460         virt_dev->cmd_status = cmd_comp_code;
1461         complete(&virt_dev->cmd_completion);
1462         return;
1463 }
1464
1465 static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1466                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1467 {
1468         struct xhci_virt_device *virt_dev;
1469
1470         virt_dev = xhci->devs[slot_id];
1471         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1472                 return;
1473         virt_dev->cmd_status = cmd_comp_code;
1474         complete(&virt_dev->cmd_completion);
1475 }
1476
1477 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1478                 u32 cmd_comp_code)
1479 {
1480         xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1481         complete(&xhci->addr_dev);
1482 }
1483
1484 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1485                 struct xhci_event_cmd *event)
1486 {
1487         struct xhci_virt_device *virt_dev;
1488
1489         xhci_dbg(xhci, "Completed reset device command.\n");
1490         virt_dev = xhci->devs[slot_id];
1491         if (virt_dev)
1492                 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1493         else
1494                 xhci_warn(xhci, "Reset device command completion "
1495                                 "for disabled slot %u\n", slot_id);
1496 }
1497
1498 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1499                 struct xhci_event_cmd *event)
1500 {
1501         if (!(xhci->quirks & XHCI_NEC_HOST)) {
1502                 xhci->error_bitmask |= 1 << 6;
1503                 return;
1504         }
1505         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1506                         "NEC firmware version %2x.%02x",
1507                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1508                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1509 }
1510
1511 static void handle_cmd_completion(struct xhci_hcd *xhci,
1512                 struct xhci_event_cmd *event)
1513 {
1514         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1515         u64 cmd_dma;
1516         dma_addr_t cmd_dequeue_dma;
1517         u32 cmd_comp_code;
1518         union xhci_trb *cmd_trb;
1519         u32 cmd_type;
1520
1521         cmd_dma = le64_to_cpu(event->cmd_trb);
1522         cmd_trb = xhci->cmd_ring->dequeue;
1523         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1524                         cmd_trb);
1525         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1526         if (cmd_dequeue_dma == 0) {
1527                 xhci->error_bitmask |= 1 << 4;
1528                 return;
1529         }
1530         /* Does the DMA address match our internal dequeue pointer address? */
1531         if (cmd_dma != (u64) cmd_dequeue_dma) {
1532                 xhci->error_bitmask |= 1 << 5;
1533                 return;
1534         }
1535
1536         trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1537
1538         cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1539         if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1540                 /* If the return value is 0, we think the trb pointed by
1541                  * command ring dequeue pointer is a good trb. The good
1542                  * trb means we don't want to cancel the trb, but it have
1543                  * been stopped by host. So we should handle it normally.
1544                  * Otherwise, driver should invoke inc_deq() and return.
1545                  */
1546                 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1547                         inc_deq(xhci, xhci->cmd_ring);
1548                         return;
1549                 }
1550                 /* There is no command to handle if we get a stop event when the
1551                  * command ring is empty, event->cmd_trb points to the next
1552                  * unset command
1553                  */
1554                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1555                         return;
1556         }
1557
1558         cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1559         switch (cmd_type) {
1560         case TRB_ENABLE_SLOT:
1561                 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1562                 break;
1563         case TRB_DISABLE_SLOT:
1564                 xhci_handle_cmd_disable_slot(xhci, slot_id);
1565                 break;
1566         case TRB_CONFIG_EP:
1567                 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1568                 break;
1569         case TRB_EVAL_CONTEXT:
1570                 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1571                 break;
1572         case TRB_ADDR_DEV:
1573                 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1574                 break;
1575         case TRB_STOP_RING:
1576                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1577                                 le32_to_cpu(cmd_trb->generic.field[3])));
1578                 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1579                 break;
1580         case TRB_SET_DEQ:
1581                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1582                                 le32_to_cpu(cmd_trb->generic.field[3])));
1583                 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1584                 break;
1585         case TRB_CMD_NOOP:
1586                 break;
1587         case TRB_RESET_EP:
1588                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1589                                 le32_to_cpu(cmd_trb->generic.field[3])));
1590                 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1591                 break;
1592         case TRB_RESET_DEV:
1593                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1594                                 le32_to_cpu(cmd_trb->generic.field[3])));
1595                 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1596                 break;
1597         case TRB_NEC_GET_FW:
1598                 xhci_handle_cmd_nec_get_fw(xhci, event);
1599                 break;
1600         default:
1601                 /* Skip over unknown commands on the event ring */
1602                 xhci->error_bitmask |= 1 << 6;
1603                 break;
1604         }
1605         inc_deq(xhci, xhci->cmd_ring);
1606 }
1607
1608 static void handle_vendor_event(struct xhci_hcd *xhci,
1609                 union xhci_trb *event)
1610 {
1611         u32 trb_type;
1612
1613         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1614         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1615         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1616                 handle_cmd_completion(xhci, &event->event_cmd);
1617 }
1618
1619 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1620  * port registers -- USB 3.0 and USB 2.0).
1621  *
1622  * Returns a zero-based port number, which is suitable for indexing into each of
1623  * the split roothubs' port arrays and bus state arrays.
1624  * Add one to it in order to call xhci_find_slot_id_by_port.
1625  */
1626 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1627                 struct xhci_hcd *xhci, u32 port_id)
1628 {
1629         unsigned int i;
1630         unsigned int num_similar_speed_ports = 0;
1631
1632         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1633          * and usb2_ports are 0-based indexes.  Count the number of similar
1634          * speed ports, up to 1 port before this port.
1635          */
1636         for (i = 0; i < (port_id - 1); i++) {
1637                 u8 port_speed = xhci->port_array[i];
1638
1639                 /*
1640                  * Skip ports that don't have known speeds, or have duplicate
1641                  * Extended Capabilities port speed entries.
1642                  */
1643                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1644                         continue;
1645
1646                 /*
1647                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1648                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1649                  * matches the device speed, it's a similar speed port.
1650                  */
1651                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1652                         num_similar_speed_ports++;
1653         }
1654         return num_similar_speed_ports;
1655 }
1656
1657 static void handle_device_notification(struct xhci_hcd *xhci,
1658                 union xhci_trb *event)
1659 {
1660         u32 slot_id;
1661         struct usb_device *udev;
1662
1663         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1664         if (!xhci->devs[slot_id]) {
1665                 xhci_warn(xhci, "Device Notification event for "
1666                                 "unused slot %u\n", slot_id);
1667                 return;
1668         }
1669
1670         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1671                         slot_id);
1672         udev = xhci->devs[slot_id]->udev;
1673         if (udev && udev->parent)
1674                 usb_wakeup_notification(udev->parent, udev->portnum);
1675 }
1676
1677 static void handle_port_status(struct xhci_hcd *xhci,
1678                 union xhci_trb *event)
1679 {
1680         struct usb_hcd *hcd;
1681         u32 port_id;
1682         u32 temp, temp1;
1683         int max_ports;
1684         int slot_id;
1685         unsigned int faked_port_index;
1686         u8 major_revision;
1687         struct xhci_bus_state *bus_state;
1688         __le32 __iomem **port_array;
1689         bool bogus_port_status = false;
1690
1691         /* Port status change events always have a successful completion code */
1692         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1693                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1694                 xhci->error_bitmask |= 1 << 8;
1695         }
1696         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1697         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1698
1699         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1700         if ((port_id <= 0) || (port_id > max_ports)) {
1701                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1702                 inc_deq(xhci, xhci->event_ring);
1703                 return;
1704         }
1705
1706         /* Figure out which usb_hcd this port is attached to:
1707          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1708          */
1709         major_revision = xhci->port_array[port_id - 1];
1710
1711         /* Find the right roothub. */
1712         hcd = xhci_to_hcd(xhci);
1713         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1714                 hcd = xhci->shared_hcd;
1715
1716         if (major_revision == 0) {
1717                 xhci_warn(xhci, "Event for port %u not in "
1718                                 "Extended Capabilities, ignoring.\n",
1719                                 port_id);
1720                 bogus_port_status = true;
1721                 goto cleanup;
1722         }
1723         if (major_revision == DUPLICATE_ENTRY) {
1724                 xhci_warn(xhci, "Event for port %u duplicated in"
1725                                 "Extended Capabilities, ignoring.\n",
1726                                 port_id);
1727                 bogus_port_status = true;
1728                 goto cleanup;
1729         }
1730
1731         /*
1732          * Hardware port IDs reported by a Port Status Change Event include USB
1733          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1734          * resume event, but we first need to translate the hardware port ID
1735          * into the index into the ports on the correct split roothub, and the
1736          * correct bus_state structure.
1737          */
1738         bus_state = &xhci->bus_state[hcd_index(hcd)];
1739         if (hcd->speed == HCD_USB3)
1740                 port_array = xhci->usb3_ports;
1741         else
1742                 port_array = xhci->usb2_ports;
1743         /* Find the faked port hub number */
1744         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1745                         port_id);
1746
1747         temp = readl(port_array[faked_port_index]);
1748         if (hcd->state == HC_STATE_SUSPENDED) {
1749                 xhci_dbg(xhci, "resume root hub\n");
1750                 usb_hcd_resume_root_hub(hcd);
1751         }
1752
1753         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1754                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1755
1756                 temp1 = readl(&xhci->op_regs->command);
1757                 if (!(temp1 & CMD_RUN)) {
1758                         xhci_warn(xhci, "xHC is not running.\n");
1759                         goto cleanup;
1760                 }
1761
1762                 if (DEV_SUPERSPEED(temp)) {
1763                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1764                         /* Set a flag to say the port signaled remote wakeup,
1765                          * so we can tell the difference between the end of
1766                          * device and host initiated resume.
1767                          */
1768                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1769                         xhci_test_and_clear_bit(xhci, port_array,
1770                                         faked_port_index, PORT_PLC);
1771                         xhci_set_link_state(xhci, port_array, faked_port_index,
1772                                                 XDEV_U0);
1773                         /* Need to wait until the next link state change
1774                          * indicates the device is actually in U0.
1775                          */
1776                         bogus_port_status = true;
1777                         goto cleanup;
1778                 } else {
1779                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1780                         bus_state->resume_done[faked_port_index] = jiffies +
1781                                 msecs_to_jiffies(20);
1782                         set_bit(faked_port_index, &bus_state->resuming_ports);
1783                         mod_timer(&hcd->rh_timer,
1784                                   bus_state->resume_done[faked_port_index]);
1785                         /* Do the rest in GetPortStatus */
1786                 }
1787         }
1788
1789         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1790                         DEV_SUPERSPEED(temp)) {
1791                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1792                 /* We've just brought the device into U0 through either the
1793                  * Resume state after a device remote wakeup, or through the
1794                  * U3Exit state after a host-initiated resume.  If it's a device
1795                  * initiated remote wake, don't pass up the link state change,
1796                  * so the roothub behavior is consistent with external
1797                  * USB 3.0 hub behavior.
1798                  */
1799                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1800                                 faked_port_index + 1);
1801                 if (slot_id && xhci->devs[slot_id])
1802                         xhci_ring_device(xhci, slot_id);
1803                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1804                         bus_state->port_remote_wakeup &=
1805                                 ~(1 << faked_port_index);
1806                         xhci_test_and_clear_bit(xhci, port_array,
1807                                         faked_port_index, PORT_PLC);
1808                         usb_wakeup_notification(hcd->self.root_hub,
1809                                         faked_port_index + 1);
1810                         bogus_port_status = true;
1811                         goto cleanup;
1812                 }
1813         }
1814
1815         /*
1816          * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1817          * RExit to a disconnect state).  If so, let the the driver know it's
1818          * out of the RExit state.
1819          */
1820         if (!DEV_SUPERSPEED(temp) &&
1821                         test_and_clear_bit(faked_port_index,
1822                                 &bus_state->rexit_ports)) {
1823                 complete(&bus_state->rexit_done[faked_port_index]);
1824                 bogus_port_status = true;
1825                 goto cleanup;
1826         }
1827
1828         if (hcd->speed != HCD_USB3)
1829                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1830                                         PORT_PLC);
1831
1832 cleanup:
1833         /* Update event ring dequeue pointer before dropping the lock */
1834         inc_deq(xhci, xhci->event_ring);
1835
1836         /* Don't make the USB core poll the roothub if we got a bad port status
1837          * change event.  Besides, at that point we can't tell which roothub
1838          * (USB 2.0 or USB 3.0) to kick.
1839          */
1840         if (bogus_port_status)
1841                 return;
1842
1843         /*
1844          * xHCI port-status-change events occur when the "or" of all the
1845          * status-change bits in the portsc register changes from 0 to 1.
1846          * New status changes won't cause an event if any other change
1847          * bits are still set.  When an event occurs, switch over to
1848          * polling to avoid losing status changes.
1849          */
1850         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1851         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1852         spin_unlock(&xhci->lock);
1853         /* Pass this up to the core */
1854         usb_hcd_poll_rh_status(hcd);
1855         spin_lock(&xhci->lock);
1856 }
1857
1858 /*
1859  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1860  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1861  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1862  * returns 0.
1863  */
1864 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1865                 union xhci_trb  *start_trb,
1866                 union xhci_trb  *end_trb,
1867                 dma_addr_t      suspect_dma)
1868 {
1869         dma_addr_t start_dma;
1870         dma_addr_t end_seg_dma;
1871         dma_addr_t end_trb_dma;
1872         struct xhci_segment *cur_seg;
1873
1874         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1875         cur_seg = start_seg;
1876
1877         do {
1878                 if (start_dma == 0)
1879                         return NULL;
1880                 /* We may get an event for a Link TRB in the middle of a TD */
1881                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1882                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1883                 /* If the end TRB isn't in this segment, this is set to 0 */
1884                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1885
1886                 if (end_trb_dma > 0) {
1887                         /* The end TRB is in this segment, so suspect should be here */
1888                         if (start_dma <= end_trb_dma) {
1889                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1890                                         return cur_seg;
1891                         } else {
1892                                 /* Case for one segment with
1893                                  * a TD wrapped around to the top
1894                                  */
1895                                 if ((suspect_dma >= start_dma &&
1896                                                         suspect_dma <= end_seg_dma) ||
1897                                                 (suspect_dma >= cur_seg->dma &&
1898                                                  suspect_dma <= end_trb_dma))
1899                                         return cur_seg;
1900                         }
1901                         return NULL;
1902                 } else {
1903                         /* Might still be somewhere in this segment */
1904                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1905                                 return cur_seg;
1906                 }
1907                 cur_seg = cur_seg->next;
1908                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1909         } while (cur_seg != start_seg);
1910
1911         return NULL;
1912 }
1913
1914 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1915                 unsigned int slot_id, unsigned int ep_index,
1916                 unsigned int stream_id,
1917                 struct xhci_td *td, union xhci_trb *event_trb)
1918 {
1919         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1920         ep->ep_state |= EP_HALTED;
1921         ep->stopped_td = td;
1922         ep->stopped_trb = event_trb;
1923         ep->stopped_stream = stream_id;
1924
1925         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1926         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1927
1928         ep->stopped_td = NULL;
1929         ep->stopped_trb = NULL;
1930         ep->stopped_stream = 0;
1931
1932         xhci_ring_cmd_db(xhci);
1933 }
1934
1935 /* Check if an error has halted the endpoint ring.  The class driver will
1936  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1937  * However, a babble and other errors also halt the endpoint ring, and the class
1938  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1939  * Ring Dequeue Pointer command manually.
1940  */
1941 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1942                 struct xhci_ep_ctx *ep_ctx,
1943                 unsigned int trb_comp_code)
1944 {
1945         /* TRB completion codes that may require a manual halt cleanup */
1946         if (trb_comp_code == COMP_TX_ERR ||
1947                         trb_comp_code == COMP_BABBLE ||
1948                         trb_comp_code == COMP_SPLIT_ERR)
1949                 /* The 0.96 spec says a babbling control endpoint
1950                  * is not halted. The 0.96 spec says it is.  Some HW
1951                  * claims to be 0.95 compliant, but it halts the control
1952                  * endpoint anyway.  Check if a babble halted the
1953                  * endpoint.
1954                  */
1955                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1956                     cpu_to_le32(EP_STATE_HALTED))
1957                         return 1;
1958
1959         return 0;
1960 }
1961
1962 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1963 {
1964         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1965                 /* Vendor defined "informational" completion code,
1966                  * treat as not-an-error.
1967                  */
1968                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1969                                 trb_comp_code);
1970                 xhci_dbg(xhci, "Treating code as success.\n");
1971                 return 1;
1972         }
1973         return 0;
1974 }
1975
1976 /*
1977  * Finish the td processing, remove the td from td list;
1978  * Return 1 if the urb can be given back.
1979  */
1980 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1981         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1982         struct xhci_virt_ep *ep, int *status, bool skip)
1983 {
1984         struct xhci_virt_device *xdev;
1985         struct xhci_ring *ep_ring;
1986         unsigned int slot_id;
1987         int ep_index;
1988         struct urb *urb = NULL;
1989         struct xhci_ep_ctx *ep_ctx;
1990         int ret = 0;
1991         struct urb_priv *urb_priv;
1992         u32 trb_comp_code;
1993
1994         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1995         xdev = xhci->devs[slot_id];
1996         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1997         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1998         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1999         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2000
2001         if (skip)
2002                 goto td_cleanup;
2003
2004         if (trb_comp_code == COMP_STOP_INVAL ||
2005                         trb_comp_code == COMP_STOP) {
2006                 /* The Endpoint Stop Command completion will take care of any
2007                  * stopped TDs.  A stopped TD may be restarted, so don't update
2008                  * the ring dequeue pointer or take this TD off any lists yet.
2009                  */
2010                 ep->stopped_td = td;
2011                 ep->stopped_trb = event_trb;
2012                 return 0;
2013         } else {
2014                 if (trb_comp_code == COMP_STALL) {
2015                         /* The transfer is completed from the driver's
2016                          * perspective, but we need to issue a set dequeue
2017                          * command for this stalled endpoint to move the dequeue
2018                          * pointer past the TD.  We can't do that here because
2019                          * the halt condition must be cleared first.  Let the
2020                          * USB class driver clear the stall later.
2021                          */
2022                         ep->stopped_td = td;
2023                         ep->stopped_trb = event_trb;
2024                         ep->stopped_stream = ep_ring->stream_id;
2025                 } else if (xhci_requires_manual_halt_cleanup(xhci,
2026                                         ep_ctx, trb_comp_code)) {
2027                         /* Other types of errors halt the endpoint, but the
2028                          * class driver doesn't call usb_reset_endpoint() unless
2029                          * the error is -EPIPE.  Clear the halted status in the
2030                          * xHCI hardware manually.
2031                          */
2032                         xhci_cleanup_halted_endpoint(xhci,
2033                                         slot_id, ep_index, ep_ring->stream_id,
2034                                         td, event_trb);
2035                 } else {
2036                         /* Update ring dequeue pointer */
2037                         while (ep_ring->dequeue != td->last_trb)
2038                                 inc_deq(xhci, ep_ring);
2039                         inc_deq(xhci, ep_ring);
2040                 }
2041
2042 td_cleanup:
2043                 /* Clean up the endpoint's TD list */
2044                 urb = td->urb;
2045                 urb_priv = urb->hcpriv;
2046
2047                 /* Do one last check of the actual transfer length.
2048                  * If the host controller said we transferred more data than
2049                  * the buffer length, urb->actual_length will be a very big
2050                  * number (since it's unsigned).  Play it safe and say we didn't
2051                  * transfer anything.
2052                  */
2053                 if (urb->actual_length > urb->transfer_buffer_length) {
2054                         xhci_warn(xhci, "URB transfer length is wrong, "
2055                                         "xHC issue? req. len = %u, "
2056                                         "act. len = %u\n",
2057                                         urb->transfer_buffer_length,
2058                                         urb->actual_length);
2059                         urb->actual_length = 0;
2060                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2061                                 *status = -EREMOTEIO;
2062                         else
2063                                 *status = 0;
2064                 }
2065                 list_del_init(&td->td_list);
2066                 /* Was this TD slated to be cancelled but completed anyway? */
2067                 if (!list_empty(&td->cancelled_td_list))
2068                         list_del_init(&td->cancelled_td_list);
2069
2070                 urb_priv->td_cnt++;
2071                 /* Giveback the urb when all the tds are completed */
2072                 if (urb_priv->td_cnt == urb_priv->length) {
2073                         ret = 1;
2074                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2075                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2076                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2077                                         == 0) {
2078                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
2079                                                 usb_amd_quirk_pll_enable();
2080                                 }
2081                         }
2082                 }
2083         }
2084
2085         return ret;
2086 }
2087
2088 /*
2089  * Process control tds, update urb status and actual_length.
2090  */
2091 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2092         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2093         struct xhci_virt_ep *ep, int *status)
2094 {
2095         struct xhci_virt_device *xdev;
2096         struct xhci_ring *ep_ring;
2097         unsigned int slot_id;
2098         int ep_index;
2099         struct xhci_ep_ctx *ep_ctx;
2100         u32 trb_comp_code;
2101
2102         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2103         xdev = xhci->devs[slot_id];
2104         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2105         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2106         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2107         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2108
2109         switch (trb_comp_code) {
2110         case COMP_SUCCESS:
2111                 if (event_trb == ep_ring->dequeue) {
2112                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2113                                         "without IOC set??\n");
2114                         *status = -ESHUTDOWN;
2115                 } else if (event_trb != td->last_trb) {
2116                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2117                                         "without IOC set??\n");
2118                         *status = -ESHUTDOWN;
2119                 } else {
2120                         *status = 0;
2121                 }
2122                 break;
2123         case COMP_SHORT_TX:
2124                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2125                         *status = -EREMOTEIO;
2126                 else
2127                         *status = 0;
2128                 break;
2129         case COMP_STOP_INVAL:
2130         case COMP_STOP:
2131                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2132         default:
2133                 if (!xhci_requires_manual_halt_cleanup(xhci,
2134                                         ep_ctx, trb_comp_code))
2135                         break;
2136                 xhci_dbg(xhci, "TRB error code %u, "
2137                                 "halted endpoint index = %u\n",
2138                                 trb_comp_code, ep_index);
2139                 /* else fall through */
2140         case COMP_STALL:
2141                 /* Did we transfer part of the data (middle) phase? */
2142                 if (event_trb != ep_ring->dequeue &&
2143                                 event_trb != td->last_trb)
2144                         td->urb->actual_length =
2145                                 td->urb->transfer_buffer_length -
2146                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2147                 else
2148                         td->urb->actual_length = 0;
2149
2150                 xhci_cleanup_halted_endpoint(xhci,
2151                         slot_id, ep_index, 0, td, event_trb);
2152                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2153         }
2154         /*
2155          * Did we transfer any data, despite the errors that might have
2156          * happened?  I.e. did we get past the setup stage?
2157          */
2158         if (event_trb != ep_ring->dequeue) {
2159                 /* The event was for the status stage */
2160                 if (event_trb == td->last_trb) {
2161                         if (td->urb->actual_length != 0) {
2162                                 /* Don't overwrite a previously set error code
2163                                  */
2164                                 if ((*status == -EINPROGRESS || *status == 0) &&
2165                                                 (td->urb->transfer_flags
2166                                                  & URB_SHORT_NOT_OK))
2167                                         /* Did we already see a short data
2168                                          * stage? */
2169                                         *status = -EREMOTEIO;
2170                         } else {
2171                                 td->urb->actual_length =
2172                                         td->urb->transfer_buffer_length;
2173                         }
2174                 } else {
2175                 /* Maybe the event was for the data stage? */
2176                         td->urb->actual_length =
2177                                 td->urb->transfer_buffer_length -
2178                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2179                         xhci_dbg(xhci, "Waiting for status "
2180                                         "stage event\n");
2181                         return 0;
2182                 }
2183         }
2184
2185         return finish_td(xhci, td, event_trb, event, ep, status, false);
2186 }
2187
2188 /*
2189  * Process isochronous tds, update urb packet status and actual_length.
2190  */
2191 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2192         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2193         struct xhci_virt_ep *ep, int *status)
2194 {
2195         struct xhci_ring *ep_ring;
2196         struct urb_priv *urb_priv;
2197         int idx;
2198         int len = 0;
2199         union xhci_trb *cur_trb;
2200         struct xhci_segment *cur_seg;
2201         struct usb_iso_packet_descriptor *frame;
2202         u32 trb_comp_code;
2203         bool skip_td = false;
2204
2205         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2206         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2207         urb_priv = td->urb->hcpriv;
2208         idx = urb_priv->td_cnt;
2209         frame = &td->urb->iso_frame_desc[idx];
2210
2211         /* handle completion code */
2212         switch (trb_comp_code) {
2213         case COMP_SUCCESS:
2214                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2215                         frame->status = 0;
2216                         break;
2217                 }
2218                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2219                         trb_comp_code = COMP_SHORT_TX;
2220         case COMP_SHORT_TX:
2221                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2222                                 -EREMOTEIO : 0;
2223                 break;
2224         case COMP_BW_OVER:
2225                 frame->status = -ECOMM;
2226                 skip_td = true;
2227                 break;
2228         case COMP_BUFF_OVER:
2229         case COMP_BABBLE:
2230                 frame->status = -EOVERFLOW;
2231                 skip_td = true;
2232                 break;
2233         case COMP_DEV_ERR:
2234         case COMP_STALL:
2235         case COMP_TX_ERR:
2236                 frame->status = -EPROTO;
2237                 skip_td = true;
2238                 break;
2239         case COMP_STOP:
2240         case COMP_STOP_INVAL:
2241                 break;
2242         default:
2243                 frame->status = -1;
2244                 break;
2245         }
2246
2247         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2248                 frame->actual_length = frame->length;
2249                 td->urb->actual_length += frame->length;
2250         } else {
2251                 for (cur_trb = ep_ring->dequeue,
2252                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2253                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2254                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2255                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2256                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2257                 }
2258                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2259                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2260
2261                 if (trb_comp_code != COMP_STOP_INVAL) {
2262                         frame->actual_length = len;
2263                         td->urb->actual_length += len;
2264                 }
2265         }
2266
2267         return finish_td(xhci, td, event_trb, event, ep, status, false);
2268 }
2269
2270 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2271                         struct xhci_transfer_event *event,
2272                         struct xhci_virt_ep *ep, int *status)
2273 {
2274         struct xhci_ring *ep_ring;
2275         struct urb_priv *urb_priv;
2276         struct usb_iso_packet_descriptor *frame;
2277         int idx;
2278
2279         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2280         urb_priv = td->urb->hcpriv;
2281         idx = urb_priv->td_cnt;
2282         frame = &td->urb->iso_frame_desc[idx];
2283
2284         /* The transfer is partly done. */
2285         frame->status = -EXDEV;
2286
2287         /* calc actual length */
2288         frame->actual_length = 0;
2289
2290         /* Update ring dequeue pointer */
2291         while (ep_ring->dequeue != td->last_trb)
2292                 inc_deq(xhci, ep_ring);
2293         inc_deq(xhci, ep_ring);
2294
2295         return finish_td(xhci, td, NULL, event, ep, status, true);
2296 }
2297
2298 /*
2299  * Process bulk and interrupt tds, update urb status and actual_length.
2300  */
2301 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2302         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2303         struct xhci_virt_ep *ep, int *status)
2304 {
2305         struct xhci_ring *ep_ring;
2306         union xhci_trb *cur_trb;
2307         struct xhci_segment *cur_seg;
2308         u32 trb_comp_code;
2309
2310         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2311         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2312
2313         switch (trb_comp_code) {
2314         case COMP_SUCCESS:
2315                 /* Double check that the HW transferred everything. */
2316                 if (event_trb != td->last_trb ||
2317                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2318                         xhci_warn(xhci, "WARN Successful completion "
2319                                         "on short TX\n");
2320                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2321                                 *status = -EREMOTEIO;
2322                         else
2323                                 *status = 0;
2324                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2325                                 trb_comp_code = COMP_SHORT_TX;
2326                 } else {
2327                         *status = 0;
2328                 }
2329                 break;
2330         case COMP_SHORT_TX:
2331                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2332                         *status = -EREMOTEIO;
2333                 else
2334                         *status = 0;
2335                 break;
2336         default:
2337                 /* Others already handled above */
2338                 break;
2339         }
2340         if (trb_comp_code == COMP_SHORT_TX)
2341                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2342                                 "%d bytes untransferred\n",
2343                                 td->urb->ep->desc.bEndpointAddress,
2344                                 td->urb->transfer_buffer_length,
2345                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2346         /* Fast path - was this the last TRB in the TD for this URB? */
2347         if (event_trb == td->last_trb) {
2348                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2349                         td->urb->actual_length =
2350                                 td->urb->transfer_buffer_length -
2351                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2352                         if (td->urb->transfer_buffer_length <
2353                                         td->urb->actual_length) {
2354                                 xhci_warn(xhci, "HC gave bad length "
2355                                                 "of %d bytes left\n",
2356                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2357                                 td->urb->actual_length = 0;
2358                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2359                                         *status = -EREMOTEIO;
2360                                 else
2361                                         *status = 0;
2362                         }
2363                         /* Don't overwrite a previously set error code */
2364                         if (*status == -EINPROGRESS) {
2365                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2366                                         *status = -EREMOTEIO;
2367                                 else
2368                                         *status = 0;
2369                         }
2370                 } else {
2371                         td->urb->actual_length =
2372                                 td->urb->transfer_buffer_length;
2373                         /* Ignore a short packet completion if the
2374                          * untransferred length was zero.
2375                          */
2376                         if (*status == -EREMOTEIO)
2377                                 *status = 0;
2378                 }
2379         } else {
2380                 /* Slow path - walk the list, starting from the dequeue
2381                  * pointer, to get the actual length transferred.
2382                  */
2383                 td->urb->actual_length = 0;
2384                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2385                                 cur_trb != event_trb;
2386                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2387                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2388                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2389                                 td->urb->actual_length +=
2390                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2391                 }
2392                 /* If the ring didn't stop on a Link or No-op TRB, add
2393                  * in the actual bytes transferred from the Normal TRB
2394                  */
2395                 if (trb_comp_code != COMP_STOP_INVAL)
2396                         td->urb->actual_length +=
2397                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2398                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2399         }
2400
2401         return finish_td(xhci, td, event_trb, event, ep, status, false);
2402 }
2403
2404 /*
2405  * If this function returns an error condition, it means it got a Transfer
2406  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2407  * At this point, the host controller is probably hosed and should be reset.
2408  */
2409 static int handle_tx_event(struct xhci_hcd *xhci,
2410                 struct xhci_transfer_event *event)
2411         __releases(&xhci->lock)
2412         __acquires(&xhci->lock)
2413 {
2414         struct xhci_virt_device *xdev;
2415         struct xhci_virt_ep *ep;
2416         struct xhci_ring *ep_ring;
2417         unsigned int slot_id;
2418         int ep_index;
2419         struct xhci_td *td = NULL;
2420         dma_addr_t event_dma;
2421         struct xhci_segment *event_seg;
2422         union xhci_trb *event_trb;
2423         struct urb *urb = NULL;
2424         int status = -EINPROGRESS;
2425         struct urb_priv *urb_priv;
2426         struct xhci_ep_ctx *ep_ctx;
2427         struct list_head *tmp;
2428         u32 trb_comp_code;
2429         int ret = 0;
2430         int td_num = 0;
2431
2432         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2433         xdev = xhci->devs[slot_id];
2434         if (!xdev) {
2435                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2436                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2437                          (unsigned long long) xhci_trb_virt_to_dma(
2438                                  xhci->event_ring->deq_seg,
2439                                  xhci->event_ring->dequeue),
2440                          lower_32_bits(le64_to_cpu(event->buffer)),
2441                          upper_32_bits(le64_to_cpu(event->buffer)),
2442                          le32_to_cpu(event->transfer_len),
2443                          le32_to_cpu(event->flags));
2444                 xhci_dbg(xhci, "Event ring:\n");
2445                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2446                 return -ENODEV;
2447         }
2448
2449         /* Endpoint ID is 1 based, our index is zero based */
2450         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2451         ep = &xdev->eps[ep_index];
2452         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2453         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2454         if (!ep_ring ||
2455             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2456             EP_STATE_DISABLED) {
2457                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2458                                 "or incorrect stream ring\n");
2459                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2460                          (unsigned long long) xhci_trb_virt_to_dma(
2461                                  xhci->event_ring->deq_seg,
2462                                  xhci->event_ring->dequeue),
2463                          lower_32_bits(le64_to_cpu(event->buffer)),
2464                          upper_32_bits(le64_to_cpu(event->buffer)),
2465                          le32_to_cpu(event->transfer_len),
2466                          le32_to_cpu(event->flags));
2467                 xhci_dbg(xhci, "Event ring:\n");
2468                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2469                 return -ENODEV;
2470         }
2471
2472         /* Count current td numbers if ep->skip is set */
2473         if (ep->skip) {
2474                 list_for_each(tmp, &ep_ring->td_list)
2475                         td_num++;
2476         }
2477
2478         event_dma = le64_to_cpu(event->buffer);
2479         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2480         /* Look for common error cases */
2481         switch (trb_comp_code) {
2482         /* Skip codes that require special handling depending on
2483          * transfer type
2484          */
2485         case COMP_SUCCESS:
2486                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2487                         break;
2488                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2489                         trb_comp_code = COMP_SHORT_TX;
2490                 else
2491                         xhci_warn_ratelimited(xhci,
2492                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2493         case COMP_SHORT_TX:
2494                 break;
2495         case COMP_STOP:
2496                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2497                 break;
2498         case COMP_STOP_INVAL:
2499                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2500                 break;
2501         case COMP_STALL:
2502                 xhci_dbg(xhci, "Stalled endpoint\n");
2503                 ep->ep_state |= EP_HALTED;
2504                 status = -EPIPE;
2505                 break;
2506         case COMP_TRB_ERR:
2507                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2508                 status = -EILSEQ;
2509                 break;
2510         case COMP_SPLIT_ERR:
2511         case COMP_TX_ERR:
2512                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2513                 status = -EPROTO;
2514                 break;
2515         case COMP_BABBLE:
2516                 xhci_dbg(xhci, "Babble error on endpoint\n");
2517                 status = -EOVERFLOW;
2518                 break;
2519         case COMP_DB_ERR:
2520                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2521                 status = -ENOSR;
2522                 break;
2523         case COMP_BW_OVER:
2524                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2525                 break;
2526         case COMP_BUFF_OVER:
2527                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2528                 break;
2529         case COMP_UNDERRUN:
2530                 /*
2531                  * When the Isoch ring is empty, the xHC will generate
2532                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2533                  * Underrun Event for OUT Isoch endpoint.
2534                  */
2535                 xhci_dbg(xhci, "underrun event on endpoint\n");
2536                 if (!list_empty(&ep_ring->td_list))
2537                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2538                                         "still with TDs queued?\n",
2539                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2540                                  ep_index);
2541                 goto cleanup;
2542         case COMP_OVERRUN:
2543                 xhci_dbg(xhci, "overrun event on endpoint\n");
2544                 if (!list_empty(&ep_ring->td_list))
2545                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2546                                         "still with TDs queued?\n",
2547                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2548                                  ep_index);
2549                 goto cleanup;
2550         case COMP_DEV_ERR:
2551                 xhci_warn(xhci, "WARN: detect an incompatible device");
2552                 status = -EPROTO;
2553                 break;
2554         case COMP_MISSED_INT:
2555                 /*
2556                  * When encounter missed service error, one or more isoc tds
2557                  * may be missed by xHC.
2558                  * Set skip flag of the ep_ring; Complete the missed tds as
2559                  * short transfer when process the ep_ring next time.
2560                  */
2561                 ep->skip = true;
2562                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2563                 goto cleanup;
2564         default:
2565                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2566                         status = 0;
2567                         break;
2568                 }
2569                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2570                                 "busted\n");
2571                 goto cleanup;
2572         }
2573
2574         do {
2575                 /* This TRB should be in the TD at the head of this ring's
2576                  * TD list.
2577                  */
2578                 if (list_empty(&ep_ring->td_list)) {
2579                         /*
2580                          * A stopped endpoint may generate an extra completion
2581                          * event if the device was suspended.  Don't print
2582                          * warnings.
2583                          */
2584                         if (!(trb_comp_code == COMP_STOP ||
2585                                                 trb_comp_code == COMP_STOP_INVAL)) {
2586                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2587                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2588                                                 ep_index);
2589                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2590                                                 (le32_to_cpu(event->flags) &
2591                                                  TRB_TYPE_BITMASK)>>10);
2592                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2593                         }
2594                         if (ep->skip) {
2595                                 ep->skip = false;
2596                                 xhci_dbg(xhci, "td_list is empty while skip "
2597                                                 "flag set. Clear skip flag.\n");
2598                         }
2599                         ret = 0;
2600                         goto cleanup;
2601                 }
2602
2603                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2604                 if (ep->skip && td_num == 0) {
2605                         ep->skip = false;
2606                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2607                                                 "Clear skip flag.\n");
2608                         ret = 0;
2609                         goto cleanup;
2610                 }
2611
2612                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2613                 if (ep->skip)
2614                         td_num--;
2615
2616                 /* Is this a TRB in the currently executing TD? */
2617                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2618                                 td->last_trb, event_dma);
2619
2620                 /*
2621                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2622                  * is not in the current TD pointed by ep_ring->dequeue because
2623                  * that the hardware dequeue pointer still at the previous TRB
2624                  * of the current TD. The previous TRB maybe a Link TD or the
2625                  * last TRB of the previous TD. The command completion handle
2626                  * will take care the rest.
2627                  */
2628                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2629                         ret = 0;
2630                         goto cleanup;
2631                 }
2632
2633                 if (!event_seg) {
2634                         if (!ep->skip ||
2635                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2636                                 /* Some host controllers give a spurious
2637                                  * successful event after a short transfer.
2638                                  * Ignore it.
2639                                  */
2640                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2641                                                 ep_ring->last_td_was_short) {
2642                                         ep_ring->last_td_was_short = false;
2643                                         ret = 0;
2644                                         goto cleanup;
2645                                 }
2646                                 /* HC is busted, give up! */
2647                                 xhci_err(xhci,
2648                                         "ERROR Transfer event TRB DMA ptr not "
2649                                         "part of current TD\n");
2650                                 return -ESHUTDOWN;
2651                         }
2652
2653                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2654                         goto cleanup;
2655                 }
2656                 if (trb_comp_code == COMP_SHORT_TX)
2657                         ep_ring->last_td_was_short = true;
2658                 else
2659                         ep_ring->last_td_was_short = false;
2660
2661                 if (ep->skip) {
2662                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2663                         ep->skip = false;
2664                 }
2665
2666                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2667                                                 sizeof(*event_trb)];
2668                 /*
2669                  * No-op TRB should not trigger interrupts.
2670                  * If event_trb is a no-op TRB, it means the
2671                  * corresponding TD has been cancelled. Just ignore
2672                  * the TD.
2673                  */
2674                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2675                         xhci_dbg(xhci,
2676                                  "event_trb is a no-op TRB. Skip it\n");
2677                         goto cleanup;
2678                 }
2679
2680                 /* Now update the urb's actual_length and give back to
2681                  * the core
2682                  */
2683                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2684                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2685                                                  &status);
2686                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2687                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2688                                                  &status);
2689                 else
2690                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2691                                                  ep, &status);
2692
2693 cleanup:
2694                 /*
2695                  * Do not update event ring dequeue pointer if ep->skip is set.
2696                  * Will roll back to continue process missed tds.
2697                  */
2698                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2699                         inc_deq(xhci, xhci->event_ring);
2700                 }
2701
2702                 if (ret) {
2703                         urb = td->urb;
2704                         urb_priv = urb->hcpriv;
2705                         /* Leave the TD around for the reset endpoint function
2706                          * to use(but only if it's not a control endpoint,
2707                          * since we already queued the Set TR dequeue pointer
2708                          * command for stalled control endpoints).
2709                          */
2710                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2711                                 (trb_comp_code != COMP_STALL &&
2712                                         trb_comp_code != COMP_BABBLE))
2713                                 xhci_urb_free_priv(xhci, urb_priv);
2714                         else
2715                                 kfree(urb_priv);
2716
2717                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2718                         if ((urb->actual_length != urb->transfer_buffer_length &&
2719                                                 (urb->transfer_flags &
2720                                                  URB_SHORT_NOT_OK)) ||
2721                                         (status != 0 &&
2722                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2723                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2724                                                 "expected = %d, status = %d\n",
2725                                                 urb, urb->actual_length,
2726                                                 urb->transfer_buffer_length,
2727                                                 status);
2728                         spin_unlock(&xhci->lock);
2729                         /* EHCI, UHCI, and OHCI always unconditionally set the
2730                          * urb->status of an isochronous endpoint to 0.
2731                          */
2732                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2733                                 status = 0;
2734                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2735                         spin_lock(&xhci->lock);
2736                 }
2737
2738         /*
2739          * If ep->skip is set, it means there are missed tds on the
2740          * endpoint ring need to take care of.
2741          * Process them as short transfer until reach the td pointed by
2742          * the event.
2743          */
2744         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2745
2746         return 0;
2747 }
2748
2749 /*
2750  * This function handles all OS-owned events on the event ring.  It may drop
2751  * xhci->lock between event processing (e.g. to pass up port status changes).
2752  * Returns >0 for "possibly more events to process" (caller should call again),
2753  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2754  */
2755 static int xhci_handle_event(struct xhci_hcd *xhci)
2756 {
2757         union xhci_trb *event;
2758         int update_ptrs = 1;
2759         int ret;
2760
2761         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2762                 xhci->error_bitmask |= 1 << 1;
2763                 return 0;
2764         }
2765
2766         event = xhci->event_ring->dequeue;
2767         /* Does the HC or OS own the TRB? */
2768         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2769             xhci->event_ring->cycle_state) {
2770                 xhci->error_bitmask |= 1 << 2;
2771                 return 0;
2772         }
2773
2774         /*
2775          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2776          * speculative reads of the event's flags/data below.
2777          */
2778         rmb();
2779         /* FIXME: Handle more event types. */
2780         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2781         case TRB_TYPE(TRB_COMPLETION):
2782                 handle_cmd_completion(xhci, &event->event_cmd);
2783                 break;
2784         case TRB_TYPE(TRB_PORT_STATUS):
2785                 handle_port_status(xhci, event);
2786                 update_ptrs = 0;
2787                 break;
2788         case TRB_TYPE(TRB_TRANSFER):
2789                 ret = handle_tx_event(xhci, &event->trans_event);
2790                 if (ret < 0)
2791                         xhci->error_bitmask |= 1 << 9;
2792                 else
2793                         update_ptrs = 0;
2794                 break;
2795         case TRB_TYPE(TRB_DEV_NOTE):
2796                 handle_device_notification(xhci, event);
2797                 break;
2798         default:
2799                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2800                     TRB_TYPE(48))
2801                         handle_vendor_event(xhci, event);
2802                 else
2803                         xhci->error_bitmask |= 1 << 3;
2804         }
2805         /* Any of the above functions may drop and re-acquire the lock, so check
2806          * to make sure a watchdog timer didn't mark the host as non-responsive.
2807          */
2808         if (xhci->xhc_state & XHCI_STATE_DYING) {
2809                 xhci_dbg(xhci, "xHCI host dying, returning from "
2810                                 "event handler.\n");
2811                 return 0;
2812         }
2813
2814         if (update_ptrs)
2815                 /* Update SW event ring dequeue pointer */
2816                 inc_deq(xhci, xhci->event_ring);
2817
2818         /* Are there more items on the event ring?  Caller will call us again to
2819          * check.
2820          */
2821         return 1;
2822 }
2823
2824 /*
2825  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2826  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2827  * indicators of an event TRB error, but we check the status *first* to be safe.
2828  */
2829 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2830 {
2831         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2832         u32 status;
2833         u64 temp_64;
2834         union xhci_trb *event_ring_deq;
2835         dma_addr_t deq;
2836
2837         spin_lock(&xhci->lock);
2838         /* Check if the xHC generated the interrupt, or the irq is shared */
2839         status = readl(&xhci->op_regs->status);
2840         if (status == 0xffffffff)
2841                 goto hw_died;
2842
2843         if (!(status & STS_EINT)) {
2844                 spin_unlock(&xhci->lock);
2845                 return IRQ_NONE;
2846         }
2847         if (status & STS_FATAL) {
2848                 xhci_warn(xhci, "WARNING: Host System Error\n");
2849                 xhci_halt(xhci);
2850 hw_died:
2851                 spin_unlock(&xhci->lock);
2852                 return -ESHUTDOWN;
2853         }
2854
2855         /*
2856          * Clear the op reg interrupt status first,
2857          * so we can receive interrupts from other MSI-X interrupters.
2858          * Write 1 to clear the interrupt status.
2859          */
2860         status |= STS_EINT;
2861         writel(status, &xhci->op_regs->status);
2862         /* FIXME when MSI-X is supported and there are multiple vectors */
2863         /* Clear the MSI-X event interrupt status */
2864
2865         if (hcd->irq) {
2866                 u32 irq_pending;
2867                 /* Acknowledge the PCI interrupt */
2868                 irq_pending = readl(&xhci->ir_set->irq_pending);
2869                 irq_pending |= IMAN_IP;
2870                 writel(irq_pending, &xhci->ir_set->irq_pending);
2871         }
2872
2873         if (xhci->xhc_state & XHCI_STATE_DYING) {
2874                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2875                                 "Shouldn't IRQs be disabled?\n");
2876                 /* Clear the event handler busy flag (RW1C);
2877                  * the event ring should be empty.
2878                  */
2879                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2880                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2881                                 &xhci->ir_set->erst_dequeue);
2882                 spin_unlock(&xhci->lock);
2883
2884                 return IRQ_HANDLED;
2885         }
2886
2887         event_ring_deq = xhci->event_ring->dequeue;
2888         /* FIXME this should be a delayed service routine
2889          * that clears the EHB.
2890          */
2891         while (xhci_handle_event(xhci) > 0) {}
2892
2893         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2894         /* If necessary, update the HW's version of the event ring deq ptr. */
2895         if (event_ring_deq != xhci->event_ring->dequeue) {
2896                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2897                                 xhci->event_ring->dequeue);
2898                 if (deq == 0)
2899                         xhci_warn(xhci, "WARN something wrong with SW event "
2900                                         "ring dequeue ptr.\n");
2901                 /* Update HC event ring dequeue pointer */
2902                 temp_64 &= ERST_PTR_MASK;
2903                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2904         }
2905
2906         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2907         temp_64 |= ERST_EHB;
2908         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2909
2910         spin_unlock(&xhci->lock);
2911
2912         return IRQ_HANDLED;
2913 }
2914
2915 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2916 {
2917         return xhci_irq(hcd);
2918 }
2919
2920 /****           Endpoint Ring Operations        ****/
2921
2922 /*
2923  * Generic function for queueing a TRB on a ring.
2924  * The caller must have checked to make sure there's room on the ring.
2925  *
2926  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2927  *                      prepare_transfer()?
2928  */
2929 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2930                 bool more_trbs_coming,
2931                 u32 field1, u32 field2, u32 field3, u32 field4)
2932 {
2933         struct xhci_generic_trb *trb;
2934
2935         trb = &ring->enqueue->generic;
2936         trb->field[0] = cpu_to_le32(field1);
2937         trb->field[1] = cpu_to_le32(field2);
2938         trb->field[2] = cpu_to_le32(field3);
2939         trb->field[3] = cpu_to_le32(field4);
2940         inc_enq(xhci, ring, more_trbs_coming);
2941 }
2942
2943 /*
2944  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2945  * FIXME allocate segments if the ring is full.
2946  */
2947 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2948                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2949 {
2950         unsigned int num_trbs_needed;
2951
2952         /* Make sure the endpoint has been added to xHC schedule */
2953         switch (ep_state) {
2954         case EP_STATE_DISABLED:
2955                 /*
2956                  * USB core changed config/interfaces without notifying us,
2957                  * or hardware is reporting the wrong state.
2958                  */
2959                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2960                 return -ENOENT;
2961         case EP_STATE_ERROR:
2962                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2963                 /* FIXME event handling code for error needs to clear it */
2964                 /* XXX not sure if this should be -ENOENT or not */
2965                 return -EINVAL;
2966         case EP_STATE_HALTED:
2967                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2968         case EP_STATE_STOPPED:
2969         case EP_STATE_RUNNING:
2970                 break;
2971         default:
2972                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2973                 /*
2974                  * FIXME issue Configure Endpoint command to try to get the HC
2975                  * back into a known state.
2976                  */
2977                 return -EINVAL;
2978         }
2979
2980         while (1) {
2981                 if (room_on_ring(xhci, ep_ring, num_trbs))
2982                         break;
2983
2984                 if (ep_ring == xhci->cmd_ring) {
2985                         xhci_err(xhci, "Do not support expand command ring\n");
2986                         return -ENOMEM;
2987                 }
2988
2989                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2990                                 "ERROR no room on ep ring, try ring expansion");
2991                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2992                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2993                                         mem_flags)) {
2994                         xhci_err(xhci, "Ring expansion failed\n");
2995                         return -ENOMEM;
2996                 }
2997         }
2998
2999         if (enqueue_is_link_trb(ep_ring)) {
3000                 struct xhci_ring *ring = ep_ring;
3001                 union xhci_trb *next;
3002
3003                 next = ring->enqueue;
3004
3005                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
3006                         /* If we're not dealing with 0.95 hardware or isoc rings
3007                          * on AMD 0.96 host, clear the chain bit.
3008                          */
3009                         if (!xhci_link_trb_quirk(xhci) &&
3010                                         !(ring->type == TYPE_ISOC &&
3011                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
3012                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
3013                         else
3014                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
3015
3016                         wmb();
3017                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
3018
3019                         /* Toggle the cycle bit after the last ring segment. */
3020                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
3021                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
3022                         }
3023                         ring->enq_seg = ring->enq_seg->next;
3024                         ring->enqueue = ring->enq_seg->trbs;
3025                         next = ring->enqueue;
3026                 }
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int prepare_transfer(struct xhci_hcd *xhci,
3033                 struct xhci_virt_device *xdev,
3034                 unsigned int ep_index,
3035                 unsigned int stream_id,
3036                 unsigned int num_trbs,
3037                 struct urb *urb,
3038                 unsigned int td_index,
3039                 gfp_t mem_flags)
3040 {
3041         int ret;
3042         struct urb_priv *urb_priv;
3043         struct xhci_td  *td;
3044         struct xhci_ring *ep_ring;
3045         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3046
3047         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3048         if (!ep_ring) {
3049                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3050                                 stream_id);
3051                 return -EINVAL;
3052         }
3053
3054         ret = prepare_ring(xhci, ep_ring,
3055                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3056                            num_trbs, mem_flags);
3057         if (ret)
3058                 return ret;
3059
3060         urb_priv = urb->hcpriv;
3061         td = urb_priv->td[td_index];
3062
3063         INIT_LIST_HEAD(&td->td_list);
3064         INIT_LIST_HEAD(&td->cancelled_td_list);
3065
3066         if (td_index == 0) {
3067                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3068                 if (unlikely(ret))
3069                         return ret;
3070         }
3071
3072         td->urb = urb;
3073         /* Add this TD to the tail of the endpoint ring's TD list */
3074         list_add_tail(&td->td_list, &ep_ring->td_list);
3075         td->start_seg = ep_ring->enq_seg;
3076         td->first_trb = ep_ring->enqueue;
3077
3078         urb_priv->td[td_index] = td;
3079
3080         return 0;
3081 }
3082
3083 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3084 {
3085         int num_sgs, num_trbs, running_total, temp, i;
3086         struct scatterlist *sg;
3087
3088         sg = NULL;
3089         num_sgs = urb->num_mapped_sgs;
3090         temp = urb->transfer_buffer_length;
3091
3092         num_trbs = 0;
3093         for_each_sg(urb->sg, sg, num_sgs, i) {
3094                 unsigned int len = sg_dma_len(sg);
3095
3096                 /* Scatter gather list entries may cross 64KB boundaries */
3097                 running_total = TRB_MAX_BUFF_SIZE -
3098                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3099                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3100                 if (running_total != 0)
3101                         num_trbs++;
3102
3103                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3104                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3105                         num_trbs++;
3106                         running_total += TRB_MAX_BUFF_SIZE;
3107                 }
3108                 len = min_t(int, len, temp);
3109                 temp -= len;
3110                 if (temp == 0)
3111                         break;
3112         }
3113         return num_trbs;
3114 }
3115
3116 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3117 {
3118         if (num_trbs != 0)
3119                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3120                                 "TRBs, %d left\n", __func__,
3121                                 urb->ep->desc.bEndpointAddress, num_trbs);
3122         if (running_total != urb->transfer_buffer_length)
3123                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3124                                 "queued %#x (%d), asked for %#x (%d)\n",
3125                                 __func__,
3126                                 urb->ep->desc.bEndpointAddress,
3127                                 running_total, running_total,
3128                                 urb->transfer_buffer_length,
3129                                 urb->transfer_buffer_length);
3130 }
3131
3132 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3133                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3134                 struct xhci_generic_trb *start_trb)
3135 {
3136         /*
3137          * Pass all the TRBs to the hardware at once and make sure this write
3138          * isn't reordered.
3139          */
3140         wmb();
3141         if (start_cycle)
3142                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3143         else
3144                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3145         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3146 }
3147
3148 /*
3149  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3150  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3151  * (comprised of sg list entries) can take several service intervals to
3152  * transmit.
3153  */
3154 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3155                 struct urb *urb, int slot_id, unsigned int ep_index)
3156 {
3157         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3158                         xhci->devs[slot_id]->out_ctx, ep_index);
3159         int xhci_interval;
3160         int ep_interval;
3161
3162         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3163         ep_interval = urb->interval;
3164         /* Convert to microframes */
3165         if (urb->dev->speed == USB_SPEED_LOW ||
3166                         urb->dev->speed == USB_SPEED_FULL)
3167                 ep_interval *= 8;
3168         /* FIXME change this to a warning and a suggestion to use the new API
3169          * to set the polling interval (once the API is added).
3170          */
3171         if (xhci_interval != ep_interval) {
3172                 dev_dbg_ratelimited(&urb->dev->dev,
3173                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3174                                 ep_interval, ep_interval == 1 ? "" : "s",
3175                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3176                 urb->interval = xhci_interval;
3177                 /* Convert back to frames for LS/FS devices */
3178                 if (urb->dev->speed == USB_SPEED_LOW ||
3179                                 urb->dev->speed == USB_SPEED_FULL)
3180                         urb->interval /= 8;
3181         }
3182         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3183 }
3184
3185 /*
3186  * The TD size is the number of bytes remaining in the TD (including this TRB),
3187  * right shifted by 10.
3188  * It must fit in bits 21:17, so it can't be bigger than 31.
3189  */
3190 static u32 xhci_td_remainder(unsigned int remainder)
3191 {
3192         u32 max = (1 << (21 - 17 + 1)) - 1;
3193
3194         if ((remainder >> 10) >= max)
3195                 return max << 17;
3196         else
3197                 return (remainder >> 10) << 17;
3198 }
3199
3200 /*
3201  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3202  * packets remaining in the TD (*not* including this TRB).
3203  *
3204  * Total TD packet count = total_packet_count =
3205  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3206  *
3207  * Packets transferred up to and including this TRB = packets_transferred =
3208  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3209  *
3210  * TD size = total_packet_count - packets_transferred
3211  *
3212  * It must fit in bits 21:17, so it can't be bigger than 31.
3213  * The last TRB in a TD must have the TD size set to zero.
3214  */
3215 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3216                 unsigned int total_packet_count, struct urb *urb,
3217                 unsigned int num_trbs_left)
3218 {
3219         int packets_transferred;
3220
3221         /* One TRB with a zero-length data packet. */
3222         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3223                 return 0;
3224
3225         /* All the TRB queueing functions don't count the current TRB in
3226          * running_total.
3227          */
3228         packets_transferred = (running_total + trb_buff_len) /
3229                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3230
3231         if ((total_packet_count - packets_transferred) > 31)
3232                 return 31 << 17;
3233         return (total_packet_count - packets_transferred) << 17;
3234 }
3235
3236 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3237                 struct urb *urb, int slot_id, unsigned int ep_index)
3238 {
3239         struct xhci_ring *ep_ring;
3240         unsigned int num_trbs;
3241         struct urb_priv *urb_priv;
3242         struct xhci_td *td;
3243         struct scatterlist *sg;
3244         int num_sgs;
3245         int trb_buff_len, this_sg_len, running_total;
3246         unsigned int total_packet_count;
3247         bool first_trb;
3248         u64 addr;
3249         bool more_trbs_coming;
3250
3251         struct xhci_generic_trb *start_trb;
3252         int start_cycle;
3253
3254         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3255         if (!ep_ring)
3256                 return -EINVAL;
3257
3258         num_trbs = count_sg_trbs_needed(xhci, urb);
3259         num_sgs = urb->num_mapped_sgs;
3260         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3261                         usb_endpoint_maxp(&urb->ep->desc));
3262
3263         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3264                         ep_index, urb->stream_id,
3265                         num_trbs, urb, 0, mem_flags);
3266         if (trb_buff_len < 0)
3267                 return trb_buff_len;
3268
3269         urb_priv = urb->hcpriv;
3270         td = urb_priv->td[0];
3271
3272         /*
3273          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3274          * until we've finished creating all the other TRBs.  The ring's cycle
3275          * state may change as we enqueue the other TRBs, so save it too.
3276          */
3277         start_trb = &ep_ring->enqueue->generic;
3278         start_cycle = ep_ring->cycle_state;
3279
3280         running_total = 0;
3281         /*
3282          * How much data is in the first TRB?
3283          *
3284          * There are three forces at work for TRB buffer pointers and lengths:
3285          * 1. We don't want to walk off the end of this sg-list entry buffer.
3286          * 2. The transfer length that the driver requested may be smaller than
3287          *    the amount of memory allocated for this scatter-gather list.
3288          * 3. TRBs buffers can't cross 64KB boundaries.
3289          */
3290         sg = urb->sg;
3291         addr = (u64) sg_dma_address(sg);
3292         this_sg_len = sg_dma_len(sg);
3293         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3294         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3295         if (trb_buff_len > urb->transfer_buffer_length)
3296                 trb_buff_len = urb->transfer_buffer_length;
3297
3298         first_trb = true;
3299         /* Queue the first TRB, even if it's zero-length */
3300         do {
3301                 u32 field = 0;
3302                 u32 length_field = 0;
3303                 u32 remainder = 0;
3304
3305                 /* Don't change the cycle bit of the first TRB until later */
3306                 if (first_trb) {
3307                         first_trb = false;
3308                         if (start_cycle == 0)
3309                                 field |= 0x1;
3310                 } else
3311                         field |= ep_ring->cycle_state;
3312
3313                 /* Chain all the TRBs together; clear the chain bit in the last
3314                  * TRB to indicate it's the last TRB in the chain.
3315                  */
3316                 if (num_trbs > 1) {
3317                         field |= TRB_CHAIN;
3318                 } else {
3319                         /* FIXME - add check for ZERO_PACKET flag before this */
3320                         td->last_trb = ep_ring->enqueue;
3321                         field |= TRB_IOC;
3322                 }
3323
3324                 /* Only set interrupt on short packet for IN endpoints */
3325                 if (usb_urb_dir_in(urb))
3326                         field |= TRB_ISP;
3327
3328                 if (TRB_MAX_BUFF_SIZE -
3329                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3330                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3331                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3332                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3333                                         (unsigned int) addr + trb_buff_len);
3334                 }
3335
3336                 /* Set the TRB length, TD size, and interrupter fields. */
3337                 if (xhci->hci_version < 0x100) {
3338                         remainder = xhci_td_remainder(
3339                                         urb->transfer_buffer_length -
3340                                         running_total);
3341                 } else {
3342                         remainder = xhci_v1_0_td_remainder(running_total,
3343                                         trb_buff_len, total_packet_count, urb,
3344                                         num_trbs - 1);
3345                 }
3346                 length_field = TRB_LEN(trb_buff_len) |
3347                         remainder |
3348                         TRB_INTR_TARGET(0);
3349
3350                 if (num_trbs > 1)
3351                         more_trbs_coming = true;
3352                 else
3353                         more_trbs_coming = false;
3354                 queue_trb(xhci, ep_ring, more_trbs_coming,
3355                                 lower_32_bits(addr),
3356                                 upper_32_bits(addr),
3357                                 length_field,
3358                                 field | TRB_TYPE(TRB_NORMAL));
3359                 --num_trbs;
3360                 running_total += trb_buff_len;
3361
3362                 /* Calculate length for next transfer --
3363                  * Are we done queueing all the TRBs for this sg entry?
3364                  */
3365                 this_sg_len -= trb_buff_len;
3366                 if (this_sg_len == 0) {
3367                         --num_sgs;
3368                         if (num_sgs == 0)
3369                                 break;
3370                         sg = sg_next(sg);
3371                         addr = (u64) sg_dma_address(sg);
3372                         this_sg_len = sg_dma_len(sg);
3373                 } else {
3374                         addr += trb_buff_len;
3375                 }
3376
3377                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3378                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3379                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3380                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3381                         trb_buff_len =
3382                                 urb->transfer_buffer_length - running_total;
3383         } while (running_total < urb->transfer_buffer_length);
3384
3385         check_trb_math(urb, num_trbs, running_total);
3386         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3387                         start_cycle, start_trb);
3388         return 0;
3389 }
3390
3391 /* This is very similar to what ehci-q.c qtd_fill() does */
3392 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3393                 struct urb *urb, int slot_id, unsigned int ep_index)
3394 {
3395         struct xhci_ring *ep_ring;
3396         struct urb_priv *urb_priv;
3397         struct xhci_td *td;
3398         int num_trbs;
3399         struct xhci_generic_trb *start_trb;
3400         bool first_trb;
3401         bool more_trbs_coming;
3402         int start_cycle;
3403         u32 field, length_field;
3404
3405         int running_total, trb_buff_len, ret;
3406         unsigned int total_packet_count;
3407         u64 addr;
3408
3409         if (urb->num_sgs)
3410                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3411
3412         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3413         if (!ep_ring)
3414                 return -EINVAL;
3415
3416         num_trbs = 0;
3417         /* How much data is (potentially) left before the 64KB boundary? */
3418         running_total = TRB_MAX_BUFF_SIZE -
3419                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3420         running_total &= TRB_MAX_BUFF_SIZE - 1;
3421
3422         /* If there's some data on this 64KB chunk, or we have to send a
3423          * zero-length transfer, we need at least one TRB
3424          */
3425         if (running_total != 0 || urb->transfer_buffer_length == 0)
3426                 num_trbs++;
3427         /* How many more 64KB chunks to transfer, how many more TRBs? */
3428         while (running_total < urb->transfer_buffer_length) {
3429                 num_trbs++;
3430                 running_total += TRB_MAX_BUFF_SIZE;
3431         }
3432         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3433
3434         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3435                         ep_index, urb->stream_id,
3436                         num_trbs, urb, 0, mem_flags);
3437         if (ret < 0)
3438                 return ret;
3439
3440         urb_priv = urb->hcpriv;
3441         td = urb_priv->td[0];
3442
3443         /*
3444          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3445          * until we've finished creating all the other TRBs.  The ring's cycle
3446          * state may change as we enqueue the other TRBs, so save it too.
3447          */
3448         start_trb = &ep_ring->enqueue->generic;
3449         start_cycle = ep_ring->cycle_state;
3450
3451         running_total = 0;
3452         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3453                         usb_endpoint_maxp(&urb->ep->desc));
3454         /* How much data is in the first TRB? */
3455         addr = (u64) urb->transfer_dma;
3456         trb_buff_len = TRB_MAX_BUFF_SIZE -
3457                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3458         if (trb_buff_len > urb->transfer_buffer_length)
3459                 trb_buff_len = urb->transfer_buffer_length;
3460
3461         first_trb = true;
3462
3463         /* Queue the first TRB, even if it's zero-length */
3464         do {
3465                 u32 remainder = 0;
3466                 field = 0;
3467
3468                 /* Don't change the cycle bit of the first TRB until later */
3469                 if (first_trb) {
3470                         first_trb = false;
3471                         if (start_cycle == 0)
3472                                 field |= 0x1;
3473                 } else
3474                         field |= ep_ring->cycle_state;
3475
3476                 /* Chain all the TRBs together; clear the chain bit in the last
3477                  * TRB to indicate it's the last TRB in the chain.
3478                  */
3479                 if (num_trbs > 1) {
3480                         field |= TRB_CHAIN;
3481                 } else {
3482                         /* FIXME - add check for ZERO_PACKET flag before this */
3483                         td->last_trb = ep_ring->enqueue;
3484                         field |= TRB_IOC;
3485                 }
3486
3487                 /* Only set interrupt on short packet for IN endpoints */
3488                 if (usb_urb_dir_in(urb))
3489                         field |= TRB_ISP;
3490
3491                 /* Set the TRB length, TD size, and interrupter fields. */
3492                 if (xhci->hci_version < 0x100) {
3493                         remainder = xhci_td_remainder(
3494                                         urb->transfer_buffer_length -
3495                                         running_total);
3496                 } else {
3497                         remainder = xhci_v1_0_td_remainder(running_total,
3498                                         trb_buff_len, total_packet_count, urb,
3499                                         num_trbs - 1);
3500                 }
3501                 length_field = TRB_LEN(trb_buff_len) |
3502                         remainder |
3503                         TRB_INTR_TARGET(0);
3504
3505                 if (num_trbs > 1)
3506                         more_trbs_coming = true;
3507                 else
3508                         more_trbs_coming = false;
3509                 queue_trb(xhci, ep_ring, more_trbs_coming,
3510                                 lower_32_bits(addr),
3511                                 upper_32_bits(addr),
3512                                 length_field,
3513                                 field | TRB_TYPE(TRB_NORMAL));
3514                 --num_trbs;
3515                 running_total += trb_buff_len;
3516
3517                 /* Calculate length for next transfer */
3518                 addr += trb_buff_len;
3519                 trb_buff_len = urb->transfer_buffer_length - running_total;
3520                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3521                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3522         } while (running_total < urb->transfer_buffer_length);
3523
3524         check_trb_math(urb, num_trbs, running_total);
3525         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3526                         start_cycle, start_trb);
3527         return 0;
3528 }
3529
3530 /* Caller must have locked xhci->lock */
3531 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3532                 struct urb *urb, int slot_id, unsigned int ep_index)
3533 {
3534         struct xhci_ring *ep_ring;
3535         int num_trbs;
3536         int ret;
3537         struct usb_ctrlrequest *setup;
3538         struct xhci_generic_trb *start_trb;
3539         int start_cycle;
3540         u32 field, length_field;
3541         struct urb_priv *urb_priv;
3542         struct xhci_td *td;
3543
3544         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3545         if (!ep_ring)
3546                 return -EINVAL;
3547
3548         /*
3549          * Need to copy setup packet into setup TRB, so we can't use the setup
3550          * DMA address.
3551          */
3552         if (!urb->setup_packet)
3553                 return -EINVAL;
3554
3555         /* 1 TRB for setup, 1 for status */
3556         num_trbs = 2;
3557         /*
3558          * Don't need to check if we need additional event data and normal TRBs,
3559          * since data in control transfers will never get bigger than 16MB
3560          * XXX: can we get a buffer that crosses 64KB boundaries?
3561          */
3562         if (urb->transfer_buffer_length > 0)
3563                 num_trbs++;
3564         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3565                         ep_index, urb->stream_id,
3566                         num_trbs, urb, 0, mem_flags);
3567         if (ret < 0)
3568                 return ret;
3569
3570         urb_priv = urb->hcpriv;
3571         td = urb_priv->td[0];
3572
3573         /*
3574          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3575          * until we've finished creating all the other TRBs.  The ring's cycle
3576          * state may change as we enqueue the other TRBs, so save it too.
3577          */
3578         start_trb = &ep_ring->enqueue->generic;
3579         start_cycle = ep_ring->cycle_state;
3580
3581         /* Queue setup TRB - see section 6.4.1.2.1 */
3582         /* FIXME better way to translate setup_packet into two u32 fields? */
3583         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3584         field = 0;
3585         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3586         if (start_cycle == 0)
3587                 field |= 0x1;
3588
3589         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3590         if (xhci->hci_version == 0x100) {
3591                 if (urb->transfer_buffer_length > 0) {
3592                         if (setup->bRequestType & USB_DIR_IN)
3593                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3594                         else
3595                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3596                 }
3597         }
3598
3599         queue_trb(xhci, ep_ring, true,
3600                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3601                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3602                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3603                   /* Immediate data in pointer */
3604                   field);
3605
3606         /* If there's data, queue data TRBs */
3607         /* Only set interrupt on short packet for IN endpoints */
3608         if (usb_urb_dir_in(urb))
3609                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3610         else
3611                 field = TRB_TYPE(TRB_DATA);
3612
3613         length_field = TRB_LEN(urb->transfer_buffer_length) |
3614                 xhci_td_remainder(urb->transfer_buffer_length) |
3615                 TRB_INTR_TARGET(0);
3616         if (urb->transfer_buffer_length > 0) {
3617                 if (setup->bRequestType & USB_DIR_IN)
3618                         field |= TRB_DIR_IN;
3619                 queue_trb(xhci, ep_ring, true,
3620                                 lower_32_bits(urb->transfer_dma),
3621                                 upper_32_bits(urb->transfer_dma),
3622                                 length_field,
3623                                 field | ep_ring->cycle_state);
3624         }
3625
3626         /* Save the DMA address of the last TRB in the TD */
3627         td->last_trb = ep_ring->enqueue;
3628
3629         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3630         /* If the device sent data, the status stage is an OUT transfer */
3631         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3632                 field = 0;
3633         else
3634                 field = TRB_DIR_IN;
3635         queue_trb(xhci, ep_ring, false,
3636                         0,
3637                         0,
3638                         TRB_INTR_TARGET(0),
3639                         /* Event on completion */
3640                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3641
3642         giveback_first_trb(xhci, slot_id, ep_index, 0,
3643                         start_cycle, start_trb);
3644         return 0;
3645 }
3646
3647 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3648                 struct urb *urb, int i)
3649 {
3650         int num_trbs = 0;
3651         u64 addr, td_len;
3652
3653         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3654         td_len = urb->iso_frame_desc[i].length;
3655
3656         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3657                         TRB_MAX_BUFF_SIZE);
3658         if (num_trbs == 0)
3659                 num_trbs++;
3660
3661         return num_trbs;
3662 }
3663
3664 /*
3665  * The transfer burst count field of the isochronous TRB defines the number of
3666  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3667  * devices can burst up to bMaxBurst number of packets per service interval.
3668  * This field is zero based, meaning a value of zero in the field means one
3669  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3670  * zero.  Only xHCI 1.0 host controllers support this field.
3671  */
3672 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3673                 struct usb_device *udev,
3674                 struct urb *urb, unsigned int total_packet_count)
3675 {
3676         unsigned int max_burst;
3677
3678         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3679                 return 0;
3680
3681         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3682         return roundup(total_packet_count, max_burst + 1) - 1;
3683 }
3684
3685 /*
3686  * Returns the number of packets in the last "burst" of packets.  This field is
3687  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3688  * the last burst packet count is equal to the total number of packets in the
3689  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3690  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3691  * contain 1 to (bMaxBurst + 1) packets.
3692  */
3693 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3694                 struct usb_device *udev,
3695                 struct urb *urb, unsigned int total_packet_count)
3696 {
3697         unsigned int max_burst;
3698         unsigned int residue;
3699
3700         if (xhci->hci_version < 0x100)
3701                 return 0;
3702
3703         switch (udev->speed) {
3704         case USB_SPEED_SUPER:
3705                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3706                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3707                 residue = total_packet_count % (max_burst + 1);
3708                 /* If residue is zero, the last burst contains (max_burst + 1)
3709                  * number of packets, but the TLBPC field is zero-based.
3710                  */
3711                 if (residue == 0)
3712                         return max_burst;
3713                 return residue - 1;
3714         default:
3715                 if (total_packet_count == 0)
3716                         return 0;
3717                 return total_packet_count - 1;
3718         }
3719 }
3720
3721 /* This is for isoc transfer */
3722 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3723                 struct urb *urb, int slot_id, unsigned int ep_index)
3724 {
3725         struct xhci_ring *ep_ring;
3726         struct urb_priv *urb_priv;
3727         struct xhci_td *td;
3728         int num_tds, trbs_per_td;
3729         struct xhci_generic_trb *start_trb;
3730         bool first_trb;
3731         int start_cycle;
3732         u32 field, length_field;
3733         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3734         u64 start_addr, addr;
3735         int i, j;
3736         bool more_trbs_coming;
3737
3738         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3739
3740         num_tds = urb->number_of_packets;
3741         if (num_tds < 1) {
3742                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3743                 return -EINVAL;
3744         }
3745
3746         start_addr = (u64) urb->transfer_dma;
3747         start_trb = &ep_ring->enqueue->generic;
3748         start_cycle = ep_ring->cycle_state;
3749
3750         urb_priv = urb->hcpriv;
3751         /* Queue the first TRB, even if it's zero-length */
3752         for (i = 0; i < num_tds; i++) {
3753                 unsigned int total_packet_count;
3754                 unsigned int burst_count;
3755                 unsigned int residue;
3756
3757                 first_trb = true;
3758                 running_total = 0;
3759                 addr = start_addr + urb->iso_frame_desc[i].offset;
3760                 td_len = urb->iso_frame_desc[i].length;
3761                 td_remain_len = td_len;
3762                 total_packet_count = DIV_ROUND_UP(td_len,
3763                                 GET_MAX_PACKET(
3764                                         usb_endpoint_maxp(&urb->ep->desc)));
3765                 /* A zero-length transfer still involves at least one packet. */
3766                 if (total_packet_count == 0)
3767                         total_packet_count++;
3768                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3769                                 total_packet_count);
3770                 residue = xhci_get_last_burst_packet_count(xhci,
3771                                 urb->dev, urb, total_packet_count);
3772
3773                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3774
3775                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3776                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3777                 if (ret < 0) {
3778                         if (i == 0)
3779                                 return ret;
3780                         goto cleanup;
3781                 }
3782
3783                 td = urb_priv->td[i];
3784                 for (j = 0; j < trbs_per_td; j++) {
3785                         u32 remainder = 0;
3786                         field = 0;
3787
3788                         if (first_trb) {
3789                                 field = TRB_TBC(burst_count) |
3790                                         TRB_TLBPC(residue);
3791                                 /* Queue the isoc TRB */
3792                                 field |= TRB_TYPE(TRB_ISOC);
3793                                 /* Assume URB_ISO_ASAP is set */
3794                                 field |= TRB_SIA;
3795                                 if (i == 0) {
3796                                         if (start_cycle == 0)
3797                                                 field |= 0x1;
3798                                 } else
3799                                         field |= ep_ring->cycle_state;
3800                                 first_trb = false;
3801                         } else {
3802                                 /* Queue other normal TRBs */
3803                                 field |= TRB_TYPE(TRB_NORMAL);
3804                                 field |= ep_ring->cycle_state;
3805                         }
3806
3807                         /* Only set interrupt on short packet for IN EPs */
3808                         if (usb_urb_dir_in(urb))
3809                                 field |= TRB_ISP;
3810
3811                         /* Chain all the TRBs together; clear the chain bit in
3812                          * the last TRB to indicate it's the last TRB in the
3813                          * chain.
3814                          */
3815                         if (j < trbs_per_td - 1) {
3816                                 field |= TRB_CHAIN;
3817                                 more_trbs_coming = true;
3818                         } else {
3819                                 td->last_trb = ep_ring->enqueue;
3820                                 field |= TRB_IOC;
3821                                 if (xhci->hci_version == 0x100 &&
3822                                                 !(xhci->quirks &
3823                                                         XHCI_AVOID_BEI)) {
3824                                         /* Set BEI bit except for the last td */
3825                                         if (i < num_tds - 1)
3826                                                 field |= TRB_BEI;
3827                                 }
3828                                 more_trbs_coming = false;
3829                         }
3830
3831                         /* Calculate TRB length */
3832                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3833                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3834                         if (trb_buff_len > td_remain_len)
3835                                 trb_buff_len = td_remain_len;
3836
3837                         /* Set the TRB length, TD size, & interrupter fields. */
3838                         if (xhci->hci_version < 0x100) {
3839                                 remainder = xhci_td_remainder(
3840                                                 td_len - running_total);
3841                         } else {
3842                                 remainder = xhci_v1_0_td_remainder(
3843                                                 running_total, trb_buff_len,
3844                                                 total_packet_count, urb,
3845                                                 (trbs_per_td - j - 1));
3846                         }
3847                         length_field = TRB_LEN(trb_buff_len) |
3848                                 remainder |
3849                                 TRB_INTR_TARGET(0);
3850
3851                         queue_trb(xhci, ep_ring, more_trbs_coming,
3852                                 lower_32_bits(addr),
3853                                 upper_32_bits(addr),
3854                                 length_field,
3855                                 field);
3856                         running_total += trb_buff_len;
3857
3858                         addr += trb_buff_len;
3859                         td_remain_len -= trb_buff_len;
3860                 }
3861
3862                 /* Check TD length */
3863                 if (running_total != td_len) {
3864                         xhci_err(xhci, "ISOC TD length unmatch\n");
3865                         ret = -EINVAL;
3866                         goto cleanup;
3867                 }
3868         }
3869
3870         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3871                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3872                         usb_amd_quirk_pll_disable();
3873         }
3874         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3875
3876         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3877                         start_cycle, start_trb);
3878         return 0;
3879 cleanup:
3880         /* Clean up a partially enqueued isoc transfer. */
3881
3882         for (i--; i >= 0; i--)
3883                 list_del_init(&urb_priv->td[i]->td_list);
3884
3885         /* Use the first TD as a temporary variable to turn the TDs we've queued
3886          * into No-ops with a software-owned cycle bit. That way the hardware
3887          * won't accidentally start executing bogus TDs when we partially
3888          * overwrite them.  td->first_trb and td->start_seg are already set.
3889          */
3890         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3891         /* Every TRB except the first & last will have its cycle bit flipped. */
3892         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3893
3894         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3895         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3896         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3897         ep_ring->cycle_state = start_cycle;
3898         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3899         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3900         return ret;
3901 }
3902
3903 /*
3904  * Check transfer ring to guarantee there is enough room for the urb.
3905  * Update ISO URB start_frame and interval.
3906  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3907  * update the urb->start_frame by now.
3908  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3909  */
3910 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3911                 struct urb *urb, int slot_id, unsigned int ep_index)
3912 {
3913         struct xhci_virt_device *xdev;
3914         struct xhci_ring *ep_ring;
3915         struct xhci_ep_ctx *ep_ctx;
3916         int start_frame;
3917         int xhci_interval;
3918         int ep_interval;
3919         int num_tds, num_trbs, i;
3920         int ret;
3921
3922         xdev = xhci->devs[slot_id];
3923         ep_ring = xdev->eps[ep_index].ring;
3924         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3925
3926         num_trbs = 0;
3927         num_tds = urb->number_of_packets;
3928         for (i = 0; i < num_tds; i++)
3929                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3930
3931         /* Check the ring to guarantee there is enough room for the whole urb.
3932          * Do not insert any td of the urb to the ring if the check failed.
3933          */
3934         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3935                            num_trbs, mem_flags);
3936         if (ret)
3937                 return ret;
3938
3939         start_frame = readl(&xhci->run_regs->microframe_index);
3940         start_frame &= 0x3fff;
3941
3942         urb->start_frame = start_frame;
3943         if (urb->dev->speed == USB_SPEED_LOW ||
3944                         urb->dev->speed == USB_SPEED_FULL)
3945                 urb->start_frame >>= 3;
3946
3947         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3948         ep_interval = urb->interval;
3949         /* Convert to microframes */
3950         if (urb->dev->speed == USB_SPEED_LOW ||
3951                         urb->dev->speed == USB_SPEED_FULL)
3952                 ep_interval *= 8;
3953         /* FIXME change this to a warning and a suggestion to use the new API
3954          * to set the polling interval (once the API is added).
3955          */
3956         if (xhci_interval != ep_interval) {
3957                 dev_dbg_ratelimited(&urb->dev->dev,
3958                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3959                                 ep_interval, ep_interval == 1 ? "" : "s",
3960                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3961                 urb->interval = xhci_interval;
3962                 /* Convert back to frames for LS/FS devices */
3963                 if (urb->dev->speed == USB_SPEED_LOW ||
3964                                 urb->dev->speed == USB_SPEED_FULL)
3965                         urb->interval /= 8;
3966         }
3967         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3968
3969         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3970 }
3971
3972 /****           Command Ring Operations         ****/
3973
3974 /* Generic function for queueing a command TRB on the command ring.
3975  * Check to make sure there's room on the command ring for one command TRB.
3976  * Also check that there's room reserved for commands that must not fail.
3977  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3978  * then only check for the number of reserved spots.
3979  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3980  * because the command event handler may want to resubmit a failed command.
3981  */
3982 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3983                 u32 field3, u32 field4, bool command_must_succeed)
3984 {
3985         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3986         int ret;
3987
3988         if (!command_must_succeed)
3989                 reserved_trbs++;
3990
3991         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3992                         reserved_trbs, GFP_ATOMIC);
3993         if (ret < 0) {
3994                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3995                 if (command_must_succeed)
3996                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3997                                         "unfailable commands failed.\n");
3998                 return ret;
3999         }
4000         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4001                         field4 | xhci->cmd_ring->cycle_state);
4002         return 0;
4003 }
4004
4005 /* Queue a slot enable or disable request on the command ring */
4006 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
4007 {
4008         return queue_command(xhci, 0, 0, 0,
4009                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4010 }
4011
4012 /* Queue an address device command TRB */
4013 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4014                               u32 slot_id, enum xhci_setup_dev setup)
4015 {
4016         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4017                         upper_32_bits(in_ctx_ptr), 0,
4018                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4019                         | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4020 }
4021
4022 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
4023                 u32 field1, u32 field2, u32 field3, u32 field4)
4024 {
4025         return queue_command(xhci, field1, field2, field3, field4, false);
4026 }
4027
4028 /* Queue a reset device command TRB */
4029 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
4030 {
4031         return queue_command(xhci, 0, 0, 0,
4032                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4033                         false);
4034 }
4035
4036 /* Queue a configure endpoint command TRB */
4037 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4038                 u32 slot_id, bool command_must_succeed)
4039 {
4040         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4041                         upper_32_bits(in_ctx_ptr), 0,
4042                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4043                         command_must_succeed);
4044 }
4045
4046 /* Queue an evaluate context command TRB */
4047 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4048                 u32 slot_id, bool command_must_succeed)
4049 {
4050         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4051                         upper_32_bits(in_ctx_ptr), 0,
4052                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4053                         command_must_succeed);
4054 }
4055
4056 /*
4057  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4058  * activity on an endpoint that is about to be suspended.
4059  */
4060 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
4061                 unsigned int ep_index, int suspend)
4062 {
4063         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4064         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4065         u32 type = TRB_TYPE(TRB_STOP_RING);
4066         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4067
4068         return queue_command(xhci, 0, 0, 0,
4069                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4070 }
4071
4072 /* Set Transfer Ring Dequeue Pointer command.
4073  * This should not be used for endpoints that have streams enabled.
4074  */
4075 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4076                 unsigned int ep_index, unsigned int stream_id,
4077                 struct xhci_segment *deq_seg,
4078                 union xhci_trb *deq_ptr, u32 cycle_state)
4079 {
4080         dma_addr_t addr;
4081         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4082         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4083         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4084         u32 trb_sct = 0;
4085         u32 type = TRB_TYPE(TRB_SET_DEQ);
4086         struct xhci_virt_ep *ep;
4087
4088         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4089         if (addr == 0) {
4090                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4091                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4092                                 deq_seg, deq_ptr);
4093                 return 0;
4094         }
4095         ep = &xhci->devs[slot_id]->eps[ep_index];
4096         if ((ep->ep_state & SET_DEQ_PENDING)) {
4097                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4098                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4099                 return 0;
4100         }
4101         ep->queued_deq_seg = deq_seg;
4102         ep->queued_deq_ptr = deq_ptr;
4103         if (stream_id)
4104                 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4105         return queue_command(xhci, lower_32_bits(addr) | trb_sct | cycle_state,
4106                         upper_32_bits(addr), trb_stream_id,
4107                         trb_slot_id | trb_ep_index | type, false);
4108 }
4109
4110 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4111                 unsigned int ep_index)
4112 {
4113         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4114         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4115         u32 type = TRB_TYPE(TRB_RESET_EP);
4116
4117         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4118                         false);
4119 }