2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
36 #define DRIVER_AUTHOR "Sarah Sharp"
37 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
39 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
41 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42 static int link_quirk;
43 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
46 static unsigned int quirks;
47 module_param(quirks, uint, S_IRUGO);
48 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
50 /* TODO: copied from ehci-hcd.c - can this be refactored? */
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70 if (result == ~(u32)0) /* card removed */
82 * Disable interrupts and begin the xHCI halting process.
84 void xhci_quiesce(struct xhci_hcd *xhci)
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 cmd = readl(&xhci->op_regs->command);
97 writel(cmd, &xhci->op_regs->command);
101 * Force HC into halt state.
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
108 int xhci_halt(struct xhci_hcd *xhci)
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
117 xhci_warn(xhci, "Host halt failed, %d\n", ret);
120 xhci->xhc_state |= XHCI_STATE_HALTED;
121 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
126 * Set the run bit and wait for the host to be running.
128 static int xhci_start(struct xhci_hcd *xhci)
133 temp = readl(&xhci->op_regs->command);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
137 writel(temp, &xhci->op_regs->command);
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
150 /* clear state flags. Including dying, halted or removing */
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd *xhci)
169 state = readl(&xhci->op_regs->status);
171 if (state == ~(u32)0) {
172 xhci_warn(xhci, "Host not accessible, reset failed.\n");
176 if ((state & STS_HALT) == 0) {
177 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
182 command = readl(&xhci->op_regs->command);
183 command |= CMD_RESET;
184 writel(command, &xhci->op_regs->command);
186 /* Existing Intel xHCI controllers require a delay of 1 mS,
187 * after setting the CMD_RESET bit, and before accessing any
188 * HC registers. This allows the HC to complete the
189 * reset operation and be ready for HC register access.
190 * Without this delay, the subsequent HC register access,
191 * may result in a system hang very rarely.
193 if (xhci->quirks & XHCI_INTEL_HOST)
196 ret = xhci_handshake(&xhci->op_regs->command,
197 CMD_RESET, 0, 10 * 1000 * 1000);
201 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
202 "Wait for controller to be ready for doorbell rings");
204 * xHCI cannot write to any doorbells or operational registers other
205 * than status until the "Controller Not Ready" flag is cleared.
207 ret = xhci_handshake(&xhci->op_regs->status,
208 STS_CNR, 0, 10 * 1000 * 1000);
210 for (i = 0; i < 2; i++) {
211 xhci->bus_state[i].port_c_suspend = 0;
212 xhci->bus_state[i].suspended_ports = 0;
213 xhci->bus_state[i].resuming_ports = 0;
220 static int xhci_free_msi(struct xhci_hcd *xhci)
224 if (!xhci->msix_entries)
227 for (i = 0; i < xhci->msix_count; i++)
228 if (xhci->msix_entries[i].vector)
229 free_irq(xhci->msix_entries[i].vector,
237 static int xhci_setup_msi(struct xhci_hcd *xhci)
240 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
242 ret = pci_enable_msi(pdev);
244 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
245 "failed to allocate MSI entry");
249 ret = request_irq(pdev->irq, xhci_msi_irq,
250 0, "xhci_hcd", xhci_to_hcd(xhci));
252 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
253 "disable MSI interrupt");
254 pci_disable_msi(pdev);
262 * free all IRQs request
264 static void xhci_free_irq(struct xhci_hcd *xhci)
266 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
269 /* return if using legacy interrupt */
270 if (xhci_to_hcd(xhci)->irq > 0)
273 ret = xhci_free_msi(xhci);
277 free_irq(pdev->irq, xhci_to_hcd(xhci));
285 static int xhci_setup_msix(struct xhci_hcd *xhci)
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
292 * calculate number of msi-x vectors supported.
293 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
294 * with max number of interrupters based on the xhci HCSPARAMS1.
295 * - num_online_cpus: maximum msi-x vectors per CPUs core.
296 * Add additional 1 vector to ensure always available interrupt.
298 xhci->msix_count = min(num_online_cpus() + 1,
299 HCS_MAX_INTRS(xhci->hcs_params1));
302 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
304 if (!xhci->msix_entries)
307 for (i = 0; i < xhci->msix_count; i++) {
308 xhci->msix_entries[i].entry = i;
309 xhci->msix_entries[i].vector = 0;
312 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "Failed to enable MSI-X");
319 for (i = 0; i < xhci->msix_count; i++) {
320 ret = request_irq(xhci->msix_entries[i].vector,
322 0, "xhci_hcd", xhci_to_hcd(xhci));
327 hcd->msix_enabled = 1;
331 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
333 pci_disable_msix(pdev);
335 kfree(xhci->msix_entries);
336 xhci->msix_entries = NULL;
340 /* Free any IRQs and disable MSI-X */
341 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
343 struct usb_hcd *hcd = xhci_to_hcd(xhci);
344 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
346 if (xhci->quirks & XHCI_PLAT)
351 if (xhci->msix_entries) {
352 pci_disable_msix(pdev);
353 kfree(xhci->msix_entries);
354 xhci->msix_entries = NULL;
356 pci_disable_msi(pdev);
359 hcd->msix_enabled = 0;
363 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
367 if (xhci->msix_entries) {
368 for (i = 0; i < xhci->msix_count; i++)
369 synchronize_irq(xhci->msix_entries[i].vector);
373 static int xhci_try_enable_msi(struct usb_hcd *hcd)
375 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
376 struct pci_dev *pdev;
379 /* The xhci platform device has set up IRQs through usb_add_hcd. */
380 if (xhci->quirks & XHCI_PLAT)
383 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
385 * Some Fresco Logic host controllers advertise MSI, but fail to
386 * generate interrupts. Don't even try to enable MSI.
388 if (xhci->quirks & XHCI_BROKEN_MSI)
391 /* unregister the legacy interrupt */
393 free_irq(hcd->irq, hcd);
396 ret = xhci_setup_msix(xhci);
398 /* fall back to msi*/
399 ret = xhci_setup_msi(xhci);
402 /* hcd->irq is 0, we have MSI */
406 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
411 if (!strlen(hcd->irq_descr))
412 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
413 hcd->driver->description, hcd->self.busnum);
415 /* fall back to legacy interrupt*/
416 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
417 hcd->irq_descr, hcd);
419 xhci_err(xhci, "request interrupt %d failed\n",
423 hcd->irq = pdev->irq;
429 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
434 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
438 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
444 static void compliance_mode_recovery(unsigned long arg)
446 struct xhci_hcd *xhci;
451 xhci = (struct xhci_hcd *)arg;
453 for (i = 0; i < xhci->num_usb3_ports; i++) {
454 temp = readl(xhci->usb3_ports[i]);
455 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
457 * Compliance Mode Detected. Letting USB Core
458 * handle the Warm Reset
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "Compliance mode detected->port %d",
463 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
464 "Attempting compliance mode recovery");
465 hcd = xhci->shared_hcd;
467 if (hcd->state == HC_STATE_SUSPENDED)
468 usb_hcd_resume_root_hub(hcd);
470 usb_hcd_poll_rh_status(hcd);
474 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
475 mod_timer(&xhci->comp_mode_recovery_timer,
476 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
480 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
481 * that causes ports behind that hardware to enter compliance mode sometimes.
482 * The quirk creates a timer that polls every 2 seconds the link state of
483 * each host controller's port and recovers it by issuing a Warm reset
484 * if Compliance mode is detected, otherwise the port will become "dead" (no
485 * device connections or disconnections will be detected anymore). Becasue no
486 * status event is generated when entering compliance mode (per xhci spec),
487 * this quirk is needed on systems that have the failing hardware installed.
489 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
491 xhci->port_status_u0 = 0;
492 setup_timer(&xhci->comp_mode_recovery_timer,
493 compliance_mode_recovery, (unsigned long)xhci);
494 xhci->comp_mode_recovery_timer.expires = jiffies +
495 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
497 add_timer(&xhci->comp_mode_recovery_timer);
498 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
499 "Compliance mode recovery timer initialized");
503 * This function identifies the systems that have installed the SN65LVPE502CP
504 * USB3.0 re-driver and that need the Compliance Mode Quirk.
506 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
508 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
510 const char *dmi_product_name, *dmi_sys_vendor;
512 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
513 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
514 if (!dmi_product_name || !dmi_sys_vendor)
517 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
520 if (strstr(dmi_product_name, "Z420") ||
521 strstr(dmi_product_name, "Z620") ||
522 strstr(dmi_product_name, "Z820") ||
523 strstr(dmi_product_name, "Z1 Workstation"))
529 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
531 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
536 * Initialize memory for HCD and xHC (one-time init).
538 * Program the PAGESIZE register, initialize the device context array, create
539 * device contexts (?), set up a command ring segment (or two?), create event
540 * ring (one for now).
542 int xhci_init(struct usb_hcd *hcd)
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
547 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
548 spin_lock_init(&xhci->lock);
549 if (xhci->hci_version == 0x95 && link_quirk) {
550 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
551 "QUIRK: Not clearing Link TRB chain bits.");
552 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
554 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
555 "xHCI doesn't need link TRB QUIRK");
557 retval = xhci_mem_init(xhci, GFP_KERNEL);
558 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
560 /* Initializing Compliance Mode Recovery Data If Needed */
561 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
562 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
563 compliance_mode_recovery_timer_init(xhci);
569 /*-------------------------------------------------------------------------*/
572 static int xhci_run_finished(struct xhci_hcd *xhci)
574 if (xhci_start(xhci)) {
578 xhci->shared_hcd->state = HC_STATE_RUNNING;
579 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
581 if (xhci->quirks & XHCI_NEC_HOST)
582 xhci_ring_cmd_db(xhci);
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
585 "Finished xhci_run for USB3 roothub");
590 * Start the HC after it was halted.
592 * This function is called by the USB core when the HC driver is added.
593 * Its opposite is xhci_stop().
595 * xhci_init() must be called once before this function can be called.
596 * Reset the HC, enable device slot contexts, program DCBAAP, and
597 * set command ring pointer and event ring pointer.
599 * Setup MSI-X vectors and enable interrupts.
601 int xhci_run(struct usb_hcd *hcd)
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
608 /* Start the xHCI host controller running only after the USB 2.0 roothub
612 hcd->uses_new_polling = 1;
613 if (!usb_hcd_is_primary_hcd(hcd))
614 return xhci_run_finished(xhci);
616 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
618 ret = xhci_try_enable_msi(hcd);
622 xhci_dbg(xhci, "Command ring memory map follows:\n");
623 xhci_debug_ring(xhci, xhci->cmd_ring);
624 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
625 xhci_dbg_cmd_ptrs(xhci);
627 xhci_dbg(xhci, "ERST memory map follows:\n");
628 xhci_dbg_erst(xhci, &xhci->erst);
629 xhci_dbg(xhci, "Event ring:\n");
630 xhci_debug_ring(xhci, xhci->event_ring);
631 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
632 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
633 temp_64 &= ~ERST_PTR_MASK;
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
637 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
638 "// Set the interrupt modulation register");
639 temp = readl(&xhci->ir_set->irq_control);
640 temp &= ~ER_IRQ_INTERVAL_MASK;
642 * the increment interval is 8 times as much as that defined
643 * in xHCI spec on MTK's controller
645 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
646 writel(temp, &xhci->ir_set->irq_control);
648 /* Set the HCD state before we enable the irqs */
649 temp = readl(&xhci->op_regs->command);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enable interrupts, cmd = 0x%x.", temp);
653 writel(temp, &xhci->op_regs->command);
655 temp = readl(&xhci->ir_set->irq_pending);
656 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
657 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
658 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
659 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
660 xhci_print_ir_set(xhci, 0);
662 if (xhci->quirks & XHCI_NEC_HOST) {
663 struct xhci_command *command;
664 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
667 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
668 TRB_TYPE(TRB_NEC_GET_FW));
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "Finished xhci_run for USB2 roothub");
674 EXPORT_SYMBOL_GPL(xhci_run);
679 * This function is called by the USB core when the HC driver is removed.
680 * Its opposite is xhci_run().
682 * Disable device contexts, disable IRQs, and quiesce the HC.
683 * Reset the HC, finish any completed transactions, and cleanup memory.
685 void xhci_stop(struct usb_hcd *hcd)
688 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
690 mutex_lock(&xhci->mutex);
692 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
693 spin_lock_irq(&xhci->lock);
695 xhci->xhc_state |= XHCI_STATE_HALTED;
696 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
699 spin_unlock_irq(&xhci->lock);
702 if (!usb_hcd_is_primary_hcd(hcd)) {
703 mutex_unlock(&xhci->mutex);
707 xhci_cleanup_msix(xhci);
709 /* Deleting Compliance Mode Recovery Timer */
710 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
711 (!(xhci_all_ports_seen_u0(xhci)))) {
712 del_timer_sync(&xhci->comp_mode_recovery_timer);
713 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
714 "%s: compliance mode recovery timer deleted",
718 if (xhci->quirks & XHCI_AMD_PLL_FIX)
721 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
722 "// Disabling event ring interrupts");
723 temp = readl(&xhci->op_regs->status);
724 writel(temp & ~STS_EINT, &xhci->op_regs->status);
725 temp = readl(&xhci->ir_set->irq_pending);
726 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
727 xhci_print_ir_set(xhci, 0);
729 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
730 xhci_mem_cleanup(xhci);
731 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
732 "xhci_stop completed - status = %x",
733 readl(&xhci->op_regs->status));
734 mutex_unlock(&xhci->mutex);
738 * Shutdown HC (not bus-specific)
740 * This is called when the machine is rebooting or halting. We assume that the
741 * machine will be powered off, and the HC's internal state will be reset.
742 * Don't bother to free memory.
744 * This will only ever be called with the main usb_hcd (the USB3 roothub).
746 void xhci_shutdown(struct usb_hcd *hcd)
748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
750 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
751 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
753 spin_lock_irq(&xhci->lock);
755 /* Workaround for spurious wakeups at shutdown with HSW */
756 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
758 spin_unlock_irq(&xhci->lock);
760 xhci_cleanup_msix(xhci);
762 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
763 "xhci_shutdown completed - status = %x",
764 readl(&xhci->op_regs->status));
766 /* Yet another workaround for spurious wakeups at shutdown with HSW */
767 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
768 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
772 static void xhci_save_registers(struct xhci_hcd *xhci)
774 xhci->s3.command = readl(&xhci->op_regs->command);
775 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
776 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
777 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
778 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
779 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
780 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
781 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
782 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
785 static void xhci_restore_registers(struct xhci_hcd *xhci)
787 writel(xhci->s3.command, &xhci->op_regs->command);
788 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
789 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
790 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
791 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
792 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
793 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
794 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
795 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
798 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
802 /* step 2: initialize command ring buffer */
803 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
804 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
805 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
806 xhci->cmd_ring->dequeue) &
807 (u64) ~CMD_RING_RSVD_BITS) |
808 xhci->cmd_ring->cycle_state;
809 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
810 "// Setting command ring address to 0x%llx",
811 (long unsigned long) val_64);
812 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
816 * The whole command ring must be cleared to zero when we suspend the host.
818 * The host doesn't save the command ring pointer in the suspend well, so we
819 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
820 * aligned, because of the reserved bits in the command ring dequeue pointer
821 * register. Therefore, we can't just set the dequeue pointer back in the
822 * middle of the ring (TRBs are 16-byte aligned).
824 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
826 struct xhci_ring *ring;
827 struct xhci_segment *seg;
829 ring = xhci->cmd_ring;
833 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
834 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
835 cpu_to_le32(~TRB_CYCLE);
837 } while (seg != ring->deq_seg);
839 /* Reset the software enqueue and dequeue pointers */
840 ring->deq_seg = ring->first_seg;
841 ring->dequeue = ring->first_seg->trbs;
842 ring->enq_seg = ring->deq_seg;
843 ring->enqueue = ring->dequeue;
845 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
847 * Ring is now zeroed, so the HW should look for change of ownership
848 * when the cycle bit is set to 1.
850 ring->cycle_state = 1;
853 * Reset the hardware dequeue pointer.
854 * Yes, this will need to be re-written after resume, but we're paranoid
855 * and want to make sure the hardware doesn't access bogus memory
856 * because, say, the BIOS or an SMI started the host without changing
857 * the command ring pointers.
859 xhci_set_cmd_ring_deq(xhci);
862 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
865 __le32 __iomem **port_array;
869 spin_lock_irqsave(&xhci->lock, flags);
871 /* disble usb3 ports Wake bits*/
872 port_index = xhci->num_usb3_ports;
873 port_array = xhci->usb3_ports;
874 while (port_index--) {
875 t1 = readl(port_array[port_index]);
876 t1 = xhci_port_state_to_neutral(t1);
877 t2 = t1 & ~PORT_WAKE_BITS;
879 writel(t2, port_array[port_index]);
882 /* disble usb2 ports Wake bits*/
883 port_index = xhci->num_usb2_ports;
884 port_array = xhci->usb2_ports;
885 while (port_index--) {
886 t1 = readl(port_array[port_index]);
887 t1 = xhci_port_state_to_neutral(t1);
888 t2 = t1 & ~PORT_WAKE_BITS;
890 writel(t2, port_array[port_index]);
893 spin_unlock_irqrestore(&xhci->lock, flags);
897 * Stop HC (not bus-specific)
899 * This is called when the machine transition into S3/S4 mode.
902 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
905 unsigned int delay = XHCI_MAX_HALT_USEC;
906 struct usb_hcd *hcd = xhci_to_hcd(xhci);
912 if (hcd->state != HC_STATE_SUSPENDED ||
913 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
916 /* Clear root port wake on bits if wakeup not allowed. */
918 xhci_disable_port_wake_on_bits(xhci);
920 /* Don't poll the roothubs on bus suspend. */
921 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
922 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
923 del_timer_sync(&hcd->rh_timer);
924 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
925 del_timer_sync(&xhci->shared_hcd->rh_timer);
927 spin_lock_irq(&xhci->lock);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
929 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
930 /* step 1: stop endpoint */
931 /* skipped assuming that port suspend has done */
933 /* step 2: clear Run/Stop bit */
934 command = readl(&xhci->op_regs->command);
936 writel(command, &xhci->op_regs->command);
938 /* Some chips from Fresco Logic need an extraordinary delay */
939 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
941 if (xhci_handshake(&xhci->op_regs->status,
942 STS_HALT, STS_HALT, delay)) {
943 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
944 spin_unlock_irq(&xhci->lock);
947 xhci_clear_command_ring(xhci);
949 /* step 3: save registers */
950 xhci_save_registers(xhci);
952 /* step 4: set CSS flag */
953 command = readl(&xhci->op_regs->command);
955 writel(command, &xhci->op_regs->command);
956 if (xhci_handshake(&xhci->op_regs->status,
957 STS_SAVE, 0, 10 * 1000)) {
958 xhci_warn(xhci, "WARN: xHC save state timeout\n");
959 spin_unlock_irq(&xhci->lock);
962 spin_unlock_irq(&xhci->lock);
965 * Deleting Compliance Mode Recovery Timer because the xHCI Host
966 * is about to be suspended.
968 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
969 (!(xhci_all_ports_seen_u0(xhci)))) {
970 del_timer_sync(&xhci->comp_mode_recovery_timer);
971 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
972 "%s: compliance mode recovery timer deleted",
976 /* step 5: remove core well power */
977 /* synchronize irq when using MSI-X */
978 xhci_msix_sync_irqs(xhci);
982 EXPORT_SYMBOL_GPL(xhci_suspend);
985 * start xHC (not bus-specific)
987 * This is called when the machine transition from S3/S4 mode.
990 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
992 u32 command, temp = 0, status;
993 struct usb_hcd *hcd = xhci_to_hcd(xhci);
994 struct usb_hcd *secondary_hcd;
996 bool comp_timer_running = false;
1001 /* Wait a bit if either of the roothubs need to settle from the
1002 * transition into bus suspend.
1004 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1005 time_before(jiffies,
1006 xhci->bus_state[1].next_statechange))
1009 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1010 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1012 spin_lock_irq(&xhci->lock);
1013 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1017 /* step 1: restore register */
1018 xhci_restore_registers(xhci);
1019 /* step 2: initialize command ring buffer */
1020 xhci_set_cmd_ring_deq(xhci);
1021 /* step 3: restore state and start state*/
1022 /* step 3: set CRS flag */
1023 command = readl(&xhci->op_regs->command);
1025 writel(command, &xhci->op_regs->command);
1026 if (xhci_handshake(&xhci->op_regs->status,
1027 STS_RESTORE, 0, 10 * 1000)) {
1028 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1029 spin_unlock_irq(&xhci->lock);
1032 temp = readl(&xhci->op_regs->status);
1035 /* If restore operation fails, re-initialize the HC during resume */
1036 if ((temp & STS_SRE) || hibernated) {
1038 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1039 !(xhci_all_ports_seen_u0(xhci))) {
1040 del_timer_sync(&xhci->comp_mode_recovery_timer);
1041 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1042 "Compliance Mode Recovery Timer deleted!");
1045 /* Let the USB core know _both_ roothubs lost power. */
1046 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1047 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1049 xhci_dbg(xhci, "Stop HCD\n");
1052 spin_unlock_irq(&xhci->lock);
1053 xhci_cleanup_msix(xhci);
1055 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1056 temp = readl(&xhci->op_regs->status);
1057 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1058 temp = readl(&xhci->ir_set->irq_pending);
1059 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1060 xhci_print_ir_set(xhci, 0);
1062 xhci_dbg(xhci, "cleaning up memory\n");
1063 xhci_mem_cleanup(xhci);
1064 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1065 readl(&xhci->op_regs->status));
1067 /* USB core calls the PCI reinit and start functions twice:
1068 * first with the primary HCD, and then with the secondary HCD.
1069 * If we don't do the same, the host will never be started.
1071 if (!usb_hcd_is_primary_hcd(hcd))
1072 secondary_hcd = hcd;
1074 secondary_hcd = xhci->shared_hcd;
1076 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1077 retval = xhci_init(hcd->primary_hcd);
1080 comp_timer_running = true;
1082 xhci_dbg(xhci, "Start the primary HCD\n");
1083 retval = xhci_run(hcd->primary_hcd);
1085 xhci_dbg(xhci, "Start the secondary HCD\n");
1086 retval = xhci_run(secondary_hcd);
1088 hcd->state = HC_STATE_SUSPENDED;
1089 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1093 /* step 4: set Run/Stop bit */
1094 command = readl(&xhci->op_regs->command);
1096 writel(command, &xhci->op_regs->command);
1097 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1100 /* step 5: walk topology and initialize portsc,
1101 * portpmsc and portli
1103 /* this is done in bus_resume */
1105 /* step 6: restart each of the previously
1106 * Running endpoints by ringing their doorbells
1109 spin_unlock_irq(&xhci->lock);
1113 /* Resume root hubs only when have pending events. */
1114 status = readl(&xhci->op_regs->status);
1115 if (status & STS_EINT) {
1116 usb_hcd_resume_root_hub(xhci->shared_hcd);
1117 usb_hcd_resume_root_hub(hcd);
1122 * If system is subject to the Quirk, Compliance Mode Timer needs to
1123 * be re-initialized Always after a system resume. Ports are subject
1124 * to suffer the Compliance Mode issue again. It doesn't matter if
1125 * ports have entered previously to U0 before system's suspension.
1127 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1128 compliance_mode_recovery_timer_init(xhci);
1130 /* Re-enable port polling. */
1131 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1132 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1133 usb_hcd_poll_rh_status(xhci->shared_hcd);
1134 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1135 usb_hcd_poll_rh_status(hcd);
1139 EXPORT_SYMBOL_GPL(xhci_resume);
1140 #endif /* CONFIG_PM */
1142 /*-------------------------------------------------------------------------*/
1145 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1146 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1147 * value to right shift 1 for the bitmask.
1149 * Index = (epnum * 2) + direction - 1,
1150 * where direction = 0 for OUT, 1 for IN.
1151 * For control endpoints, the IN index is used (OUT index is unused), so
1152 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1154 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1157 if (usb_endpoint_xfer_control(desc))
1158 index = (unsigned int) (usb_endpoint_num(desc)*2);
1160 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1161 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1165 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1166 * address from the XHCI endpoint index.
1168 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1170 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1171 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1172 return direction | number;
1175 /* Find the flag for this endpoint (for use in the control context). Use the
1176 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1179 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1181 return 1 << (xhci_get_endpoint_index(desc) + 1);
1184 /* Find the flag for this endpoint (for use in the control context). Use the
1185 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1188 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1190 return 1 << (ep_index + 1);
1193 /* Compute the last valid endpoint context index. Basically, this is the
1194 * endpoint index plus one. For slot contexts with more than valid endpoint,
1195 * we find the most significant bit set in the added contexts flags.
1196 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1197 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1199 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1201 return fls(added_ctxs) - 1;
1204 /* Returns 1 if the arguments are OK;
1205 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1207 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1208 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1210 struct xhci_hcd *xhci;
1211 struct xhci_virt_device *virt_dev;
1213 if (!hcd || (check_ep && !ep) || !udev) {
1214 pr_debug("xHCI %s called with invalid args\n", func);
1217 if (!udev->parent) {
1218 pr_debug("xHCI %s called for root hub\n", func);
1222 xhci = hcd_to_xhci(hcd);
1223 if (check_virt_dev) {
1224 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1225 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1230 virt_dev = xhci->devs[udev->slot_id];
1231 if (virt_dev->udev != udev) {
1232 xhci_dbg(xhci, "xHCI %s called with udev and "
1233 "virt_dev does not match\n", func);
1238 if (xhci->xhc_state & XHCI_STATE_HALTED)
1244 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1245 struct usb_device *udev, struct xhci_command *command,
1246 bool ctx_change, bool must_succeed);
1249 * Full speed devices may have a max packet size greater than 8 bytes, but the
1250 * USB core doesn't know that until it reads the first 8 bytes of the
1251 * descriptor. If the usb_device's max packet size changes after that point,
1252 * we need to issue an evaluate context command and wait on it.
1254 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1255 unsigned int ep_index, struct urb *urb)
1257 struct xhci_container_ctx *out_ctx;
1258 struct xhci_input_control_ctx *ctrl_ctx;
1259 struct xhci_ep_ctx *ep_ctx;
1260 struct xhci_command *command;
1261 int max_packet_size;
1262 int hw_max_packet_size;
1265 out_ctx = xhci->devs[slot_id]->out_ctx;
1266 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1267 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1268 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1269 if (hw_max_packet_size != max_packet_size) {
1270 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1271 "Max Packet Size for ep 0 changed.");
1272 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1273 "Max packet size in usb_device = %d",
1275 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1276 "Max packet size in xHCI HW = %d",
1277 hw_max_packet_size);
1278 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1279 "Issuing evaluate context command.");
1281 /* Set up the input context flags for the command */
1282 /* FIXME: This won't work if a non-default control endpoint
1283 * changes max packet sizes.
1286 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1290 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1291 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1293 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1296 goto command_cleanup;
1298 /* Set up the modified control endpoint 0 */
1299 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1300 xhci->devs[slot_id]->out_ctx, ep_index);
1302 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1303 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1304 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1306 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1307 ctrl_ctx->drop_flags = 0;
1309 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1310 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1311 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1312 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1314 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1317 /* Clean up the input context for later use by bandwidth
1320 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1322 kfree(command->completion);
1329 * non-error returns are a promise to giveback() the urb later
1330 * we drop ownership so next owner (or urb unlink) can get it
1332 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1334 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1335 struct xhci_td *buffer;
1336 unsigned long flags;
1338 unsigned int slot_id, ep_index;
1339 struct urb_priv *urb_priv;
1342 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1343 true, true, __func__) <= 0)
1346 slot_id = urb->dev->slot_id;
1347 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1349 if (!HCD_HW_ACCESSIBLE(hcd)) {
1350 if (!in_interrupt())
1351 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1356 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1357 size = urb->number_of_packets;
1358 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1359 urb->transfer_buffer_length > 0 &&
1360 urb->transfer_flags & URB_ZERO_PACKET &&
1361 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1366 urb_priv = kzalloc(sizeof(struct urb_priv) +
1367 size * sizeof(struct xhci_td *), mem_flags);
1371 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1377 for (i = 0; i < size; i++) {
1378 urb_priv->td[i] = buffer;
1382 urb_priv->length = size;
1383 urb_priv->td_cnt = 0;
1384 urb->hcpriv = urb_priv;
1386 trace_xhci_urb_enqueue(urb);
1388 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1389 /* Check to see if the max packet size for the default control
1390 * endpoint changed during FS device enumeration
1392 if (urb->dev->speed == USB_SPEED_FULL) {
1393 ret = xhci_check_maxpacket(xhci, slot_id,
1396 xhci_urb_free_priv(urb_priv);
1402 /* We have a spinlock and interrupts disabled, so we must pass
1403 * atomic context to this function, which may allocate memory.
1405 spin_lock_irqsave(&xhci->lock, flags);
1406 if (xhci->xhc_state & XHCI_STATE_DYING)
1408 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1412 spin_unlock_irqrestore(&xhci->lock, flags);
1413 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1414 spin_lock_irqsave(&xhci->lock, flags);
1415 if (xhci->xhc_state & XHCI_STATE_DYING)
1417 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1418 EP_GETTING_STREAMS) {
1419 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1420 "is transitioning to using streams.\n");
1422 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1423 EP_GETTING_NO_STREAMS) {
1424 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1425 "is transitioning to "
1426 "not having streams.\n");
1429 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1434 spin_unlock_irqrestore(&xhci->lock, flags);
1435 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1436 spin_lock_irqsave(&xhci->lock, flags);
1437 if (xhci->xhc_state & XHCI_STATE_DYING)
1439 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1443 spin_unlock_irqrestore(&xhci->lock, flags);
1445 spin_lock_irqsave(&xhci->lock, flags);
1446 if (xhci->xhc_state & XHCI_STATE_DYING)
1448 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1452 spin_unlock_irqrestore(&xhci->lock, flags);
1457 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1458 "non-responsive xHCI host.\n",
1459 urb->ep->desc.bEndpointAddress, urb);
1462 xhci_urb_free_priv(urb_priv);
1464 spin_unlock_irqrestore(&xhci->lock, flags);
1469 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1470 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1471 * should pick up where it left off in the TD, unless a Set Transfer Ring
1472 * Dequeue Pointer is issued.
1474 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1475 * the ring. Since the ring is a contiguous structure, they can't be physically
1476 * removed. Instead, there are two options:
1478 * 1) If the HC is in the middle of processing the URB to be canceled, we
1479 * simply move the ring's dequeue pointer past those TRBs using the Set
1480 * Transfer Ring Dequeue Pointer command. This will be the common case,
1481 * when drivers timeout on the last submitted URB and attempt to cancel.
1483 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1484 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1485 * HC will need to invalidate the any TRBs it has cached after the stop
1486 * endpoint command, as noted in the xHCI 0.95 errata.
1488 * 3) The TD may have completed by the time the Stop Endpoint Command
1489 * completes, so software needs to handle that case too.
1491 * This function should protect against the TD enqueueing code ringing the
1492 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1493 * It also needs to account for multiple cancellations on happening at the same
1494 * time for the same endpoint.
1496 * Note that this function can be called in any context, or so says
1497 * usb_hcd_unlink_urb()
1499 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1501 unsigned long flags;
1504 struct xhci_hcd *xhci;
1505 struct urb_priv *urb_priv;
1507 unsigned int ep_index;
1508 struct xhci_ring *ep_ring;
1509 struct xhci_virt_ep *ep;
1510 struct xhci_command *command;
1512 xhci = hcd_to_xhci(hcd);
1513 spin_lock_irqsave(&xhci->lock, flags);
1515 trace_xhci_urb_dequeue(urb);
1517 /* Make sure the URB hasn't completed or been unlinked already */
1518 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1519 if (ret || !urb->hcpriv)
1521 temp = readl(&xhci->op_regs->status);
1522 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1523 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1524 "HW died, freeing TD.");
1525 urb_priv = urb->hcpriv;
1526 for (i = urb_priv->td_cnt;
1527 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1529 td = urb_priv->td[i];
1530 if (!list_empty(&td->td_list))
1531 list_del_init(&td->td_list);
1532 if (!list_empty(&td->cancelled_td_list))
1533 list_del_init(&td->cancelled_td_list);
1536 usb_hcd_unlink_urb_from_ep(hcd, urb);
1537 spin_unlock_irqrestore(&xhci->lock, flags);
1538 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1539 xhci_urb_free_priv(urb_priv);
1543 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1544 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1545 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1551 urb_priv = urb->hcpriv;
1552 i = urb_priv->td_cnt;
1553 if (i < urb_priv->length)
1554 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1555 "Cancel URB %p, dev %s, ep 0x%x, "
1556 "starting at offset 0x%llx",
1557 urb, urb->dev->devpath,
1558 urb->ep->desc.bEndpointAddress,
1559 (unsigned long long) xhci_trb_virt_to_dma(
1560 urb_priv->td[i]->start_seg,
1561 urb_priv->td[i]->first_trb));
1563 for (; i < urb_priv->length; i++) {
1564 td = urb_priv->td[i];
1565 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1568 /* Queue a stop endpoint command, but only if this is
1569 * the first cancellation to be handled.
1571 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1572 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1577 ep->ep_state |= EP_STOP_CMD_PENDING;
1578 ep->stop_cmd_timer.expires = jiffies +
1579 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1580 add_timer(&ep->stop_cmd_timer);
1581 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1583 xhci_ring_cmd_db(xhci);
1586 spin_unlock_irqrestore(&xhci->lock, flags);
1590 /* Drop an endpoint from a new bandwidth configuration for this device.
1591 * Only one call to this function is allowed per endpoint before
1592 * check_bandwidth() or reset_bandwidth() must be called.
1593 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1594 * add the endpoint to the schedule with possibly new parameters denoted by a
1595 * different endpoint descriptor in usb_host_endpoint.
1596 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1599 * The USB core will not allow URBs to be queued to an endpoint that is being
1600 * disabled, so there's no need for mutual exclusion to protect
1601 * the xhci->devs[slot_id] structure.
1603 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1604 struct usb_host_endpoint *ep)
1606 struct xhci_hcd *xhci;
1607 struct xhci_container_ctx *in_ctx, *out_ctx;
1608 struct xhci_input_control_ctx *ctrl_ctx;
1609 unsigned int ep_index;
1610 struct xhci_ep_ctx *ep_ctx;
1612 u32 new_add_flags, new_drop_flags;
1615 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1618 xhci = hcd_to_xhci(hcd);
1619 if (xhci->xhc_state & XHCI_STATE_DYING)
1622 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1623 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1624 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1625 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1626 __func__, drop_flag);
1630 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1631 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1632 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1634 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1639 ep_index = xhci_get_endpoint_index(&ep->desc);
1640 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1641 /* If the HC already knows the endpoint is disabled,
1642 * or the HCD has noted it is disabled, ignore this request
1644 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1645 le32_to_cpu(ctrl_ctx->drop_flags) &
1646 xhci_get_endpoint_flag(&ep->desc)) {
1647 /* Do not warn when called after a usb_device_reset */
1648 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1649 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1654 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1655 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1657 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1658 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1660 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1662 if (xhci->quirks & XHCI_MTK_HOST)
1663 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1665 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1666 (unsigned int) ep->desc.bEndpointAddress,
1668 (unsigned int) new_drop_flags,
1669 (unsigned int) new_add_flags);
1673 /* Add an endpoint to a new possible bandwidth configuration for this device.
1674 * Only one call to this function is allowed per endpoint before
1675 * check_bandwidth() or reset_bandwidth() must be called.
1676 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1677 * add the endpoint to the schedule with possibly new parameters denoted by a
1678 * different endpoint descriptor in usb_host_endpoint.
1679 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1682 * The USB core will not allow URBs to be queued to an endpoint until the
1683 * configuration or alt setting is installed in the device, so there's no need
1684 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1686 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1687 struct usb_host_endpoint *ep)
1689 struct xhci_hcd *xhci;
1690 struct xhci_container_ctx *in_ctx;
1691 unsigned int ep_index;
1692 struct xhci_input_control_ctx *ctrl_ctx;
1694 u32 new_add_flags, new_drop_flags;
1695 struct xhci_virt_device *virt_dev;
1698 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1700 /* So we won't queue a reset ep command for a root hub */
1704 xhci = hcd_to_xhci(hcd);
1705 if (xhci->xhc_state & XHCI_STATE_DYING)
1708 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1709 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1710 /* FIXME when we have to issue an evaluate endpoint command to
1711 * deal with ep0 max packet size changing once we get the
1714 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1715 __func__, added_ctxs);
1719 virt_dev = xhci->devs[udev->slot_id];
1720 in_ctx = virt_dev->in_ctx;
1721 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1723 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1728 ep_index = xhci_get_endpoint_index(&ep->desc);
1729 /* If this endpoint is already in use, and the upper layers are trying
1730 * to add it again without dropping it, reject the addition.
1732 if (virt_dev->eps[ep_index].ring &&
1733 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1734 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1735 "without dropping it.\n",
1736 (unsigned int) ep->desc.bEndpointAddress);
1740 /* If the HCD has already noted the endpoint is enabled,
1741 * ignore this request.
1743 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1744 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1750 * Configuration and alternate setting changes must be done in
1751 * process context, not interrupt context (or so documenation
1752 * for usb_set_interface() and usb_set_configuration() claim).
1754 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1755 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1756 __func__, ep->desc.bEndpointAddress);
1760 if (xhci->quirks & XHCI_MTK_HOST) {
1761 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1763 xhci_free_or_cache_endpoint_ring(xhci,
1764 virt_dev, ep_index);
1769 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1770 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1772 /* If xhci_endpoint_disable() was called for this endpoint, but the
1773 * xHC hasn't been notified yet through the check_bandwidth() call,
1774 * this re-adds a new state for the endpoint from the new endpoint
1775 * descriptors. We must drop and re-add this endpoint, so we leave the
1778 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1780 /* Store the usb_device pointer for later use */
1783 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1784 (unsigned int) ep->desc.bEndpointAddress,
1786 (unsigned int) new_drop_flags,
1787 (unsigned int) new_add_flags);
1791 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1793 struct xhci_input_control_ctx *ctrl_ctx;
1794 struct xhci_ep_ctx *ep_ctx;
1795 struct xhci_slot_ctx *slot_ctx;
1798 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1800 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1805 /* When a device's add flag and drop flag are zero, any subsequent
1806 * configure endpoint command will leave that endpoint's state
1807 * untouched. Make sure we don't leave any old state in the input
1808 * endpoint contexts.
1810 ctrl_ctx->drop_flags = 0;
1811 ctrl_ctx->add_flags = 0;
1812 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1813 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1814 /* Endpoint 0 is always valid */
1815 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1816 for (i = 1; i < 31; i++) {
1817 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1818 ep_ctx->ep_info = 0;
1819 ep_ctx->ep_info2 = 0;
1821 ep_ctx->tx_info = 0;
1825 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1826 struct usb_device *udev, u32 *cmd_status)
1830 switch (*cmd_status) {
1831 case COMP_COMMAND_ABORTED:
1833 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1836 case COMP_RESOURCE_ERROR:
1837 dev_warn(&udev->dev,
1838 "Not enough host controller resources for new device state.\n");
1840 /* FIXME: can we allocate more resources for the HC? */
1842 case COMP_BANDWIDTH_ERROR:
1843 case COMP_SECONDARY_BANDWIDTH_ERROR:
1844 dev_warn(&udev->dev,
1845 "Not enough bandwidth for new device state.\n");
1847 /* FIXME: can we go back to the old state? */
1849 case COMP_TRB_ERROR:
1850 /* the HCD set up something wrong */
1851 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1853 "and endpoint is not disabled.\n");
1856 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1857 dev_warn(&udev->dev,
1858 "ERROR: Incompatible device for endpoint configure command.\n");
1862 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1863 "Successful Endpoint Configure command");
1867 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1875 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1876 struct usb_device *udev, u32 *cmd_status)
1879 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1881 switch (*cmd_status) {
1882 case COMP_COMMAND_ABORTED:
1884 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1887 case COMP_PARAMETER_ERROR:
1888 dev_warn(&udev->dev,
1889 "WARN: xHCI driver setup invalid evaluate context command.\n");
1892 case COMP_SLOT_NOT_ENABLED_ERROR:
1893 dev_warn(&udev->dev,
1894 "WARN: slot not enabled for evaluate context command.\n");
1897 case COMP_CONTEXT_STATE_ERROR:
1898 dev_warn(&udev->dev,
1899 "WARN: invalid context state for evaluate context command.\n");
1900 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1903 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1904 dev_warn(&udev->dev,
1905 "ERROR: Incompatible device for evaluate context command.\n");
1908 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1909 /* Max Exit Latency too large error */
1910 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1914 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1915 "Successful evaluate context command");
1919 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1927 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1928 struct xhci_input_control_ctx *ctrl_ctx)
1930 u32 valid_add_flags;
1931 u32 valid_drop_flags;
1933 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1934 * (bit 1). The default control endpoint is added during the Address
1935 * Device command and is never removed until the slot is disabled.
1937 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1938 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1940 /* Use hweight32 to count the number of ones in the add flags, or
1941 * number of endpoints added. Don't count endpoints that are changed
1942 * (both added and dropped).
1944 return hweight32(valid_add_flags) -
1945 hweight32(valid_add_flags & valid_drop_flags);
1948 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1949 struct xhci_input_control_ctx *ctrl_ctx)
1951 u32 valid_add_flags;
1952 u32 valid_drop_flags;
1954 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1955 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1957 return hweight32(valid_drop_flags) -
1958 hweight32(valid_add_flags & valid_drop_flags);
1962 * We need to reserve the new number of endpoints before the configure endpoint
1963 * command completes. We can't subtract the dropped endpoints from the number
1964 * of active endpoints until the command completes because we can oversubscribe
1965 * the host in this case:
1967 * - the first configure endpoint command drops more endpoints than it adds
1968 * - a second configure endpoint command that adds more endpoints is queued
1969 * - the first configure endpoint command fails, so the config is unchanged
1970 * - the second command may succeed, even though there isn't enough resources
1972 * Must be called with xhci->lock held.
1974 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1975 struct xhci_input_control_ctx *ctrl_ctx)
1979 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1980 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1981 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1982 "Not enough ep ctxs: "
1983 "%u active, need to add %u, limit is %u.",
1984 xhci->num_active_eps, added_eps,
1985 xhci->limit_active_eps);
1988 xhci->num_active_eps += added_eps;
1989 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1990 "Adding %u ep ctxs, %u now active.", added_eps,
1991 xhci->num_active_eps);
1996 * The configure endpoint was failed by the xHC for some other reason, so we
1997 * need to revert the resources that failed configuration would have used.
1999 * Must be called with xhci->lock held.
2001 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2002 struct xhci_input_control_ctx *ctrl_ctx)
2006 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2007 xhci->num_active_eps -= num_failed_eps;
2008 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2009 "Removing %u failed ep ctxs, %u now active.",
2011 xhci->num_active_eps);
2015 * Now that the command has completed, clean up the active endpoint count by
2016 * subtracting out the endpoints that were dropped (but not changed).
2018 * Must be called with xhci->lock held.
2020 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2021 struct xhci_input_control_ctx *ctrl_ctx)
2023 u32 num_dropped_eps;
2025 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2026 xhci->num_active_eps -= num_dropped_eps;
2027 if (num_dropped_eps)
2028 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2029 "Removing %u dropped ep ctxs, %u now active.",
2031 xhci->num_active_eps);
2034 static unsigned int xhci_get_block_size(struct usb_device *udev)
2036 switch (udev->speed) {
2038 case USB_SPEED_FULL:
2040 case USB_SPEED_HIGH:
2042 case USB_SPEED_SUPER:
2043 case USB_SPEED_SUPER_PLUS:
2045 case USB_SPEED_UNKNOWN:
2046 case USB_SPEED_WIRELESS:
2048 /* Should never happen */
2054 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2056 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2058 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2063 /* If we are changing a LS/FS device under a HS hub,
2064 * make sure (if we are activating a new TT) that the HS bus has enough
2065 * bandwidth for this new TT.
2067 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2068 struct xhci_virt_device *virt_dev,
2071 struct xhci_interval_bw_table *bw_table;
2072 struct xhci_tt_bw_info *tt_info;
2074 /* Find the bandwidth table for the root port this TT is attached to. */
2075 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2076 tt_info = virt_dev->tt_info;
2077 /* If this TT already had active endpoints, the bandwidth for this TT
2078 * has already been added. Removing all periodic endpoints (and thus
2079 * making the TT enactive) will only decrease the bandwidth used.
2083 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2084 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2088 /* Not sure why we would have no new active endpoints...
2090 * Maybe because of an Evaluate Context change for a hub update or a
2091 * control endpoint 0 max packet size change?
2092 * FIXME: skip the bandwidth calculation in that case.
2097 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2098 struct xhci_virt_device *virt_dev)
2100 unsigned int bw_reserved;
2102 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2103 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2106 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2107 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2114 * This algorithm is a very conservative estimate of the worst-case scheduling
2115 * scenario for any one interval. The hardware dynamically schedules the
2116 * packets, so we can't tell which microframe could be the limiting factor in
2117 * the bandwidth scheduling. This only takes into account periodic endpoints.
2119 * Obviously, we can't solve an NP complete problem to find the minimum worst
2120 * case scenario. Instead, we come up with an estimate that is no less than
2121 * the worst case bandwidth used for any one microframe, but may be an
2124 * We walk the requirements for each endpoint by interval, starting with the
2125 * smallest interval, and place packets in the schedule where there is only one
2126 * possible way to schedule packets for that interval. In order to simplify
2127 * this algorithm, we record the largest max packet size for each interval, and
2128 * assume all packets will be that size.
2130 * For interval 0, we obviously must schedule all packets for each interval.
2131 * The bandwidth for interval 0 is just the amount of data to be transmitted
2132 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2133 * the number of packets).
2135 * For interval 1, we have two possible microframes to schedule those packets
2136 * in. For this algorithm, if we can schedule the same number of packets for
2137 * each possible scheduling opportunity (each microframe), we will do so. The
2138 * remaining number of packets will be saved to be transmitted in the gaps in
2139 * the next interval's scheduling sequence.
2141 * As we move those remaining packets to be scheduled with interval 2 packets,
2142 * we have to double the number of remaining packets to transmit. This is
2143 * because the intervals are actually powers of 2, and we would be transmitting
2144 * the previous interval's packets twice in this interval. We also have to be
2145 * sure that when we look at the largest max packet size for this interval, we
2146 * also look at the largest max packet size for the remaining packets and take
2147 * the greater of the two.
2149 * The algorithm continues to evenly distribute packets in each scheduling
2150 * opportunity, and push the remaining packets out, until we get to the last
2151 * interval. Then those packets and their associated overhead are just added
2152 * to the bandwidth used.
2154 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2155 struct xhci_virt_device *virt_dev,
2158 unsigned int bw_reserved;
2159 unsigned int max_bandwidth;
2160 unsigned int bw_used;
2161 unsigned int block_size;
2162 struct xhci_interval_bw_table *bw_table;
2163 unsigned int packet_size = 0;
2164 unsigned int overhead = 0;
2165 unsigned int packets_transmitted = 0;
2166 unsigned int packets_remaining = 0;
2169 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2170 return xhci_check_ss_bw(xhci, virt_dev);
2172 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2173 max_bandwidth = HS_BW_LIMIT;
2174 /* Convert percent of bus BW reserved to blocks reserved */
2175 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2177 max_bandwidth = FS_BW_LIMIT;
2178 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2181 bw_table = virt_dev->bw_table;
2182 /* We need to translate the max packet size and max ESIT payloads into
2183 * the units the hardware uses.
2185 block_size = xhci_get_block_size(virt_dev->udev);
2187 /* If we are manipulating a LS/FS device under a HS hub, double check
2188 * that the HS bus has enough bandwidth if we are activing a new TT.
2190 if (virt_dev->tt_info) {
2191 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2192 "Recalculating BW for rootport %u",
2193 virt_dev->real_port);
2194 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2195 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2196 "newly activated TT.\n");
2199 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2200 "Recalculating BW for TT slot %u port %u",
2201 virt_dev->tt_info->slot_id,
2202 virt_dev->tt_info->ttport);
2204 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2205 "Recalculating BW for rootport %u",
2206 virt_dev->real_port);
2209 /* Add in how much bandwidth will be used for interval zero, or the
2210 * rounded max ESIT payload + number of packets * largest overhead.
2212 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2213 bw_table->interval_bw[0].num_packets *
2214 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2216 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2217 unsigned int bw_added;
2218 unsigned int largest_mps;
2219 unsigned int interval_overhead;
2222 * How many packets could we transmit in this interval?
2223 * If packets didn't fit in the previous interval, we will need
2224 * to transmit that many packets twice within this interval.
2226 packets_remaining = 2 * packets_remaining +
2227 bw_table->interval_bw[i].num_packets;
2229 /* Find the largest max packet size of this or the previous
2232 if (list_empty(&bw_table->interval_bw[i].endpoints))
2235 struct xhci_virt_ep *virt_ep;
2236 struct list_head *ep_entry;
2238 ep_entry = bw_table->interval_bw[i].endpoints.next;
2239 virt_ep = list_entry(ep_entry,
2240 struct xhci_virt_ep, bw_endpoint_list);
2241 /* Convert to blocks, rounding up */
2242 largest_mps = DIV_ROUND_UP(
2243 virt_ep->bw_info.max_packet_size,
2246 if (largest_mps > packet_size)
2247 packet_size = largest_mps;
2249 /* Use the larger overhead of this or the previous interval. */
2250 interval_overhead = xhci_get_largest_overhead(
2251 &bw_table->interval_bw[i]);
2252 if (interval_overhead > overhead)
2253 overhead = interval_overhead;
2255 /* How many packets can we evenly distribute across
2256 * (1 << (i + 1)) possible scheduling opportunities?
2258 packets_transmitted = packets_remaining >> (i + 1);
2260 /* Add in the bandwidth used for those scheduled packets */
2261 bw_added = packets_transmitted * (overhead + packet_size);
2263 /* How many packets do we have remaining to transmit? */
2264 packets_remaining = packets_remaining % (1 << (i + 1));
2266 /* What largest max packet size should those packets have? */
2267 /* If we've transmitted all packets, don't carry over the
2268 * largest packet size.
2270 if (packets_remaining == 0) {
2273 } else if (packets_transmitted > 0) {
2274 /* Otherwise if we do have remaining packets, and we've
2275 * scheduled some packets in this interval, take the
2276 * largest max packet size from endpoints with this
2279 packet_size = largest_mps;
2280 overhead = interval_overhead;
2282 /* Otherwise carry over packet_size and overhead from the last
2283 * time we had a remainder.
2285 bw_used += bw_added;
2286 if (bw_used > max_bandwidth) {
2287 xhci_warn(xhci, "Not enough bandwidth. "
2288 "Proposed: %u, Max: %u\n",
2289 bw_used, max_bandwidth);
2294 * Ok, we know we have some packets left over after even-handedly
2295 * scheduling interval 15. We don't know which microframes they will
2296 * fit into, so we over-schedule and say they will be scheduled every
2299 if (packets_remaining > 0)
2300 bw_used += overhead + packet_size;
2302 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2303 unsigned int port_index = virt_dev->real_port - 1;
2305 /* OK, we're manipulating a HS device attached to a
2306 * root port bandwidth domain. Include the number of active TTs
2307 * in the bandwidth used.
2309 bw_used += TT_HS_OVERHEAD *
2310 xhci->rh_bw[port_index].num_active_tts;
2313 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2314 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2315 "Available: %u " "percent",
2316 bw_used, max_bandwidth, bw_reserved,
2317 (max_bandwidth - bw_used - bw_reserved) * 100 /
2320 bw_used += bw_reserved;
2321 if (bw_used > max_bandwidth) {
2322 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2323 bw_used, max_bandwidth);
2327 bw_table->bw_used = bw_used;
2331 static bool xhci_is_async_ep(unsigned int ep_type)
2333 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2334 ep_type != ISOC_IN_EP &&
2335 ep_type != INT_IN_EP);
2338 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2340 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2343 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2345 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2347 if (ep_bw->ep_interval == 0)
2348 return SS_OVERHEAD_BURST +
2349 (ep_bw->mult * ep_bw->num_packets *
2350 (SS_OVERHEAD + mps));
2351 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2352 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2353 1 << ep_bw->ep_interval);
2357 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2358 struct xhci_bw_info *ep_bw,
2359 struct xhci_interval_bw_table *bw_table,
2360 struct usb_device *udev,
2361 struct xhci_virt_ep *virt_ep,
2362 struct xhci_tt_bw_info *tt_info)
2364 struct xhci_interval_bw *interval_bw;
2365 int normalized_interval;
2367 if (xhci_is_async_ep(ep_bw->type))
2370 if (udev->speed >= USB_SPEED_SUPER) {
2371 if (xhci_is_sync_in_ep(ep_bw->type))
2372 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2373 xhci_get_ss_bw_consumed(ep_bw);
2375 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2376 xhci_get_ss_bw_consumed(ep_bw);
2380 /* SuperSpeed endpoints never get added to intervals in the table, so
2381 * this check is only valid for HS/FS/LS devices.
2383 if (list_empty(&virt_ep->bw_endpoint_list))
2385 /* For LS/FS devices, we need to translate the interval expressed in
2386 * microframes to frames.
2388 if (udev->speed == USB_SPEED_HIGH)
2389 normalized_interval = ep_bw->ep_interval;
2391 normalized_interval = ep_bw->ep_interval - 3;
2393 if (normalized_interval == 0)
2394 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2395 interval_bw = &bw_table->interval_bw[normalized_interval];
2396 interval_bw->num_packets -= ep_bw->num_packets;
2397 switch (udev->speed) {
2399 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2401 case USB_SPEED_FULL:
2402 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2404 case USB_SPEED_HIGH:
2405 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2407 case USB_SPEED_SUPER:
2408 case USB_SPEED_SUPER_PLUS:
2409 case USB_SPEED_UNKNOWN:
2410 case USB_SPEED_WIRELESS:
2411 /* Should never happen because only LS/FS/HS endpoints will get
2412 * added to the endpoint list.
2417 tt_info->active_eps -= 1;
2418 list_del_init(&virt_ep->bw_endpoint_list);
2421 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2422 struct xhci_bw_info *ep_bw,
2423 struct xhci_interval_bw_table *bw_table,
2424 struct usb_device *udev,
2425 struct xhci_virt_ep *virt_ep,
2426 struct xhci_tt_bw_info *tt_info)
2428 struct xhci_interval_bw *interval_bw;
2429 struct xhci_virt_ep *smaller_ep;
2430 int normalized_interval;
2432 if (xhci_is_async_ep(ep_bw->type))
2435 if (udev->speed == USB_SPEED_SUPER) {
2436 if (xhci_is_sync_in_ep(ep_bw->type))
2437 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2438 xhci_get_ss_bw_consumed(ep_bw);
2440 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2441 xhci_get_ss_bw_consumed(ep_bw);
2445 /* For LS/FS devices, we need to translate the interval expressed in
2446 * microframes to frames.
2448 if (udev->speed == USB_SPEED_HIGH)
2449 normalized_interval = ep_bw->ep_interval;
2451 normalized_interval = ep_bw->ep_interval - 3;
2453 if (normalized_interval == 0)
2454 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2455 interval_bw = &bw_table->interval_bw[normalized_interval];
2456 interval_bw->num_packets += ep_bw->num_packets;
2457 switch (udev->speed) {
2459 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2461 case USB_SPEED_FULL:
2462 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2464 case USB_SPEED_HIGH:
2465 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2467 case USB_SPEED_SUPER:
2468 case USB_SPEED_SUPER_PLUS:
2469 case USB_SPEED_UNKNOWN:
2470 case USB_SPEED_WIRELESS:
2471 /* Should never happen because only LS/FS/HS endpoints will get
2472 * added to the endpoint list.
2478 tt_info->active_eps += 1;
2479 /* Insert the endpoint into the list, largest max packet size first. */
2480 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2482 if (ep_bw->max_packet_size >=
2483 smaller_ep->bw_info.max_packet_size) {
2484 /* Add the new ep before the smaller endpoint */
2485 list_add_tail(&virt_ep->bw_endpoint_list,
2486 &smaller_ep->bw_endpoint_list);
2490 /* Add the new endpoint at the end of the list. */
2491 list_add_tail(&virt_ep->bw_endpoint_list,
2492 &interval_bw->endpoints);
2495 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2496 struct xhci_virt_device *virt_dev,
2499 struct xhci_root_port_bw_info *rh_bw_info;
2500 if (!virt_dev->tt_info)
2503 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2504 if (old_active_eps == 0 &&
2505 virt_dev->tt_info->active_eps != 0) {
2506 rh_bw_info->num_active_tts += 1;
2507 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2508 } else if (old_active_eps != 0 &&
2509 virt_dev->tt_info->active_eps == 0) {
2510 rh_bw_info->num_active_tts -= 1;
2511 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2515 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2516 struct xhci_virt_device *virt_dev,
2517 struct xhci_container_ctx *in_ctx)
2519 struct xhci_bw_info ep_bw_info[31];
2521 struct xhci_input_control_ctx *ctrl_ctx;
2522 int old_active_eps = 0;
2524 if (virt_dev->tt_info)
2525 old_active_eps = virt_dev->tt_info->active_eps;
2527 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2529 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2534 for (i = 0; i < 31; i++) {
2535 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2538 /* Make a copy of the BW info in case we need to revert this */
2539 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2540 sizeof(ep_bw_info[i]));
2541 /* Drop the endpoint from the interval table if the endpoint is
2542 * being dropped or changed.
2544 if (EP_IS_DROPPED(ctrl_ctx, i))
2545 xhci_drop_ep_from_interval_table(xhci,
2546 &virt_dev->eps[i].bw_info,
2552 /* Overwrite the information stored in the endpoints' bw_info */
2553 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2554 for (i = 0; i < 31; i++) {
2555 /* Add any changed or added endpoints to the interval table */
2556 if (EP_IS_ADDED(ctrl_ctx, i))
2557 xhci_add_ep_to_interval_table(xhci,
2558 &virt_dev->eps[i].bw_info,
2565 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2566 /* Ok, this fits in the bandwidth we have.
2567 * Update the number of active TTs.
2569 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2573 /* We don't have enough bandwidth for this, revert the stored info. */
2574 for (i = 0; i < 31; i++) {
2575 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2578 /* Drop the new copies of any added or changed endpoints from
2579 * the interval table.
2581 if (EP_IS_ADDED(ctrl_ctx, i)) {
2582 xhci_drop_ep_from_interval_table(xhci,
2583 &virt_dev->eps[i].bw_info,
2589 /* Revert the endpoint back to its old information */
2590 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2591 sizeof(ep_bw_info[i]));
2592 /* Add any changed or dropped endpoints back into the table */
2593 if (EP_IS_DROPPED(ctrl_ctx, i))
2594 xhci_add_ep_to_interval_table(xhci,
2595 &virt_dev->eps[i].bw_info,
2605 /* Issue a configure endpoint command or evaluate context command
2606 * and wait for it to finish.
2608 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2609 struct usb_device *udev,
2610 struct xhci_command *command,
2611 bool ctx_change, bool must_succeed)
2614 unsigned long flags;
2615 struct xhci_input_control_ctx *ctrl_ctx;
2616 struct xhci_virt_device *virt_dev;
2621 spin_lock_irqsave(&xhci->lock, flags);
2622 virt_dev = xhci->devs[udev->slot_id];
2624 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2626 spin_unlock_irqrestore(&xhci->lock, flags);
2627 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2632 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2633 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2634 spin_unlock_irqrestore(&xhci->lock, flags);
2635 xhci_warn(xhci, "Not enough host resources, "
2636 "active endpoint contexts = %u\n",
2637 xhci->num_active_eps);
2640 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2641 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2642 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2643 xhci_free_host_resources(xhci, ctrl_ctx);
2644 spin_unlock_irqrestore(&xhci->lock, flags);
2645 xhci_warn(xhci, "Not enough bandwidth\n");
2650 ret = xhci_queue_configure_endpoint(xhci, command,
2651 command->in_ctx->dma,
2652 udev->slot_id, must_succeed);
2654 ret = xhci_queue_evaluate_context(xhci, command,
2655 command->in_ctx->dma,
2656 udev->slot_id, must_succeed);
2658 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2659 xhci_free_host_resources(xhci, ctrl_ctx);
2660 spin_unlock_irqrestore(&xhci->lock, flags);
2661 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2662 "FIXME allocate a new ring segment");
2665 xhci_ring_cmd_db(xhci);
2666 spin_unlock_irqrestore(&xhci->lock, flags);
2668 /* Wait for the configure endpoint command to complete */
2669 wait_for_completion(command->completion);
2672 ret = xhci_configure_endpoint_result(xhci, udev,
2675 ret = xhci_evaluate_context_result(xhci, udev,
2678 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2679 spin_lock_irqsave(&xhci->lock, flags);
2680 /* If the command failed, remove the reserved resources.
2681 * Otherwise, clean up the estimate to include dropped eps.
2684 xhci_free_host_resources(xhci, ctrl_ctx);
2686 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2687 spin_unlock_irqrestore(&xhci->lock, flags);
2692 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2693 struct xhci_virt_device *vdev, int i)
2695 struct xhci_virt_ep *ep = &vdev->eps[i];
2697 if (ep->ep_state & EP_HAS_STREAMS) {
2698 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2699 xhci_get_endpoint_address(i));
2700 xhci_free_stream_info(xhci, ep->stream_info);
2701 ep->stream_info = NULL;
2702 ep->ep_state &= ~EP_HAS_STREAMS;
2706 /* Called after one or more calls to xhci_add_endpoint() or
2707 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2708 * to call xhci_reset_bandwidth().
2710 * Since we are in the middle of changing either configuration or
2711 * installing a new alt setting, the USB core won't allow URBs to be
2712 * enqueued for any endpoint on the old config or interface. Nothing
2713 * else should be touching the xhci->devs[slot_id] structure, so we
2714 * don't need to take the xhci->lock for manipulating that.
2716 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2720 struct xhci_hcd *xhci;
2721 struct xhci_virt_device *virt_dev;
2722 struct xhci_input_control_ctx *ctrl_ctx;
2723 struct xhci_slot_ctx *slot_ctx;
2724 struct xhci_command *command;
2726 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2729 xhci = hcd_to_xhci(hcd);
2730 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2731 (xhci->xhc_state & XHCI_STATE_REMOVING))
2734 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2735 virt_dev = xhci->devs[udev->slot_id];
2737 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2741 command->in_ctx = virt_dev->in_ctx;
2743 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2744 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2746 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2749 goto command_cleanup;
2751 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2752 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2753 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2755 /* Don't issue the command if there's no endpoints to update. */
2756 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2757 ctrl_ctx->drop_flags == 0) {
2759 goto command_cleanup;
2761 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2762 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2763 for (i = 31; i >= 1; i--) {
2764 __le32 le32 = cpu_to_le32(BIT(i));
2766 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2767 || (ctrl_ctx->add_flags & le32) || i == 1) {
2768 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2769 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2773 xhci_dbg(xhci, "New Input Control Context:\n");
2774 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2775 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2777 ret = xhci_configure_endpoint(xhci, udev, command,
2780 /* Callee should call reset_bandwidth() */
2781 goto command_cleanup;
2783 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2784 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2785 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2787 /* Free any rings that were dropped, but not changed. */
2788 for (i = 1; i < 31; i++) {
2789 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2790 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2791 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2792 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2795 xhci_zero_in_ctx(xhci, virt_dev);
2797 * Install any rings for completely new endpoints or changed endpoints,
2798 * and free or cache any old rings from changed endpoints.
2800 for (i = 1; i < 31; i++) {
2801 if (!virt_dev->eps[i].new_ring)
2803 /* Only cache or free the old ring if it exists.
2804 * It may not if this is the first add of an endpoint.
2806 if (virt_dev->eps[i].ring) {
2807 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2809 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2810 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2811 virt_dev->eps[i].new_ring = NULL;
2814 kfree(command->completion);
2820 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2822 struct xhci_hcd *xhci;
2823 struct xhci_virt_device *virt_dev;
2826 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2829 xhci = hcd_to_xhci(hcd);
2831 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2832 virt_dev = xhci->devs[udev->slot_id];
2833 /* Free any rings allocated for added endpoints */
2834 for (i = 0; i < 31; i++) {
2835 if (virt_dev->eps[i].new_ring) {
2836 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2837 virt_dev->eps[i].new_ring = NULL;
2840 xhci_zero_in_ctx(xhci, virt_dev);
2843 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2844 struct xhci_container_ctx *in_ctx,
2845 struct xhci_container_ctx *out_ctx,
2846 struct xhci_input_control_ctx *ctrl_ctx,
2847 u32 add_flags, u32 drop_flags)
2849 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2850 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2851 xhci_slot_copy(xhci, in_ctx, out_ctx);
2852 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2854 xhci_dbg(xhci, "Input Context:\n");
2855 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2858 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2859 unsigned int slot_id, unsigned int ep_index,
2860 struct xhci_dequeue_state *deq_state)
2862 struct xhci_input_control_ctx *ctrl_ctx;
2863 struct xhci_container_ctx *in_ctx;
2864 struct xhci_ep_ctx *ep_ctx;
2868 in_ctx = xhci->devs[slot_id]->in_ctx;
2869 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2871 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2876 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2877 xhci->devs[slot_id]->out_ctx, ep_index);
2878 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2879 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2880 deq_state->new_deq_ptr);
2882 xhci_warn(xhci, "WARN Cannot submit config ep after "
2883 "reset ep command\n");
2884 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2885 deq_state->new_deq_seg,
2886 deq_state->new_deq_ptr);
2889 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2891 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2892 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2893 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2894 added_ctxs, added_ctxs);
2897 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2898 unsigned int ep_index, struct xhci_td *td)
2900 struct xhci_dequeue_state deq_state;
2901 struct xhci_virt_ep *ep;
2902 struct usb_device *udev = td->urb->dev;
2904 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2905 "Cleaning up stalled endpoint ring");
2906 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2907 /* We need to move the HW's dequeue pointer past this TD,
2908 * or it will attempt to resend it on the next doorbell ring.
2910 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2911 ep_index, ep->stopped_stream, td, &deq_state);
2913 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2916 /* HW with the reset endpoint quirk will use the saved dequeue state to
2917 * issue a configure endpoint command later.
2919 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2920 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2921 "Queueing new dequeue state");
2922 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2923 ep_index, ep->stopped_stream, &deq_state);
2925 /* Better hope no one uses the input context between now and the
2926 * reset endpoint completion!
2927 * XXX: No idea how this hardware will react when stream rings
2930 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2931 "Setting up input context for "
2932 "configure endpoint command");
2933 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2934 ep_index, &deq_state);
2938 /* Called when clearing halted device. The core should have sent the control
2939 * message to clear the device halt condition. The host side of the halt should
2940 * already be cleared with a reset endpoint command issued when the STALL tx
2941 * event was received.
2943 * Context: in_interrupt
2946 void xhci_endpoint_reset(struct usb_hcd *hcd,
2947 struct usb_host_endpoint *ep)
2949 struct xhci_hcd *xhci;
2951 xhci = hcd_to_xhci(hcd);
2954 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2955 * The Reset Endpoint Command may only be issued to endpoints in the
2956 * Halted state. If software wishes reset the Data Toggle or Sequence
2957 * Number of an endpoint that isn't in the Halted state, then software
2958 * may issue a Configure Endpoint Command with the Drop and Add bits set
2959 * for the target endpoint. that is in the Stopped state.
2962 /* For now just print debug to follow the situation */
2963 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2964 ep->desc.bEndpointAddress);
2967 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2968 struct usb_device *udev, struct usb_host_endpoint *ep,
2969 unsigned int slot_id)
2972 unsigned int ep_index;
2973 unsigned int ep_state;
2977 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2980 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2981 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2982 " descriptor for ep 0x%x does not support streams\n",
2983 ep->desc.bEndpointAddress);
2987 ep_index = xhci_get_endpoint_index(&ep->desc);
2988 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2989 if (ep_state & EP_HAS_STREAMS ||
2990 ep_state & EP_GETTING_STREAMS) {
2991 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2992 "already has streams set up.\n",
2993 ep->desc.bEndpointAddress);
2994 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2995 "dynamic stream context array reallocation.\n");
2998 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2999 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3000 "endpoint 0x%x; URBs are pending.\n",
3001 ep->desc.bEndpointAddress);
3007 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3008 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3010 unsigned int max_streams;
3012 /* The stream context array size must be a power of two */
3013 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3015 * Find out how many primary stream array entries the host controller
3016 * supports. Later we may use secondary stream arrays (similar to 2nd
3017 * level page entries), but that's an optional feature for xHCI host
3018 * controllers. xHCs must support at least 4 stream IDs.
3020 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3021 if (*num_stream_ctxs > max_streams) {
3022 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3024 *num_stream_ctxs = max_streams;
3025 *num_streams = max_streams;
3029 /* Returns an error code if one of the endpoint already has streams.
3030 * This does not change any data structures, it only checks and gathers
3033 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3034 struct usb_device *udev,
3035 struct usb_host_endpoint **eps, unsigned int num_eps,
3036 unsigned int *num_streams, u32 *changed_ep_bitmask)
3038 unsigned int max_streams;
3039 unsigned int endpoint_flag;
3043 for (i = 0; i < num_eps; i++) {
3044 ret = xhci_check_streams_endpoint(xhci, udev,
3045 eps[i], udev->slot_id);
3049 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3050 if (max_streams < (*num_streams - 1)) {
3051 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3052 eps[i]->desc.bEndpointAddress,
3054 *num_streams = max_streams+1;
3057 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3058 if (*changed_ep_bitmask & endpoint_flag)
3060 *changed_ep_bitmask |= endpoint_flag;
3065 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3066 struct usb_device *udev,
3067 struct usb_host_endpoint **eps, unsigned int num_eps)
3069 u32 changed_ep_bitmask = 0;
3070 unsigned int slot_id;
3071 unsigned int ep_index;
3072 unsigned int ep_state;
3075 slot_id = udev->slot_id;
3076 if (!xhci->devs[slot_id])
3079 for (i = 0; i < num_eps; i++) {
3080 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3081 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3082 /* Are streams already being freed for the endpoint? */
3083 if (ep_state & EP_GETTING_NO_STREAMS) {
3084 xhci_warn(xhci, "WARN Can't disable streams for "
3086 "streams are being disabled already\n",
3087 eps[i]->desc.bEndpointAddress);
3090 /* Are there actually any streams to free? */
3091 if (!(ep_state & EP_HAS_STREAMS) &&
3092 !(ep_state & EP_GETTING_STREAMS)) {
3093 xhci_warn(xhci, "WARN Can't disable streams for "
3095 "streams are already disabled!\n",
3096 eps[i]->desc.bEndpointAddress);
3097 xhci_warn(xhci, "WARN xhci_free_streams() called "
3098 "with non-streams endpoint\n");
3101 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3103 return changed_ep_bitmask;
3107 * The USB device drivers use this function (through the HCD interface in USB
3108 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3109 * coordinate mass storage command queueing across multiple endpoints (basically
3110 * a stream ID == a task ID).
3112 * Setting up streams involves allocating the same size stream context array
3113 * for each endpoint and issuing a configure endpoint command for all endpoints.
3115 * Don't allow the call to succeed if one endpoint only supports one stream
3116 * (which means it doesn't support streams at all).
3118 * Drivers may get less stream IDs than they asked for, if the host controller
3119 * hardware or endpoints claim they can't support the number of requested
3122 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3123 struct usb_host_endpoint **eps, unsigned int num_eps,
3124 unsigned int num_streams, gfp_t mem_flags)
3127 struct xhci_hcd *xhci;
3128 struct xhci_virt_device *vdev;
3129 struct xhci_command *config_cmd;
3130 struct xhci_input_control_ctx *ctrl_ctx;
3131 unsigned int ep_index;
3132 unsigned int num_stream_ctxs;
3133 unsigned int max_packet;
3134 unsigned long flags;
3135 u32 changed_ep_bitmask = 0;
3140 /* Add one to the number of streams requested to account for
3141 * stream 0 that is reserved for xHCI usage.
3144 xhci = hcd_to_xhci(hcd);
3145 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3148 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3149 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3150 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3151 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3155 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3157 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3160 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3162 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3164 xhci_free_command(xhci, config_cmd);
3168 /* Check to make sure all endpoints are not already configured for
3169 * streams. While we're at it, find the maximum number of streams that
3170 * all the endpoints will support and check for duplicate endpoints.
3172 spin_lock_irqsave(&xhci->lock, flags);
3173 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3174 num_eps, &num_streams, &changed_ep_bitmask);
3176 xhci_free_command(xhci, config_cmd);
3177 spin_unlock_irqrestore(&xhci->lock, flags);
3180 if (num_streams <= 1) {
3181 xhci_warn(xhci, "WARN: endpoints can't handle "
3182 "more than one stream.\n");
3183 xhci_free_command(xhci, config_cmd);
3184 spin_unlock_irqrestore(&xhci->lock, flags);
3187 vdev = xhci->devs[udev->slot_id];
3188 /* Mark each endpoint as being in transition, so
3189 * xhci_urb_enqueue() will reject all URBs.
3191 for (i = 0; i < num_eps; i++) {
3192 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3193 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3195 spin_unlock_irqrestore(&xhci->lock, flags);
3197 /* Setup internal data structures and allocate HW data structures for
3198 * streams (but don't install the HW structures in the input context
3199 * until we're sure all memory allocation succeeded).
3201 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3202 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3203 num_stream_ctxs, num_streams);
3205 for (i = 0; i < num_eps; i++) {
3206 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3207 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3208 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3211 max_packet, mem_flags);
3212 if (!vdev->eps[ep_index].stream_info)
3214 /* Set maxPstreams in endpoint context and update deq ptr to
3215 * point to stream context array. FIXME
3219 /* Set up the input context for a configure endpoint command. */
3220 for (i = 0; i < num_eps; i++) {
3221 struct xhci_ep_ctx *ep_ctx;
3223 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3224 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3226 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3227 vdev->out_ctx, ep_index);
3228 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3229 vdev->eps[ep_index].stream_info);
3231 /* Tell the HW to drop its old copy of the endpoint context info
3232 * and add the updated copy from the input context.
3234 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3235 vdev->out_ctx, ctrl_ctx,
3236 changed_ep_bitmask, changed_ep_bitmask);
3238 /* Issue and wait for the configure endpoint command */
3239 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3242 /* xHC rejected the configure endpoint command for some reason, so we
3243 * leave the old ring intact and free our internal streams data
3249 spin_lock_irqsave(&xhci->lock, flags);
3250 for (i = 0; i < num_eps; i++) {
3251 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3252 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3253 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3254 udev->slot_id, ep_index);
3255 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3257 xhci_free_command(xhci, config_cmd);
3258 spin_unlock_irqrestore(&xhci->lock, flags);
3260 /* Subtract 1 for stream 0, which drivers can't use */
3261 return num_streams - 1;
3264 /* If it didn't work, free the streams! */
3265 for (i = 0; i < num_eps; i++) {
3266 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3267 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3268 vdev->eps[ep_index].stream_info = NULL;
3269 /* FIXME Unset maxPstreams in endpoint context and
3270 * update deq ptr to point to normal string ring.
3272 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3273 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3274 xhci_endpoint_zero(xhci, vdev, eps[i]);
3276 xhci_free_command(xhci, config_cmd);
3280 /* Transition the endpoint from using streams to being a "normal" endpoint
3283 * Modify the endpoint context state, submit a configure endpoint command,
3284 * and free all endpoint rings for streams if that completes successfully.
3286 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3287 struct usb_host_endpoint **eps, unsigned int num_eps,
3291 struct xhci_hcd *xhci;
3292 struct xhci_virt_device *vdev;
3293 struct xhci_command *command;
3294 struct xhci_input_control_ctx *ctrl_ctx;
3295 unsigned int ep_index;
3296 unsigned long flags;
3297 u32 changed_ep_bitmask;
3299 xhci = hcd_to_xhci(hcd);
3300 vdev = xhci->devs[udev->slot_id];
3302 /* Set up a configure endpoint command to remove the streams rings */
3303 spin_lock_irqsave(&xhci->lock, flags);
3304 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3305 udev, eps, num_eps);
3306 if (changed_ep_bitmask == 0) {
3307 spin_unlock_irqrestore(&xhci->lock, flags);
3311 /* Use the xhci_command structure from the first endpoint. We may have
3312 * allocated too many, but the driver may call xhci_free_streams() for
3313 * each endpoint it grouped into one call to xhci_alloc_streams().
3315 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3316 command = vdev->eps[ep_index].stream_info->free_streams_command;
3317 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3319 spin_unlock_irqrestore(&xhci->lock, flags);
3320 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3325 for (i = 0; i < num_eps; i++) {
3326 struct xhci_ep_ctx *ep_ctx;
3328 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3329 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3330 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3331 EP_GETTING_NO_STREAMS;
3333 xhci_endpoint_copy(xhci, command->in_ctx,
3334 vdev->out_ctx, ep_index);
3335 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3336 &vdev->eps[ep_index]);
3338 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3339 vdev->out_ctx, ctrl_ctx,
3340 changed_ep_bitmask, changed_ep_bitmask);
3341 spin_unlock_irqrestore(&xhci->lock, flags);
3343 /* Issue and wait for the configure endpoint command,
3344 * which must succeed.
3346 ret = xhci_configure_endpoint(xhci, udev, command,
3349 /* xHC rejected the configure endpoint command for some reason, so we
3350 * leave the streams rings intact.
3355 spin_lock_irqsave(&xhci->lock, flags);
3356 for (i = 0; i < num_eps; i++) {
3357 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3358 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3359 vdev->eps[ep_index].stream_info = NULL;
3360 /* FIXME Unset maxPstreams in endpoint context and
3361 * update deq ptr to point to normal string ring.
3363 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3364 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3366 spin_unlock_irqrestore(&xhci->lock, flags);
3372 * Deletes endpoint resources for endpoints that were active before a Reset
3373 * Device command, or a Disable Slot command. The Reset Device command leaves
3374 * the control endpoint intact, whereas the Disable Slot command deletes it.
3376 * Must be called with xhci->lock held.
3378 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3379 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3382 unsigned int num_dropped_eps = 0;
3383 unsigned int drop_flags = 0;
3385 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3386 if (virt_dev->eps[i].ring) {
3387 drop_flags |= 1 << i;
3391 xhci->num_active_eps -= num_dropped_eps;
3392 if (num_dropped_eps)
3393 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3394 "Dropped %u ep ctxs, flags = 0x%x, "
3396 num_dropped_eps, drop_flags,
3397 xhci->num_active_eps);
3401 * This submits a Reset Device Command, which will set the device state to 0,
3402 * set the device address to 0, and disable all the endpoints except the default
3403 * control endpoint. The USB core should come back and call
3404 * xhci_address_device(), and then re-set up the configuration. If this is
3405 * called because of a usb_reset_and_verify_device(), then the old alternate
3406 * settings will be re-installed through the normal bandwidth allocation
3409 * Wait for the Reset Device command to finish. Remove all structures
3410 * associated with the endpoints that were disabled. Clear the input device
3411 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3413 * If the virt_dev to be reset does not exist or does not match the udev,
3414 * it means the device is lost, possibly due to the xHC restore error and
3415 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3416 * re-allocate the device.
3418 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3421 unsigned long flags;
3422 struct xhci_hcd *xhci;
3423 unsigned int slot_id;
3424 struct xhci_virt_device *virt_dev;
3425 struct xhci_command *reset_device_cmd;
3426 int last_freed_endpoint;
3427 struct xhci_slot_ctx *slot_ctx;
3428 int old_active_eps = 0;
3430 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3433 xhci = hcd_to_xhci(hcd);
3434 slot_id = udev->slot_id;
3435 virt_dev = xhci->devs[slot_id];
3437 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3438 "not exist. Re-allocate the device\n", slot_id);
3439 ret = xhci_alloc_dev(hcd, udev);
3446 if (virt_dev->tt_info)
3447 old_active_eps = virt_dev->tt_info->active_eps;
3449 if (virt_dev->udev != udev) {
3450 /* If the virt_dev and the udev does not match, this virt_dev
3451 * may belong to another udev.
3452 * Re-allocate the device.
3454 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3455 "not match the udev. Re-allocate the device\n",
3457 ret = xhci_alloc_dev(hcd, udev);
3464 /* If device is not setup, there is no point in resetting it */
3465 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3466 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3467 SLOT_STATE_DISABLED)
3470 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3471 /* Allocate the command structure that holds the struct completion.
3472 * Assume we're in process context, since the normal device reset
3473 * process has to wait for the device anyway. Storage devices are
3474 * reset as part of error handling, so use GFP_NOIO instead of
3477 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3478 if (!reset_device_cmd) {
3479 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3483 /* Attempt to submit the Reset Device command to the command ring */
3484 spin_lock_irqsave(&xhci->lock, flags);
3486 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3488 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3489 spin_unlock_irqrestore(&xhci->lock, flags);
3490 goto command_cleanup;
3492 xhci_ring_cmd_db(xhci);
3493 spin_unlock_irqrestore(&xhci->lock, flags);
3495 /* Wait for the Reset Device command to finish */
3496 wait_for_completion(reset_device_cmd->completion);
3498 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3499 * unless we tried to reset a slot ID that wasn't enabled,
3500 * or the device wasn't in the addressed or configured state.
3502 ret = reset_device_cmd->status;
3504 case COMP_COMMAND_ABORTED:
3506 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3508 goto command_cleanup;
3509 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3510 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3511 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3513 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3514 xhci_dbg(xhci, "Not freeing device rings.\n");
3515 /* Don't treat this as an error. May change my mind later. */
3517 goto command_cleanup;
3519 xhci_dbg(xhci, "Successful reset device command.\n");
3522 if (xhci_is_vendor_info_code(xhci, ret))
3524 xhci_warn(xhci, "Unknown completion code %u for "
3525 "reset device command.\n", ret);
3527 goto command_cleanup;
3530 /* Free up host controller endpoint resources */
3531 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3532 spin_lock_irqsave(&xhci->lock, flags);
3533 /* Don't delete the default control endpoint resources */
3534 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3535 spin_unlock_irqrestore(&xhci->lock, flags);
3538 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3539 last_freed_endpoint = 1;
3540 for (i = 1; i < 31; i++) {
3541 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3543 if (ep->ep_state & EP_HAS_STREAMS) {
3544 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3545 xhci_get_endpoint_address(i));
3546 xhci_free_stream_info(xhci, ep->stream_info);
3547 ep->stream_info = NULL;
3548 ep->ep_state &= ~EP_HAS_STREAMS;
3552 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3553 last_freed_endpoint = i;
3555 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3556 xhci_drop_ep_from_interval_table(xhci,
3557 &virt_dev->eps[i].bw_info,
3562 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3564 /* If necessary, update the number of active TTs on this root port */
3565 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3567 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3568 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3572 xhci_free_command(xhci, reset_device_cmd);
3577 * At this point, the struct usb_device is about to go away, the device has
3578 * disconnected, and all traffic has been stopped and the endpoints have been
3579 * disabled. Free any HC data structures associated with that device.
3581 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3583 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3584 struct xhci_virt_device *virt_dev;
3585 unsigned long flags;
3588 struct xhci_command *command;
3590 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3594 #ifndef CONFIG_USB_DEFAULT_PERSIST
3596 * We called pm_runtime_get_noresume when the device was attached.
3597 * Decrement the counter here to allow controller to runtime suspend
3598 * if no devices remain.
3600 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3601 pm_runtime_put_noidle(hcd->self.controller);
3604 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3605 /* If the host is halted due to driver unload, we still need to free the
3608 if (ret <= 0 && ret != -ENODEV) {
3613 virt_dev = xhci->devs[udev->slot_id];
3615 /* Stop any wayward timer functions (which may grab the lock) */
3616 for (i = 0; i < 31; i++) {
3617 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3618 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3621 spin_lock_irqsave(&xhci->lock, flags);
3622 /* Don't disable the slot if the host controller is dead. */
3623 state = readl(&xhci->op_regs->status);
3624 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3625 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3626 xhci_free_virt_device(xhci, udev->slot_id);
3627 spin_unlock_irqrestore(&xhci->lock, flags);
3632 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3634 spin_unlock_irqrestore(&xhci->lock, flags);
3635 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3638 xhci_ring_cmd_db(xhci);
3639 spin_unlock_irqrestore(&xhci->lock, flags);
3642 * Event command completion handler will free any data structures
3643 * associated with the slot. XXX Can free sleep?
3648 * Checks if we have enough host controller resources for the default control
3651 * Must be called with xhci->lock held.
3653 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3655 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3656 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3657 "Not enough ep ctxs: "
3658 "%u active, need to add 1, limit is %u.",
3659 xhci->num_active_eps, xhci->limit_active_eps);
3662 xhci->num_active_eps += 1;
3663 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3664 "Adding 1 ep ctx, %u now active.",
3665 xhci->num_active_eps);
3671 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3672 * timed out, or allocating memory failed. Returns 1 on success.
3674 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3676 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3677 unsigned long flags;
3679 struct xhci_command *command;
3681 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3685 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3686 mutex_lock(&xhci->mutex);
3687 spin_lock_irqsave(&xhci->lock, flags);
3688 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3690 spin_unlock_irqrestore(&xhci->lock, flags);
3691 mutex_unlock(&xhci->mutex);
3692 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3693 xhci_free_command(xhci, command);
3696 xhci_ring_cmd_db(xhci);
3697 spin_unlock_irqrestore(&xhci->lock, flags);
3699 wait_for_completion(command->completion);
3700 slot_id = command->slot_id;
3701 mutex_unlock(&xhci->mutex);
3703 if (!slot_id || command->status != COMP_SUCCESS) {
3704 xhci_err(xhci, "Error while assigning device slot ID\n");
3705 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3707 readl(&xhci->cap_regs->hcs_params1)));
3708 xhci_free_command(xhci, command);
3712 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3713 spin_lock_irqsave(&xhci->lock, flags);
3714 ret = xhci_reserve_host_control_ep_resources(xhci);
3716 spin_unlock_irqrestore(&xhci->lock, flags);
3717 xhci_warn(xhci, "Not enough host resources, "
3718 "active endpoint contexts = %u\n",
3719 xhci->num_active_eps);
3722 spin_unlock_irqrestore(&xhci->lock, flags);
3724 /* Use GFP_NOIO, since this function can be called from
3725 * xhci_discover_or_reset_device(), which may be called as part of
3726 * mass storage driver error handling.
3728 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3729 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3732 udev->slot_id = slot_id;
3734 #ifndef CONFIG_USB_DEFAULT_PERSIST
3736 * If resetting upon resume, we can't put the controller into runtime
3737 * suspend if there is a device attached.
3739 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3740 pm_runtime_get_noresume(hcd->self.controller);
3744 xhci_free_command(xhci, command);
3745 /* Is this a LS or FS device under a HS hub? */
3746 /* Hub or peripherial? */
3750 /* Disable slot, if we can do it without mem alloc */
3751 spin_lock_irqsave(&xhci->lock, flags);
3752 kfree(command->completion);
3753 command->completion = NULL;
3754 command->status = 0;
3755 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3757 xhci_ring_cmd_db(xhci);
3758 spin_unlock_irqrestore(&xhci->lock, flags);
3763 * Issue an Address Device command and optionally send a corresponding
3764 * SetAddress request to the device.
3766 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3767 enum xhci_setup_dev setup)
3769 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3770 unsigned long flags;
3771 struct xhci_virt_device *virt_dev;
3773 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3774 struct xhci_slot_ctx *slot_ctx;
3775 struct xhci_input_control_ctx *ctrl_ctx;
3777 struct xhci_command *command = NULL;
3779 mutex_lock(&xhci->mutex);
3781 if (xhci->xhc_state) { /* dying, removing or halted */
3786 if (!udev->slot_id) {
3787 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3788 "Bad Slot ID %d", udev->slot_id);
3793 virt_dev = xhci->devs[udev->slot_id];
3795 if (WARN_ON(!virt_dev)) {
3797 * In plug/unplug torture test with an NEC controller,
3798 * a zero-dereference was observed once due to virt_dev = 0.
3799 * Print useful debug rather than crash if it is observed again!
3801 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3807 if (setup == SETUP_CONTEXT_ONLY) {
3808 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3809 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3810 SLOT_STATE_DEFAULT) {
3811 xhci_dbg(xhci, "Slot already in default state\n");
3816 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3822 command->in_ctx = virt_dev->in_ctx;
3824 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3825 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3827 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3833 * If this is the first Set Address since device plug-in or
3834 * virt_device realloaction after a resume with an xHCI power loss,
3835 * then set up the slot context.
3837 if (!slot_ctx->dev_info)
3838 xhci_setup_addressable_virt_dev(xhci, udev);
3839 /* Otherwise, update the control endpoint ring enqueue pointer. */
3841 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3842 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3843 ctrl_ctx->drop_flags = 0;
3845 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3846 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3847 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3848 le32_to_cpu(slot_ctx->dev_info) >> 27);
3850 spin_lock_irqsave(&xhci->lock, flags);
3851 trace_xhci_setup_device(virt_dev);
3852 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3853 udev->slot_id, setup);
3855 spin_unlock_irqrestore(&xhci->lock, flags);
3856 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3857 "FIXME: allocate a command ring segment");
3860 xhci_ring_cmd_db(xhci);
3861 spin_unlock_irqrestore(&xhci->lock, flags);
3863 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3864 wait_for_completion(command->completion);
3866 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3867 * the SetAddress() "recovery interval" required by USB and aborting the
3868 * command on a timeout.
3870 switch (command->status) {
3871 case COMP_COMMAND_ABORTED:
3873 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3876 case COMP_CONTEXT_STATE_ERROR:
3877 case COMP_SLOT_NOT_ENABLED_ERROR:
3878 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3879 act, udev->slot_id);
3882 case COMP_USB_TRANSACTION_ERROR:
3883 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3886 case COMP_INCOMPATIBLE_DEVICE_ERROR:
3887 dev_warn(&udev->dev,
3888 "ERROR: Incompatible device for setup %s command\n", act);
3892 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3893 "Successful setup %s command", act);
3897 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3898 act, command->status);
3899 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3900 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3901 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3907 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3908 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3909 "Op regs DCBAA ptr = %#016llx", temp_64);
3910 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3911 "Slot ID %d dcbaa entry @%p = %#016llx",
3913 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3914 (unsigned long long)
3915 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3916 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3917 "Output Context DMA address = %#08llx",
3918 (unsigned long long)virt_dev->out_ctx->dma);
3919 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3920 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3921 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3922 le32_to_cpu(slot_ctx->dev_info) >> 27);
3923 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3924 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3926 * USB core uses address 1 for the roothubs, so we add one to the
3927 * address given back to us by the HC.
3929 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3930 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3931 le32_to_cpu(slot_ctx->dev_info) >> 27);
3932 /* Zero the input context control for later use */
3933 ctrl_ctx->add_flags = 0;
3934 ctrl_ctx->drop_flags = 0;
3936 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3937 "Internal device address = %d",
3938 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3940 mutex_unlock(&xhci->mutex);
3942 kfree(command->completion);
3948 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3950 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3953 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3955 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3959 * Transfer the port index into real index in the HW port status
3960 * registers. Caculate offset between the port's PORTSC register
3961 * and port status base. Divide the number of per port register
3962 * to get the real index. The raw port number bases 1.
3964 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3966 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3967 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3968 __le32 __iomem *addr;
3971 if (hcd->speed < HCD_USB3)
3972 addr = xhci->usb2_ports[port1 - 1];
3974 addr = xhci->usb3_ports[port1 - 1];
3976 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3981 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3982 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3984 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3985 struct usb_device *udev, u16 max_exit_latency)
3987 struct xhci_virt_device *virt_dev;
3988 struct xhci_command *command;
3989 struct xhci_input_control_ctx *ctrl_ctx;
3990 struct xhci_slot_ctx *slot_ctx;
3991 unsigned long flags;
3994 spin_lock_irqsave(&xhci->lock, flags);
3996 virt_dev = xhci->devs[udev->slot_id];
3999 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4000 * xHC was re-initialized. Exit latency will be set later after
4001 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4004 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4005 spin_unlock_irqrestore(&xhci->lock, flags);
4009 /* Attempt to issue an Evaluate Context command to change the MEL. */
4010 command = xhci->lpm_command;
4011 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4013 spin_unlock_irqrestore(&xhci->lock, flags);
4014 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4019 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4020 spin_unlock_irqrestore(&xhci->lock, flags);
4022 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4023 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4024 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4025 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4026 slot_ctx->dev_state = 0;
4028 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4029 "Set up evaluate context for LPM MEL change.");
4030 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4031 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4033 /* Issue and wait for the evaluate context command. */
4034 ret = xhci_configure_endpoint(xhci, udev, command,
4036 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4037 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4040 spin_lock_irqsave(&xhci->lock, flags);
4041 virt_dev->current_mel = max_exit_latency;
4042 spin_unlock_irqrestore(&xhci->lock, flags);
4049 /* BESL to HIRD Encoding array for USB2 LPM */
4050 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4051 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4053 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4054 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4055 struct usb_device *udev)
4057 int u2del, besl, besl_host;
4058 int besl_device = 0;
4061 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4062 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4064 if (field & USB_BESL_SUPPORT) {
4065 for (besl_host = 0; besl_host < 16; besl_host++) {
4066 if (xhci_besl_encoding[besl_host] >= u2del)
4069 /* Use baseline BESL value as default */
4070 if (field & USB_BESL_BASELINE_VALID)
4071 besl_device = USB_GET_BESL_BASELINE(field);
4072 else if (field & USB_BESL_DEEP_VALID)
4073 besl_device = USB_GET_BESL_DEEP(field);
4078 besl_host = (u2del - 51) / 75 + 1;
4081 besl = besl_host + besl_device;
4088 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4089 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4096 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4098 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4099 l1 = udev->l1_params.timeout / 256;
4101 /* device has preferred BESLD */
4102 if (field & USB_BESL_DEEP_VALID) {
4103 besld = USB_GET_BESL_DEEP(field);
4107 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4110 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4111 struct usb_device *udev, int enable)
4113 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4114 __le32 __iomem **port_array;
4115 __le32 __iomem *pm_addr, *hlpm_addr;
4116 u32 pm_val, hlpm_val, field;
4117 unsigned int port_num;
4118 unsigned long flags;
4119 int hird, exit_latency;
4122 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4126 if (!udev->parent || udev->parent->parent ||
4127 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4130 if (udev->usb2_hw_lpm_capable != 1)
4133 spin_lock_irqsave(&xhci->lock, flags);
4135 port_array = xhci->usb2_ports;
4136 port_num = udev->portnum - 1;
4137 pm_addr = port_array[port_num] + PORTPMSC;
4138 pm_val = readl(pm_addr);
4139 hlpm_addr = port_array[port_num] + PORTHLPMC;
4140 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4142 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4143 enable ? "enable" : "disable", port_num + 1);
4146 /* Host supports BESL timeout instead of HIRD */
4147 if (udev->usb2_hw_lpm_besl_capable) {
4148 /* if device doesn't have a preferred BESL value use a
4149 * default one which works with mixed HIRD and BESL
4150 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4152 if ((field & USB_BESL_SUPPORT) &&
4153 (field & USB_BESL_BASELINE_VALID))
4154 hird = USB_GET_BESL_BASELINE(field);
4156 hird = udev->l1_params.besl;
4158 exit_latency = xhci_besl_encoding[hird];
4159 spin_unlock_irqrestore(&xhci->lock, flags);
4161 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4162 * input context for link powermanagement evaluate
4163 * context commands. It is protected by hcd->bandwidth
4164 * mutex and is shared by all devices. We need to set
4165 * the max ext latency in USB 2 BESL LPM as well, so
4166 * use the same mutex and xhci_change_max_exit_latency()
4168 mutex_lock(hcd->bandwidth_mutex);
4169 ret = xhci_change_max_exit_latency(xhci, udev,
4171 mutex_unlock(hcd->bandwidth_mutex);
4175 spin_lock_irqsave(&xhci->lock, flags);
4177 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4178 writel(hlpm_val, hlpm_addr);
4182 hird = xhci_calculate_hird_besl(xhci, udev);
4185 pm_val &= ~PORT_HIRD_MASK;
4186 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4187 writel(pm_val, pm_addr);
4188 pm_val = readl(pm_addr);
4190 writel(pm_val, pm_addr);
4194 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4195 writel(pm_val, pm_addr);
4198 if (udev->usb2_hw_lpm_besl_capable) {
4199 spin_unlock_irqrestore(&xhci->lock, flags);
4200 mutex_lock(hcd->bandwidth_mutex);
4201 xhci_change_max_exit_latency(xhci, udev, 0);
4202 mutex_unlock(hcd->bandwidth_mutex);
4207 spin_unlock_irqrestore(&xhci->lock, flags);
4211 /* check if a usb2 port supports a given extened capability protocol
4212 * only USB2 ports extended protocol capability values are cached.
4213 * Return 1 if capability is supported
4215 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4216 unsigned capability)
4218 u32 port_offset, port_count;
4221 for (i = 0; i < xhci->num_ext_caps; i++) {
4222 if (xhci->ext_caps[i] & capability) {
4223 /* port offsets starts at 1 */
4224 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4225 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4226 if (port >= port_offset &&
4227 port < port_offset + port_count)
4234 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4236 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4237 int portnum = udev->portnum - 1;
4239 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4243 /* we only support lpm for non-hub device connected to root hub yet */
4244 if (!udev->parent || udev->parent->parent ||
4245 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4248 if (xhci->hw_lpm_support == 1 &&
4249 xhci_check_usb2_port_capability(
4250 xhci, portnum, XHCI_HLC)) {
4251 udev->usb2_hw_lpm_capable = 1;
4252 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4253 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4254 if (xhci_check_usb2_port_capability(xhci, portnum,
4256 udev->usb2_hw_lpm_besl_capable = 1;
4262 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4264 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4265 static unsigned long long xhci_service_interval_to_ns(
4266 struct usb_endpoint_descriptor *desc)
4268 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4271 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4272 enum usb3_link_state state)
4274 unsigned long long sel;
4275 unsigned long long pel;
4276 unsigned int max_sel_pel;
4281 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4282 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4283 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4284 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4288 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4289 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4290 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4294 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4296 return USB3_LPM_DISABLED;
4299 if (sel <= max_sel_pel && pel <= max_sel_pel)
4300 return USB3_LPM_DEVICE_INITIATED;
4302 if (sel > max_sel_pel)
4303 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4304 "due to long SEL %llu ms\n",
4307 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4308 "due to long PEL %llu ms\n",
4310 return USB3_LPM_DISABLED;
4313 /* The U1 timeout should be the maximum of the following values:
4314 * - For control endpoints, U1 system exit latency (SEL) * 3
4315 * - For bulk endpoints, U1 SEL * 5
4316 * - For interrupt endpoints:
4317 * - Notification EPs, U1 SEL * 3
4318 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4319 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4321 static unsigned long long xhci_calculate_intel_u1_timeout(
4322 struct usb_device *udev,
4323 struct usb_endpoint_descriptor *desc)
4325 unsigned long long timeout_ns;
4329 ep_type = usb_endpoint_type(desc);
4331 case USB_ENDPOINT_XFER_CONTROL:
4332 timeout_ns = udev->u1_params.sel * 3;
4334 case USB_ENDPOINT_XFER_BULK:
4335 timeout_ns = udev->u1_params.sel * 5;
4337 case USB_ENDPOINT_XFER_INT:
4338 intr_type = usb_endpoint_interrupt_type(desc);
4339 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4340 timeout_ns = udev->u1_params.sel * 3;
4343 /* Otherwise the calculation is the same as isoc eps */
4344 case USB_ENDPOINT_XFER_ISOC:
4345 timeout_ns = xhci_service_interval_to_ns(desc);
4346 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4347 if (timeout_ns < udev->u1_params.sel * 2)
4348 timeout_ns = udev->u1_params.sel * 2;
4357 /* Returns the hub-encoded U1 timeout value. */
4358 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4359 struct usb_device *udev,
4360 struct usb_endpoint_descriptor *desc)
4362 unsigned long long timeout_ns;
4364 if (xhci->quirks & XHCI_INTEL_HOST)
4365 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4367 timeout_ns = udev->u1_params.sel;
4369 /* The U1 timeout is encoded in 1us intervals.
4370 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4372 if (timeout_ns == USB3_LPM_DISABLED)
4375 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4377 /* If the necessary timeout value is bigger than what we can set in the
4378 * USB 3.0 hub, we have to disable hub-initiated U1.
4380 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4382 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4383 "due to long timeout %llu ms\n", timeout_ns);
4384 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4387 /* The U2 timeout should be the maximum of:
4388 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4389 * - largest bInterval of any active periodic endpoint (to avoid going
4390 * into lower power link states between intervals).
4391 * - the U2 Exit Latency of the device
4393 static unsigned long long xhci_calculate_intel_u2_timeout(
4394 struct usb_device *udev,
4395 struct usb_endpoint_descriptor *desc)
4397 unsigned long long timeout_ns;
4398 unsigned long long u2_del_ns;
4400 timeout_ns = 10 * 1000 * 1000;
4402 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4403 (xhci_service_interval_to_ns(desc) > timeout_ns))
4404 timeout_ns = xhci_service_interval_to_ns(desc);
4406 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4407 if (u2_del_ns > timeout_ns)
4408 timeout_ns = u2_del_ns;
4413 /* Returns the hub-encoded U2 timeout value. */
4414 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4415 struct usb_device *udev,
4416 struct usb_endpoint_descriptor *desc)
4418 unsigned long long timeout_ns;
4420 if (xhci->quirks & XHCI_INTEL_HOST)
4421 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4423 timeout_ns = udev->u2_params.sel;
4425 /* The U2 timeout is encoded in 256us intervals */
4426 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4427 /* If the necessary timeout value is bigger than what we can set in the
4428 * USB 3.0 hub, we have to disable hub-initiated U2.
4430 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4432 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4433 "due to long timeout %llu ms\n", timeout_ns);
4434 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4437 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4438 struct usb_device *udev,
4439 struct usb_endpoint_descriptor *desc,
4440 enum usb3_link_state state,
4443 if (state == USB3_LPM_U1)
4444 return xhci_calculate_u1_timeout(xhci, udev, desc);
4445 else if (state == USB3_LPM_U2)
4446 return xhci_calculate_u2_timeout(xhci, udev, desc);
4448 return USB3_LPM_DISABLED;
4451 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4452 struct usb_device *udev,
4453 struct usb_endpoint_descriptor *desc,
4454 enum usb3_link_state state,
4459 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4460 desc, state, timeout);
4462 /* If we found we can't enable hub-initiated LPM, or
4463 * the U1 or U2 exit latency was too high to allow
4464 * device-initiated LPM as well, just stop searching.
4466 if (alt_timeout == USB3_LPM_DISABLED ||
4467 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4468 *timeout = alt_timeout;
4471 if (alt_timeout > *timeout)
4472 *timeout = alt_timeout;
4476 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4477 struct usb_device *udev,
4478 struct usb_host_interface *alt,
4479 enum usb3_link_state state,
4484 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4485 if (xhci_update_timeout_for_endpoint(xhci, udev,
4486 &alt->endpoint[j].desc, state, timeout))
4493 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4494 enum usb3_link_state state)
4496 struct usb_device *parent;
4497 unsigned int num_hubs;
4499 if (state == USB3_LPM_U2)
4502 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4503 for (parent = udev->parent, num_hubs = 0; parent->parent;
4504 parent = parent->parent)
4510 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4511 " below second-tier hub.\n");
4512 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4513 "to decrease power consumption.\n");
4517 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4518 struct usb_device *udev,
4519 enum usb3_link_state state)
4521 if (xhci->quirks & XHCI_INTEL_HOST)
4522 return xhci_check_intel_tier_policy(udev, state);
4527 /* Returns the U1 or U2 timeout that should be enabled.
4528 * If the tier check or timeout setting functions return with a non-zero exit
4529 * code, that means the timeout value has been finalized and we shouldn't look
4530 * at any more endpoints.
4532 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4533 struct usb_device *udev, enum usb3_link_state state)
4535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4536 struct usb_host_config *config;
4539 u16 timeout = USB3_LPM_DISABLED;
4541 if (state == USB3_LPM_U1)
4543 else if (state == USB3_LPM_U2)
4546 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4551 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4554 /* Gather some information about the currently installed configuration
4555 * and alternate interface settings.
4557 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4561 config = udev->actconfig;
4565 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4566 struct usb_driver *driver;
4567 struct usb_interface *intf = config->interface[i];
4572 /* Check if any currently bound drivers want hub-initiated LPM
4575 if (intf->dev.driver) {
4576 driver = to_usb_driver(intf->dev.driver);
4577 if (driver && driver->disable_hub_initiated_lpm) {
4578 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4579 "at request of driver %s\n",
4580 state_name, driver->name);
4581 return xhci_get_timeout_no_hub_lpm(udev, state);
4585 /* Not sure how this could happen... */
4586 if (!intf->cur_altsetting)
4589 if (xhci_update_timeout_for_interface(xhci, udev,
4590 intf->cur_altsetting,
4597 static int calculate_max_exit_latency(struct usb_device *udev,
4598 enum usb3_link_state state_changed,
4599 u16 hub_encoded_timeout)
4601 unsigned long long u1_mel_us = 0;
4602 unsigned long long u2_mel_us = 0;
4603 unsigned long long mel_us = 0;
4609 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4610 hub_encoded_timeout == USB3_LPM_DISABLED);
4611 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4612 hub_encoded_timeout == USB3_LPM_DISABLED);
4614 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4615 hub_encoded_timeout != USB3_LPM_DISABLED);
4616 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4617 hub_encoded_timeout != USB3_LPM_DISABLED);
4619 /* If U1 was already enabled and we're not disabling it,
4620 * or we're going to enable U1, account for the U1 max exit latency.
4622 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4624 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4625 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4627 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4629 if (u1_mel_us > u2_mel_us)
4633 /* xHCI host controller max exit latency field is only 16 bits wide. */
4634 if (mel_us > MAX_EXIT) {
4635 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4636 "is too big.\n", mel_us);
4642 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4643 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4644 struct usb_device *udev, enum usb3_link_state state)
4646 struct xhci_hcd *xhci;
4647 u16 hub_encoded_timeout;
4651 xhci = hcd_to_xhci(hcd);
4652 /* The LPM timeout values are pretty host-controller specific, so don't
4653 * enable hub-initiated timeouts unless the vendor has provided
4654 * information about their timeout algorithm.
4656 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4657 !xhci->devs[udev->slot_id])
4658 return USB3_LPM_DISABLED;
4660 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4661 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4663 /* Max Exit Latency is too big, disable LPM. */
4664 hub_encoded_timeout = USB3_LPM_DISABLED;
4668 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4671 return hub_encoded_timeout;
4674 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4675 struct usb_device *udev, enum usb3_link_state state)
4677 struct xhci_hcd *xhci;
4680 xhci = hcd_to_xhci(hcd);
4681 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4682 !xhci->devs[udev->slot_id])
4685 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4686 return xhci_change_max_exit_latency(xhci, udev, mel);
4688 #else /* CONFIG_PM */
4690 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4691 struct usb_device *udev, int enable)
4696 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4701 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4702 struct usb_device *udev, enum usb3_link_state state)
4704 return USB3_LPM_DISABLED;
4707 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4708 struct usb_device *udev, enum usb3_link_state state)
4712 #endif /* CONFIG_PM */
4714 /*-------------------------------------------------------------------------*/
4716 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4717 * internal data structures for the device.
4719 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4720 struct usb_tt *tt, gfp_t mem_flags)
4722 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4723 struct xhci_virt_device *vdev;
4724 struct xhci_command *config_cmd;
4725 struct xhci_input_control_ctx *ctrl_ctx;
4726 struct xhci_slot_ctx *slot_ctx;
4727 unsigned long flags;
4728 unsigned think_time;
4731 /* Ignore root hubs */
4735 vdev = xhci->devs[hdev->slot_id];
4737 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4740 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4742 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4745 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4747 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4749 xhci_free_command(xhci, config_cmd);
4753 spin_lock_irqsave(&xhci->lock, flags);
4754 if (hdev->speed == USB_SPEED_HIGH &&
4755 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4756 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4757 xhci_free_command(xhci, config_cmd);
4758 spin_unlock_irqrestore(&xhci->lock, flags);
4762 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4763 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4764 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4765 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4767 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4768 * but it may be already set to 1 when setup an xHCI virtual
4769 * device, so clear it anyway.
4772 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4773 else if (hdev->speed == USB_SPEED_FULL)
4774 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4776 if (xhci->hci_version > 0x95) {
4777 xhci_dbg(xhci, "xHCI version %x needs hub "
4778 "TT think time and number of ports\n",
4779 (unsigned int) xhci->hci_version);
4780 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4781 /* Set TT think time - convert from ns to FS bit times.
4782 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4783 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4785 * xHCI 1.0: this field shall be 0 if the device is not a
4788 think_time = tt->think_time;
4789 if (think_time != 0)
4790 think_time = (think_time / 666) - 1;
4791 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4792 slot_ctx->tt_info |=
4793 cpu_to_le32(TT_THINK_TIME(think_time));
4795 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4796 "TT think time or number of ports\n",
4797 (unsigned int) xhci->hci_version);
4799 slot_ctx->dev_state = 0;
4800 spin_unlock_irqrestore(&xhci->lock, flags);
4802 xhci_dbg(xhci, "Set up %s for hub device.\n",
4803 (xhci->hci_version > 0x95) ?
4804 "configure endpoint" : "evaluate context");
4805 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4806 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4808 /* Issue and wait for the configure endpoint or
4809 * evaluate context command.
4811 if (xhci->hci_version > 0x95)
4812 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4815 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4818 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4819 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4821 xhci_free_command(xhci, config_cmd);
4825 int xhci_get_frame(struct usb_hcd *hcd)
4827 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4828 /* EHCI mods by the periodic size. Why? */
4829 return readl(&xhci->run_regs->microframe_index) >> 3;
4832 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4834 struct xhci_hcd *xhci;
4835 struct device *dev = hcd->self.controller;
4838 /* Accept arbitrarily long scatter-gather lists */
4839 hcd->self.sg_tablesize = ~0;
4841 /* support to build packet from discontinuous buffers */
4842 hcd->self.no_sg_constraint = 1;
4844 /* XHCI controllers don't stop the ep queue on short packets :| */
4845 hcd->self.no_stop_on_short = 1;
4847 xhci = hcd_to_xhci(hcd);
4849 if (usb_hcd_is_primary_hcd(hcd)) {
4850 xhci->main_hcd = hcd;
4851 /* Mark the first roothub as being USB 2.0.
4852 * The xHCI driver will register the USB 3.0 roothub.
4854 hcd->speed = HCD_USB2;
4855 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4857 * USB 2.0 roothub under xHCI has an integrated TT,
4858 * (rate matching hub) as opposed to having an OHCI/UHCI
4859 * companion controller.
4863 if (xhci->sbrn == 0x31) {
4864 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4865 hcd->speed = HCD_USB31;
4866 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4868 /* xHCI private pointer was set in xhci_pci_probe for the second
4869 * registered roothub.
4874 mutex_init(&xhci->mutex);
4875 xhci->cap_regs = hcd->regs;
4876 xhci->op_regs = hcd->regs +
4877 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4878 xhci->run_regs = hcd->regs +
4879 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4880 /* Cache read-only capability registers */
4881 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4882 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4883 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4884 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4885 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4886 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4887 if (xhci->hci_version > 0x100)
4888 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4889 xhci_print_registers(xhci);
4891 xhci->quirks |= quirks;
4893 get_quirks(dev, xhci);
4895 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4896 * success event after a short transfer. This quirk will ignore such
4899 if (xhci->hci_version > 0x96)
4900 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4902 /* Make sure the HC is halted. */
4903 retval = xhci_halt(xhci);
4907 xhci_dbg(xhci, "Resetting HCD\n");
4908 /* Reset the internal HC memory state and registers. */
4909 retval = xhci_reset(xhci);
4912 xhci_dbg(xhci, "Reset complete\n");
4915 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4916 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4917 * address memory pointers actually. So, this driver clears the AC64
4918 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4919 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4921 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4922 xhci->hcc_params &= ~BIT(0);
4924 /* Set dma_mask and coherent_dma_mask to 64-bits,
4925 * if xHC supports 64-bit addressing */
4926 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4927 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4928 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4929 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4932 * This is to avoid error in cases where a 32-bit USB
4933 * controller is used on a 64-bit capable system.
4935 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4938 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4939 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4942 xhci_dbg(xhci, "Calling HCD init\n");
4943 /* Initialize HCD and host controller data structures. */
4944 retval = xhci_init(hcd);
4947 xhci_dbg(xhci, "Called HCD init\n");
4949 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4950 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4954 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4956 static const struct hc_driver xhci_hc_driver = {
4957 .description = "xhci-hcd",
4958 .product_desc = "xHCI Host Controller",
4959 .hcd_priv_size = sizeof(struct xhci_hcd),
4962 * generic hardware linkage
4965 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4968 * basic lifecycle operations
4970 .reset = NULL, /* set in xhci_init_driver() */
4973 .shutdown = xhci_shutdown,
4976 * managing i/o requests and associated device resources
4978 .urb_enqueue = xhci_urb_enqueue,
4979 .urb_dequeue = xhci_urb_dequeue,
4980 .alloc_dev = xhci_alloc_dev,
4981 .free_dev = xhci_free_dev,
4982 .alloc_streams = xhci_alloc_streams,
4983 .free_streams = xhci_free_streams,
4984 .add_endpoint = xhci_add_endpoint,
4985 .drop_endpoint = xhci_drop_endpoint,
4986 .endpoint_reset = xhci_endpoint_reset,
4987 .check_bandwidth = xhci_check_bandwidth,
4988 .reset_bandwidth = xhci_reset_bandwidth,
4989 .address_device = xhci_address_device,
4990 .enable_device = xhci_enable_device,
4991 .update_hub_device = xhci_update_hub_device,
4992 .reset_device = xhci_discover_or_reset_device,
4995 * scheduling support
4997 .get_frame_number = xhci_get_frame,
5002 .hub_control = xhci_hub_control,
5003 .hub_status_data = xhci_hub_status_data,
5004 .bus_suspend = xhci_bus_suspend,
5005 .bus_resume = xhci_bus_resume,
5008 * call back when device connected and addressed
5010 .update_device = xhci_update_device,
5011 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5012 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5013 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5014 .find_raw_port_number = xhci_find_raw_port_number,
5017 void xhci_init_driver(struct hc_driver *drv,
5018 const struct xhci_driver_overrides *over)
5022 /* Copy the generic table to drv then apply the overrides */
5023 *drv = xhci_hc_driver;
5026 drv->hcd_priv_size += over->extra_priv_size;
5028 drv->reset = over->reset;
5030 drv->start = over->start;
5033 EXPORT_SYMBOL_GPL(xhci_init_driver);
5035 MODULE_DESCRIPTION(DRIVER_DESC);
5036 MODULE_AUTHOR(DRIVER_AUTHOR);
5037 MODULE_LICENSE("GPL");
5039 static int __init xhci_hcd_init(void)
5042 * Check the compiler generated sizes of structures that must be laid
5043 * out in specific ways for hardware access.
5045 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5046 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5047 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5048 /* xhci_device_control has eight fields, and also
5049 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5051 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5052 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5053 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5054 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5055 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5056 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5057 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5066 * If an init function is provided, an exit function must also be provided
5067 * to allow module unload.
5069 static void __exit xhci_hcd_fini(void) { }
5071 module_init(xhci_hcd_init);
5072 module_exit(xhci_hcd_fini);