2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
36 #define DRIVER_AUTHOR "Sarah Sharp"
37 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
39 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
41 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42 static int link_quirk;
43 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
46 static unsigned int quirks;
47 module_param(quirks, uint, S_IRUGO);
48 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
50 /* TODO: copied from ehci-hcd.c - can this be refactored? */
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70 if (result == ~(u32)0) /* card removed */
82 * Disable interrupts and begin the xHCI halting process.
84 void xhci_quiesce(struct xhci_hcd *xhci)
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 cmd = readl(&xhci->op_regs->command);
97 writel(cmd, &xhci->op_regs->command);
101 * Force HC into halt state.
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
108 int xhci_halt(struct xhci_hcd *xhci)
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
117 xhci_warn(xhci, "Host halt failed, %d\n", ret);
120 xhci->xhc_state |= XHCI_STATE_HALTED;
121 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
126 * Set the run bit and wait for the host to be running.
128 static int xhci_start(struct xhci_hcd *xhci)
133 temp = readl(&xhci->op_regs->command);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
137 writel(temp, &xhci->op_regs->command);
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
150 /* clear state flags. Including dying, halted or removing */
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd *xhci)
169 state = readl(&xhci->op_regs->status);
171 if (state == ~(u32)0) {
172 xhci_warn(xhci, "Host not accessible, reset failed.\n");
176 if ((state & STS_HALT) == 0) {
177 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
182 command = readl(&xhci->op_regs->command);
183 command |= CMD_RESET;
184 writel(command, &xhci->op_regs->command);
186 /* Existing Intel xHCI controllers require a delay of 1 mS,
187 * after setting the CMD_RESET bit, and before accessing any
188 * HC registers. This allows the HC to complete the
189 * reset operation and be ready for HC register access.
190 * Without this delay, the subsequent HC register access,
191 * may result in a system hang very rarely.
193 if (xhci->quirks & XHCI_INTEL_HOST)
196 ret = xhci_handshake(&xhci->op_regs->command,
197 CMD_RESET, 0, 10 * 1000 * 1000);
201 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
202 "Wait for controller to be ready for doorbell rings");
204 * xHCI cannot write to any doorbells or operational registers other
205 * than status until the "Controller Not Ready" flag is cleared.
207 ret = xhci_handshake(&xhci->op_regs->status,
208 STS_CNR, 0, 10 * 1000 * 1000);
210 for (i = 0; i < 2; ++i) {
211 xhci->bus_state[i].port_c_suspend = 0;
212 xhci->bus_state[i].suspended_ports = 0;
213 xhci->bus_state[i].resuming_ports = 0;
220 static int xhci_free_msi(struct xhci_hcd *xhci)
224 if (!xhci->msix_entries)
227 for (i = 0; i < xhci->msix_count; i++)
228 if (xhci->msix_entries[i].vector)
229 free_irq(xhci->msix_entries[i].vector,
237 static int xhci_setup_msi(struct xhci_hcd *xhci)
240 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
242 ret = pci_enable_msi(pdev);
244 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
245 "failed to allocate MSI entry");
249 ret = request_irq(pdev->irq, xhci_msi_irq,
250 0, "xhci_hcd", xhci_to_hcd(xhci));
252 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
253 "disable MSI interrupt");
254 pci_disable_msi(pdev);
262 * free all IRQs request
264 static void xhci_free_irq(struct xhci_hcd *xhci)
266 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
269 /* return if using legacy interrupt */
270 if (xhci_to_hcd(xhci)->irq > 0)
273 ret = xhci_free_msi(xhci);
277 free_irq(pdev->irq, xhci_to_hcd(xhci));
285 static int xhci_setup_msix(struct xhci_hcd *xhci)
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
292 * calculate number of msi-x vectors supported.
293 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
294 * with max number of interrupters based on the xhci HCSPARAMS1.
295 * - num_online_cpus: maximum msi-x vectors per CPUs core.
296 * Add additional 1 vector to ensure always available interrupt.
298 xhci->msix_count = min(num_online_cpus() + 1,
299 HCS_MAX_INTRS(xhci->hcs_params1));
302 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
304 if (!xhci->msix_entries)
307 for (i = 0; i < xhci->msix_count; i++) {
308 xhci->msix_entries[i].entry = i;
309 xhci->msix_entries[i].vector = 0;
312 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "Failed to enable MSI-X");
319 for (i = 0; i < xhci->msix_count; i++) {
320 ret = request_irq(xhci->msix_entries[i].vector,
322 0, "xhci_hcd", xhci_to_hcd(xhci));
327 hcd->msix_enabled = 1;
331 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
333 pci_disable_msix(pdev);
335 kfree(xhci->msix_entries);
336 xhci->msix_entries = NULL;
340 /* Free any IRQs and disable MSI-X */
341 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
343 struct usb_hcd *hcd = xhci_to_hcd(xhci);
344 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
346 if (xhci->quirks & XHCI_PLAT)
351 if (xhci->msix_entries) {
352 pci_disable_msix(pdev);
353 kfree(xhci->msix_entries);
354 xhci->msix_entries = NULL;
356 pci_disable_msi(pdev);
359 hcd->msix_enabled = 0;
363 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
367 if (xhci->msix_entries) {
368 for (i = 0; i < xhci->msix_count; i++)
369 synchronize_irq(xhci->msix_entries[i].vector);
373 static int xhci_try_enable_msi(struct usb_hcd *hcd)
375 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
376 struct pci_dev *pdev;
379 /* The xhci platform device has set up IRQs through usb_add_hcd. */
380 if (xhci->quirks & XHCI_PLAT)
383 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
385 * Some Fresco Logic host controllers advertise MSI, but fail to
386 * generate interrupts. Don't even try to enable MSI.
388 if (xhci->quirks & XHCI_BROKEN_MSI)
391 /* unregister the legacy interrupt */
393 free_irq(hcd->irq, hcd);
396 ret = xhci_setup_msix(xhci);
398 /* fall back to msi*/
399 ret = xhci_setup_msi(xhci);
402 /* hcd->irq is 0, we have MSI */
406 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
411 if (!strlen(hcd->irq_descr))
412 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
413 hcd->driver->description, hcd->self.busnum);
415 /* fall back to legacy interrupt*/
416 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
417 hcd->irq_descr, hcd);
419 xhci_err(xhci, "request interrupt %d failed\n",
423 hcd->irq = pdev->irq;
429 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
434 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
438 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
444 static void compliance_mode_recovery(unsigned long arg)
446 struct xhci_hcd *xhci;
451 xhci = (struct xhci_hcd *)arg;
453 for (i = 0; i < xhci->num_usb3_ports; i++) {
454 temp = readl(xhci->usb3_ports[i]);
455 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
457 * Compliance Mode Detected. Letting USB Core
458 * handle the Warm Reset
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "Compliance mode detected->port %d",
463 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
464 "Attempting compliance mode recovery");
465 hcd = xhci->shared_hcd;
467 if (hcd->state == HC_STATE_SUSPENDED)
468 usb_hcd_resume_root_hub(hcd);
470 usb_hcd_poll_rh_status(hcd);
474 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
475 mod_timer(&xhci->comp_mode_recovery_timer,
476 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
480 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
481 * that causes ports behind that hardware to enter compliance mode sometimes.
482 * The quirk creates a timer that polls every 2 seconds the link state of
483 * each host controller's port and recovers it by issuing a Warm reset
484 * if Compliance mode is detected, otherwise the port will become "dead" (no
485 * device connections or disconnections will be detected anymore). Becasue no
486 * status event is generated when entering compliance mode (per xhci spec),
487 * this quirk is needed on systems that have the failing hardware installed.
489 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
491 xhci->port_status_u0 = 0;
492 setup_timer(&xhci->comp_mode_recovery_timer,
493 compliance_mode_recovery, (unsigned long)xhci);
494 xhci->comp_mode_recovery_timer.expires = jiffies +
495 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
497 add_timer(&xhci->comp_mode_recovery_timer);
498 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
499 "Compliance mode recovery timer initialized");
503 * This function identifies the systems that have installed the SN65LVPE502CP
504 * USB3.0 re-driver and that need the Compliance Mode Quirk.
506 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
508 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
510 const char *dmi_product_name, *dmi_sys_vendor;
512 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
513 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
514 if (!dmi_product_name || !dmi_sys_vendor)
517 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
520 if (strstr(dmi_product_name, "Z420") ||
521 strstr(dmi_product_name, "Z620") ||
522 strstr(dmi_product_name, "Z820") ||
523 strstr(dmi_product_name, "Z1 Workstation"))
529 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
531 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
536 * Initialize memory for HCD and xHC (one-time init).
538 * Program the PAGESIZE register, initialize the device context array, create
539 * device contexts (?), set up a command ring segment (or two?), create event
540 * ring (one for now).
542 int xhci_init(struct usb_hcd *hcd)
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
547 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
548 spin_lock_init(&xhci->lock);
549 if (xhci->hci_version == 0x95 && link_quirk) {
550 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
551 "QUIRK: Not clearing Link TRB chain bits.");
552 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
554 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
555 "xHCI doesn't need link TRB QUIRK");
557 retval = xhci_mem_init(xhci, GFP_KERNEL);
558 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
560 /* Initializing Compliance Mode Recovery Data If Needed */
561 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
562 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
563 compliance_mode_recovery_timer_init(xhci);
569 /*-------------------------------------------------------------------------*/
572 static int xhci_run_finished(struct xhci_hcd *xhci)
574 if (xhci_start(xhci)) {
578 xhci->shared_hcd->state = HC_STATE_RUNNING;
579 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
581 if (xhci->quirks & XHCI_NEC_HOST)
582 xhci_ring_cmd_db(xhci);
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
585 "Finished xhci_run for USB3 roothub");
590 * Start the HC after it was halted.
592 * This function is called by the USB core when the HC driver is added.
593 * Its opposite is xhci_stop().
595 * xhci_init() must be called once before this function can be called.
596 * Reset the HC, enable device slot contexts, program DCBAAP, and
597 * set command ring pointer and event ring pointer.
599 * Setup MSI-X vectors and enable interrupts.
601 int xhci_run(struct usb_hcd *hcd)
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
608 /* Start the xHCI host controller running only after the USB 2.0 roothub
612 hcd->uses_new_polling = 1;
613 if (!usb_hcd_is_primary_hcd(hcd))
614 return xhci_run_finished(xhci);
616 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
618 ret = xhci_try_enable_msi(hcd);
622 xhci_dbg(xhci, "Command ring memory map follows:\n");
623 xhci_debug_ring(xhci, xhci->cmd_ring);
624 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
625 xhci_dbg_cmd_ptrs(xhci);
627 xhci_dbg(xhci, "ERST memory map follows:\n");
628 xhci_dbg_erst(xhci, &xhci->erst);
629 xhci_dbg(xhci, "Event ring:\n");
630 xhci_debug_ring(xhci, xhci->event_ring);
631 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
632 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
633 temp_64 &= ~ERST_PTR_MASK;
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
637 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
638 "// Set the interrupt modulation register");
639 temp = readl(&xhci->ir_set->irq_control);
640 temp &= ~ER_IRQ_INTERVAL_MASK;
642 * the increment interval is 8 times as much as that defined
643 * in xHCI spec on MTK's controller
645 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
646 writel(temp, &xhci->ir_set->irq_control);
648 /* Set the HCD state before we enable the irqs */
649 temp = readl(&xhci->op_regs->command);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enable interrupts, cmd = 0x%x.", temp);
653 writel(temp, &xhci->op_regs->command);
655 temp = readl(&xhci->ir_set->irq_pending);
656 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
657 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
658 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
659 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
660 xhci_print_ir_set(xhci, 0);
662 if (xhci->quirks & XHCI_NEC_HOST) {
663 struct xhci_command *command;
664 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
667 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
668 TRB_TYPE(TRB_NEC_GET_FW));
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "Finished xhci_run for USB2 roothub");
674 EXPORT_SYMBOL_GPL(xhci_run);
679 * This function is called by the USB core when the HC driver is removed.
680 * Its opposite is xhci_run().
682 * Disable device contexts, disable IRQs, and quiesce the HC.
683 * Reset the HC, finish any completed transactions, and cleanup memory.
685 void xhci_stop(struct usb_hcd *hcd)
688 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
690 mutex_lock(&xhci->mutex);
692 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
693 spin_lock_irq(&xhci->lock);
695 xhci->xhc_state |= XHCI_STATE_HALTED;
696 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
699 spin_unlock_irq(&xhci->lock);
702 if (!usb_hcd_is_primary_hcd(hcd)) {
703 mutex_unlock(&xhci->mutex);
707 xhci_cleanup_msix(xhci);
709 /* Deleting Compliance Mode Recovery Timer */
710 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
711 (!(xhci_all_ports_seen_u0(xhci)))) {
712 del_timer_sync(&xhci->comp_mode_recovery_timer);
713 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
714 "%s: compliance mode recovery timer deleted",
718 if (xhci->quirks & XHCI_AMD_PLL_FIX)
721 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
722 "// Disabling event ring interrupts");
723 temp = readl(&xhci->op_regs->status);
724 writel(temp & ~STS_EINT, &xhci->op_regs->status);
725 temp = readl(&xhci->ir_set->irq_pending);
726 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
727 xhci_print_ir_set(xhci, 0);
729 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
730 xhci_mem_cleanup(xhci);
731 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
732 "xhci_stop completed - status = %x",
733 readl(&xhci->op_regs->status));
734 mutex_unlock(&xhci->mutex);
738 * Shutdown HC (not bus-specific)
740 * This is called when the machine is rebooting or halting. We assume that the
741 * machine will be powered off, and the HC's internal state will be reset.
742 * Don't bother to free memory.
744 * This will only ever be called with the main usb_hcd (the USB3 roothub).
746 void xhci_shutdown(struct usb_hcd *hcd)
748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
750 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
751 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
753 spin_lock_irq(&xhci->lock);
755 /* Workaround for spurious wakeups at shutdown with HSW */
756 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
758 spin_unlock_irq(&xhci->lock);
760 xhci_cleanup_msix(xhci);
762 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
763 "xhci_shutdown completed - status = %x",
764 readl(&xhci->op_regs->status));
766 /* Yet another workaround for spurious wakeups at shutdown with HSW */
767 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
768 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
772 static void xhci_save_registers(struct xhci_hcd *xhci)
774 xhci->s3.command = readl(&xhci->op_regs->command);
775 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
776 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
777 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
778 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
779 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
780 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
781 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
782 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
785 static void xhci_restore_registers(struct xhci_hcd *xhci)
787 writel(xhci->s3.command, &xhci->op_regs->command);
788 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
789 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
790 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
791 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
792 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
793 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
794 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
795 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
798 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
802 /* step 2: initialize command ring buffer */
803 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
804 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
805 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
806 xhci->cmd_ring->dequeue) &
807 (u64) ~CMD_RING_RSVD_BITS) |
808 xhci->cmd_ring->cycle_state;
809 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
810 "// Setting command ring address to 0x%llx",
811 (long unsigned long) val_64);
812 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
816 * The whole command ring must be cleared to zero when we suspend the host.
818 * The host doesn't save the command ring pointer in the suspend well, so we
819 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
820 * aligned, because of the reserved bits in the command ring dequeue pointer
821 * register. Therefore, we can't just set the dequeue pointer back in the
822 * middle of the ring (TRBs are 16-byte aligned).
824 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
826 struct xhci_ring *ring;
827 struct xhci_segment *seg;
829 ring = xhci->cmd_ring;
833 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
834 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
835 cpu_to_le32(~TRB_CYCLE);
837 } while (seg != ring->deq_seg);
839 /* Reset the software enqueue and dequeue pointers */
840 ring->deq_seg = ring->first_seg;
841 ring->dequeue = ring->first_seg->trbs;
842 ring->enq_seg = ring->deq_seg;
843 ring->enqueue = ring->dequeue;
845 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
847 * Ring is now zeroed, so the HW should look for change of ownership
848 * when the cycle bit is set to 1.
850 ring->cycle_state = 1;
853 * Reset the hardware dequeue pointer.
854 * Yes, this will need to be re-written after resume, but we're paranoid
855 * and want to make sure the hardware doesn't access bogus memory
856 * because, say, the BIOS or an SMI started the host without changing
857 * the command ring pointers.
859 xhci_set_cmd_ring_deq(xhci);
862 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
865 __le32 __iomem **port_array;
869 spin_lock_irqsave(&xhci->lock, flags);
871 /* disble usb3 ports Wake bits*/
872 port_index = xhci->num_usb3_ports;
873 port_array = xhci->usb3_ports;
874 while (port_index--) {
875 t1 = readl(port_array[port_index]);
876 t1 = xhci_port_state_to_neutral(t1);
877 t2 = t1 & ~PORT_WAKE_BITS;
879 writel(t2, port_array[port_index]);
882 /* disble usb2 ports Wake bits*/
883 port_index = xhci->num_usb2_ports;
884 port_array = xhci->usb2_ports;
885 while (port_index--) {
886 t1 = readl(port_array[port_index]);
887 t1 = xhci_port_state_to_neutral(t1);
888 t2 = t1 & ~PORT_WAKE_BITS;
890 writel(t2, port_array[port_index]);
893 spin_unlock_irqrestore(&xhci->lock, flags);
897 * Stop HC (not bus-specific)
899 * This is called when the machine transition into S3/S4 mode.
902 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
905 unsigned int delay = XHCI_MAX_HALT_USEC;
906 struct usb_hcd *hcd = xhci_to_hcd(xhci);
912 if (hcd->state != HC_STATE_SUSPENDED ||
913 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
916 /* Clear root port wake on bits if wakeup not allowed. */
918 xhci_disable_port_wake_on_bits(xhci);
920 /* Don't poll the roothubs on bus suspend. */
921 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
922 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
923 del_timer_sync(&hcd->rh_timer);
924 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
925 del_timer_sync(&xhci->shared_hcd->rh_timer);
927 spin_lock_irq(&xhci->lock);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
929 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
930 /* step 1: stop endpoint */
931 /* skipped assuming that port suspend has done */
933 /* step 2: clear Run/Stop bit */
934 command = readl(&xhci->op_regs->command);
936 writel(command, &xhci->op_regs->command);
938 /* Some chips from Fresco Logic need an extraordinary delay */
939 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
941 if (xhci_handshake(&xhci->op_regs->status,
942 STS_HALT, STS_HALT, delay)) {
943 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
944 spin_unlock_irq(&xhci->lock);
947 xhci_clear_command_ring(xhci);
949 /* step 3: save registers */
950 xhci_save_registers(xhci);
952 /* step 4: set CSS flag */
953 command = readl(&xhci->op_regs->command);
955 writel(command, &xhci->op_regs->command);
956 if (xhci_handshake(&xhci->op_regs->status,
957 STS_SAVE, 0, 10 * 1000)) {
958 xhci_warn(xhci, "WARN: xHC save state timeout\n");
959 spin_unlock_irq(&xhci->lock);
962 spin_unlock_irq(&xhci->lock);
965 * Deleting Compliance Mode Recovery Timer because the xHCI Host
966 * is about to be suspended.
968 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
969 (!(xhci_all_ports_seen_u0(xhci)))) {
970 del_timer_sync(&xhci->comp_mode_recovery_timer);
971 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
972 "%s: compliance mode recovery timer deleted",
976 /* step 5: remove core well power */
977 /* synchronize irq when using MSI-X */
978 xhci_msix_sync_irqs(xhci);
982 EXPORT_SYMBOL_GPL(xhci_suspend);
985 * start xHC (not bus-specific)
987 * This is called when the machine transition from S3/S4 mode.
990 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
992 u32 command, temp = 0, status;
993 struct usb_hcd *hcd = xhci_to_hcd(xhci);
994 struct usb_hcd *secondary_hcd;
996 bool comp_timer_running = false;
1001 /* Wait a bit if either of the roothubs need to settle from the
1002 * transition into bus suspend.
1004 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1005 time_before(jiffies,
1006 xhci->bus_state[1].next_statechange))
1009 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1010 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1012 spin_lock_irq(&xhci->lock);
1013 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1017 /* step 1: restore register */
1018 xhci_restore_registers(xhci);
1019 /* step 2: initialize command ring buffer */
1020 xhci_set_cmd_ring_deq(xhci);
1021 /* step 3: restore state and start state*/
1022 /* step 3: set CRS flag */
1023 command = readl(&xhci->op_regs->command);
1025 writel(command, &xhci->op_regs->command);
1026 if (xhci_handshake(&xhci->op_regs->status,
1027 STS_RESTORE, 0, 10 * 1000)) {
1028 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1029 spin_unlock_irq(&xhci->lock);
1032 temp = readl(&xhci->op_regs->status);
1035 /* If restore operation fails, re-initialize the HC during resume */
1036 if ((temp & STS_SRE) || hibernated) {
1038 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1039 !(xhci_all_ports_seen_u0(xhci))) {
1040 del_timer_sync(&xhci->comp_mode_recovery_timer);
1041 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1042 "Compliance Mode Recovery Timer deleted!");
1045 /* Let the USB core know _both_ roothubs lost power. */
1046 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1047 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1049 xhci_dbg(xhci, "Stop HCD\n");
1052 spin_unlock_irq(&xhci->lock);
1053 xhci_cleanup_msix(xhci);
1055 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1056 temp = readl(&xhci->op_regs->status);
1057 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1058 temp = readl(&xhci->ir_set->irq_pending);
1059 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1060 xhci_print_ir_set(xhci, 0);
1062 xhci_dbg(xhci, "cleaning up memory\n");
1063 xhci_mem_cleanup(xhci);
1064 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1065 readl(&xhci->op_regs->status));
1067 /* USB core calls the PCI reinit and start functions twice:
1068 * first with the primary HCD, and then with the secondary HCD.
1069 * If we don't do the same, the host will never be started.
1071 if (!usb_hcd_is_primary_hcd(hcd))
1072 secondary_hcd = hcd;
1074 secondary_hcd = xhci->shared_hcd;
1076 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1077 retval = xhci_init(hcd->primary_hcd);
1080 comp_timer_running = true;
1082 xhci_dbg(xhci, "Start the primary HCD\n");
1083 retval = xhci_run(hcd->primary_hcd);
1085 xhci_dbg(xhci, "Start the secondary HCD\n");
1086 retval = xhci_run(secondary_hcd);
1088 hcd->state = HC_STATE_SUSPENDED;
1089 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1093 /* step 4: set Run/Stop bit */
1094 command = readl(&xhci->op_regs->command);
1096 writel(command, &xhci->op_regs->command);
1097 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1100 /* step 5: walk topology and initialize portsc,
1101 * portpmsc and portli
1103 /* this is done in bus_resume */
1105 /* step 6: restart each of the previously
1106 * Running endpoints by ringing their doorbells
1109 spin_unlock_irq(&xhci->lock);
1113 /* Resume root hubs only when have pending events. */
1114 status = readl(&xhci->op_regs->status);
1115 if (status & STS_EINT) {
1116 usb_hcd_resume_root_hub(xhci->shared_hcd);
1117 usb_hcd_resume_root_hub(hcd);
1122 * If system is subject to the Quirk, Compliance Mode Timer needs to
1123 * be re-initialized Always after a system resume. Ports are subject
1124 * to suffer the Compliance Mode issue again. It doesn't matter if
1125 * ports have entered previously to U0 before system's suspension.
1127 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1128 compliance_mode_recovery_timer_init(xhci);
1130 /* Re-enable port polling. */
1131 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1132 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1133 usb_hcd_poll_rh_status(xhci->shared_hcd);
1134 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1135 usb_hcd_poll_rh_status(hcd);
1139 EXPORT_SYMBOL_GPL(xhci_resume);
1140 #endif /* CONFIG_PM */
1142 /*-------------------------------------------------------------------------*/
1145 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1146 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1147 * value to right shift 1 for the bitmask.
1149 * Index = (epnum * 2) + direction - 1,
1150 * where direction = 0 for OUT, 1 for IN.
1151 * For control endpoints, the IN index is used (OUT index is unused), so
1152 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1154 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1157 if (usb_endpoint_xfer_control(desc))
1158 index = (unsigned int) (usb_endpoint_num(desc)*2);
1160 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1161 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1165 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1166 * address from the XHCI endpoint index.
1168 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1170 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1171 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1172 return direction | number;
1175 /* Find the flag for this endpoint (for use in the control context). Use the
1176 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1179 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1181 return 1 << (xhci_get_endpoint_index(desc) + 1);
1184 /* Find the flag for this endpoint (for use in the control context). Use the
1185 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1188 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1190 return 1 << (ep_index + 1);
1193 /* Compute the last valid endpoint context index. Basically, this is the
1194 * endpoint index plus one. For slot contexts with more than valid endpoint,
1195 * we find the most significant bit set in the added contexts flags.
1196 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1197 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1199 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1201 return fls(added_ctxs) - 1;
1204 /* Returns 1 if the arguments are OK;
1205 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1207 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1208 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1210 struct xhci_hcd *xhci;
1211 struct xhci_virt_device *virt_dev;
1213 if (!hcd || (check_ep && !ep) || !udev) {
1214 pr_debug("xHCI %s called with invalid args\n", func);
1217 if (!udev->parent) {
1218 pr_debug("xHCI %s called for root hub\n", func);
1222 xhci = hcd_to_xhci(hcd);
1223 if (check_virt_dev) {
1224 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1225 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1230 virt_dev = xhci->devs[udev->slot_id];
1231 if (virt_dev->udev != udev) {
1232 xhci_dbg(xhci, "xHCI %s called with udev and "
1233 "virt_dev does not match\n", func);
1238 if (xhci->xhc_state & XHCI_STATE_HALTED)
1244 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1245 struct usb_device *udev, struct xhci_command *command,
1246 bool ctx_change, bool must_succeed);
1249 * Full speed devices may have a max packet size greater than 8 bytes, but the
1250 * USB core doesn't know that until it reads the first 8 bytes of the
1251 * descriptor. If the usb_device's max packet size changes after that point,
1252 * we need to issue an evaluate context command and wait on it.
1254 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1255 unsigned int ep_index, struct urb *urb)
1257 struct xhci_container_ctx *out_ctx;
1258 struct xhci_input_control_ctx *ctrl_ctx;
1259 struct xhci_ep_ctx *ep_ctx;
1260 struct xhci_command *command;
1261 int max_packet_size;
1262 int hw_max_packet_size;
1265 out_ctx = xhci->devs[slot_id]->out_ctx;
1266 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1267 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1268 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1269 if (hw_max_packet_size != max_packet_size) {
1270 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1271 "Max Packet Size for ep 0 changed.");
1272 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1273 "Max packet size in usb_device = %d",
1275 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1276 "Max packet size in xHCI HW = %d",
1277 hw_max_packet_size);
1278 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1279 "Issuing evaluate context command.");
1281 /* Set up the input context flags for the command */
1282 /* FIXME: This won't work if a non-default control endpoint
1283 * changes max packet sizes.
1286 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1290 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1291 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1293 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1296 goto command_cleanup;
1298 /* Set up the modified control endpoint 0 */
1299 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1300 xhci->devs[slot_id]->out_ctx, ep_index);
1302 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1303 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1304 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1306 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1307 ctrl_ctx->drop_flags = 0;
1309 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1310 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1311 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1312 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1314 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1317 /* Clean up the input context for later use by bandwidth
1320 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1322 kfree(command->completion);
1329 * non-error returns are a promise to giveback() the urb later
1330 * we drop ownership so next owner (or urb unlink) can get it
1332 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1334 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1335 struct xhci_td *buffer;
1336 unsigned long flags;
1338 unsigned int slot_id, ep_index;
1339 struct urb_priv *urb_priv;
1342 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1343 true, true, __func__) <= 0)
1346 slot_id = urb->dev->slot_id;
1347 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1349 if (!HCD_HW_ACCESSIBLE(hcd)) {
1350 if (!in_interrupt())
1351 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1356 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1357 size = urb->number_of_packets;
1358 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1359 urb->transfer_buffer_length > 0 &&
1360 urb->transfer_flags & URB_ZERO_PACKET &&
1361 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1366 urb_priv = kzalloc(sizeof(struct urb_priv) +
1367 size * sizeof(struct xhci_td *), mem_flags);
1371 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1377 for (i = 0; i < size; i++) {
1378 urb_priv->td[i] = buffer;
1382 urb_priv->length = size;
1383 urb_priv->td_cnt = 0;
1384 urb->hcpriv = urb_priv;
1386 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1387 /* Check to see if the max packet size for the default control
1388 * endpoint changed during FS device enumeration
1390 if (urb->dev->speed == USB_SPEED_FULL) {
1391 ret = xhci_check_maxpacket(xhci, slot_id,
1394 xhci_urb_free_priv(urb_priv);
1400 /* We have a spinlock and interrupts disabled, so we must pass
1401 * atomic context to this function, which may allocate memory.
1403 spin_lock_irqsave(&xhci->lock, flags);
1404 if (xhci->xhc_state & XHCI_STATE_DYING)
1406 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1410 spin_unlock_irqrestore(&xhci->lock, flags);
1411 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1412 spin_lock_irqsave(&xhci->lock, flags);
1413 if (xhci->xhc_state & XHCI_STATE_DYING)
1415 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1416 EP_GETTING_STREAMS) {
1417 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1418 "is transitioning to using streams.\n");
1420 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1421 EP_GETTING_NO_STREAMS) {
1422 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1423 "is transitioning to "
1424 "not having streams.\n");
1427 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1432 spin_unlock_irqrestore(&xhci->lock, flags);
1433 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1434 spin_lock_irqsave(&xhci->lock, flags);
1435 if (xhci->xhc_state & XHCI_STATE_DYING)
1437 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1441 spin_unlock_irqrestore(&xhci->lock, flags);
1443 spin_lock_irqsave(&xhci->lock, flags);
1444 if (xhci->xhc_state & XHCI_STATE_DYING)
1446 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1450 spin_unlock_irqrestore(&xhci->lock, flags);
1455 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1456 "non-responsive xHCI host.\n",
1457 urb->ep->desc.bEndpointAddress, urb);
1460 xhci_urb_free_priv(urb_priv);
1462 spin_unlock_irqrestore(&xhci->lock, flags);
1467 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1468 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1469 * should pick up where it left off in the TD, unless a Set Transfer Ring
1470 * Dequeue Pointer is issued.
1472 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1473 * the ring. Since the ring is a contiguous structure, they can't be physically
1474 * removed. Instead, there are two options:
1476 * 1) If the HC is in the middle of processing the URB to be canceled, we
1477 * simply move the ring's dequeue pointer past those TRBs using the Set
1478 * Transfer Ring Dequeue Pointer command. This will be the common case,
1479 * when drivers timeout on the last submitted URB and attempt to cancel.
1481 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1482 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1483 * HC will need to invalidate the any TRBs it has cached after the stop
1484 * endpoint command, as noted in the xHCI 0.95 errata.
1486 * 3) The TD may have completed by the time the Stop Endpoint Command
1487 * completes, so software needs to handle that case too.
1489 * This function should protect against the TD enqueueing code ringing the
1490 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1491 * It also needs to account for multiple cancellations on happening at the same
1492 * time for the same endpoint.
1494 * Note that this function can be called in any context, or so says
1495 * usb_hcd_unlink_urb()
1497 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1499 unsigned long flags;
1502 struct xhci_hcd *xhci;
1503 struct urb_priv *urb_priv;
1505 unsigned int ep_index;
1506 struct xhci_ring *ep_ring;
1507 struct xhci_virt_ep *ep;
1508 struct xhci_command *command;
1510 xhci = hcd_to_xhci(hcd);
1511 spin_lock_irqsave(&xhci->lock, flags);
1512 /* Make sure the URB hasn't completed or been unlinked already */
1513 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1514 if (ret || !urb->hcpriv)
1516 temp = readl(&xhci->op_regs->status);
1517 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1518 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1519 "HW died, freeing TD.");
1520 urb_priv = urb->hcpriv;
1521 for (i = urb_priv->td_cnt;
1522 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1524 td = urb_priv->td[i];
1525 if (!list_empty(&td->td_list))
1526 list_del_init(&td->td_list);
1527 if (!list_empty(&td->cancelled_td_list))
1528 list_del_init(&td->cancelled_td_list);
1531 usb_hcd_unlink_urb_from_ep(hcd, urb);
1532 spin_unlock_irqrestore(&xhci->lock, flags);
1533 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1534 xhci_urb_free_priv(urb_priv);
1538 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1539 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1540 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1546 urb_priv = urb->hcpriv;
1547 i = urb_priv->td_cnt;
1548 if (i < urb_priv->length)
1549 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1550 "Cancel URB %p, dev %s, ep 0x%x, "
1551 "starting at offset 0x%llx",
1552 urb, urb->dev->devpath,
1553 urb->ep->desc.bEndpointAddress,
1554 (unsigned long long) xhci_trb_virt_to_dma(
1555 urb_priv->td[i]->start_seg,
1556 urb_priv->td[i]->first_trb));
1558 for (; i < urb_priv->length; i++) {
1559 td = urb_priv->td[i];
1560 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1563 /* Queue a stop endpoint command, but only if this is
1564 * the first cancellation to be handled.
1566 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1567 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1572 ep->ep_state |= EP_STOP_CMD_PENDING;
1573 ep->stop_cmd_timer.expires = jiffies +
1574 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1575 add_timer(&ep->stop_cmd_timer);
1576 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1578 xhci_ring_cmd_db(xhci);
1581 spin_unlock_irqrestore(&xhci->lock, flags);
1585 /* Drop an endpoint from a new bandwidth configuration for this device.
1586 * Only one call to this function is allowed per endpoint before
1587 * check_bandwidth() or reset_bandwidth() must be called.
1588 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1589 * add the endpoint to the schedule with possibly new parameters denoted by a
1590 * different endpoint descriptor in usb_host_endpoint.
1591 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1594 * The USB core will not allow URBs to be queued to an endpoint that is being
1595 * disabled, so there's no need for mutual exclusion to protect
1596 * the xhci->devs[slot_id] structure.
1598 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1599 struct usb_host_endpoint *ep)
1601 struct xhci_hcd *xhci;
1602 struct xhci_container_ctx *in_ctx, *out_ctx;
1603 struct xhci_input_control_ctx *ctrl_ctx;
1604 unsigned int ep_index;
1605 struct xhci_ep_ctx *ep_ctx;
1607 u32 new_add_flags, new_drop_flags;
1610 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1613 xhci = hcd_to_xhci(hcd);
1614 if (xhci->xhc_state & XHCI_STATE_DYING)
1617 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1618 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1619 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1620 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1621 __func__, drop_flag);
1625 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1626 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1627 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1629 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1634 ep_index = xhci_get_endpoint_index(&ep->desc);
1635 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1636 /* If the HC already knows the endpoint is disabled,
1637 * or the HCD has noted it is disabled, ignore this request
1639 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1640 le32_to_cpu(ctrl_ctx->drop_flags) &
1641 xhci_get_endpoint_flag(&ep->desc)) {
1642 /* Do not warn when called after a usb_device_reset */
1643 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1644 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1649 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1650 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1652 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1653 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1655 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1657 if (xhci->quirks & XHCI_MTK_HOST)
1658 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1660 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1661 (unsigned int) ep->desc.bEndpointAddress,
1663 (unsigned int) new_drop_flags,
1664 (unsigned int) new_add_flags);
1668 /* Add an endpoint to a new possible bandwidth configuration for this device.
1669 * Only one call to this function is allowed per endpoint before
1670 * check_bandwidth() or reset_bandwidth() must be called.
1671 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1672 * add the endpoint to the schedule with possibly new parameters denoted by a
1673 * different endpoint descriptor in usb_host_endpoint.
1674 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1677 * The USB core will not allow URBs to be queued to an endpoint until the
1678 * configuration or alt setting is installed in the device, so there's no need
1679 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1681 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1682 struct usb_host_endpoint *ep)
1684 struct xhci_hcd *xhci;
1685 struct xhci_container_ctx *in_ctx;
1686 unsigned int ep_index;
1687 struct xhci_input_control_ctx *ctrl_ctx;
1689 u32 new_add_flags, new_drop_flags;
1690 struct xhci_virt_device *virt_dev;
1693 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1695 /* So we won't queue a reset ep command for a root hub */
1699 xhci = hcd_to_xhci(hcd);
1700 if (xhci->xhc_state & XHCI_STATE_DYING)
1703 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1704 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1705 /* FIXME when we have to issue an evaluate endpoint command to
1706 * deal with ep0 max packet size changing once we get the
1709 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1710 __func__, added_ctxs);
1714 virt_dev = xhci->devs[udev->slot_id];
1715 in_ctx = virt_dev->in_ctx;
1716 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1718 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1723 ep_index = xhci_get_endpoint_index(&ep->desc);
1724 /* If this endpoint is already in use, and the upper layers are trying
1725 * to add it again without dropping it, reject the addition.
1727 if (virt_dev->eps[ep_index].ring &&
1728 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1729 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1730 "without dropping it.\n",
1731 (unsigned int) ep->desc.bEndpointAddress);
1735 /* If the HCD has already noted the endpoint is enabled,
1736 * ignore this request.
1738 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1739 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1745 * Configuration and alternate setting changes must be done in
1746 * process context, not interrupt context (or so documenation
1747 * for usb_set_interface() and usb_set_configuration() claim).
1749 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1750 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1751 __func__, ep->desc.bEndpointAddress);
1755 if (xhci->quirks & XHCI_MTK_HOST) {
1756 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1758 xhci_free_or_cache_endpoint_ring(xhci,
1759 virt_dev, ep_index);
1764 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1765 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1767 /* If xhci_endpoint_disable() was called for this endpoint, but the
1768 * xHC hasn't been notified yet through the check_bandwidth() call,
1769 * this re-adds a new state for the endpoint from the new endpoint
1770 * descriptors. We must drop and re-add this endpoint, so we leave the
1773 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1775 /* Store the usb_device pointer for later use */
1778 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1779 (unsigned int) ep->desc.bEndpointAddress,
1781 (unsigned int) new_drop_flags,
1782 (unsigned int) new_add_flags);
1786 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1788 struct xhci_input_control_ctx *ctrl_ctx;
1789 struct xhci_ep_ctx *ep_ctx;
1790 struct xhci_slot_ctx *slot_ctx;
1793 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1795 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1800 /* When a device's add flag and drop flag are zero, any subsequent
1801 * configure endpoint command will leave that endpoint's state
1802 * untouched. Make sure we don't leave any old state in the input
1803 * endpoint contexts.
1805 ctrl_ctx->drop_flags = 0;
1806 ctrl_ctx->add_flags = 0;
1807 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1808 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1809 /* Endpoint 0 is always valid */
1810 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1811 for (i = 1; i < 31; ++i) {
1812 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1813 ep_ctx->ep_info = 0;
1814 ep_ctx->ep_info2 = 0;
1816 ep_ctx->tx_info = 0;
1820 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1821 struct usb_device *udev, u32 *cmd_status)
1825 switch (*cmd_status) {
1826 case COMP_CMD_ABORT:
1828 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1832 dev_warn(&udev->dev,
1833 "Not enough host controller resources for new device state.\n");
1835 /* FIXME: can we allocate more resources for the HC? */
1838 case COMP_2ND_BW_ERR:
1839 dev_warn(&udev->dev,
1840 "Not enough bandwidth for new device state.\n");
1842 /* FIXME: can we go back to the old state? */
1845 /* the HCD set up something wrong */
1846 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1848 "and endpoint is not disabled.\n");
1852 dev_warn(&udev->dev,
1853 "ERROR: Incompatible device for endpoint configure command.\n");
1857 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1858 "Successful Endpoint Configure command");
1862 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1870 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1871 struct usb_device *udev, u32 *cmd_status)
1874 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1876 switch (*cmd_status) {
1877 case COMP_CMD_ABORT:
1879 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1883 dev_warn(&udev->dev,
1884 "WARN: xHCI driver setup invalid evaluate context command.\n");
1888 dev_warn(&udev->dev,
1889 "WARN: slot not enabled for evaluate context command.\n");
1892 case COMP_CTX_STATE:
1893 dev_warn(&udev->dev,
1894 "WARN: invalid context state for evaluate context command.\n");
1895 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1899 dev_warn(&udev->dev,
1900 "ERROR: Incompatible device for evaluate context command.\n");
1904 /* Max Exit Latency too large error */
1905 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1909 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1910 "Successful evaluate context command");
1914 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1922 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1923 struct xhci_input_control_ctx *ctrl_ctx)
1925 u32 valid_add_flags;
1926 u32 valid_drop_flags;
1928 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1929 * (bit 1). The default control endpoint is added during the Address
1930 * Device command and is never removed until the slot is disabled.
1932 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1933 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1935 /* Use hweight32 to count the number of ones in the add flags, or
1936 * number of endpoints added. Don't count endpoints that are changed
1937 * (both added and dropped).
1939 return hweight32(valid_add_flags) -
1940 hweight32(valid_add_flags & valid_drop_flags);
1943 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1944 struct xhci_input_control_ctx *ctrl_ctx)
1946 u32 valid_add_flags;
1947 u32 valid_drop_flags;
1949 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1950 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1952 return hweight32(valid_drop_flags) -
1953 hweight32(valid_add_flags & valid_drop_flags);
1957 * We need to reserve the new number of endpoints before the configure endpoint
1958 * command completes. We can't subtract the dropped endpoints from the number
1959 * of active endpoints until the command completes because we can oversubscribe
1960 * the host in this case:
1962 * - the first configure endpoint command drops more endpoints than it adds
1963 * - a second configure endpoint command that adds more endpoints is queued
1964 * - the first configure endpoint command fails, so the config is unchanged
1965 * - the second command may succeed, even though there isn't enough resources
1967 * Must be called with xhci->lock held.
1969 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1970 struct xhci_input_control_ctx *ctrl_ctx)
1974 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1975 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1976 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1977 "Not enough ep ctxs: "
1978 "%u active, need to add %u, limit is %u.",
1979 xhci->num_active_eps, added_eps,
1980 xhci->limit_active_eps);
1983 xhci->num_active_eps += added_eps;
1984 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1985 "Adding %u ep ctxs, %u now active.", added_eps,
1986 xhci->num_active_eps);
1991 * The configure endpoint was failed by the xHC for some other reason, so we
1992 * need to revert the resources that failed configuration would have used.
1994 * Must be called with xhci->lock held.
1996 static void xhci_free_host_resources(struct xhci_hcd *xhci,
1997 struct xhci_input_control_ctx *ctrl_ctx)
2001 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2002 xhci->num_active_eps -= num_failed_eps;
2003 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2004 "Removing %u failed ep ctxs, %u now active.",
2006 xhci->num_active_eps);
2010 * Now that the command has completed, clean up the active endpoint count by
2011 * subtracting out the endpoints that were dropped (but not changed).
2013 * Must be called with xhci->lock held.
2015 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2016 struct xhci_input_control_ctx *ctrl_ctx)
2018 u32 num_dropped_eps;
2020 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2021 xhci->num_active_eps -= num_dropped_eps;
2022 if (num_dropped_eps)
2023 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2024 "Removing %u dropped ep ctxs, %u now active.",
2026 xhci->num_active_eps);
2029 static unsigned int xhci_get_block_size(struct usb_device *udev)
2031 switch (udev->speed) {
2033 case USB_SPEED_FULL:
2035 case USB_SPEED_HIGH:
2037 case USB_SPEED_SUPER:
2038 case USB_SPEED_SUPER_PLUS:
2040 case USB_SPEED_UNKNOWN:
2041 case USB_SPEED_WIRELESS:
2043 /* Should never happen */
2049 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2051 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2053 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2058 /* If we are changing a LS/FS device under a HS hub,
2059 * make sure (if we are activating a new TT) that the HS bus has enough
2060 * bandwidth for this new TT.
2062 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2063 struct xhci_virt_device *virt_dev,
2066 struct xhci_interval_bw_table *bw_table;
2067 struct xhci_tt_bw_info *tt_info;
2069 /* Find the bandwidth table for the root port this TT is attached to. */
2070 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2071 tt_info = virt_dev->tt_info;
2072 /* If this TT already had active endpoints, the bandwidth for this TT
2073 * has already been added. Removing all periodic endpoints (and thus
2074 * making the TT enactive) will only decrease the bandwidth used.
2078 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2079 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2083 /* Not sure why we would have no new active endpoints...
2085 * Maybe because of an Evaluate Context change for a hub update or a
2086 * control endpoint 0 max packet size change?
2087 * FIXME: skip the bandwidth calculation in that case.
2092 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2093 struct xhci_virt_device *virt_dev)
2095 unsigned int bw_reserved;
2097 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2098 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2101 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2102 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2109 * This algorithm is a very conservative estimate of the worst-case scheduling
2110 * scenario for any one interval. The hardware dynamically schedules the
2111 * packets, so we can't tell which microframe could be the limiting factor in
2112 * the bandwidth scheduling. This only takes into account periodic endpoints.
2114 * Obviously, we can't solve an NP complete problem to find the minimum worst
2115 * case scenario. Instead, we come up with an estimate that is no less than
2116 * the worst case bandwidth used for any one microframe, but may be an
2119 * We walk the requirements for each endpoint by interval, starting with the
2120 * smallest interval, and place packets in the schedule where there is only one
2121 * possible way to schedule packets for that interval. In order to simplify
2122 * this algorithm, we record the largest max packet size for each interval, and
2123 * assume all packets will be that size.
2125 * For interval 0, we obviously must schedule all packets for each interval.
2126 * The bandwidth for interval 0 is just the amount of data to be transmitted
2127 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2128 * the number of packets).
2130 * For interval 1, we have two possible microframes to schedule those packets
2131 * in. For this algorithm, if we can schedule the same number of packets for
2132 * each possible scheduling opportunity (each microframe), we will do so. The
2133 * remaining number of packets will be saved to be transmitted in the gaps in
2134 * the next interval's scheduling sequence.
2136 * As we move those remaining packets to be scheduled with interval 2 packets,
2137 * we have to double the number of remaining packets to transmit. This is
2138 * because the intervals are actually powers of 2, and we would be transmitting
2139 * the previous interval's packets twice in this interval. We also have to be
2140 * sure that when we look at the largest max packet size for this interval, we
2141 * also look at the largest max packet size for the remaining packets and take
2142 * the greater of the two.
2144 * The algorithm continues to evenly distribute packets in each scheduling
2145 * opportunity, and push the remaining packets out, until we get to the last
2146 * interval. Then those packets and their associated overhead are just added
2147 * to the bandwidth used.
2149 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2150 struct xhci_virt_device *virt_dev,
2153 unsigned int bw_reserved;
2154 unsigned int max_bandwidth;
2155 unsigned int bw_used;
2156 unsigned int block_size;
2157 struct xhci_interval_bw_table *bw_table;
2158 unsigned int packet_size = 0;
2159 unsigned int overhead = 0;
2160 unsigned int packets_transmitted = 0;
2161 unsigned int packets_remaining = 0;
2164 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2165 return xhci_check_ss_bw(xhci, virt_dev);
2167 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2168 max_bandwidth = HS_BW_LIMIT;
2169 /* Convert percent of bus BW reserved to blocks reserved */
2170 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2172 max_bandwidth = FS_BW_LIMIT;
2173 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2176 bw_table = virt_dev->bw_table;
2177 /* We need to translate the max packet size and max ESIT payloads into
2178 * the units the hardware uses.
2180 block_size = xhci_get_block_size(virt_dev->udev);
2182 /* If we are manipulating a LS/FS device under a HS hub, double check
2183 * that the HS bus has enough bandwidth if we are activing a new TT.
2185 if (virt_dev->tt_info) {
2186 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2187 "Recalculating BW for rootport %u",
2188 virt_dev->real_port);
2189 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2190 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2191 "newly activated TT.\n");
2194 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2195 "Recalculating BW for TT slot %u port %u",
2196 virt_dev->tt_info->slot_id,
2197 virt_dev->tt_info->ttport);
2199 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2200 "Recalculating BW for rootport %u",
2201 virt_dev->real_port);
2204 /* Add in how much bandwidth will be used for interval zero, or the
2205 * rounded max ESIT payload + number of packets * largest overhead.
2207 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2208 bw_table->interval_bw[0].num_packets *
2209 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2211 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2212 unsigned int bw_added;
2213 unsigned int largest_mps;
2214 unsigned int interval_overhead;
2217 * How many packets could we transmit in this interval?
2218 * If packets didn't fit in the previous interval, we will need
2219 * to transmit that many packets twice within this interval.
2221 packets_remaining = 2 * packets_remaining +
2222 bw_table->interval_bw[i].num_packets;
2224 /* Find the largest max packet size of this or the previous
2227 if (list_empty(&bw_table->interval_bw[i].endpoints))
2230 struct xhci_virt_ep *virt_ep;
2231 struct list_head *ep_entry;
2233 ep_entry = bw_table->interval_bw[i].endpoints.next;
2234 virt_ep = list_entry(ep_entry,
2235 struct xhci_virt_ep, bw_endpoint_list);
2236 /* Convert to blocks, rounding up */
2237 largest_mps = DIV_ROUND_UP(
2238 virt_ep->bw_info.max_packet_size,
2241 if (largest_mps > packet_size)
2242 packet_size = largest_mps;
2244 /* Use the larger overhead of this or the previous interval. */
2245 interval_overhead = xhci_get_largest_overhead(
2246 &bw_table->interval_bw[i]);
2247 if (interval_overhead > overhead)
2248 overhead = interval_overhead;
2250 /* How many packets can we evenly distribute across
2251 * (1 << (i + 1)) possible scheduling opportunities?
2253 packets_transmitted = packets_remaining >> (i + 1);
2255 /* Add in the bandwidth used for those scheduled packets */
2256 bw_added = packets_transmitted * (overhead + packet_size);
2258 /* How many packets do we have remaining to transmit? */
2259 packets_remaining = packets_remaining % (1 << (i + 1));
2261 /* What largest max packet size should those packets have? */
2262 /* If we've transmitted all packets, don't carry over the
2263 * largest packet size.
2265 if (packets_remaining == 0) {
2268 } else if (packets_transmitted > 0) {
2269 /* Otherwise if we do have remaining packets, and we've
2270 * scheduled some packets in this interval, take the
2271 * largest max packet size from endpoints with this
2274 packet_size = largest_mps;
2275 overhead = interval_overhead;
2277 /* Otherwise carry over packet_size and overhead from the last
2278 * time we had a remainder.
2280 bw_used += bw_added;
2281 if (bw_used > max_bandwidth) {
2282 xhci_warn(xhci, "Not enough bandwidth. "
2283 "Proposed: %u, Max: %u\n",
2284 bw_used, max_bandwidth);
2289 * Ok, we know we have some packets left over after even-handedly
2290 * scheduling interval 15. We don't know which microframes they will
2291 * fit into, so we over-schedule and say they will be scheduled every
2294 if (packets_remaining > 0)
2295 bw_used += overhead + packet_size;
2297 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2298 unsigned int port_index = virt_dev->real_port - 1;
2300 /* OK, we're manipulating a HS device attached to a
2301 * root port bandwidth domain. Include the number of active TTs
2302 * in the bandwidth used.
2304 bw_used += TT_HS_OVERHEAD *
2305 xhci->rh_bw[port_index].num_active_tts;
2308 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2309 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2310 "Available: %u " "percent",
2311 bw_used, max_bandwidth, bw_reserved,
2312 (max_bandwidth - bw_used - bw_reserved) * 100 /
2315 bw_used += bw_reserved;
2316 if (bw_used > max_bandwidth) {
2317 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2318 bw_used, max_bandwidth);
2322 bw_table->bw_used = bw_used;
2326 static bool xhci_is_async_ep(unsigned int ep_type)
2328 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2329 ep_type != ISOC_IN_EP &&
2330 ep_type != INT_IN_EP);
2333 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2335 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2338 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2340 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2342 if (ep_bw->ep_interval == 0)
2343 return SS_OVERHEAD_BURST +
2344 (ep_bw->mult * ep_bw->num_packets *
2345 (SS_OVERHEAD + mps));
2346 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2347 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2348 1 << ep_bw->ep_interval);
2352 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2353 struct xhci_bw_info *ep_bw,
2354 struct xhci_interval_bw_table *bw_table,
2355 struct usb_device *udev,
2356 struct xhci_virt_ep *virt_ep,
2357 struct xhci_tt_bw_info *tt_info)
2359 struct xhci_interval_bw *interval_bw;
2360 int normalized_interval;
2362 if (xhci_is_async_ep(ep_bw->type))
2365 if (udev->speed >= USB_SPEED_SUPER) {
2366 if (xhci_is_sync_in_ep(ep_bw->type))
2367 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2368 xhci_get_ss_bw_consumed(ep_bw);
2370 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2371 xhci_get_ss_bw_consumed(ep_bw);
2375 /* SuperSpeed endpoints never get added to intervals in the table, so
2376 * this check is only valid for HS/FS/LS devices.
2378 if (list_empty(&virt_ep->bw_endpoint_list))
2380 /* For LS/FS devices, we need to translate the interval expressed in
2381 * microframes to frames.
2383 if (udev->speed == USB_SPEED_HIGH)
2384 normalized_interval = ep_bw->ep_interval;
2386 normalized_interval = ep_bw->ep_interval - 3;
2388 if (normalized_interval == 0)
2389 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2390 interval_bw = &bw_table->interval_bw[normalized_interval];
2391 interval_bw->num_packets -= ep_bw->num_packets;
2392 switch (udev->speed) {
2394 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2396 case USB_SPEED_FULL:
2397 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2399 case USB_SPEED_HIGH:
2400 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2402 case USB_SPEED_SUPER:
2403 case USB_SPEED_SUPER_PLUS:
2404 case USB_SPEED_UNKNOWN:
2405 case USB_SPEED_WIRELESS:
2406 /* Should never happen because only LS/FS/HS endpoints will get
2407 * added to the endpoint list.
2412 tt_info->active_eps -= 1;
2413 list_del_init(&virt_ep->bw_endpoint_list);
2416 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2417 struct xhci_bw_info *ep_bw,
2418 struct xhci_interval_bw_table *bw_table,
2419 struct usb_device *udev,
2420 struct xhci_virt_ep *virt_ep,
2421 struct xhci_tt_bw_info *tt_info)
2423 struct xhci_interval_bw *interval_bw;
2424 struct xhci_virt_ep *smaller_ep;
2425 int normalized_interval;
2427 if (xhci_is_async_ep(ep_bw->type))
2430 if (udev->speed == USB_SPEED_SUPER) {
2431 if (xhci_is_sync_in_ep(ep_bw->type))
2432 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2433 xhci_get_ss_bw_consumed(ep_bw);
2435 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2436 xhci_get_ss_bw_consumed(ep_bw);
2440 /* For LS/FS devices, we need to translate the interval expressed in
2441 * microframes to frames.
2443 if (udev->speed == USB_SPEED_HIGH)
2444 normalized_interval = ep_bw->ep_interval;
2446 normalized_interval = ep_bw->ep_interval - 3;
2448 if (normalized_interval == 0)
2449 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2450 interval_bw = &bw_table->interval_bw[normalized_interval];
2451 interval_bw->num_packets += ep_bw->num_packets;
2452 switch (udev->speed) {
2454 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2456 case USB_SPEED_FULL:
2457 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2459 case USB_SPEED_HIGH:
2460 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2462 case USB_SPEED_SUPER:
2463 case USB_SPEED_SUPER_PLUS:
2464 case USB_SPEED_UNKNOWN:
2465 case USB_SPEED_WIRELESS:
2466 /* Should never happen because only LS/FS/HS endpoints will get
2467 * added to the endpoint list.
2473 tt_info->active_eps += 1;
2474 /* Insert the endpoint into the list, largest max packet size first. */
2475 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2477 if (ep_bw->max_packet_size >=
2478 smaller_ep->bw_info.max_packet_size) {
2479 /* Add the new ep before the smaller endpoint */
2480 list_add_tail(&virt_ep->bw_endpoint_list,
2481 &smaller_ep->bw_endpoint_list);
2485 /* Add the new endpoint at the end of the list. */
2486 list_add_tail(&virt_ep->bw_endpoint_list,
2487 &interval_bw->endpoints);
2490 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2491 struct xhci_virt_device *virt_dev,
2494 struct xhci_root_port_bw_info *rh_bw_info;
2495 if (!virt_dev->tt_info)
2498 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2499 if (old_active_eps == 0 &&
2500 virt_dev->tt_info->active_eps != 0) {
2501 rh_bw_info->num_active_tts += 1;
2502 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2503 } else if (old_active_eps != 0 &&
2504 virt_dev->tt_info->active_eps == 0) {
2505 rh_bw_info->num_active_tts -= 1;
2506 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2510 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2511 struct xhci_virt_device *virt_dev,
2512 struct xhci_container_ctx *in_ctx)
2514 struct xhci_bw_info ep_bw_info[31];
2516 struct xhci_input_control_ctx *ctrl_ctx;
2517 int old_active_eps = 0;
2519 if (virt_dev->tt_info)
2520 old_active_eps = virt_dev->tt_info->active_eps;
2522 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2524 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2529 for (i = 0; i < 31; i++) {
2530 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2533 /* Make a copy of the BW info in case we need to revert this */
2534 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2535 sizeof(ep_bw_info[i]));
2536 /* Drop the endpoint from the interval table if the endpoint is
2537 * being dropped or changed.
2539 if (EP_IS_DROPPED(ctrl_ctx, i))
2540 xhci_drop_ep_from_interval_table(xhci,
2541 &virt_dev->eps[i].bw_info,
2547 /* Overwrite the information stored in the endpoints' bw_info */
2548 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2549 for (i = 0; i < 31; i++) {
2550 /* Add any changed or added endpoints to the interval table */
2551 if (EP_IS_ADDED(ctrl_ctx, i))
2552 xhci_add_ep_to_interval_table(xhci,
2553 &virt_dev->eps[i].bw_info,
2560 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2561 /* Ok, this fits in the bandwidth we have.
2562 * Update the number of active TTs.
2564 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2568 /* We don't have enough bandwidth for this, revert the stored info. */
2569 for (i = 0; i < 31; i++) {
2570 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2573 /* Drop the new copies of any added or changed endpoints from
2574 * the interval table.
2576 if (EP_IS_ADDED(ctrl_ctx, i)) {
2577 xhci_drop_ep_from_interval_table(xhci,
2578 &virt_dev->eps[i].bw_info,
2584 /* Revert the endpoint back to its old information */
2585 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2586 sizeof(ep_bw_info[i]));
2587 /* Add any changed or dropped endpoints back into the table */
2588 if (EP_IS_DROPPED(ctrl_ctx, i))
2589 xhci_add_ep_to_interval_table(xhci,
2590 &virt_dev->eps[i].bw_info,
2600 /* Issue a configure endpoint command or evaluate context command
2601 * and wait for it to finish.
2603 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2604 struct usb_device *udev,
2605 struct xhci_command *command,
2606 bool ctx_change, bool must_succeed)
2609 unsigned long flags;
2610 struct xhci_input_control_ctx *ctrl_ctx;
2611 struct xhci_virt_device *virt_dev;
2616 spin_lock_irqsave(&xhci->lock, flags);
2617 virt_dev = xhci->devs[udev->slot_id];
2619 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2621 spin_unlock_irqrestore(&xhci->lock, flags);
2622 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2627 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2628 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2629 spin_unlock_irqrestore(&xhci->lock, flags);
2630 xhci_warn(xhci, "Not enough host resources, "
2631 "active endpoint contexts = %u\n",
2632 xhci->num_active_eps);
2635 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2636 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2637 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2638 xhci_free_host_resources(xhci, ctrl_ctx);
2639 spin_unlock_irqrestore(&xhci->lock, flags);
2640 xhci_warn(xhci, "Not enough bandwidth\n");
2645 ret = xhci_queue_configure_endpoint(xhci, command,
2646 command->in_ctx->dma,
2647 udev->slot_id, must_succeed);
2649 ret = xhci_queue_evaluate_context(xhci, command,
2650 command->in_ctx->dma,
2651 udev->slot_id, must_succeed);
2653 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2654 xhci_free_host_resources(xhci, ctrl_ctx);
2655 spin_unlock_irqrestore(&xhci->lock, flags);
2656 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2657 "FIXME allocate a new ring segment");
2660 xhci_ring_cmd_db(xhci);
2661 spin_unlock_irqrestore(&xhci->lock, flags);
2663 /* Wait for the configure endpoint command to complete */
2664 wait_for_completion(command->completion);
2667 ret = xhci_configure_endpoint_result(xhci, udev,
2670 ret = xhci_evaluate_context_result(xhci, udev,
2673 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2674 spin_lock_irqsave(&xhci->lock, flags);
2675 /* If the command failed, remove the reserved resources.
2676 * Otherwise, clean up the estimate to include dropped eps.
2679 xhci_free_host_resources(xhci, ctrl_ctx);
2681 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2682 spin_unlock_irqrestore(&xhci->lock, flags);
2687 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2688 struct xhci_virt_device *vdev, int i)
2690 struct xhci_virt_ep *ep = &vdev->eps[i];
2692 if (ep->ep_state & EP_HAS_STREAMS) {
2693 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2694 xhci_get_endpoint_address(i));
2695 xhci_free_stream_info(xhci, ep->stream_info);
2696 ep->stream_info = NULL;
2697 ep->ep_state &= ~EP_HAS_STREAMS;
2701 /* Called after one or more calls to xhci_add_endpoint() or
2702 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2703 * to call xhci_reset_bandwidth().
2705 * Since we are in the middle of changing either configuration or
2706 * installing a new alt setting, the USB core won't allow URBs to be
2707 * enqueued for any endpoint on the old config or interface. Nothing
2708 * else should be touching the xhci->devs[slot_id] structure, so we
2709 * don't need to take the xhci->lock for manipulating that.
2711 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2715 struct xhci_hcd *xhci;
2716 struct xhci_virt_device *virt_dev;
2717 struct xhci_input_control_ctx *ctrl_ctx;
2718 struct xhci_slot_ctx *slot_ctx;
2719 struct xhci_command *command;
2721 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2724 xhci = hcd_to_xhci(hcd);
2725 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2726 (xhci->xhc_state & XHCI_STATE_REMOVING))
2729 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2730 virt_dev = xhci->devs[udev->slot_id];
2732 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2736 command->in_ctx = virt_dev->in_ctx;
2738 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2739 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2741 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2744 goto command_cleanup;
2746 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2747 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2748 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2750 /* Don't issue the command if there's no endpoints to update. */
2751 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2752 ctrl_ctx->drop_flags == 0) {
2754 goto command_cleanup;
2756 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2757 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2758 for (i = 31; i >= 1; i--) {
2759 __le32 le32 = cpu_to_le32(BIT(i));
2761 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2762 || (ctrl_ctx->add_flags & le32) || i == 1) {
2763 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2764 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2768 xhci_dbg(xhci, "New Input Control Context:\n");
2769 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2770 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2772 ret = xhci_configure_endpoint(xhci, udev, command,
2775 /* Callee should call reset_bandwidth() */
2776 goto command_cleanup;
2778 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2779 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2780 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2782 /* Free any rings that were dropped, but not changed. */
2783 for (i = 1; i < 31; ++i) {
2784 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2785 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2786 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2787 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2790 xhci_zero_in_ctx(xhci, virt_dev);
2792 * Install any rings for completely new endpoints or changed endpoints,
2793 * and free or cache any old rings from changed endpoints.
2795 for (i = 1; i < 31; ++i) {
2796 if (!virt_dev->eps[i].new_ring)
2798 /* Only cache or free the old ring if it exists.
2799 * It may not if this is the first add of an endpoint.
2801 if (virt_dev->eps[i].ring) {
2802 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2804 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2805 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2806 virt_dev->eps[i].new_ring = NULL;
2809 kfree(command->completion);
2815 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2817 struct xhci_hcd *xhci;
2818 struct xhci_virt_device *virt_dev;
2821 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2824 xhci = hcd_to_xhci(hcd);
2826 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2827 virt_dev = xhci->devs[udev->slot_id];
2828 /* Free any rings allocated for added endpoints */
2829 for (i = 0; i < 31; ++i) {
2830 if (virt_dev->eps[i].new_ring) {
2831 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2832 virt_dev->eps[i].new_ring = NULL;
2835 xhci_zero_in_ctx(xhci, virt_dev);
2838 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2839 struct xhci_container_ctx *in_ctx,
2840 struct xhci_container_ctx *out_ctx,
2841 struct xhci_input_control_ctx *ctrl_ctx,
2842 u32 add_flags, u32 drop_flags)
2844 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2845 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2846 xhci_slot_copy(xhci, in_ctx, out_ctx);
2847 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2849 xhci_dbg(xhci, "Input Context:\n");
2850 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2853 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2854 unsigned int slot_id, unsigned int ep_index,
2855 struct xhci_dequeue_state *deq_state)
2857 struct xhci_input_control_ctx *ctrl_ctx;
2858 struct xhci_container_ctx *in_ctx;
2859 struct xhci_ep_ctx *ep_ctx;
2863 in_ctx = xhci->devs[slot_id]->in_ctx;
2864 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2866 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2871 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2872 xhci->devs[slot_id]->out_ctx, ep_index);
2873 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2874 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2875 deq_state->new_deq_ptr);
2877 xhci_warn(xhci, "WARN Cannot submit config ep after "
2878 "reset ep command\n");
2879 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2880 deq_state->new_deq_seg,
2881 deq_state->new_deq_ptr);
2884 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2886 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2887 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2888 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2889 added_ctxs, added_ctxs);
2892 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2893 unsigned int ep_index, struct xhci_td *td)
2895 struct xhci_dequeue_state deq_state;
2896 struct xhci_virt_ep *ep;
2897 struct usb_device *udev = td->urb->dev;
2899 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2900 "Cleaning up stalled endpoint ring");
2901 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2902 /* We need to move the HW's dequeue pointer past this TD,
2903 * or it will attempt to resend it on the next doorbell ring.
2905 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2906 ep_index, ep->stopped_stream, td, &deq_state);
2908 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2911 /* HW with the reset endpoint quirk will use the saved dequeue state to
2912 * issue a configure endpoint command later.
2914 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2915 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2916 "Queueing new dequeue state");
2917 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2918 ep_index, ep->stopped_stream, &deq_state);
2920 /* Better hope no one uses the input context between now and the
2921 * reset endpoint completion!
2922 * XXX: No idea how this hardware will react when stream rings
2925 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2926 "Setting up input context for "
2927 "configure endpoint command");
2928 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2929 ep_index, &deq_state);
2933 /* Called when clearing halted device. The core should have sent the control
2934 * message to clear the device halt condition. The host side of the halt should
2935 * already be cleared with a reset endpoint command issued when the STALL tx
2936 * event was received.
2938 * Context: in_interrupt
2941 void xhci_endpoint_reset(struct usb_hcd *hcd,
2942 struct usb_host_endpoint *ep)
2944 struct xhci_hcd *xhci;
2946 xhci = hcd_to_xhci(hcd);
2949 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2950 * The Reset Endpoint Command may only be issued to endpoints in the
2951 * Halted state. If software wishes reset the Data Toggle or Sequence
2952 * Number of an endpoint that isn't in the Halted state, then software
2953 * may issue a Configure Endpoint Command with the Drop and Add bits set
2954 * for the target endpoint. that is in the Stopped state.
2957 /* For now just print debug to follow the situation */
2958 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2959 ep->desc.bEndpointAddress);
2962 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2963 struct usb_device *udev, struct usb_host_endpoint *ep,
2964 unsigned int slot_id)
2967 unsigned int ep_index;
2968 unsigned int ep_state;
2972 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2975 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2976 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2977 " descriptor for ep 0x%x does not support streams\n",
2978 ep->desc.bEndpointAddress);
2982 ep_index = xhci_get_endpoint_index(&ep->desc);
2983 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2984 if (ep_state & EP_HAS_STREAMS ||
2985 ep_state & EP_GETTING_STREAMS) {
2986 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2987 "already has streams set up.\n",
2988 ep->desc.bEndpointAddress);
2989 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2990 "dynamic stream context array reallocation.\n");
2993 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2994 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2995 "endpoint 0x%x; URBs are pending.\n",
2996 ep->desc.bEndpointAddress);
3002 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3003 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3005 unsigned int max_streams;
3007 /* The stream context array size must be a power of two */
3008 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3010 * Find out how many primary stream array entries the host controller
3011 * supports. Later we may use secondary stream arrays (similar to 2nd
3012 * level page entries), but that's an optional feature for xHCI host
3013 * controllers. xHCs must support at least 4 stream IDs.
3015 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3016 if (*num_stream_ctxs > max_streams) {
3017 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3019 *num_stream_ctxs = max_streams;
3020 *num_streams = max_streams;
3024 /* Returns an error code if one of the endpoint already has streams.
3025 * This does not change any data structures, it only checks and gathers
3028 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3029 struct usb_device *udev,
3030 struct usb_host_endpoint **eps, unsigned int num_eps,
3031 unsigned int *num_streams, u32 *changed_ep_bitmask)
3033 unsigned int max_streams;
3034 unsigned int endpoint_flag;
3038 for (i = 0; i < num_eps; i++) {
3039 ret = xhci_check_streams_endpoint(xhci, udev,
3040 eps[i], udev->slot_id);
3044 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3045 if (max_streams < (*num_streams - 1)) {
3046 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3047 eps[i]->desc.bEndpointAddress,
3049 *num_streams = max_streams+1;
3052 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3053 if (*changed_ep_bitmask & endpoint_flag)
3055 *changed_ep_bitmask |= endpoint_flag;
3060 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3061 struct usb_device *udev,
3062 struct usb_host_endpoint **eps, unsigned int num_eps)
3064 u32 changed_ep_bitmask = 0;
3065 unsigned int slot_id;
3066 unsigned int ep_index;
3067 unsigned int ep_state;
3070 slot_id = udev->slot_id;
3071 if (!xhci->devs[slot_id])
3074 for (i = 0; i < num_eps; i++) {
3075 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3076 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3077 /* Are streams already being freed for the endpoint? */
3078 if (ep_state & EP_GETTING_NO_STREAMS) {
3079 xhci_warn(xhci, "WARN Can't disable streams for "
3081 "streams are being disabled already\n",
3082 eps[i]->desc.bEndpointAddress);
3085 /* Are there actually any streams to free? */
3086 if (!(ep_state & EP_HAS_STREAMS) &&
3087 !(ep_state & EP_GETTING_STREAMS)) {
3088 xhci_warn(xhci, "WARN Can't disable streams for "
3090 "streams are already disabled!\n",
3091 eps[i]->desc.bEndpointAddress);
3092 xhci_warn(xhci, "WARN xhci_free_streams() called "
3093 "with non-streams endpoint\n");
3096 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3098 return changed_ep_bitmask;
3102 * The USB device drivers use this function (through the HCD interface in USB
3103 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3104 * coordinate mass storage command queueing across multiple endpoints (basically
3105 * a stream ID == a task ID).
3107 * Setting up streams involves allocating the same size stream context array
3108 * for each endpoint and issuing a configure endpoint command for all endpoints.
3110 * Don't allow the call to succeed if one endpoint only supports one stream
3111 * (which means it doesn't support streams at all).
3113 * Drivers may get less stream IDs than they asked for, if the host controller
3114 * hardware or endpoints claim they can't support the number of requested
3117 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3118 struct usb_host_endpoint **eps, unsigned int num_eps,
3119 unsigned int num_streams, gfp_t mem_flags)
3122 struct xhci_hcd *xhci;
3123 struct xhci_virt_device *vdev;
3124 struct xhci_command *config_cmd;
3125 struct xhci_input_control_ctx *ctrl_ctx;
3126 unsigned int ep_index;
3127 unsigned int num_stream_ctxs;
3128 unsigned int max_packet;
3129 unsigned long flags;
3130 u32 changed_ep_bitmask = 0;
3135 /* Add one to the number of streams requested to account for
3136 * stream 0 that is reserved for xHCI usage.
3139 xhci = hcd_to_xhci(hcd);
3140 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3143 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3144 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3145 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3146 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3150 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3152 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3155 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3157 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3159 xhci_free_command(xhci, config_cmd);
3163 /* Check to make sure all endpoints are not already configured for
3164 * streams. While we're at it, find the maximum number of streams that
3165 * all the endpoints will support and check for duplicate endpoints.
3167 spin_lock_irqsave(&xhci->lock, flags);
3168 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3169 num_eps, &num_streams, &changed_ep_bitmask);
3171 xhci_free_command(xhci, config_cmd);
3172 spin_unlock_irqrestore(&xhci->lock, flags);
3175 if (num_streams <= 1) {
3176 xhci_warn(xhci, "WARN: endpoints can't handle "
3177 "more than one stream.\n");
3178 xhci_free_command(xhci, config_cmd);
3179 spin_unlock_irqrestore(&xhci->lock, flags);
3182 vdev = xhci->devs[udev->slot_id];
3183 /* Mark each endpoint as being in transition, so
3184 * xhci_urb_enqueue() will reject all URBs.
3186 for (i = 0; i < num_eps; i++) {
3187 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3188 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3190 spin_unlock_irqrestore(&xhci->lock, flags);
3192 /* Setup internal data structures and allocate HW data structures for
3193 * streams (but don't install the HW structures in the input context
3194 * until we're sure all memory allocation succeeded).
3196 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3197 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3198 num_stream_ctxs, num_streams);
3200 for (i = 0; i < num_eps; i++) {
3201 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3202 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3203 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3206 max_packet, mem_flags);
3207 if (!vdev->eps[ep_index].stream_info)
3209 /* Set maxPstreams in endpoint context and update deq ptr to
3210 * point to stream context array. FIXME
3214 /* Set up the input context for a configure endpoint command. */
3215 for (i = 0; i < num_eps; i++) {
3216 struct xhci_ep_ctx *ep_ctx;
3218 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3219 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3221 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3222 vdev->out_ctx, ep_index);
3223 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3224 vdev->eps[ep_index].stream_info);
3226 /* Tell the HW to drop its old copy of the endpoint context info
3227 * and add the updated copy from the input context.
3229 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3230 vdev->out_ctx, ctrl_ctx,
3231 changed_ep_bitmask, changed_ep_bitmask);
3233 /* Issue and wait for the configure endpoint command */
3234 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3237 /* xHC rejected the configure endpoint command for some reason, so we
3238 * leave the old ring intact and free our internal streams data
3244 spin_lock_irqsave(&xhci->lock, flags);
3245 for (i = 0; i < num_eps; i++) {
3246 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3247 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3248 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3249 udev->slot_id, ep_index);
3250 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3252 xhci_free_command(xhci, config_cmd);
3253 spin_unlock_irqrestore(&xhci->lock, flags);
3255 /* Subtract 1 for stream 0, which drivers can't use */
3256 return num_streams - 1;
3259 /* If it didn't work, free the streams! */
3260 for (i = 0; i < num_eps; i++) {
3261 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3262 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3263 vdev->eps[ep_index].stream_info = NULL;
3264 /* FIXME Unset maxPstreams in endpoint context and
3265 * update deq ptr to point to normal string ring.
3267 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3268 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3269 xhci_endpoint_zero(xhci, vdev, eps[i]);
3271 xhci_free_command(xhci, config_cmd);
3275 /* Transition the endpoint from using streams to being a "normal" endpoint
3278 * Modify the endpoint context state, submit a configure endpoint command,
3279 * and free all endpoint rings for streams if that completes successfully.
3281 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3282 struct usb_host_endpoint **eps, unsigned int num_eps,
3286 struct xhci_hcd *xhci;
3287 struct xhci_virt_device *vdev;
3288 struct xhci_command *command;
3289 struct xhci_input_control_ctx *ctrl_ctx;
3290 unsigned int ep_index;
3291 unsigned long flags;
3292 u32 changed_ep_bitmask;
3294 xhci = hcd_to_xhci(hcd);
3295 vdev = xhci->devs[udev->slot_id];
3297 /* Set up a configure endpoint command to remove the streams rings */
3298 spin_lock_irqsave(&xhci->lock, flags);
3299 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3300 udev, eps, num_eps);
3301 if (changed_ep_bitmask == 0) {
3302 spin_unlock_irqrestore(&xhci->lock, flags);
3306 /* Use the xhci_command structure from the first endpoint. We may have
3307 * allocated too many, but the driver may call xhci_free_streams() for
3308 * each endpoint it grouped into one call to xhci_alloc_streams().
3310 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3311 command = vdev->eps[ep_index].stream_info->free_streams_command;
3312 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3314 spin_unlock_irqrestore(&xhci->lock, flags);
3315 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3320 for (i = 0; i < num_eps; i++) {
3321 struct xhci_ep_ctx *ep_ctx;
3323 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3324 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3325 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3326 EP_GETTING_NO_STREAMS;
3328 xhci_endpoint_copy(xhci, command->in_ctx,
3329 vdev->out_ctx, ep_index);
3330 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3331 &vdev->eps[ep_index]);
3333 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3334 vdev->out_ctx, ctrl_ctx,
3335 changed_ep_bitmask, changed_ep_bitmask);
3336 spin_unlock_irqrestore(&xhci->lock, flags);
3338 /* Issue and wait for the configure endpoint command,
3339 * which must succeed.
3341 ret = xhci_configure_endpoint(xhci, udev, command,
3344 /* xHC rejected the configure endpoint command for some reason, so we
3345 * leave the streams rings intact.
3350 spin_lock_irqsave(&xhci->lock, flags);
3351 for (i = 0; i < num_eps; i++) {
3352 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3353 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3354 vdev->eps[ep_index].stream_info = NULL;
3355 /* FIXME Unset maxPstreams in endpoint context and
3356 * update deq ptr to point to normal string ring.
3358 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3359 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3361 spin_unlock_irqrestore(&xhci->lock, flags);
3367 * Deletes endpoint resources for endpoints that were active before a Reset
3368 * Device command, or a Disable Slot command. The Reset Device command leaves
3369 * the control endpoint intact, whereas the Disable Slot command deletes it.
3371 * Must be called with xhci->lock held.
3373 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3374 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3377 unsigned int num_dropped_eps = 0;
3378 unsigned int drop_flags = 0;
3380 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3381 if (virt_dev->eps[i].ring) {
3382 drop_flags |= 1 << i;
3386 xhci->num_active_eps -= num_dropped_eps;
3387 if (num_dropped_eps)
3388 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3389 "Dropped %u ep ctxs, flags = 0x%x, "
3391 num_dropped_eps, drop_flags,
3392 xhci->num_active_eps);
3396 * This submits a Reset Device Command, which will set the device state to 0,
3397 * set the device address to 0, and disable all the endpoints except the default
3398 * control endpoint. The USB core should come back and call
3399 * xhci_address_device(), and then re-set up the configuration. If this is
3400 * called because of a usb_reset_and_verify_device(), then the old alternate
3401 * settings will be re-installed through the normal bandwidth allocation
3404 * Wait for the Reset Device command to finish. Remove all structures
3405 * associated with the endpoints that were disabled. Clear the input device
3406 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3408 * If the virt_dev to be reset does not exist or does not match the udev,
3409 * it means the device is lost, possibly due to the xHC restore error and
3410 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3411 * re-allocate the device.
3413 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3416 unsigned long flags;
3417 struct xhci_hcd *xhci;
3418 unsigned int slot_id;
3419 struct xhci_virt_device *virt_dev;
3420 struct xhci_command *reset_device_cmd;
3421 int last_freed_endpoint;
3422 struct xhci_slot_ctx *slot_ctx;
3423 int old_active_eps = 0;
3425 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3428 xhci = hcd_to_xhci(hcd);
3429 slot_id = udev->slot_id;
3430 virt_dev = xhci->devs[slot_id];
3432 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3433 "not exist. Re-allocate the device\n", slot_id);
3434 ret = xhci_alloc_dev(hcd, udev);
3441 if (virt_dev->tt_info)
3442 old_active_eps = virt_dev->tt_info->active_eps;
3444 if (virt_dev->udev != udev) {
3445 /* If the virt_dev and the udev does not match, this virt_dev
3446 * may belong to another udev.
3447 * Re-allocate the device.
3449 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3450 "not match the udev. Re-allocate the device\n",
3452 ret = xhci_alloc_dev(hcd, udev);
3459 /* If device is not setup, there is no point in resetting it */
3460 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3461 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3462 SLOT_STATE_DISABLED)
3465 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3466 /* Allocate the command structure that holds the struct completion.
3467 * Assume we're in process context, since the normal device reset
3468 * process has to wait for the device anyway. Storage devices are
3469 * reset as part of error handling, so use GFP_NOIO instead of
3472 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3473 if (!reset_device_cmd) {
3474 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3478 /* Attempt to submit the Reset Device command to the command ring */
3479 spin_lock_irqsave(&xhci->lock, flags);
3481 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3483 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3484 spin_unlock_irqrestore(&xhci->lock, flags);
3485 goto command_cleanup;
3487 xhci_ring_cmd_db(xhci);
3488 spin_unlock_irqrestore(&xhci->lock, flags);
3490 /* Wait for the Reset Device command to finish */
3491 wait_for_completion(reset_device_cmd->completion);
3493 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3494 * unless we tried to reset a slot ID that wasn't enabled,
3495 * or the device wasn't in the addressed or configured state.
3497 ret = reset_device_cmd->status;
3499 case COMP_CMD_ABORT:
3501 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3503 goto command_cleanup;
3504 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3505 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3506 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3508 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3509 xhci_dbg(xhci, "Not freeing device rings.\n");
3510 /* Don't treat this as an error. May change my mind later. */
3512 goto command_cleanup;
3514 xhci_dbg(xhci, "Successful reset device command.\n");
3517 if (xhci_is_vendor_info_code(xhci, ret))
3519 xhci_warn(xhci, "Unknown completion code %u for "
3520 "reset device command.\n", ret);
3522 goto command_cleanup;
3525 /* Free up host controller endpoint resources */
3526 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3527 spin_lock_irqsave(&xhci->lock, flags);
3528 /* Don't delete the default control endpoint resources */
3529 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3530 spin_unlock_irqrestore(&xhci->lock, flags);
3533 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3534 last_freed_endpoint = 1;
3535 for (i = 1; i < 31; ++i) {
3536 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3538 if (ep->ep_state & EP_HAS_STREAMS) {
3539 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3540 xhci_get_endpoint_address(i));
3541 xhci_free_stream_info(xhci, ep->stream_info);
3542 ep->stream_info = NULL;
3543 ep->ep_state &= ~EP_HAS_STREAMS;
3547 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3548 last_freed_endpoint = i;
3550 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3551 xhci_drop_ep_from_interval_table(xhci,
3552 &virt_dev->eps[i].bw_info,
3557 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3559 /* If necessary, update the number of active TTs on this root port */
3560 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3562 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3563 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3567 xhci_free_command(xhci, reset_device_cmd);
3572 * At this point, the struct usb_device is about to go away, the device has
3573 * disconnected, and all traffic has been stopped and the endpoints have been
3574 * disabled. Free any HC data structures associated with that device.
3576 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3578 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3579 struct xhci_virt_device *virt_dev;
3580 unsigned long flags;
3583 struct xhci_command *command;
3585 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3589 #ifndef CONFIG_USB_DEFAULT_PERSIST
3591 * We called pm_runtime_get_noresume when the device was attached.
3592 * Decrement the counter here to allow controller to runtime suspend
3593 * if no devices remain.
3595 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3596 pm_runtime_put_noidle(hcd->self.controller);
3599 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3600 /* If the host is halted due to driver unload, we still need to free the
3603 if (ret <= 0 && ret != -ENODEV) {
3608 virt_dev = xhci->devs[udev->slot_id];
3610 /* Stop any wayward timer functions (which may grab the lock) */
3611 for (i = 0; i < 31; ++i) {
3612 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3613 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3616 spin_lock_irqsave(&xhci->lock, flags);
3617 /* Don't disable the slot if the host controller is dead. */
3618 state = readl(&xhci->op_regs->status);
3619 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3620 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3621 xhci_free_virt_device(xhci, udev->slot_id);
3622 spin_unlock_irqrestore(&xhci->lock, flags);
3627 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3629 spin_unlock_irqrestore(&xhci->lock, flags);
3630 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3633 xhci_ring_cmd_db(xhci);
3634 spin_unlock_irqrestore(&xhci->lock, flags);
3637 * Event command completion handler will free any data structures
3638 * associated with the slot. XXX Can free sleep?
3643 * Checks if we have enough host controller resources for the default control
3646 * Must be called with xhci->lock held.
3648 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3650 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3651 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3652 "Not enough ep ctxs: "
3653 "%u active, need to add 1, limit is %u.",
3654 xhci->num_active_eps, xhci->limit_active_eps);
3657 xhci->num_active_eps += 1;
3658 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3659 "Adding 1 ep ctx, %u now active.",
3660 xhci->num_active_eps);
3666 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3667 * timed out, or allocating memory failed. Returns 1 on success.
3669 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3671 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3672 unsigned long flags;
3674 struct xhci_command *command;
3676 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3680 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3681 mutex_lock(&xhci->mutex);
3682 spin_lock_irqsave(&xhci->lock, flags);
3683 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3685 spin_unlock_irqrestore(&xhci->lock, flags);
3686 mutex_unlock(&xhci->mutex);
3687 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3688 xhci_free_command(xhci, command);
3691 xhci_ring_cmd_db(xhci);
3692 spin_unlock_irqrestore(&xhci->lock, flags);
3694 wait_for_completion(command->completion);
3695 slot_id = command->slot_id;
3696 mutex_unlock(&xhci->mutex);
3698 if (!slot_id || command->status != COMP_SUCCESS) {
3699 xhci_err(xhci, "Error while assigning device slot ID\n");
3700 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3702 readl(&xhci->cap_regs->hcs_params1)));
3703 xhci_free_command(xhci, command);
3707 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3708 spin_lock_irqsave(&xhci->lock, flags);
3709 ret = xhci_reserve_host_control_ep_resources(xhci);
3711 spin_unlock_irqrestore(&xhci->lock, flags);
3712 xhci_warn(xhci, "Not enough host resources, "
3713 "active endpoint contexts = %u\n",
3714 xhci->num_active_eps);
3717 spin_unlock_irqrestore(&xhci->lock, flags);
3719 /* Use GFP_NOIO, since this function can be called from
3720 * xhci_discover_or_reset_device(), which may be called as part of
3721 * mass storage driver error handling.
3723 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3724 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3727 udev->slot_id = slot_id;
3729 #ifndef CONFIG_USB_DEFAULT_PERSIST
3731 * If resetting upon resume, we can't put the controller into runtime
3732 * suspend if there is a device attached.
3734 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3735 pm_runtime_get_noresume(hcd->self.controller);
3739 xhci_free_command(xhci, command);
3740 /* Is this a LS or FS device under a HS hub? */
3741 /* Hub or peripherial? */
3745 /* Disable slot, if we can do it without mem alloc */
3746 spin_lock_irqsave(&xhci->lock, flags);
3747 kfree(command->completion);
3748 command->completion = NULL;
3749 command->status = 0;
3750 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3752 xhci_ring_cmd_db(xhci);
3753 spin_unlock_irqrestore(&xhci->lock, flags);
3758 * Issue an Address Device command and optionally send a corresponding
3759 * SetAddress request to the device.
3761 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3762 enum xhci_setup_dev setup)
3764 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3765 unsigned long flags;
3766 struct xhci_virt_device *virt_dev;
3768 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3769 struct xhci_slot_ctx *slot_ctx;
3770 struct xhci_input_control_ctx *ctrl_ctx;
3772 struct xhci_command *command = NULL;
3774 mutex_lock(&xhci->mutex);
3776 if (xhci->xhc_state) { /* dying, removing or halted */
3781 if (!udev->slot_id) {
3782 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3783 "Bad Slot ID %d", udev->slot_id);
3788 virt_dev = xhci->devs[udev->slot_id];
3790 if (WARN_ON(!virt_dev)) {
3792 * In plug/unplug torture test with an NEC controller,
3793 * a zero-dereference was observed once due to virt_dev = 0.
3794 * Print useful debug rather than crash if it is observed again!
3796 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3802 if (setup == SETUP_CONTEXT_ONLY) {
3803 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3804 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3805 SLOT_STATE_DEFAULT) {
3806 xhci_dbg(xhci, "Slot already in default state\n");
3811 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3817 command->in_ctx = virt_dev->in_ctx;
3819 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3820 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3822 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3828 * If this is the first Set Address since device plug-in or
3829 * virt_device realloaction after a resume with an xHCI power loss,
3830 * then set up the slot context.
3832 if (!slot_ctx->dev_info)
3833 xhci_setup_addressable_virt_dev(xhci, udev);
3834 /* Otherwise, update the control endpoint ring enqueue pointer. */
3836 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3837 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3838 ctrl_ctx->drop_flags = 0;
3840 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3841 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3842 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3843 le32_to_cpu(slot_ctx->dev_info) >> 27);
3845 spin_lock_irqsave(&xhci->lock, flags);
3846 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3847 udev->slot_id, setup);
3849 spin_unlock_irqrestore(&xhci->lock, flags);
3850 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3851 "FIXME: allocate a command ring segment");
3854 xhci_ring_cmd_db(xhci);
3855 spin_unlock_irqrestore(&xhci->lock, flags);
3857 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3858 wait_for_completion(command->completion);
3860 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3861 * the SetAddress() "recovery interval" required by USB and aborting the
3862 * command on a timeout.
3864 switch (command->status) {
3865 case COMP_CMD_ABORT:
3867 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3870 case COMP_CTX_STATE:
3872 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3873 act, udev->slot_id);
3877 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3881 dev_warn(&udev->dev,
3882 "ERROR: Incompatible device for setup %s command\n", act);
3886 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3887 "Successful setup %s command", act);
3891 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3892 act, command->status);
3893 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3894 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3895 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3901 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3902 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3903 "Op regs DCBAA ptr = %#016llx", temp_64);
3904 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3905 "Slot ID %d dcbaa entry @%p = %#016llx",
3907 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3908 (unsigned long long)
3909 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3910 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3911 "Output Context DMA address = %#08llx",
3912 (unsigned long long)virt_dev->out_ctx->dma);
3913 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3914 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3915 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3916 le32_to_cpu(slot_ctx->dev_info) >> 27);
3917 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3918 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3920 * USB core uses address 1 for the roothubs, so we add one to the
3921 * address given back to us by the HC.
3923 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3924 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3925 le32_to_cpu(slot_ctx->dev_info) >> 27);
3926 /* Zero the input context control for later use */
3927 ctrl_ctx->add_flags = 0;
3928 ctrl_ctx->drop_flags = 0;
3930 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3931 "Internal device address = %d",
3932 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3934 mutex_unlock(&xhci->mutex);
3936 kfree(command->completion);
3942 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3944 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3947 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3949 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3953 * Transfer the port index into real index in the HW port status
3954 * registers. Caculate offset between the port's PORTSC register
3955 * and port status base. Divide the number of per port register
3956 * to get the real index. The raw port number bases 1.
3958 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3960 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3961 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3962 __le32 __iomem *addr;
3965 if (hcd->speed < HCD_USB3)
3966 addr = xhci->usb2_ports[port1 - 1];
3968 addr = xhci->usb3_ports[port1 - 1];
3970 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3975 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3976 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3978 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3979 struct usb_device *udev, u16 max_exit_latency)
3981 struct xhci_virt_device *virt_dev;
3982 struct xhci_command *command;
3983 struct xhci_input_control_ctx *ctrl_ctx;
3984 struct xhci_slot_ctx *slot_ctx;
3985 unsigned long flags;
3988 spin_lock_irqsave(&xhci->lock, flags);
3990 virt_dev = xhci->devs[udev->slot_id];
3993 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3994 * xHC was re-initialized. Exit latency will be set later after
3995 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3998 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
3999 spin_unlock_irqrestore(&xhci->lock, flags);
4003 /* Attempt to issue an Evaluate Context command to change the MEL. */
4004 command = xhci->lpm_command;
4005 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4007 spin_unlock_irqrestore(&xhci->lock, flags);
4008 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4013 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4014 spin_unlock_irqrestore(&xhci->lock, flags);
4016 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4017 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4018 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4019 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4020 slot_ctx->dev_state = 0;
4022 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4023 "Set up evaluate context for LPM MEL change.");
4024 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4025 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4027 /* Issue and wait for the evaluate context command. */
4028 ret = xhci_configure_endpoint(xhci, udev, command,
4030 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4031 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4034 spin_lock_irqsave(&xhci->lock, flags);
4035 virt_dev->current_mel = max_exit_latency;
4036 spin_unlock_irqrestore(&xhci->lock, flags);
4043 /* BESL to HIRD Encoding array for USB2 LPM */
4044 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4045 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4047 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4048 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4049 struct usb_device *udev)
4051 int u2del, besl, besl_host;
4052 int besl_device = 0;
4055 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4056 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4058 if (field & USB_BESL_SUPPORT) {
4059 for (besl_host = 0; besl_host < 16; besl_host++) {
4060 if (xhci_besl_encoding[besl_host] >= u2del)
4063 /* Use baseline BESL value as default */
4064 if (field & USB_BESL_BASELINE_VALID)
4065 besl_device = USB_GET_BESL_BASELINE(field);
4066 else if (field & USB_BESL_DEEP_VALID)
4067 besl_device = USB_GET_BESL_DEEP(field);
4072 besl_host = (u2del - 51) / 75 + 1;
4075 besl = besl_host + besl_device;
4082 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4083 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4090 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4092 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4093 l1 = udev->l1_params.timeout / 256;
4095 /* device has preferred BESLD */
4096 if (field & USB_BESL_DEEP_VALID) {
4097 besld = USB_GET_BESL_DEEP(field);
4101 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4104 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4105 struct usb_device *udev, int enable)
4107 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4108 __le32 __iomem **port_array;
4109 __le32 __iomem *pm_addr, *hlpm_addr;
4110 u32 pm_val, hlpm_val, field;
4111 unsigned int port_num;
4112 unsigned long flags;
4113 int hird, exit_latency;
4116 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4120 if (!udev->parent || udev->parent->parent ||
4121 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4124 if (udev->usb2_hw_lpm_capable != 1)
4127 spin_lock_irqsave(&xhci->lock, flags);
4129 port_array = xhci->usb2_ports;
4130 port_num = udev->portnum - 1;
4131 pm_addr = port_array[port_num] + PORTPMSC;
4132 pm_val = readl(pm_addr);
4133 hlpm_addr = port_array[port_num] + PORTHLPMC;
4134 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4136 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4137 enable ? "enable" : "disable", port_num + 1);
4140 /* Host supports BESL timeout instead of HIRD */
4141 if (udev->usb2_hw_lpm_besl_capable) {
4142 /* if device doesn't have a preferred BESL value use a
4143 * default one which works with mixed HIRD and BESL
4144 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4146 if ((field & USB_BESL_SUPPORT) &&
4147 (field & USB_BESL_BASELINE_VALID))
4148 hird = USB_GET_BESL_BASELINE(field);
4150 hird = udev->l1_params.besl;
4152 exit_latency = xhci_besl_encoding[hird];
4153 spin_unlock_irqrestore(&xhci->lock, flags);
4155 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4156 * input context for link powermanagement evaluate
4157 * context commands. It is protected by hcd->bandwidth
4158 * mutex and is shared by all devices. We need to set
4159 * the max ext latency in USB 2 BESL LPM as well, so
4160 * use the same mutex and xhci_change_max_exit_latency()
4162 mutex_lock(hcd->bandwidth_mutex);
4163 ret = xhci_change_max_exit_latency(xhci, udev,
4165 mutex_unlock(hcd->bandwidth_mutex);
4169 spin_lock_irqsave(&xhci->lock, flags);
4171 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4172 writel(hlpm_val, hlpm_addr);
4176 hird = xhci_calculate_hird_besl(xhci, udev);
4179 pm_val &= ~PORT_HIRD_MASK;
4180 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4181 writel(pm_val, pm_addr);
4182 pm_val = readl(pm_addr);
4184 writel(pm_val, pm_addr);
4188 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4189 writel(pm_val, pm_addr);
4192 if (udev->usb2_hw_lpm_besl_capable) {
4193 spin_unlock_irqrestore(&xhci->lock, flags);
4194 mutex_lock(hcd->bandwidth_mutex);
4195 xhci_change_max_exit_latency(xhci, udev, 0);
4196 mutex_unlock(hcd->bandwidth_mutex);
4201 spin_unlock_irqrestore(&xhci->lock, flags);
4205 /* check if a usb2 port supports a given extened capability protocol
4206 * only USB2 ports extended protocol capability values are cached.
4207 * Return 1 if capability is supported
4209 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4210 unsigned capability)
4212 u32 port_offset, port_count;
4215 for (i = 0; i < xhci->num_ext_caps; i++) {
4216 if (xhci->ext_caps[i] & capability) {
4217 /* port offsets starts at 1 */
4218 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4219 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4220 if (port >= port_offset &&
4221 port < port_offset + port_count)
4228 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4230 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4231 int portnum = udev->portnum - 1;
4233 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4237 /* we only support lpm for non-hub device connected to root hub yet */
4238 if (!udev->parent || udev->parent->parent ||
4239 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4242 if (xhci->hw_lpm_support == 1 &&
4243 xhci_check_usb2_port_capability(
4244 xhci, portnum, XHCI_HLC)) {
4245 udev->usb2_hw_lpm_capable = 1;
4246 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4247 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4248 if (xhci_check_usb2_port_capability(xhci, portnum,
4250 udev->usb2_hw_lpm_besl_capable = 1;
4256 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4258 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4259 static unsigned long long xhci_service_interval_to_ns(
4260 struct usb_endpoint_descriptor *desc)
4262 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4265 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4266 enum usb3_link_state state)
4268 unsigned long long sel;
4269 unsigned long long pel;
4270 unsigned int max_sel_pel;
4275 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4276 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4277 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4278 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4282 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4283 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4284 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4288 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4290 return USB3_LPM_DISABLED;
4293 if (sel <= max_sel_pel && pel <= max_sel_pel)
4294 return USB3_LPM_DEVICE_INITIATED;
4296 if (sel > max_sel_pel)
4297 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4298 "due to long SEL %llu ms\n",
4301 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4302 "due to long PEL %llu ms\n",
4304 return USB3_LPM_DISABLED;
4307 /* The U1 timeout should be the maximum of the following values:
4308 * - For control endpoints, U1 system exit latency (SEL) * 3
4309 * - For bulk endpoints, U1 SEL * 5
4310 * - For interrupt endpoints:
4311 * - Notification EPs, U1 SEL * 3
4312 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4313 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4315 static unsigned long long xhci_calculate_intel_u1_timeout(
4316 struct usb_device *udev,
4317 struct usb_endpoint_descriptor *desc)
4319 unsigned long long timeout_ns;
4323 ep_type = usb_endpoint_type(desc);
4325 case USB_ENDPOINT_XFER_CONTROL:
4326 timeout_ns = udev->u1_params.sel * 3;
4328 case USB_ENDPOINT_XFER_BULK:
4329 timeout_ns = udev->u1_params.sel * 5;
4331 case USB_ENDPOINT_XFER_INT:
4332 intr_type = usb_endpoint_interrupt_type(desc);
4333 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4334 timeout_ns = udev->u1_params.sel * 3;
4337 /* Otherwise the calculation is the same as isoc eps */
4338 case USB_ENDPOINT_XFER_ISOC:
4339 timeout_ns = xhci_service_interval_to_ns(desc);
4340 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4341 if (timeout_ns < udev->u1_params.sel * 2)
4342 timeout_ns = udev->u1_params.sel * 2;
4351 /* Returns the hub-encoded U1 timeout value. */
4352 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4353 struct usb_device *udev,
4354 struct usb_endpoint_descriptor *desc)
4356 unsigned long long timeout_ns;
4358 if (xhci->quirks & XHCI_INTEL_HOST)
4359 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4361 timeout_ns = udev->u1_params.sel;
4363 /* The U1 timeout is encoded in 1us intervals.
4364 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4366 if (timeout_ns == USB3_LPM_DISABLED)
4369 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4371 /* If the necessary timeout value is bigger than what we can set in the
4372 * USB 3.0 hub, we have to disable hub-initiated U1.
4374 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4376 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4377 "due to long timeout %llu ms\n", timeout_ns);
4378 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4381 /* The U2 timeout should be the maximum of:
4382 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4383 * - largest bInterval of any active periodic endpoint (to avoid going
4384 * into lower power link states between intervals).
4385 * - the U2 Exit Latency of the device
4387 static unsigned long long xhci_calculate_intel_u2_timeout(
4388 struct usb_device *udev,
4389 struct usb_endpoint_descriptor *desc)
4391 unsigned long long timeout_ns;
4392 unsigned long long u2_del_ns;
4394 timeout_ns = 10 * 1000 * 1000;
4396 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4397 (xhci_service_interval_to_ns(desc) > timeout_ns))
4398 timeout_ns = xhci_service_interval_to_ns(desc);
4400 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4401 if (u2_del_ns > timeout_ns)
4402 timeout_ns = u2_del_ns;
4407 /* Returns the hub-encoded U2 timeout value. */
4408 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4409 struct usb_device *udev,
4410 struct usb_endpoint_descriptor *desc)
4412 unsigned long long timeout_ns;
4414 if (xhci->quirks & XHCI_INTEL_HOST)
4415 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4417 timeout_ns = udev->u2_params.sel;
4419 /* The U2 timeout is encoded in 256us intervals */
4420 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4421 /* If the necessary timeout value is bigger than what we can set in the
4422 * USB 3.0 hub, we have to disable hub-initiated U2.
4424 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4426 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4427 "due to long timeout %llu ms\n", timeout_ns);
4428 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4431 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4432 struct usb_device *udev,
4433 struct usb_endpoint_descriptor *desc,
4434 enum usb3_link_state state,
4437 if (state == USB3_LPM_U1)
4438 return xhci_calculate_u1_timeout(xhci, udev, desc);
4439 else if (state == USB3_LPM_U2)
4440 return xhci_calculate_u2_timeout(xhci, udev, desc);
4442 return USB3_LPM_DISABLED;
4445 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4446 struct usb_device *udev,
4447 struct usb_endpoint_descriptor *desc,
4448 enum usb3_link_state state,
4453 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4454 desc, state, timeout);
4456 /* If we found we can't enable hub-initiated LPM, or
4457 * the U1 or U2 exit latency was too high to allow
4458 * device-initiated LPM as well, just stop searching.
4460 if (alt_timeout == USB3_LPM_DISABLED ||
4461 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4462 *timeout = alt_timeout;
4465 if (alt_timeout > *timeout)
4466 *timeout = alt_timeout;
4470 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4471 struct usb_device *udev,
4472 struct usb_host_interface *alt,
4473 enum usb3_link_state state,
4478 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4479 if (xhci_update_timeout_for_endpoint(xhci, udev,
4480 &alt->endpoint[j].desc, state, timeout))
4487 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4488 enum usb3_link_state state)
4490 struct usb_device *parent;
4491 unsigned int num_hubs;
4493 if (state == USB3_LPM_U2)
4496 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4497 for (parent = udev->parent, num_hubs = 0; parent->parent;
4498 parent = parent->parent)
4504 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4505 " below second-tier hub.\n");
4506 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4507 "to decrease power consumption.\n");
4511 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4512 struct usb_device *udev,
4513 enum usb3_link_state state)
4515 if (xhci->quirks & XHCI_INTEL_HOST)
4516 return xhci_check_intel_tier_policy(udev, state);
4521 /* Returns the U1 or U2 timeout that should be enabled.
4522 * If the tier check or timeout setting functions return with a non-zero exit
4523 * code, that means the timeout value has been finalized and we shouldn't look
4524 * at any more endpoints.
4526 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4527 struct usb_device *udev, enum usb3_link_state state)
4529 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4530 struct usb_host_config *config;
4533 u16 timeout = USB3_LPM_DISABLED;
4535 if (state == USB3_LPM_U1)
4537 else if (state == USB3_LPM_U2)
4540 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4545 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4548 /* Gather some information about the currently installed configuration
4549 * and alternate interface settings.
4551 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4555 config = udev->actconfig;
4559 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4560 struct usb_driver *driver;
4561 struct usb_interface *intf = config->interface[i];
4566 /* Check if any currently bound drivers want hub-initiated LPM
4569 if (intf->dev.driver) {
4570 driver = to_usb_driver(intf->dev.driver);
4571 if (driver && driver->disable_hub_initiated_lpm) {
4572 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4573 "at request of driver %s\n",
4574 state_name, driver->name);
4575 return xhci_get_timeout_no_hub_lpm(udev, state);
4579 /* Not sure how this could happen... */
4580 if (!intf->cur_altsetting)
4583 if (xhci_update_timeout_for_interface(xhci, udev,
4584 intf->cur_altsetting,
4591 static int calculate_max_exit_latency(struct usb_device *udev,
4592 enum usb3_link_state state_changed,
4593 u16 hub_encoded_timeout)
4595 unsigned long long u1_mel_us = 0;
4596 unsigned long long u2_mel_us = 0;
4597 unsigned long long mel_us = 0;
4603 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4604 hub_encoded_timeout == USB3_LPM_DISABLED);
4605 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4606 hub_encoded_timeout == USB3_LPM_DISABLED);
4608 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4609 hub_encoded_timeout != USB3_LPM_DISABLED);
4610 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4611 hub_encoded_timeout != USB3_LPM_DISABLED);
4613 /* If U1 was already enabled and we're not disabling it,
4614 * or we're going to enable U1, account for the U1 max exit latency.
4616 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4618 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4619 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4621 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4623 if (u1_mel_us > u2_mel_us)
4627 /* xHCI host controller max exit latency field is only 16 bits wide. */
4628 if (mel_us > MAX_EXIT) {
4629 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4630 "is too big.\n", mel_us);
4636 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4637 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4638 struct usb_device *udev, enum usb3_link_state state)
4640 struct xhci_hcd *xhci;
4641 u16 hub_encoded_timeout;
4645 xhci = hcd_to_xhci(hcd);
4646 /* The LPM timeout values are pretty host-controller specific, so don't
4647 * enable hub-initiated timeouts unless the vendor has provided
4648 * information about their timeout algorithm.
4650 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4651 !xhci->devs[udev->slot_id])
4652 return USB3_LPM_DISABLED;
4654 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4655 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4657 /* Max Exit Latency is too big, disable LPM. */
4658 hub_encoded_timeout = USB3_LPM_DISABLED;
4662 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4665 return hub_encoded_timeout;
4668 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4669 struct usb_device *udev, enum usb3_link_state state)
4671 struct xhci_hcd *xhci;
4674 xhci = hcd_to_xhci(hcd);
4675 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4676 !xhci->devs[udev->slot_id])
4679 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4680 return xhci_change_max_exit_latency(xhci, udev, mel);
4682 #else /* CONFIG_PM */
4684 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4685 struct usb_device *udev, int enable)
4690 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4695 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4696 struct usb_device *udev, enum usb3_link_state state)
4698 return USB3_LPM_DISABLED;
4701 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4702 struct usb_device *udev, enum usb3_link_state state)
4706 #endif /* CONFIG_PM */
4708 /*-------------------------------------------------------------------------*/
4710 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4711 * internal data structures for the device.
4713 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4714 struct usb_tt *tt, gfp_t mem_flags)
4716 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4717 struct xhci_virt_device *vdev;
4718 struct xhci_command *config_cmd;
4719 struct xhci_input_control_ctx *ctrl_ctx;
4720 struct xhci_slot_ctx *slot_ctx;
4721 unsigned long flags;
4722 unsigned think_time;
4725 /* Ignore root hubs */
4729 vdev = xhci->devs[hdev->slot_id];
4731 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4734 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4736 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4739 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4741 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4743 xhci_free_command(xhci, config_cmd);
4747 spin_lock_irqsave(&xhci->lock, flags);
4748 if (hdev->speed == USB_SPEED_HIGH &&
4749 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4750 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4751 xhci_free_command(xhci, config_cmd);
4752 spin_unlock_irqrestore(&xhci->lock, flags);
4756 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4757 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4758 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4759 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4761 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4762 * but it may be already set to 1 when setup an xHCI virtual
4763 * device, so clear it anyway.
4766 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4767 else if (hdev->speed == USB_SPEED_FULL)
4768 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4770 if (xhci->hci_version > 0x95) {
4771 xhci_dbg(xhci, "xHCI version %x needs hub "
4772 "TT think time and number of ports\n",
4773 (unsigned int) xhci->hci_version);
4774 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4775 /* Set TT think time - convert from ns to FS bit times.
4776 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4777 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4779 * xHCI 1.0: this field shall be 0 if the device is not a
4782 think_time = tt->think_time;
4783 if (think_time != 0)
4784 think_time = (think_time / 666) - 1;
4785 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4786 slot_ctx->tt_info |=
4787 cpu_to_le32(TT_THINK_TIME(think_time));
4789 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4790 "TT think time or number of ports\n",
4791 (unsigned int) xhci->hci_version);
4793 slot_ctx->dev_state = 0;
4794 spin_unlock_irqrestore(&xhci->lock, flags);
4796 xhci_dbg(xhci, "Set up %s for hub device.\n",
4797 (xhci->hci_version > 0x95) ?
4798 "configure endpoint" : "evaluate context");
4799 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4800 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4802 /* Issue and wait for the configure endpoint or
4803 * evaluate context command.
4805 if (xhci->hci_version > 0x95)
4806 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4809 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4812 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4813 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4815 xhci_free_command(xhci, config_cmd);
4819 int xhci_get_frame(struct usb_hcd *hcd)
4821 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4822 /* EHCI mods by the periodic size. Why? */
4823 return readl(&xhci->run_regs->microframe_index) >> 3;
4826 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4828 struct xhci_hcd *xhci;
4829 struct device *dev = hcd->self.controller;
4832 /* Accept arbitrarily long scatter-gather lists */
4833 hcd->self.sg_tablesize = ~0;
4835 /* support to build packet from discontinuous buffers */
4836 hcd->self.no_sg_constraint = 1;
4838 /* XHCI controllers don't stop the ep queue on short packets :| */
4839 hcd->self.no_stop_on_short = 1;
4841 xhci = hcd_to_xhci(hcd);
4843 if (usb_hcd_is_primary_hcd(hcd)) {
4844 xhci->main_hcd = hcd;
4845 /* Mark the first roothub as being USB 2.0.
4846 * The xHCI driver will register the USB 3.0 roothub.
4848 hcd->speed = HCD_USB2;
4849 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4851 * USB 2.0 roothub under xHCI has an integrated TT,
4852 * (rate matching hub) as opposed to having an OHCI/UHCI
4853 * companion controller.
4857 if (xhci->sbrn == 0x31) {
4858 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4859 hcd->speed = HCD_USB31;
4860 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4862 /* xHCI private pointer was set in xhci_pci_probe for the second
4863 * registered roothub.
4868 mutex_init(&xhci->mutex);
4869 xhci->cap_regs = hcd->regs;
4870 xhci->op_regs = hcd->regs +
4871 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4872 xhci->run_regs = hcd->regs +
4873 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4874 /* Cache read-only capability registers */
4875 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4876 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4877 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4878 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4879 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4880 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4881 if (xhci->hci_version > 0x100)
4882 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4883 xhci_print_registers(xhci);
4885 xhci->quirks |= quirks;
4887 get_quirks(dev, xhci);
4889 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4890 * success event after a short transfer. This quirk will ignore such
4893 if (xhci->hci_version > 0x96)
4894 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4896 /* Make sure the HC is halted. */
4897 retval = xhci_halt(xhci);
4901 xhci_dbg(xhci, "Resetting HCD\n");
4902 /* Reset the internal HC memory state and registers. */
4903 retval = xhci_reset(xhci);
4906 xhci_dbg(xhci, "Reset complete\n");
4909 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4910 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4911 * address memory pointers actually. So, this driver clears the AC64
4912 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4913 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4915 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4916 xhci->hcc_params &= ~BIT(0);
4918 /* Set dma_mask and coherent_dma_mask to 64-bits,
4919 * if xHC supports 64-bit addressing */
4920 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4921 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4922 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4923 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4926 * This is to avoid error in cases where a 32-bit USB
4927 * controller is used on a 64-bit capable system.
4929 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4932 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4933 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4936 xhci_dbg(xhci, "Calling HCD init\n");
4937 /* Initialize HCD and host controller data structures. */
4938 retval = xhci_init(hcd);
4941 xhci_dbg(xhci, "Called HCD init\n");
4943 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4944 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4948 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4950 static const struct hc_driver xhci_hc_driver = {
4951 .description = "xhci-hcd",
4952 .product_desc = "xHCI Host Controller",
4953 .hcd_priv_size = sizeof(struct xhci_hcd),
4956 * generic hardware linkage
4959 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4962 * basic lifecycle operations
4964 .reset = NULL, /* set in xhci_init_driver() */
4967 .shutdown = xhci_shutdown,
4970 * managing i/o requests and associated device resources
4972 .urb_enqueue = xhci_urb_enqueue,
4973 .urb_dequeue = xhci_urb_dequeue,
4974 .alloc_dev = xhci_alloc_dev,
4975 .free_dev = xhci_free_dev,
4976 .alloc_streams = xhci_alloc_streams,
4977 .free_streams = xhci_free_streams,
4978 .add_endpoint = xhci_add_endpoint,
4979 .drop_endpoint = xhci_drop_endpoint,
4980 .endpoint_reset = xhci_endpoint_reset,
4981 .check_bandwidth = xhci_check_bandwidth,
4982 .reset_bandwidth = xhci_reset_bandwidth,
4983 .address_device = xhci_address_device,
4984 .enable_device = xhci_enable_device,
4985 .update_hub_device = xhci_update_hub_device,
4986 .reset_device = xhci_discover_or_reset_device,
4989 * scheduling support
4991 .get_frame_number = xhci_get_frame,
4996 .hub_control = xhci_hub_control,
4997 .hub_status_data = xhci_hub_status_data,
4998 .bus_suspend = xhci_bus_suspend,
4999 .bus_resume = xhci_bus_resume,
5002 * call back when device connected and addressed
5004 .update_device = xhci_update_device,
5005 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5006 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5007 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5008 .find_raw_port_number = xhci_find_raw_port_number,
5011 void xhci_init_driver(struct hc_driver *drv,
5012 const struct xhci_driver_overrides *over)
5016 /* Copy the generic table to drv then apply the overrides */
5017 *drv = xhci_hc_driver;
5020 drv->hcd_priv_size += over->extra_priv_size;
5022 drv->reset = over->reset;
5024 drv->start = over->start;
5027 EXPORT_SYMBOL_GPL(xhci_init_driver);
5029 MODULE_DESCRIPTION(DRIVER_DESC);
5030 MODULE_AUTHOR(DRIVER_AUTHOR);
5031 MODULE_LICENSE("GPL");
5033 static int __init xhci_hcd_init(void)
5036 * Check the compiler generated sizes of structures that must be laid
5037 * out in specific ways for hardware access.
5039 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5040 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5041 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5042 /* xhci_device_control has eight fields, and also
5043 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5045 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5046 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5047 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5048 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5049 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5050 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5051 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5060 * If an init function is provided, an exit function must also be provided
5061 * to allow module unload.
5063 static void __exit xhci_hcd_fini(void) { }
5065 module_init(xhci_hcd_init);
5066 module_exit(xhci_hcd_fini);