2 * USB HOST XHCI Controller stack
4 * Based on xHCI host controller driver in linux-kernel
7 * Copyright (C) 2008 Intel Corp.
10 * Copyright (C) 2013 Samsung Electronics Co.Ltd
11 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
12 * Vikas Sajjan <vikas.sajjan@samsung.com>
14 * SPDX-License-Identifier: GPL-2.0+
18 * This file gives the xhci stack for usb3.0 looking into
19 * xhci specification Rev1.0 (5/21/10).
20 * The quirk devices support hasn't been given yet.
24 #include <asm/byteorder.h>
28 #include <asm/cache.h>
29 #include <asm/unaligned.h>
30 #include <asm-generic/errno.h>
33 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
37 static struct descriptor {
38 struct usb_hub_descriptor hub;
39 struct usb_device_descriptor device;
40 struct usb_config_descriptor config;
41 struct usb_interface_descriptor interface;
42 struct usb_endpoint_descriptor endpoint;
43 struct usb_ss_ep_comp_descriptor ep_companion;
44 } __attribute__ ((packed)) descriptor = {
46 0xc, /* bDescLength */
47 0x2a, /* bDescriptorType: hub descriptor */
48 2, /* bNrPorts -- runtime modified */
49 cpu_to_le16(0x8), /* wHubCharacteristics */
50 10, /* bPwrOn2PwrGood */
51 0, /* bHubCntrCurrent */
52 {}, /* Device removable */
53 {} /* at most 7 ports! XXX */
57 1, /* bDescriptorType: UDESC_DEVICE */
58 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
59 9, /* bDeviceClass: UDCLASS_HUB */
60 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
61 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
62 9, /* bMaxPacketSize: 512 bytes 2^9 */
63 0x0000, /* idVendor */
64 0x0000, /* idProduct */
65 cpu_to_le16(0x0100), /* bcdDevice */
66 1, /* iManufacturer */
68 0, /* iSerialNumber */
69 1 /* bNumConfigurations: 1 */
73 2, /* bDescriptorType: UDESC_CONFIG */
74 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
75 1, /* bNumInterface */
76 1, /* bConfigurationValue */
77 0, /* iConfiguration */
78 0x40, /* bmAttributes: UC_SELF_POWER */
83 4, /* bDescriptorType: UDESC_INTERFACE */
84 0, /* bInterfaceNumber */
85 0, /* bAlternateSetting */
86 1, /* bNumEndpoints */
87 9, /* bInterfaceClass: UICLASS_HUB */
88 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
89 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
94 5, /* bDescriptorType: UDESC_ENDPOINT */
95 0x81, /* bEndpointAddress: IN endpoint 1 */
96 3, /* bmAttributes: UE_INTERRUPT */
97 8, /* wMaxPacketSize */
101 0x06, /* ss_bLength */
102 0x30, /* ss_bDescriptorType: SS EP Companion */
103 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
104 /* ss_bmAttributes: 1 packet per service interval */
106 /* ss_wBytesPerInterval: 15 bits for max 15 ports */
111 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
113 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
115 return udev->controller;
119 * Waits for as per specified amount of time
120 * for the "result" to match with "done"
122 * @param ptr pointer to the register to be read
123 * @param mask mask for the value read
124 * @param done value to be campared with result
125 * @param usec time to wait till
126 * @return 0 if handshake is success else < 0 on failure
128 static int handshake(uint32_t volatile *ptr, uint32_t mask,
129 uint32_t done, int usec)
134 result = xhci_readl(ptr);
135 if (result == ~(uint32_t)0)
148 * Set the run bit and wait for the host to be running.
150 * @param hcor pointer to host controller operation registers
151 * @return status of the Handshake
153 static int xhci_start(struct xhci_hcor *hcor)
158 puts("Starting the controller\n");
159 temp = xhci_readl(&hcor->or_usbcmd);
161 xhci_writel(&hcor->or_usbcmd, temp);
164 * Wait for the HCHalted Status bit to be 0 to indicate the host is
167 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
169 debug("Host took too long to start, "
170 "waited %u microseconds.\n",
176 * Resets the XHCI Controller
178 * @param hcor pointer to host controller operation registers
179 * @return -EBUSY if XHCI Controller is not halted else status of handshake
181 int xhci_reset(struct xhci_hcor *hcor)
187 /* Halting the Host first */
188 debug("// Halt the HC\n");
189 state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
191 cmd = xhci_readl(&hcor->or_usbcmd);
193 xhci_writel(&hcor->or_usbcmd, cmd);
196 ret = handshake(&hcor->or_usbsts,
197 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
199 printf("Host not halted after %u microseconds.\n",
204 debug("// Reset the HC\n");
205 cmd = xhci_readl(&hcor->or_usbcmd);
207 xhci_writel(&hcor->or_usbcmd, cmd);
209 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
214 * xHCI cannot write to any doorbells or operational registers other
215 * than status until the "Controller Not Ready" flag is cleared.
217 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
221 * Used for passing endpoint bitmasks between the core and HCDs.
222 * Find the index for an endpoint given its descriptor.
223 * Use the return value to right shift 1 for the bitmask.
225 * Index = (epnum * 2) + direction - 1,
226 * where direction = 0 for OUT, 1 for IN.
227 * For control endpoints, the IN index is used (OUT index is unused), so
228 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
230 * @param desc USB enpdoint Descriptor
231 * @return index of the Endpoint
233 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
237 if (usb_endpoint_xfer_control(desc))
238 index = (unsigned int)(usb_endpoint_num(desc) * 2);
240 index = (unsigned int)((usb_endpoint_num(desc) * 2) -
241 (usb_endpoint_dir_in(desc) ? 0 : 1));
247 * Issue a configure endpoint command or evaluate context command
248 * and wait for it to finish.
250 * @param udev pointer to the Device Data Structure
251 * @param ctx_change flag to indicate the Context has changed or NOT
252 * @return 0 on success, -1 on failure
254 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
256 struct xhci_container_ctx *in_ctx;
257 struct xhci_virt_device *virt_dev;
258 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
259 union xhci_trb *event;
261 virt_dev = ctrl->devs[udev->slot_id];
262 in_ctx = virt_dev->in_ctx;
264 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
265 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
266 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
267 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
268 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
271 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
273 debug("Successful %s command\n",
274 ctx_change ? "Evaluate Context" : "Configure Endpoint");
277 printf("ERROR: %s command returned completion code %d.\n",
278 ctx_change ? "Evaluate Context" : "Configure Endpoint",
279 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
283 xhci_acknowledge_event(ctrl);
289 * Configure the endpoint, programming the device contexts.
291 * @param udev pointer to the USB device structure
292 * @return returns the status of the xhci_configure_endpoints
294 static int xhci_set_configuration(struct usb_device *udev)
296 struct xhci_container_ctx *in_ctx;
297 struct xhci_container_ctx *out_ctx;
298 struct xhci_input_control_ctx *ctrl_ctx;
299 struct xhci_slot_ctx *slot_ctx;
300 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
305 unsigned int ep_type;
306 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
310 int slot_id = udev->slot_id;
311 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
312 struct usb_interface *ifdesc;
314 out_ctx = virt_dev->out_ctx;
315 in_ctx = virt_dev->in_ctx;
317 num_of_ep = udev->config.if_desc[0].no_of_ep;
318 ifdesc = &udev->config.if_desc[0];
320 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
321 /* Zero the input context control */
322 ctrl_ctx->add_flags = 0;
323 ctrl_ctx->drop_flags = 0;
325 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
326 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
327 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
328 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
329 if (max_ep_flag < ep_flag)
330 max_ep_flag = ep_flag;
333 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
336 xhci_slot_copy(ctrl, in_ctx, out_ctx);
337 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
338 slot_ctx->dev_info &= ~(LAST_CTX_MASK);
339 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
341 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
343 /* filling up ep contexts */
344 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
345 struct usb_endpoint_descriptor *endpt_desc = NULL;
347 endpt_desc = &ifdesc->ep_desc[cur_ep];
350 ep_index = xhci_get_ep_index(endpt_desc);
351 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
353 /* Allocate the ep rings */
354 virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
355 if (!virt_dev->eps[ep_index].ring)
358 /*NOTE: ep_desc[0] actually represents EP1 and so on */
359 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
360 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
361 ep_ctx[ep_index]->ep_info2 =
362 cpu_to_le32(ep_type << EP_TYPE_SHIFT);
363 ep_ctx[ep_index]->ep_info2 |=
364 cpu_to_le32(MAX_PACKET
365 (get_unaligned(&endpt_desc->wMaxPacketSize)));
367 ep_ctx[ep_index]->ep_info2 |=
368 cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
369 ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
372 virt_dev->eps[ep_index].ring->enqueue;
373 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
374 virt_dev->eps[ep_index].ring->cycle_state);
377 return xhci_configure_endpoints(udev, false);
381 * Issue an Address Device command (which will issue a SetAddress request to
384 * @param udev pointer to the Device Data Structure
385 * @return 0 if successful else error code on failure
387 static int xhci_address_device(struct usb_device *udev)
390 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
391 struct xhci_slot_ctx *slot_ctx;
392 struct xhci_input_control_ctx *ctrl_ctx;
393 struct xhci_virt_device *virt_dev;
394 int slot_id = udev->slot_id;
395 union xhci_trb *event;
397 virt_dev = ctrl->devs[slot_id];
400 * This is the first Set Address since device plug-in
401 * so setting up the slot context.
403 debug("Setting up addressable devices\n");
404 xhci_setup_addressable_virt_dev(udev);
406 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
407 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
408 ctrl_ctx->drop_flags = 0;
410 xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
411 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
412 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
414 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
417 printf("Setup ERROR: address device command for slot %d.\n",
422 puts("Device not responding to set address.\n");
426 puts("ERROR: Incompatible device"
427 "for address device command.\n");
431 debug("Successful Address Device command\n");
435 printf("ERROR: unexpected command completion code 0x%x.\n",
436 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
441 xhci_acknowledge_event(ctrl);
445 * TODO: Unsuccessful Address Device command shall leave the
446 * slot in default state. So, issue Disable Slot command now.
450 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
451 virt_dev->out_ctx->size);
452 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
454 debug("xHC internal address is: %d\n",
455 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
461 * Issue Enable slot command to the controller to allocate
462 * device slot and assign the slot id. It fails if the xHC
463 * ran out of device slots, the Enable Slot command timed out,
464 * or allocating memory failed.
466 * @param udev pointer to the Device Data Structure
467 * @return Returns 0 on succes else return error code on failure
469 int usb_alloc_device(struct usb_device *udev)
471 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
472 union xhci_trb *event;
476 * Root hub will be first device to be initailized.
477 * If this device is root-hub, don't do any xHC related
480 if (ctrl->rootdev == 0) {
481 udev->speed = USB_SPEED_SUPER;
485 xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
486 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
487 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
490 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
492 xhci_acknowledge_event(ctrl);
494 ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
497 * TODO: Unsuccessful Address Device command shall leave
498 * the slot in default. So, issue Disable Slot command now.
500 puts("Could not allocate xHCI USB device data structures\n");
508 * Full speed devices may have a max packet size greater than 8 bytes, but the
509 * USB core doesn't know that until it reads the first 8 bytes of the
510 * descriptor. If the usb_device's max packet size changes after that point,
511 * we need to issue an evaluate context command and wait on it.
513 * @param udev pointer to the Device Data Structure
514 * @return returns the status of the xhci_configure_endpoints
516 int xhci_check_maxpacket(struct usb_device *udev)
518 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
519 unsigned int slot_id = udev->slot_id;
520 int ep_index = 0; /* control endpoint */
521 struct xhci_container_ctx *in_ctx;
522 struct xhci_container_ctx *out_ctx;
523 struct xhci_input_control_ctx *ctrl_ctx;
524 struct xhci_ep_ctx *ep_ctx;
526 int hw_max_packet_size;
528 struct usb_interface *ifdesc;
530 ifdesc = &udev->config.if_desc[0];
532 out_ctx = ctrl->devs[slot_id]->out_ctx;
533 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
535 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
536 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
537 max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]);
538 if (hw_max_packet_size != max_packet_size) {
539 debug("Max Packet Size for ep 0 changed.\n");
540 debug("Max packet size in usb_device = %d\n", max_packet_size);
541 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
542 debug("Issuing evaluate context command.\n");
544 /* Set up the modified control endpoint 0 */
545 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
546 ctrl->devs[slot_id]->out_ctx, ep_index);
547 in_ctx = ctrl->devs[slot_id]->in_ctx;
548 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
549 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
550 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
553 * Set up the input context flags for the command
554 * FIXME: This won't work if a non-default control endpoint
555 * changes max packet sizes.
557 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
558 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
559 ctrl_ctx->drop_flags = 0;
561 ret = xhci_configure_endpoints(udev, true);
567 * Clears the Change bits of the Port Status Register
569 * @param wValue request value
570 * @param wIndex request index
571 * @param addr address of posrt status register
572 * @param port_status state of port status register
575 static void xhci_clear_port_change_bit(u16 wValue,
576 u16 wIndex, volatile uint32_t *addr, u32 port_status)
578 char *port_change_bit;
582 case USB_PORT_FEAT_C_RESET:
584 port_change_bit = "reset";
586 case USB_PORT_FEAT_C_CONNECTION:
588 port_change_bit = "connect";
590 case USB_PORT_FEAT_C_OVER_CURRENT:
592 port_change_bit = "over-current";
594 case USB_PORT_FEAT_C_ENABLE:
596 port_change_bit = "enable/disable";
598 case USB_PORT_FEAT_C_SUSPEND:
600 port_change_bit = "suspend/resume";
603 /* Should never happen */
607 /* Change bits are all write 1 to clear */
608 xhci_writel(addr, port_status | status);
610 port_status = xhci_readl(addr);
611 debug("clear port %s change, actual port %d status = 0x%x\n",
612 port_change_bit, wIndex, port_status);
616 * Save Read Only (RO) bits and save read/write bits where
617 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
618 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
620 * @param state state of the Port Status and Control Regsiter
621 * @return a value that would result in the port being in the
622 * same state, if the value was written to the port
623 * status control register.
625 static u32 xhci_port_state_to_neutral(u32 state)
627 /* Save read-only status and port state */
628 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
632 * Submits the Requests to the XHCI Host Controller
634 * @param udev pointer to the USB device structure
635 * @param pipe contains the DIR_IN or OUT , devnum
636 * @param buffer buffer to be read/written based on the request
637 * @return returns 0 if successful else -1 on failure
639 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
640 void *buffer, struct devrequest *req)
647 volatile uint32_t *status_reg;
648 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
649 struct xhci_hcor *hcor = ctrl->hcor;
651 if ((req->requesttype & USB_RT_PORT) &&
652 le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
653 printf("The request port(%d) is not configured\n",
654 le16_to_cpu(req->index) - 1);
658 status_reg = (volatile uint32_t *)
659 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
662 typeReq = req->request | req->requesttype << 8;
665 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
666 switch (le16_to_cpu(req->value) >> 8) {
668 debug("USB_DT_DEVICE request\n");
669 srcptr = &descriptor.device;
673 debug("USB_DT_CONFIG config\n");
674 srcptr = &descriptor.config;
678 debug("USB_DT_STRING config\n");
679 switch (le16_to_cpu(req->value) & 0xff) {
680 case 0: /* Language */
681 srcptr = "\4\3\11\4";
684 case 1: /* Vendor String */
685 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
688 case 2: /* Product Name */
689 srcptr = "\52\3X\0H\0C\0I\0 "
691 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
695 printf("unknown value DT_STRING %x\n",
696 le16_to_cpu(req->value));
701 printf("unknown value %x\n", le16_to_cpu(req->value));
705 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
706 switch (le16_to_cpu(req->value) >> 8) {
708 debug("USB_DT_HUB config\n");
709 srcptr = &descriptor.hub;
713 printf("unknown value %x\n", le16_to_cpu(req->value));
717 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
718 debug("USB_REQ_SET_ADDRESS\n");
719 ctrl->rootdev = le16_to_cpu(req->value);
721 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
724 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
725 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
730 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
731 memset(tmpbuf, 0, 4);
732 reg = xhci_readl(status_reg);
733 if (reg & PORT_CONNECT) {
734 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
735 switch (reg & DEV_SPEED_MASK) {
737 debug("SPEED = FULLSPEED\n");
740 debug("SPEED = LOWSPEED\n");
741 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
744 debug("SPEED = HIGHSPEED\n");
745 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
748 debug("SPEED = SUPERSPEED\n");
749 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
754 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
755 if ((reg & PORT_PLS_MASK) == XDEV_U3)
756 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
758 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
759 if (reg & PORT_RESET)
760 tmpbuf[0] |= USB_PORT_STAT_RESET;
761 if (reg & PORT_POWER)
763 * XXX: This Port power bit (for USB 3.0 hub)
764 * we are faking in USB 2.0 hub port status;
765 * since there's a change in bit positions in
767 * USB 2.0 port status PP is at position[8]
768 * USB 3.0 port status PP is at position[9]
769 * So, we are still keeping it at position [8]
771 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
773 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
775 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
777 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
779 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
784 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
785 reg = xhci_readl(status_reg);
786 reg = xhci_port_state_to_neutral(reg);
787 switch (le16_to_cpu(req->value)) {
788 case USB_PORT_FEAT_ENABLE:
790 xhci_writel(status_reg, reg);
792 case USB_PORT_FEAT_POWER:
794 xhci_writel(status_reg, reg);
796 case USB_PORT_FEAT_RESET:
798 xhci_writel(status_reg, reg);
801 printf("unknown feature %x\n", le16_to_cpu(req->value));
805 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
806 reg = xhci_readl(status_reg);
807 reg = xhci_port_state_to_neutral(reg);
808 switch (le16_to_cpu(req->value)) {
809 case USB_PORT_FEAT_ENABLE:
812 case USB_PORT_FEAT_POWER:
815 case USB_PORT_FEAT_C_RESET:
816 case USB_PORT_FEAT_C_CONNECTION:
817 case USB_PORT_FEAT_C_OVER_CURRENT:
818 case USB_PORT_FEAT_C_ENABLE:
819 xhci_clear_port_change_bit((le16_to_cpu(req->value)),
820 le16_to_cpu(req->index),
824 printf("unknown feature %x\n", le16_to_cpu(req->value));
827 xhci_writel(status_reg, reg);
830 puts("Unknown request\n");
834 debug("scrlen = %d\n req->length = %d\n",
835 srclen, le16_to_cpu(req->length));
837 len = min(srclen, (int)le16_to_cpu(req->length));
839 if (srcptr != NULL && len > 0)
840 memcpy(buffer, srcptr, len);
851 udev->status = USB_ST_STALLED;
857 * Submits the INT request to XHCI Host cotroller
859 * @param udev pointer to the USB device
860 * @param pipe contains the DIR_IN or OUT , devnum
861 * @param buffer buffer to be read/written based on the request
862 * @param length length of the buffer
863 * @param interval interval of the interrupt
867 submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
868 int length, int interval)
871 * TODO: Not addressing any interrupt type transfer requests
872 * Add support for it later.
878 * submit the BULK type of request to the USB Device
880 * @param udev pointer to the USB device
881 * @param pipe contains the DIR_IN or OUT , devnum
882 * @param buffer buffer to be read/written based on the request
883 * @param length length of the buffer
884 * @return returns 0 if successful else -1 on failure
887 submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
890 if (usb_pipetype(pipe) != PIPE_BULK) {
891 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
895 return xhci_bulk_tx(udev, pipe, length, buffer);
899 * submit the control type of request to the Root hub/Device based on the devnum
901 * @param udev pointer to the USB device
902 * @param pipe contains the DIR_IN or OUT , devnum
903 * @param buffer buffer to be read/written based on the request
904 * @param length length of the buffer
905 * @param setup Request type
906 * @return returns 0 if successful else -1 on failure
909 submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
910 int length, struct devrequest *setup)
912 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
915 if (usb_pipetype(pipe) != PIPE_CONTROL) {
916 printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
920 if (usb_pipedevice(pipe) == ctrl->rootdev)
921 return xhci_submit_root(udev, pipe, buffer, setup);
923 if (setup->request == USB_REQ_SET_ADDRESS)
924 return xhci_address_device(udev);
926 if (setup->request == USB_REQ_SET_CONFIGURATION) {
927 ret = xhci_set_configuration(udev);
929 puts("Failed to configure xHCI endpoint\n");
934 return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
938 * Intialises the XHCI host controller
939 * and allocates the necessary data structures
941 * @param index index to the host controller data structure
942 * @return pointer to the intialised controller
944 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
949 struct xhci_hccr *hccr;
950 struct xhci_hcor *hcor;
951 struct xhci_ctrl *ctrl;
953 if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
956 if (xhci_reset(hcor) != 0)
959 ctrl = &xhcic[index];
965 * Program the Number of Device Slots Enabled field in the CONFIG
966 * register with the max value of slots the HC can handle.
968 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
969 val2 = xhci_readl(&hcor->or_config);
970 val |= (val2 & ~HCS_SLOTS_MASK);
971 xhci_writel(&hcor->or_config, val);
973 /* initializing xhci data structures */
974 if (xhci_mem_init(ctrl, hccr, hcor) < 0)
977 reg = xhci_readl(&hccr->cr_hcsparams1);
978 descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
979 HCS_MAX_PORTS_SHIFT);
980 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
982 /* Port Indicators */
983 reg = xhci_readl(&hccr->cr_hccparams);
984 if (HCS_INDICATOR(reg))
985 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
986 | 0x80, &descriptor.hub.wHubCharacteristics);
988 /* Port Power Control */
990 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
991 | 0x01, &descriptor.hub.wHubCharacteristics);
993 if (xhci_start(hcor)) {
998 /* Zero'ing IRQ control register and IRQ pending register */
999 xhci_writel(&ctrl->ir_set->irq_control, 0x0);
1000 xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
1002 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
1003 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
1005 *controller = &xhcic[index];
1011 * Stops the XHCI host controller
1012 * and cleans up all the related data structures
1014 * @param index index to the host controller data structure
1017 int usb_lowlevel_stop(int index)
1019 struct xhci_ctrl *ctrl = (xhcic + index);
1022 xhci_reset(ctrl->hcor);
1024 debug("// Disabling event ring interrupts\n");
1025 temp = xhci_readl(&ctrl->hcor->or_usbsts);
1026 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1027 temp = xhci_readl(&ctrl->ir_set->irq_pending);
1028 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1030 xhci_hcd_stop(index);