2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29 #include <linux/usb/hcd.h>
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
34 /* xHCI PCI Configuration Registers */
35 #define XHCI_SBRN_OFFSET (0x60)
37 /* Max number of USB devices for any host controller - limit in section 6.1 */
38 #define MAX_HC_SLOTS 256
39 /* Section 5.3.3 - MaxPorts */
40 #define MAX_HC_PORTS 127
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
58 struct xhci_cap_regs {
66 /* Reserved up to (CAPLENGTH - 0x1C) */
69 /* hc_capbase bitmasks */
70 /* bits 7:0 - how long is the Capabilities register */
71 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
75 /* HCSPARAMS1 - hcs_params1 - bitmasks */
76 /* bits 0:7, Max Device Slots */
77 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78 #define HCS_SLOTS_MASK 0xff
79 /* bits 8:18, Max Interrupters */
80 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84 /* HCSPARAMS2 - hcs_params2 - bitmasks */
85 /* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87 #define HCS_IST(p) (((p) >> 0) & 0xf)
88 /* bits 4:7, max number of Event Ring segments */
89 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
92 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94 /* HCSPARAMS3 - hcs_params3 - bitmasks */
95 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
96 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
98 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100 /* HCCPARAMS - hcc_params - bitmasks */
101 /* true: HC can use 64-bit address pointers */
102 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103 /* true: HC can do bandwidth negotiation */
104 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105 /* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
108 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109 /* true: HC has port power switches */
110 #define HCC_PPC(p) ((p) & (1 << 3))
111 /* true: HC has port indicators */
112 #define HCS_INDICATOR(p) ((p) & (1 << 4))
113 /* true: HC has Light HC Reset Capability */
114 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115 /* true: HC supports latency tolerance messaging */
116 #define HCC_LTC(p) ((p) & (1 << 6))
117 /* true: no secondary Stream ID Support */
118 #define HCC_NSS(p) ((p) & (1 << 7))
119 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
120 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
121 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
122 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124 /* db_off bitmask - bits 0:1 reserved */
125 #define DBOFF_MASK (~0x3)
127 /* run_regs_off bitmask - bits 0:4 reserved */
128 #define RTSOFF_MASK (~0x1f)
131 /* Number of registers per port */
132 #define NUM_PORT_REGS 4
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
156 struct xhci_op_regs {
162 u32 dev_notification;
164 /* rsvd: offset 0x20-2F */
168 /* rsvd: offset 0x3C-3FF */
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
175 /* registers for ports 2-255 */
176 u32 reserved6[NUM_PORT_REGS*254];
179 /* USBCMD - USB command - command bitmasks */
180 /* start/stop HC execution - do not write unless HC is halted*/
181 #define CMD_RUN XHCI_CMD_RUN
182 /* Reset HC - resets internal HC state machine and all registers (except
183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
184 * The xHCI driver must reinitialize the xHC after setting this bit.
186 #define CMD_RESET (1 << 1)
187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188 #define CMD_EIE XHCI_CMD_EIE
189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
190 #define CMD_HSEIE XHCI_CMD_HSEIE
191 /* bits 4:6 are reserved (and should be preserved on writes). */
192 /* light reset (port status stays unchanged) - reset completed when this is 0 */
193 #define CMD_LRESET (1 << 7)
194 /* host controller save/restore state. */
195 #define CMD_CSS (1 << 8)
196 #define CMD_CRS (1 << 9)
197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198 #define CMD_EWE XHCI_CMD_EWE
199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * '0' means the xHC can power it off if all ports are in the disconnect,
202 * disabled, or powered-off state.
204 #define CMD_PM_INDEX (1 << 11)
205 /* bits 12:31 are reserved (and should be preserved on writes). */
207 /* USBSTS - USB status - status bitmasks */
208 /* HC not running - set to 1 when run/stop bit is cleared. */
209 #define STS_HALT XHCI_STS_HALT
210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
211 #define STS_FATAL (1 << 2)
212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
213 #define STS_EINT (1 << 3)
214 /* port change detect */
215 #define STS_PORT (1 << 4)
216 /* bits 5:7 reserved and zeroed */
217 /* save state status - '1' means xHC is saving state */
218 #define STS_SAVE (1 << 8)
219 /* restore state status - '1' means xHC is restoring state */
220 #define STS_RESTORE (1 << 9)
221 /* true: save or restore error */
222 #define STS_SRE (1 << 10)
223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
224 #define STS_CNR XHCI_STS_CNR
225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
226 #define STS_HCE (1 << 12)
227 /* bits 13:31 reserved and should be preserved */
230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
231 * Generate a device notification event when the HC sees a transaction with a
232 * notification type that matches a bit set in this bit field.
234 #define DEV_NOTE_MASK (0xffff)
235 #define ENABLE_DEV_NOTE(x) (1 << x)
236 /* Most of the device notification types should only be used for debug.
237 * SW does need to pay attention to function wake notifications.
239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
242 /* bit 0 is the command ring cycle state */
243 /* stop ring operation after completion of the currently executing command */
244 #define CMD_RING_PAUSE (1 << 1)
245 /* stop ring immediately - abort the currently executing command */
246 #define CMD_RING_ABORT (1 << 2)
247 /* true: command ring is running */
248 #define CMD_RING_RUNNING (1 << 3)
249 /* bits 4:5 reserved and should be preserved */
250 /* Command Ring pointer - bit mask for the lower 32 bits. */
251 #define CMD_RING_RSVD_BITS (0x3f)
253 /* CONFIG - Configure Register - config_reg bitmasks */
254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255 #define MAX_DEVS(p) ((p) & 0xff)
256 /* bits 8:31 - reserved and should be preserved */
258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
259 /* true: device connected */
260 #define PORT_CONNECT (1 << 0)
261 /* true: port enabled */
262 #define PORT_PE (1 << 1)
263 /* bit 2 reserved and zeroed */
264 /* true: port has an over-current condition */
265 #define PORT_OC (1 << 3)
266 /* true: port reset signaling asserted */
267 #define PORT_RESET (1 << 4)
268 /* Port Link State - bits 5:8
269 * A read gives the current link PM state of the port,
270 * a write with Link State Write Strobe set sets the link state.
272 #define PORT_PLS_MASK (0xf << 5)
273 #define XDEV_U0 (0x0 << 5)
274 #define XDEV_U3 (0x3 << 5)
275 #define XDEV_RESUME (0xf << 5)
276 /* true: port has power (see HCC_PPC) */
277 #define PORT_POWER (1 << 9)
278 /* bits 10:13 indicate device speed:
279 * 0 - undefined speed - port hasn't be initialized by a reset yet
286 #define DEV_SPEED_MASK (0xf << 10)
287 #define XDEV_FS (0x1 << 10)
288 #define XDEV_LS (0x2 << 10)
289 #define XDEV_HS (0x3 << 10)
290 #define XDEV_SS (0x4 << 10)
291 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
292 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
293 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
294 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
295 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
296 /* Bits 20:23 in the Slot Context are the speed for the device */
297 #define SLOT_SPEED_FS (XDEV_FS << 10)
298 #define SLOT_SPEED_LS (XDEV_LS << 10)
299 #define SLOT_SPEED_HS (XDEV_HS << 10)
300 #define SLOT_SPEED_SS (XDEV_SS << 10)
301 /* Port Indicator Control */
302 #define PORT_LED_OFF (0 << 14)
303 #define PORT_LED_AMBER (1 << 14)
304 #define PORT_LED_GREEN (2 << 14)
305 #define PORT_LED_MASK (3 << 14)
306 /* Port Link State Write Strobe - set this when changing link state */
307 #define PORT_LINK_STROBE (1 << 16)
308 /* true: connect status change */
309 #define PORT_CSC (1 << 17)
310 /* true: port enable change */
311 #define PORT_PEC (1 << 18)
312 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
313 * into an enabled state, and the device into the default state. A "warm" reset
314 * also resets the link, forcing the device through the link training sequence.
315 * SW can also look at the Port Reset register to see when warm reset is done.
317 #define PORT_WRC (1 << 19)
318 /* true: over-current change */
319 #define PORT_OCC (1 << 20)
320 /* true: reset change - 1 to 0 transition of PORT_RESET */
321 #define PORT_RC (1 << 21)
322 /* port link status change - set on some port link state transitions:
324 * ------------------------------------------------------------------------------
325 * - U3 to Resume Wakeup signaling from a device
326 * - Resume to Recovery to U0 USB 3.0 device resume
327 * - Resume to U0 USB 2.0 device resume
328 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
329 * - U3 to U0 Software resume of USB 2.0 device complete
330 * - U2 to U0 L1 resume of USB 2.1 device complete
331 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
332 * - U0 to disabled L1 entry error with USB 2.1 device
333 * - Any state to inactive Error on USB 3.0 port
335 #define PORT_PLC (1 << 22)
336 /* port configure error change - port failed to configure its link partner */
337 #define PORT_CEC (1 << 23)
338 /* bit 24 reserved */
339 /* wake on connect (enable) */
340 #define PORT_WKCONN_E (1 << 25)
341 /* wake on disconnect (enable) */
342 #define PORT_WKDISC_E (1 << 26)
343 /* wake on over-current (enable) */
344 #define PORT_WKOC_E (1 << 27)
345 /* bits 28:29 reserved */
346 /* true: device is removable - for USB 3.0 roothub emulation */
347 #define PORT_DEV_REMOVE (1 << 30)
348 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
349 #define PORT_WR (1 << 31)
351 /* Port Power Management Status and Control - port_power_base bitmasks */
352 /* Inactivity timer value for transitions into U1, in microseconds.
353 * Timeout can be up to 127us. 0xFF means an infinite timeout.
355 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
356 /* Inactivity timer value for transitions into U2 */
357 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
358 /* Bits 24:31 for port testing */
360 /* USB2 Protocol PORTSPMSC */
361 #define PORT_RWE (1 << 0x3)
364 * struct xhci_intr_reg - Interrupt Register Set
365 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
366 * interrupts and check for pending interrupts.
367 * @irq_control: IMOD - Interrupt Moderation Register.
368 * Used to throttle interrupts.
369 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
370 * @erst_base: ERST base address.
371 * @erst_dequeue: Event ring dequeue pointer.
373 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
374 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
375 * multiple segments of the same size. The HC places events on the ring and
376 * "updates the Cycle bit in the TRBs to indicate to software the current
377 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
378 * updates the dequeue pointer.
380 struct xhci_intr_reg {
389 /* irq_pending bitmasks */
390 #define ER_IRQ_PENDING(p) ((p) & 0x1)
391 /* bits 2:31 need to be preserved */
392 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
393 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
394 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
395 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
397 /* irq_control bitmasks */
398 /* Minimum interval between interrupts (in 250ns intervals). The interval
399 * between interrupts will be longer if there are no events on the event ring.
400 * Default is 4000 (1 ms).
402 #define ER_IRQ_INTERVAL_MASK (0xffff)
403 /* Counter used to count down the time to the next interrupt - HW use only */
404 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
406 /* erst_size bitmasks */
407 /* Preserve bits 16:31 of erst_size */
408 #define ERST_SIZE_MASK (0xffff << 16)
410 /* erst_dequeue bitmasks */
411 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
412 * where the current dequeue pointer lies. This is an optional HW hint.
414 #define ERST_DESI_MASK (0x7)
415 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
416 * a work queue (or delayed service routine)?
418 #define ERST_EHB (1 << 3)
419 #define ERST_PTR_MASK (0xf)
422 * struct xhci_run_regs
424 * MFINDEX - current microframe number
426 * Section 5.5 Host Controller Runtime Registers:
427 * "Software should read and write these registers using only Dword (32 bit)
428 * or larger accesses"
430 struct xhci_run_regs {
431 u32 microframe_index;
433 struct xhci_intr_reg ir_set[128];
437 * struct doorbell_array
441 struct xhci_doorbell_array {
445 #define DB_TARGET_MASK 0xFFFFFF00
446 #define DB_STREAM_ID_MASK 0x0000FFFF
447 #define DB_TARGET_HOST 0x0
448 #define DB_STREAM_ID_HOST 0x0
449 #define DB_MASK (0xff << 8)
451 /* Endpoint Target - bits 0:7 */
452 #define EPI_TO_DB(p) (((p) + 1) & 0xff)
453 #define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16)
457 * struct xhci_container_ctx
458 * @type: Type of context. Used to calculated offsets to contained contexts.
459 * @size: Size of the context data
460 * @bytes: The raw context data given to HW
461 * @dma: dma address of the bytes
463 * Represents either a Device or Input context. Holds a pointer to the raw
464 * memory used for the context (bytes) and dma address of it (dma).
466 struct xhci_container_ctx {
468 #define XHCI_CTX_TYPE_DEVICE 0x1
469 #define XHCI_CTX_TYPE_INPUT 0x2
478 * struct xhci_slot_ctx
479 * @dev_info: Route string, device speed, hub info, and last valid endpoint
480 * @dev_info2: Max exit latency for device number, root hub port number
481 * @tt_info: tt_info is used to construct split transaction tokens
482 * @dev_state: slot state and device address
484 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
485 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
486 * reserved at the end of the slot context for HC internal use.
488 struct xhci_slot_ctx {
493 /* offset 0x10 to 0x1f reserved for HC internal use */
497 /* dev_info bitmasks */
498 /* Route String - 0:19 */
499 #define ROUTE_STRING_MASK (0xfffff)
500 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
501 #define DEV_SPEED (0xf << 20)
502 /* bit 24 reserved */
503 /* Is this LS/FS device connected through a HS hub? - bit 25 */
504 #define DEV_MTT (0x1 << 25)
505 /* Set if the device is a hub - bit 26 */
506 #define DEV_HUB (0x1 << 26)
507 /* Index of the last valid endpoint context in this device context - 27:31 */
508 #define LAST_CTX_MASK (0x1f << 27)
509 #define LAST_CTX(p) ((p) << 27)
510 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
511 #define SLOT_FLAG (1 << 0)
512 #define EP0_FLAG (1 << 1)
514 /* dev_info2 bitmasks */
515 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
516 #define MAX_EXIT (0xffff)
517 /* Root hub port number that is needed to access the USB device */
518 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
519 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
520 /* Maximum number of ports under a hub device */
521 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
523 /* tt_info bitmasks */
525 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
526 * The Slot ID of the hub that isolates the high speed signaling from
527 * this low or full-speed device. '0' if attached to root hub port.
529 #define TT_SLOT (0xff)
531 * The number of the downstream facing port of the high-speed hub
532 * '0' if the device is not low or full speed.
534 #define TT_PORT (0xff << 8)
535 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
537 /* dev_state bitmasks */
538 /* USB device address - assigned by the HC */
539 #define DEV_ADDR_MASK (0xff)
540 /* bits 8:26 reserved */
542 #define SLOT_STATE (0x1f << 27)
543 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
548 * @ep_info: endpoint state, streams, mult, and interval information.
549 * @ep_info2: information on endpoint type, max packet size, max burst size,
550 * error count, and whether the HC will force an event for all
552 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
553 * defines one stream, this points to the endpoint transfer ring.
554 * Otherwise, it points to a stream context array, which has a
555 * ring pointer for each flow.
557 * Average TRB lengths for the endpoint ring and
558 * max payload within an Endpoint Service Interval Time (ESIT).
560 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
561 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
562 * reserved at the end of the endpoint context for HC internal use.
569 /* offset 0x14 - 0x1f reserved for HC internal use */
573 /* ep_info bitmasks */
575 * Endpoint State - bits 0:2
578 * 2 - halted due to halt condition - ok to manipulate endpoint ring
583 #define EP_STATE_MASK (0xf)
584 #define EP_STATE_DISABLED 0
585 #define EP_STATE_RUNNING 1
586 #define EP_STATE_HALTED 2
587 #define EP_STATE_STOPPED 3
588 #define EP_STATE_ERROR 4
589 /* Mult - Max number of burtst within an interval, in EP companion desc. */
590 #define EP_MULT(p) ((p & 0x3) << 8)
591 /* bits 10:14 are Max Primary Streams */
592 /* bit 15 is Linear Stream Array */
593 /* Interval - period between requests to an endpoint - 125u increments. */
594 #define EP_INTERVAL(p) ((p & 0xff) << 16)
595 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
596 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
597 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
598 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
599 #define EP_HAS_LSA (1 << 15)
601 /* ep_info2 bitmasks */
603 * Force Event - generate transfer events for all TRBs for this endpoint
604 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
606 #define FORCE_EVENT (0x1)
607 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
608 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
609 #define EP_TYPE(p) ((p) << 3)
610 #define ISOC_OUT_EP 1
611 #define BULK_OUT_EP 2
618 /* bit 7 is Host Initiate Disable - for disabling stream selection */
619 #define MAX_BURST(p) (((p)&0xff) << 8)
620 #define MAX_PACKET(p) (((p)&0xffff) << 16)
621 #define MAX_PACKET_MASK (0xffff << 16)
622 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
624 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
627 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
629 /* tx_info bitmasks */
630 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
631 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
635 * struct xhci_input_control_context
636 * Input control context; see section 6.2.5.
638 * @drop_context: set the bit of the endpoint context you want to disable
639 * @add_context: set the bit of the endpoint context you want to enable
641 struct xhci_input_control_ctx {
647 /* Represents everything that is needed to issue a command on the command ring.
648 * It's useful to pre-allocate these for commands that cannot fail due to
649 * out-of-memory errors, like freeing streams.
651 struct xhci_command {
652 /* Input context for changing device state */
653 struct xhci_container_ctx *in_ctx;
655 /* If completion is null, no one is waiting on this command
656 * and the structure can be freed after the command completes.
658 struct completion *completion;
659 union xhci_trb *command_trb;
660 struct list_head cmd_list;
663 /* drop context bitmasks */
664 #define DROP_EP(x) (0x1 << x)
665 /* add context bitmasks */
666 #define ADD_EP(x) (0x1 << x)
668 struct xhci_stream_ctx {
669 /* 64-bit stream ring address, cycle state, and stream type */
671 /* offset 0x14 - 0x1f reserved for HC internal use */
675 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
676 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
677 /* Secondary stream array type, dequeue pointer is to a transfer ring */
679 /* Primary stream array type, dequeue pointer is to a transfer ring */
681 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
686 #define SCT_SSA_128 6
687 #define SCT_SSA_256 7
689 /* Assume no secondary streams for now */
690 struct xhci_stream_info {
691 struct xhci_ring **stream_rings;
692 /* Number of streams, including stream 0 (which drivers can't use) */
693 unsigned int num_streams;
694 /* The stream context array may be bigger than
695 * the number of streams the driver asked for
697 struct xhci_stream_ctx *stream_ctx_array;
698 unsigned int num_stream_ctxs;
699 dma_addr_t ctx_array_dma;
700 /* For mapping physical TRB addresses to segments in stream rings */
701 struct radix_tree_root trb_address_map;
702 struct xhci_command *free_streams_command;
705 #define SMALL_STREAM_ARRAY_SIZE 256
706 #define MEDIUM_STREAM_ARRAY_SIZE 1024
708 struct xhci_virt_ep {
709 struct xhci_ring *ring;
710 /* Related to endpoints that are configured to use stream IDs only */
711 struct xhci_stream_info *stream_info;
712 /* Temporary storage in case the configure endpoint command fails and we
713 * have to restore the device state to the previous state
715 struct xhci_ring *new_ring;
716 unsigned int ep_state;
717 #define SET_DEQ_PENDING (1 << 0)
718 #define EP_HALTED (1 << 1) /* For stall handling */
719 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
720 /* Transitioning the endpoint to using streams, don't enqueue URBs */
721 #define EP_GETTING_STREAMS (1 << 3)
722 #define EP_HAS_STREAMS (1 << 4)
723 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
724 #define EP_GETTING_NO_STREAMS (1 << 5)
725 /* ---- Related to URB cancellation ---- */
726 struct list_head cancelled_td_list;
727 /* The TRB that was last reported in a stopped endpoint ring */
728 union xhci_trb *stopped_trb;
729 struct xhci_td *stopped_td;
730 unsigned int stopped_stream;
731 /* Watchdog timer for stop endpoint command to cancel URBs */
732 struct timer_list stop_cmd_timer;
733 int stop_cmds_pending;
734 struct xhci_hcd *xhci;
736 * Sometimes the xHC can not process isochronous endpoint ring quickly
737 * enough, and it will miss some isoc tds on the ring and generate
738 * a Missed Service Error Event.
739 * Set skip flag when receive a Missed Service Error Event and
740 * process the missed tds on the endpoint ring.
745 struct xhci_virt_device {
746 struct usb_device *udev;
748 * Commands to the hardware are passed an "input context" that
749 * tells the hardware what to change in its data structures.
750 * The hardware will return changes in an "output context" that
751 * software must allocate for the hardware. We need to keep
752 * track of input and output contexts separately because
753 * these commands might fail and we don't trust the hardware.
755 struct xhci_container_ctx *out_ctx;
756 /* Used for addressing devices and configuration changes */
757 struct xhci_container_ctx *in_ctx;
758 /* Rings saved to ensure old alt settings can be re-instated */
759 struct xhci_ring **ring_cache;
760 int num_rings_cached;
761 /* Store xHC assigned device address */
763 #define XHCI_MAX_RINGS_CACHED 31
764 struct xhci_virt_ep eps[31];
765 struct completion cmd_completion;
766 /* Status of the last command issued for this device */
768 struct list_head cmd_list;
774 * struct xhci_device_context_array
775 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
777 struct xhci_device_context_array {
778 /* 64-bit device addresses; we only write 32-bit addresses */
779 u64 dev_context_ptrs[MAX_HC_SLOTS];
780 /* private xHCD pointers */
783 /* TODO: write function to set the 64-bit device DMA address */
785 * TODO: change this to be dynamically sized at HC mem init time since the HC
786 * might not be able to handle the maximum number of devices possible.
790 struct xhci_transfer_event {
791 /* 64-bit buffer address, or immediate data */
794 /* This field is interpreted differently based on the type of TRB */
798 /** Transfer Event bit fields **/
799 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
801 /* Completion Code - only applicable for some types of TRBs */
802 #define COMP_CODE_MASK (0xff << 24)
803 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
804 #define COMP_SUCCESS 1
805 /* Data Buffer Error */
806 #define COMP_DB_ERR 2
807 /* Babble Detected Error */
808 #define COMP_BABBLE 3
809 /* USB Transaction Error */
810 #define COMP_TX_ERR 4
811 /* TRB Error - some TRB field is invalid */
812 #define COMP_TRB_ERR 5
813 /* Stall Error - USB device is stalled */
815 /* Resource Error - HC doesn't have memory for that device configuration */
816 #define COMP_ENOMEM 7
817 /* Bandwidth Error - not enough room in schedule for this dev config */
818 #define COMP_BW_ERR 8
819 /* No Slots Available Error - HC ran out of device slots */
820 #define COMP_ENOSLOTS 9
821 /* Invalid Stream Type Error */
822 #define COMP_STREAM_ERR 10
823 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
824 #define COMP_EBADSLT 11
825 /* Endpoint Not Enabled Error */
826 #define COMP_EBADEP 12
828 #define COMP_SHORT_TX 13
829 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
830 #define COMP_UNDERRUN 14
831 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
832 #define COMP_OVERRUN 15
833 /* Virtual Function Event Ring Full Error */
834 #define COMP_VF_FULL 16
835 /* Parameter Error - Context parameter is invalid */
836 #define COMP_EINVAL 17
837 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
838 #define COMP_BW_OVER 18
839 /* Context State Error - illegal context state transition requested */
840 #define COMP_CTX_STATE 19
841 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
842 #define COMP_PING_ERR 20
843 /* Event Ring is full */
844 #define COMP_ER_FULL 21
845 /* Missed Service Error - HC couldn't service an isoc ep within interval */
846 #define COMP_MISSED_INT 23
847 /* Successfully stopped command ring */
848 #define COMP_CMD_STOP 24
849 /* Successfully aborted current command and stopped command ring */
850 #define COMP_CMD_ABORT 25
851 /* Stopped - transfer was terminated by a stop endpoint command */
853 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
854 #define COMP_STOP_INVAL 27
855 /* Control Abort Error - Debug Capability - control pipe aborted */
856 #define COMP_DBG_ABORT 28
857 /* TRB type 29 and 30 reserved */
858 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
859 #define COMP_BUFF_OVER 31
860 /* Event Lost Error - xHC has an "internal event overrun condition" */
861 #define COMP_ISSUES 32
862 /* Undefined Error - reported when other error codes don't apply */
863 #define COMP_UNKNOWN 33
864 /* Invalid Stream ID Error */
865 #define COMP_STRID_ERR 34
866 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
867 /* FIXME - check for this */
868 #define COMP_2ND_BW_ERR 35
869 /* Split Transaction Error */
870 #define COMP_SPLIT_ERR 36
872 struct xhci_link_trb {
873 /* 64-bit segment pointer*/
879 /* control bitfields */
880 #define LINK_TOGGLE (0x1<<1)
882 /* Command completion event TRB */
883 struct xhci_event_cmd {
884 /* Pointer to command TRB, or the value passed by the event data trb */
891 /* bits 16:23 are the virtual function ID */
892 /* bits 24:31 are the slot ID */
893 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
894 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
896 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
897 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
898 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
900 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
901 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
902 #define LAST_EP_INDEX 30
904 /* Set TR Dequeue Pointer command TRB fields */
905 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
906 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
909 /* Port Status Change Event TRB fields */
910 /* Port ID - bits 31:24 */
911 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
913 /* Normal TRB fields */
914 /* transfer_len bitmasks - bits 0:16 */
915 #define TRB_LEN(p) ((p) & 0x1ffff)
916 /* Interrupter Target - which MSI-X vector to target the completion event at */
917 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
918 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
920 /* Cycle bit - indicates TRB ownership by HC or HCD */
921 #define TRB_CYCLE (1<<0)
923 * Force next event data TRB to be evaluated before task switch.
924 * Used to pass OS data back after a TD completes.
926 #define TRB_ENT (1<<1)
927 /* Interrupt on short packet */
928 #define TRB_ISP (1<<2)
929 /* Set PCIe no snoop attribute */
930 #define TRB_NO_SNOOP (1<<3)
931 /* Chain multiple TRBs into a TD */
932 #define TRB_CHAIN (1<<4)
933 /* Interrupt on completion */
934 #define TRB_IOC (1<<5)
935 /* The buffer pointer contains immediate data */
936 #define TRB_IDT (1<<6)
939 /* Control transfer TRB specific fields */
940 #define TRB_DIR_IN (1<<16)
942 /* Isochronous TRB specific fields */
943 #define TRB_SIA (1<<31)
945 struct xhci_generic_trb {
950 struct xhci_link_trb link;
951 struct xhci_transfer_event trans_event;
952 struct xhci_event_cmd event_cmd;
953 struct xhci_generic_trb generic;
957 #define TRB_TYPE_BITMASK (0xfc00)
958 #define TRB_TYPE(p) ((p) << 10)
959 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
961 /* bulk, interrupt, isoc scatter/gather, and control data stage */
963 /* setup stage for control transfers */
965 /* data stage for control transfers */
967 /* status stage for control transfers */
971 /* TRB for linking ring segments */
973 #define TRB_EVENT_DATA 7
974 /* Transfer Ring No-op (not for the command ring) */
975 #define TRB_TR_NOOP 8
977 /* Enable Slot Command */
978 #define TRB_ENABLE_SLOT 9
979 /* Disable Slot Command */
980 #define TRB_DISABLE_SLOT 10
981 /* Address Device Command */
982 #define TRB_ADDR_DEV 11
983 /* Configure Endpoint Command */
984 #define TRB_CONFIG_EP 12
985 /* Evaluate Context Command */
986 #define TRB_EVAL_CONTEXT 13
987 /* Reset Endpoint Command */
988 #define TRB_RESET_EP 14
989 /* Stop Transfer Ring Command */
990 #define TRB_STOP_RING 15
991 /* Set Transfer Ring Dequeue Pointer Command */
992 #define TRB_SET_DEQ 16
993 /* Reset Device Command */
994 #define TRB_RESET_DEV 17
995 /* Force Event Command (opt) */
996 #define TRB_FORCE_EVENT 18
997 /* Negotiate Bandwidth Command (opt) */
998 #define TRB_NEG_BANDWIDTH 19
999 /* Set Latency Tolerance Value Command (opt) */
1000 #define TRB_SET_LT 20
1001 /* Get port bandwidth Command */
1002 #define TRB_GET_BW 21
1003 /* Force Header Command - generate a transaction or link management packet */
1004 #define TRB_FORCE_HEADER 22
1005 /* No-op Command - not for transfer rings */
1006 #define TRB_CMD_NOOP 23
1007 /* TRB IDs 24-31 reserved */
1009 /* Transfer Event */
1010 #define TRB_TRANSFER 32
1011 /* Command Completion Event */
1012 #define TRB_COMPLETION 33
1013 /* Port Status Change Event */
1014 #define TRB_PORT_STATUS 34
1015 /* Bandwidth Request Event (opt) */
1016 #define TRB_BANDWIDTH_EVENT 35
1017 /* Doorbell Event (opt) */
1018 #define TRB_DOORBELL 36
1019 /* Host Controller Event */
1020 #define TRB_HC_EVENT 37
1021 /* Device Notification Event - device sent function wake notification */
1022 #define TRB_DEV_NOTE 38
1023 /* MFINDEX Wrap Event - microframe counter wrapped */
1024 #define TRB_MFINDEX_WRAP 39
1025 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1027 /* Nec vendor-specific command completion event. */
1028 #define TRB_NEC_CMD_COMP 48
1029 /* Get NEC firmware revision. */
1030 #define TRB_NEC_GET_FW 49
1032 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1033 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1036 * TRBS_PER_SEGMENT must be a multiple of 4,
1037 * since the command ring is 64-byte aligned.
1038 * It must also be greater than 16.
1040 #define TRBS_PER_SEGMENT 64
1041 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1042 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1043 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1044 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1045 * Change this if you change TRBS_PER_SEGMENT!
1047 #define SEGMENT_SHIFT 10
1048 /* TRB buffer pointers can't cross 64KB boundaries */
1049 #define TRB_MAX_BUFF_SHIFT 16
1050 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1052 struct xhci_segment {
1053 union xhci_trb *trbs;
1054 /* private to HCD */
1055 struct xhci_segment *next;
1060 struct list_head td_list;
1061 struct list_head cancelled_td_list;
1063 struct xhci_segment *start_seg;
1064 union xhci_trb *first_trb;
1065 union xhci_trb *last_trb;
1068 struct xhci_dequeue_state {
1069 struct xhci_segment *new_deq_seg;
1070 union xhci_trb *new_deq_ptr;
1071 int new_cycle_state;
1075 struct xhci_segment *first_seg;
1076 union xhci_trb *enqueue;
1077 struct xhci_segment *enq_seg;
1078 unsigned int enq_updates;
1079 union xhci_trb *dequeue;
1080 struct xhci_segment *deq_seg;
1081 unsigned int deq_updates;
1082 struct list_head td_list;
1084 * Write the cycle state into the TRB cycle field to give ownership of
1085 * the TRB to the host controller (if we are the producer), or to check
1086 * if we own the TRB (if we are the consumer). See section 4.9.1.
1089 unsigned int stream_id;
1092 struct xhci_erst_entry {
1093 /* 64-bit event ring segment address */
1101 struct xhci_erst_entry *entries;
1102 unsigned int num_entries;
1103 /* xhci->event_ring keeps track of segment dma addresses */
1104 dma_addr_t erst_dma_addr;
1105 /* Num entries the ERST can contain */
1106 unsigned int erst_size;
1109 struct xhci_scratchpad {
1113 dma_addr_t *sp_dma_buffers;
1119 struct xhci_td *td[0];
1123 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1124 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1125 * meaning 64 ring segments.
1126 * Initial allocated size of the ERST, in number of entries */
1127 #define ERST_NUM_SEGS 1
1128 /* Initial allocated size of the ERST, in number of entries */
1129 #define ERST_SIZE 64
1130 /* Initial number of event segment rings allocated */
1131 #define ERST_ENTRIES 1
1132 /* Poll every 60 seconds */
1133 #define POLL_TIMEOUT 60
1134 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1135 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1136 /* XXX: Make these module parameters */
1150 /* There is one ehci_hci structure per controller */
1152 /* glue to PCI and HCD framework */
1153 struct xhci_cap_regs __iomem *cap_regs;
1154 struct xhci_op_regs __iomem *op_regs;
1155 struct xhci_run_regs __iomem *run_regs;
1156 struct xhci_doorbell_array __iomem *dba;
1157 /* Our HCD's current interrupter register set */
1158 struct xhci_intr_reg __iomem *ir_set;
1160 /* Cached register copies of read-only HC data */
1168 /* packed release number */
1172 u8 max_interrupters;
1177 /* 4KB min, 128MB max */
1179 /* Valid values are 12 to 20, inclusive */
1183 struct msix_entry *msix_entries;
1184 /* data structures */
1185 struct xhci_device_context_array *dcbaa;
1186 struct xhci_ring *cmd_ring;
1187 unsigned int cmd_ring_reserved_trbs;
1188 struct xhci_ring *event_ring;
1189 struct xhci_erst erst;
1191 struct xhci_scratchpad *scratchpad;
1193 /* slot enabling and address device helpers */
1194 struct completion addr_dev;
1196 /* Internal mirror of the HW's dcbaa */
1197 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1200 struct dma_pool *device_pool;
1201 struct dma_pool *segment_pool;
1202 struct dma_pool *small_streams_pool;
1203 struct dma_pool *medium_streams_pool;
1205 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1206 /* Poll the rings - for debugging */
1207 struct timer_list event_ring_timer;
1210 /* Host controller watchdog timer structures */
1211 unsigned int xhc_state;
1213 unsigned long bus_suspended;
1214 unsigned long next_statechange;
1218 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1220 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1221 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1222 * that sees this status (other than the timer that set it) should stop touching
1223 * hardware immediately. Interrupt handlers should return immediately when
1224 * they see this status (any time they drop and re-acquire xhci->lock).
1225 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1226 * putting the TD on the canceled list, etc.
1228 * There are no reports of xHCI host controllers that display this issue.
1230 #define XHCI_STATE_DYING (1 << 0)
1232 int noops_submitted;
1235 unsigned int quirks;
1236 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1237 #define XHCI_RESET_EP_QUIRK (1 << 1)
1238 #define XHCI_NEC_HOST (1 << 2)
1239 u32 port_c_suspend[8]; /* port suspend change*/
1240 u32 suspended_ports[8]; /* which ports are
1242 unsigned long resume_done[MAX_HC_PORTS];
1245 /* For testing purposes */
1246 #define NUM_TEST_NOOPS 0
1248 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1249 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1251 return (struct xhci_hcd *) (hcd->hcd_priv);
1254 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1256 return container_of((void *) xhci, struct usb_hcd, hcd_priv);
1259 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1260 #define XHCI_DEBUG 1
1262 #define XHCI_DEBUG 0
1265 #define xhci_dbg(xhci, fmt, args...) \
1266 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1267 #define xhci_info(xhci, fmt, args...) \
1268 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1269 #define xhci_err(xhci, fmt, args...) \
1270 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1271 #define xhci_warn(xhci, fmt, args...) \
1272 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1274 /* TODO: copied from ehci.h - can be refactored? */
1275 /* xHCI spec says all registers are little endian */
1276 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1277 __u32 __iomem *regs)
1281 static inline void xhci_writel(struct xhci_hcd *xhci,
1282 const unsigned int val, __u32 __iomem *regs)
1285 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1291 * Registers should always be accessed with double word or quad word accesses.
1293 * Some xHCI implementations may support 64-bit address pointers. Registers
1294 * with 64-bit address pointers should be written to with dword accesses by
1295 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1296 * xHCI implementations that do not support 64-bit address pointers will ignore
1297 * the high dword, and write order is irrelevant.
1299 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1300 __u64 __iomem *regs)
1302 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1303 u64 val_lo = readl(ptr);
1304 u64 val_hi = readl(ptr + 1);
1305 return val_lo + (val_hi << 32);
1307 static inline void xhci_write_64(struct xhci_hcd *xhci,
1308 const u64 val, __u64 __iomem *regs)
1310 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1311 u32 val_lo = lower_32_bits(val);
1312 u32 val_hi = upper_32_bits(val);
1315 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1316 regs, (long unsigned int) val);
1317 writel(val_lo, ptr);
1318 writel(val_hi, ptr + 1);
1321 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1323 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1324 return ((HC_VERSION(temp) == 0x95) &&
1325 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1328 /* xHCI debugging */
1329 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
1330 void xhci_print_registers(struct xhci_hcd *xhci);
1331 void xhci_dbg_regs(struct xhci_hcd *xhci);
1332 void xhci_print_run_regs(struct xhci_hcd *xhci);
1333 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1334 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1335 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1336 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1337 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1338 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1339 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1340 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1341 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1342 struct xhci_container_ctx *ctx);
1343 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1344 unsigned int slot_id, unsigned int ep_index,
1345 struct xhci_virt_ep *ep);
1347 /* xHCI memory management */
1348 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1349 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1350 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1351 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1352 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1353 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1354 struct usb_device *udev);
1355 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1356 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1357 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1358 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1359 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1360 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1361 struct xhci_container_ctx *in_ctx,
1362 struct xhci_container_ctx *out_ctx,
1363 unsigned int ep_index);
1364 void xhci_slot_copy(struct xhci_hcd *xhci,
1365 struct xhci_container_ctx *in_ctx,
1366 struct xhci_container_ctx *out_ctx);
1367 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1368 struct usb_device *udev, struct usb_host_endpoint *ep,
1370 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1371 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1372 struct xhci_virt_device *virt_dev,
1373 unsigned int ep_index);
1374 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1375 unsigned int num_stream_ctxs,
1376 unsigned int num_streams, gfp_t flags);
1377 void xhci_free_stream_info(struct xhci_hcd *xhci,
1378 struct xhci_stream_info *stream_info);
1379 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1380 struct xhci_ep_ctx *ep_ctx,
1381 struct xhci_stream_info *stream_info);
1382 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1383 struct xhci_ep_ctx *ep_ctx,
1384 struct xhci_virt_ep *ep);
1385 struct xhci_ring *xhci_dma_to_transfer_ring(
1386 struct xhci_virt_ep *ep,
1388 struct xhci_ring *xhci_stream_id_to_ring(
1389 struct xhci_virt_device *dev,
1390 unsigned int ep_index,
1391 unsigned int stream_id);
1392 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1393 bool allocate_in_ctx, bool allocate_completion,
1395 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1396 void xhci_free_command(struct xhci_hcd *xhci,
1397 struct xhci_command *command);
1401 int xhci_register_pci(void);
1402 void xhci_unregister_pci(void);
1405 /* xHCI host controller glue */
1406 void xhci_quiesce(struct xhci_hcd *xhci);
1407 int xhci_halt(struct xhci_hcd *xhci);
1408 int xhci_reset(struct xhci_hcd *xhci);
1409 int xhci_init(struct usb_hcd *hcd);
1410 int xhci_run(struct usb_hcd *hcd);
1411 void xhci_stop(struct usb_hcd *hcd);
1412 void xhci_shutdown(struct usb_hcd *hcd);
1415 int xhci_suspend(struct xhci_hcd *xhci);
1416 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1418 #define xhci_suspend NULL
1419 #define xhci_resume NULL
1422 int xhci_get_frame(struct usb_hcd *hcd);
1423 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1424 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1425 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1426 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1427 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1428 struct usb_host_endpoint **eps, unsigned int num_eps,
1429 unsigned int num_streams, gfp_t mem_flags);
1430 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1431 struct usb_host_endpoint **eps, unsigned int num_eps,
1433 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1434 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1435 struct usb_tt *tt, gfp_t mem_flags);
1436 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1437 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1438 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1439 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1440 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1441 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1442 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1443 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1445 /* xHCI ring, segment, TRB, and TD functions */
1446 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1447 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1448 union xhci_trb *start_trb, union xhci_trb *end_trb,
1449 dma_addr_t suspect_dma);
1450 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1451 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1452 void *xhci_setup_one_noop(struct xhci_hcd *xhci);
1453 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1454 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1456 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1457 u32 field1, u32 field2, u32 field3, u32 field4);
1458 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1459 unsigned int ep_index, int suspend);
1460 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1461 int slot_id, unsigned int ep_index);
1462 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1463 int slot_id, unsigned int ep_index);
1464 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1465 int slot_id, unsigned int ep_index);
1466 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1467 struct urb *urb, int slot_id, unsigned int ep_index);
1468 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1469 u32 slot_id, bool command_must_succeed);
1470 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1472 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1473 unsigned int ep_index);
1474 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1475 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1476 unsigned int slot_id, unsigned int ep_index,
1477 unsigned int stream_id, struct xhci_td *cur_td,
1478 struct xhci_dequeue_state *state);
1479 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1480 unsigned int slot_id, unsigned int ep_index,
1481 unsigned int stream_id,
1482 struct xhci_dequeue_state *deq_state);
1483 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1484 struct usb_device *udev, unsigned int ep_index);
1485 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1486 unsigned int slot_id, unsigned int ep_index,
1487 struct xhci_dequeue_state *deq_state);
1488 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1489 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1490 unsigned int ep_index, unsigned int stream_id);
1492 /* xHCI roothub code */
1493 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1494 char *buf, u16 wLength);
1495 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1498 int xhci_bus_suspend(struct usb_hcd *hcd);
1499 int xhci_bus_resume(struct usb_hcd *hcd);
1501 #define xhci_bus_suspend NULL
1502 #define xhci_bus_resume NULL
1503 #endif /* CONFIG_PM */
1505 u32 xhci_port_state_to_neutral(u32 state);
1506 int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port);
1507 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1510 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1511 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1512 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1514 #endif /* __LINUX_XHCI_HCD_H */