2 * Texas Instruments AM35x "glue layer"
4 * Copyright (c) 2010, by Texas Instruments
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/clk.h>
32 #include <linux/platform_device.h>
33 #include <linux/dma-mapping.h>
35 #include <plat/control.h>
38 #include "musb_core.h"
41 * AM35x specific definitions
43 /* USB 2.0 OTG module registers */
44 #define USB_REVISION_REG 0x00
45 #define USB_CTRL_REG 0x04
46 #define USB_STAT_REG 0x08
47 #define USB_EMULATION_REG 0x0c
49 #define USB_AUTOREQ_REG 0x14
50 #define USB_SRP_FIX_TIME_REG 0x18
51 #define USB_TEARDOWN_REG 0x1c
52 #define EP_INTR_SRC_REG 0x20
53 #define EP_INTR_SRC_SET_REG 0x24
54 #define EP_INTR_SRC_CLEAR_REG 0x28
55 #define EP_INTR_MASK_REG 0x2c
56 #define EP_INTR_MASK_SET_REG 0x30
57 #define EP_INTR_MASK_CLEAR_REG 0x34
58 #define EP_INTR_SRC_MASKED_REG 0x38
59 #define CORE_INTR_SRC_REG 0x40
60 #define CORE_INTR_SRC_SET_REG 0x44
61 #define CORE_INTR_SRC_CLEAR_REG 0x48
62 #define CORE_INTR_MASK_REG 0x4c
63 #define CORE_INTR_MASK_SET_REG 0x50
64 #define CORE_INTR_MASK_CLEAR_REG 0x54
65 #define CORE_INTR_SRC_MASKED_REG 0x58
67 #define USB_END_OF_INTR_REG 0x60
69 /* Control register bits */
70 #define AM35X_SOFT_RESET_MASK 1
72 /* USB interrupt register bits */
73 #define AM35X_INTR_USB_SHIFT 16
74 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
75 #define AM35X_INTR_DRVVBUS 0x100
76 #define AM35X_INTR_RX_SHIFT 16
77 #define AM35X_INTR_TX_SHIFT 0
78 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
79 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
80 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
81 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
83 #define USB_MENTOR_CORE_OFFSET 0x400
87 struct platform_device *musb;
91 #define glue_to_musb(g) platform_get_drvdata(g->musb)
93 static inline void phy_on(void)
95 unsigned long timeout = jiffies + msecs_to_jiffies(100);
99 * Start the on-chip PHY and its PLL.
101 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
103 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
104 devconf2 |= CONF2_PHY_PLLON;
106 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
108 DBG(1, "Waiting for PHY clock good...\n");
109 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
113 if (time_after(jiffies, timeout)) {
114 DBG(1, "musb PHY clock good timed out\n");
120 static inline void phy_off(void)
125 * Power down the on-chip PHY.
127 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
129 devconf2 &= ~CONF2_PHY_PLLON;
130 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
131 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
135 * am35x_musb_enable - enable interrupts
137 static void am35x_musb_enable(struct musb *musb)
139 void __iomem *reg_base = musb->ctrl_base;
142 /* Workaround: setup IRQs through both register sets. */
143 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
144 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
146 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
147 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
149 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
150 if (is_otg_enabled(musb))
151 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
152 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
156 * am35x_musb_disable - disable HDRC and flush interrupts
158 static void am35x_musb_disable(struct musb *musb)
160 void __iomem *reg_base = musb->ctrl_base;
162 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
163 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
164 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
165 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
166 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
169 #ifdef CONFIG_USB_MUSB_HDRC_HCD
170 #define portstate(stmt) stmt
172 #define portstate(stmt)
175 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
177 WARN_ON(is_on && is_peripheral_active(musb));
180 #define POLL_SECONDS 2
182 static struct timer_list otg_workaround;
184 static void otg_timer(unsigned long _musb)
186 struct musb *musb = (void *)_musb;
187 void __iomem *mregs = musb->mregs;
192 * We poll because AM35x's won't expose several OTG-critical
193 * status change events (from the transceiver) otherwise.
195 devctl = musb_readb(mregs, MUSB_DEVCTL);
196 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
198 spin_lock_irqsave(&musb->lock, flags);
199 switch (musb->xceiv->state) {
200 case OTG_STATE_A_WAIT_BCON:
201 devctl &= ~MUSB_DEVCTL_SESSION;
202 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
204 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
205 if (devctl & MUSB_DEVCTL_BDEVICE) {
206 musb->xceiv->state = OTG_STATE_B_IDLE;
209 musb->xceiv->state = OTG_STATE_A_IDLE;
213 case OTG_STATE_A_WAIT_VFALL:
214 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
215 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
216 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
218 case OTG_STATE_B_IDLE:
219 if (!is_peripheral_enabled(musb))
222 devctl = musb_readb(mregs, MUSB_DEVCTL);
223 if (devctl & MUSB_DEVCTL_BDEVICE)
224 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
226 musb->xceiv->state = OTG_STATE_A_IDLE;
231 spin_unlock_irqrestore(&musb->lock, flags);
234 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
236 static unsigned long last_timer;
238 if (!is_otg_enabled(musb))
242 timeout = jiffies + msecs_to_jiffies(3);
244 /* Never idle if active, or when VBUS timeout is not set as host */
245 if (musb->is_active || (musb->a_wait_bcon == 0 &&
246 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
247 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
248 del_timer(&otg_workaround);
249 last_timer = jiffies;
253 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
254 DBG(4, "Longer idle timer already pending, ignoring...\n");
257 last_timer = timeout;
259 DBG(4, "%s inactive, starting idle timer for %u ms\n",
260 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
261 mod_timer(&otg_workaround, timeout);
264 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
266 struct musb *musb = hci;
267 void __iomem *reg_base = musb->ctrl_base;
269 irqreturn_t ret = IRQ_NONE;
270 u32 epintr, usbintr, lvl_intr;
272 spin_lock_irqsave(&musb->lock, flags);
274 /* Get endpoint interrupts */
275 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
278 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
281 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
283 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
286 /* Get usb core interrupts */
287 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
288 if (!usbintr && !epintr)
292 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
295 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
298 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
299 * AM35x's missing ID change IRQ. We need an ID change IRQ to
300 * switch appropriately between halves of the OTG state machine.
301 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
302 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
303 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
305 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
306 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
307 void __iomem *mregs = musb->mregs;
308 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
311 err = is_host_enabled(musb) && (musb->int_usb &
312 MUSB_INTR_VBUSERROR);
315 * The Mentor core doesn't debounce VBUS as needed
316 * to cope with device connect current spikes. This
317 * means it's not uncommon for bus-powered devices
318 * to get VBUS errors during enumeration.
320 * This is a workaround, but newer RTL from Mentor
321 * seems to allow a better one: "re"-starting sessions
322 * without waiting for VBUS to stop registering in
325 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
326 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
327 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
328 WARNING("VBUS error workaround (delay coming)\n");
329 } else if (is_host_enabled(musb) && drvvbus) {
331 musb->xceiv->default_a = 1;
332 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
333 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
334 del_timer(&otg_workaround);
338 musb->xceiv->default_a = 0;
339 musb->xceiv->state = OTG_STATE_B_IDLE;
340 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
343 /* NOTE: this must complete power-on within 100 ms. */
344 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
345 drvvbus ? "on" : "off",
346 otg_state_string(musb),
352 if (musb->int_tx || musb->int_rx || musb->int_usb)
353 ret |= musb_interrupt(musb);
356 /* EOI needs to be written for the IRQ to be re-asserted. */
357 if (ret == IRQ_HANDLED || epintr || usbintr) {
358 /* clear level interrupt */
359 lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
360 lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
361 omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
363 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
366 /* Poll for ID change */
367 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
368 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
370 spin_unlock_irqrestore(&musb->lock, flags);
375 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
377 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
379 devconf2 &= ~CONF2_OTGMODE;
381 #ifdef CONFIG_USB_MUSB_HDRC_HCD
382 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
383 devconf2 |= CONF2_FORCE_HOST;
386 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
387 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
388 devconf2 |= CONF2_FORCE_DEVICE;
391 #ifdef CONFIG_USB_MUSB_OTG
392 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
393 devconf2 |= CONF2_NO_OVERRIDE;
397 DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
400 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
404 static int am35x_musb_init(struct musb *musb)
406 void __iomem *reg_base = musb->ctrl_base;
407 u32 rev, lvl_intr, sw_reset;
409 musb->mregs += USB_MENTOR_CORE_OFFSET;
411 /* Returns zero if e.g. not clocked */
412 rev = musb_readl(reg_base, USB_REVISION_REG);
416 usb_nop_xceiv_register();
417 musb->xceiv = otg_get_transceiver();
421 if (is_host_enabled(musb))
422 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
424 musb->board_set_vbus = am35x_musb_set_vbus;
427 sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
429 sw_reset |= AM35XX_USBOTGSS_SW_RST;
430 omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
432 sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
433 omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
435 /* Reset the controller */
436 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
438 /* Start the on-chip PHY and its PLL. */
443 musb->isr = am35x_musb_interrupt;
445 /* clear level interrupt */
446 lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
447 lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
448 omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
453 static int am35x_musb_exit(struct musb *musb)
455 if (is_host_enabled(musb))
456 del_timer_sync(&otg_workaround);
460 otg_put_transceiver(musb->xceiv);
461 usb_nop_xceiv_unregister();
466 /* AM35x supports only 32bit read operation */
467 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
469 void __iomem *fifo = hw_ep->fifo;
473 /* Read for 32bit-aligned destination address */
474 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
475 readsl(fifo, dst, len >> 2);
480 * Now read the remaining 1 to 3 byte or complete length if
484 for (i = 0; i < (len >> 2); i++) {
485 *(u32 *) dst = musb_readl(fifo, 0);
491 val = musb_readl(fifo, 0);
492 memcpy(dst, &val, len);
496 static const struct musb_platform_ops am35x_ops = {
497 .init = am35x_musb_init,
498 .exit = am35x_musb_exit,
500 .enable = am35x_musb_enable,
501 .disable = am35x_musb_disable,
503 .set_mode = am35x_musb_set_mode,
504 .try_idle = am35x_musb_try_idle,
506 .set_vbus = am35x_musb_set_vbus,
509 static u64 am35x_dmamask = DMA_BIT_MASK(32);
511 static int __init am35x_probe(struct platform_device *pdev)
513 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
514 struct platform_device *musb;
515 struct am35x_glue *glue;
522 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
524 dev_err(&pdev->dev, "failed to allocate glue context\n");
528 musb = platform_device_alloc("musb-hdrc", -1);
530 dev_err(&pdev->dev, "failed to allocate musb device\n");
534 phy_clk = clk_get(&pdev->dev, "fck");
535 if (IS_ERR(phy_clk)) {
536 dev_err(&pdev->dev, "failed to get PHY clock\n");
537 ret = PTR_ERR(phy_clk);
541 clk = clk_get(&pdev->dev, "ick");
543 dev_err(&pdev->dev, "failed to get clock\n");
548 ret = clk_enable(phy_clk);
550 dev_err(&pdev->dev, "failed to enable PHY clock\n");
554 ret = clk_enable(clk);
556 dev_err(&pdev->dev, "failed to enable clock\n");
560 musb->dev.parent = &pdev->dev;
561 musb->dev.dma_mask = &am35x_dmamask;
562 musb->dev.coherent_dma_mask = am35x_dmamask;
564 glue->dev = &pdev->dev;
566 glue->phy_clk = phy_clk;
569 pdata->platform_ops = &am35x_ops;
571 platform_set_drvdata(pdev, glue);
573 ret = platform_device_add_resources(musb, pdev->resource,
574 pdev->num_resources);
576 dev_err(&pdev->dev, "failed to add resources\n");
580 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
582 dev_err(&pdev->dev, "failed to add platform_data\n");
586 ret = platform_device_add(musb);
588 dev_err(&pdev->dev, "failed to register musb device\n");
598 clk_disable(phy_clk);
607 platform_device_put(musb);
616 static int __exit am35x_remove(struct platform_device *pdev)
618 struct am35x_glue *glue = platform_get_drvdata(pdev);
620 platform_device_del(glue->musb);
621 platform_device_put(glue->musb);
622 clk_disable(glue->clk);
623 clk_disable(glue->phy_clk);
625 clk_put(glue->phy_clk);
632 static int am35x_suspend(struct device *dev)
634 struct am35x_glue *glue = dev_get_drvdata(dev);
637 clk_disable(glue->phy_clk);
638 clk_disable(glue->clk);
643 static int am35x_resume(struct device *dev)
645 struct am35x_glue *glue = dev_get_drvdata(dev);
649 ret = clk_enable(glue->phy_clk);
651 dev_err(dev, "failed to enable PHY clock\n");
655 ret = clk_enable(glue->clk);
657 dev_err(dev, "failed to enable clock\n");
664 static struct dev_pm_ops am35x_pm_ops = {
665 .suspend = am35x_suspend,
666 .resume = am35x_resume,
669 #define DEV_PM_OPS &am35x_pm_ops
671 #define DEV_PM_OPS NULL
674 static struct platform_driver am35x_driver = {
675 .remove = __exit_p(am35x_remove),
677 .name = "musb-am35x",
682 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
683 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
684 MODULE_LICENSE("GPL v2");
686 static int __init am35x_init(void)
688 return platform_driver_probe(&am35x_driver, am35x_probe);
690 subsys_initcall(am35x_init);
692 static void __exit am35x_exit(void)
694 platform_driver_unregister(&am35x_driver);
696 module_exit(am35x_exit);