2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
136 void __iomem *addr = phy->io_priv;
142 pm_runtime_get_sync(phy->io_dev);
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173 pm_runtime_put(phy->io_dev);
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
180 void __iomem *addr = phy->io_priv;
186 pm_runtime_get_sync(phy->io_dev);
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211 pm_runtime_put(phy->io_dev);
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
225 /*-------------------------------------------------------------------------*/
227 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
230 * Load an endpoint's FIFO
232 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
234 struct musb *musb = hw_ep->musb;
235 void __iomem *fifo = hw_ep->fifo;
237 if (unlikely(len == 0))
242 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
243 'T', hw_ep->epnum, fifo, len, src);
245 /* we can't assume unaligned reads work */
246 if (likely((0x01 & (unsigned long) src) == 0)) {
249 /* best case is 32bit-aligned source address */
250 if ((0x02 & (unsigned long) src) == 0) {
252 iowrite32_rep(fifo, src + index, len >> 2);
253 index += len & ~0x03;
256 musb_writew(fifo, 0, *(u16 *)&src[index]);
261 iowrite16_rep(fifo, src + index, len >> 1);
262 index += len & ~0x01;
266 musb_writeb(fifo, 0, src[index]);
269 iowrite8_rep(fifo, src, len);
273 #if !defined(CONFIG_USB_MUSB_AM35X)
275 * Unload an endpoint's FIFO
277 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
279 struct musb *musb = hw_ep->musb;
280 void __iomem *fifo = hw_ep->fifo;
282 if (unlikely(len == 0))
285 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
286 'R', hw_ep->epnum, fifo, len, dst);
288 /* we can't assume unaligned writes work */
289 if (likely((0x01 & (unsigned long) dst) == 0)) {
292 /* best case is 32bit-aligned destination address */
293 if ((0x02 & (unsigned long) dst) == 0) {
295 ioread32_rep(fifo, dst, len >> 2);
299 *(u16 *)&dst[index] = musb_readw(fifo, 0);
304 ioread16_rep(fifo, dst, len >> 1);
309 dst[index] = musb_readb(fifo, 0);
312 ioread8_rep(fifo, dst, len);
317 #endif /* normal PIO */
320 /*-------------------------------------------------------------------------*/
322 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
323 static const u8 musb_test_packet[53] = {
324 /* implicit SYNC then DATA0 to start */
327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
329 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
331 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
332 /* JJJJJJJKKKKKKK x8 */
333 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
335 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
336 /* JKKKKKKK x10, JK */
337 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
339 /* implicit CRC16 then EOP to end */
342 void musb_load_testpacket(struct musb *musb)
344 void __iomem *regs = musb->endpoints[0].regs;
346 musb_ep_select(musb->mregs, 0);
347 musb_write_fifo(musb->control_ep,
348 sizeof(musb_test_packet), musb_test_packet);
349 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
352 /*-------------------------------------------------------------------------*/
355 * Handles OTG hnp timeouts, such as b_ase0_brst
357 static void musb_otg_timer_func(unsigned long data)
359 struct musb *musb = (struct musb *)data;
362 spin_lock_irqsave(&musb->lock, flags);
363 switch (musb->xceiv->state) {
364 case OTG_STATE_B_WAIT_ACON:
365 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
366 musb_g_disconnect(musb);
367 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
370 case OTG_STATE_A_SUSPEND:
371 case OTG_STATE_A_WAIT_BCON:
372 dev_dbg(musb->controller, "HNP: %s timeout\n",
373 usb_otg_state_string(musb->xceiv->state));
374 musb_platform_set_vbus(musb, 0);
375 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
378 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
379 usb_otg_state_string(musb->xceiv->state));
381 spin_unlock_irqrestore(&musb->lock, flags);
385 * Stops the HNP transition. Caller must take care of locking.
387 void musb_hnp_stop(struct musb *musb)
389 struct usb_hcd *hcd = musb->hcd;
390 void __iomem *mbase = musb->mregs;
393 dev_dbg(musb->controller, "HNP: stop from %s\n",
394 usb_otg_state_string(musb->xceiv->state));
396 switch (musb->xceiv->state) {
397 case OTG_STATE_A_PERIPHERAL:
398 musb_g_disconnect(musb);
399 dev_dbg(musb->controller, "HNP: back to %s\n",
400 usb_otg_state_string(musb->xceiv->state));
402 case OTG_STATE_B_HOST:
403 dev_dbg(musb->controller, "HNP: Disabling HR\n");
405 hcd->self.is_b_host = 0;
406 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
408 reg = musb_readb(mbase, MUSB_POWER);
409 reg |= MUSB_POWER_SUSPENDM;
410 musb_writeb(mbase, MUSB_POWER, reg);
411 /* REVISIT: Start SESSION_REQUEST here? */
414 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
415 usb_otg_state_string(musb->xceiv->state));
419 * When returning to A state after HNP, avoid hub_port_rebounce(),
420 * which cause occasional OPT A "Did not receive reset after connect"
423 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
427 * Interrupt Service Routine to record USB "global" interrupts.
428 * Since these do not happen often and signify things of
429 * paramount importance, it seems OK to check them individually;
430 * the order of the tests is specified in the manual
432 * @param musb instance pointer
433 * @param int_usb register contents
438 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
441 irqreturn_t handled = IRQ_NONE;
443 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
446 /* in host mode, the peripheral may issue remote wakeup.
447 * in peripheral mode, the host may resume the link.
448 * spurious RESUME irqs happen too, paired with SUSPEND.
450 if (int_usb & MUSB_INTR_RESUME) {
451 handled = IRQ_HANDLED;
452 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
454 if (devctl & MUSB_DEVCTL_HM) {
455 void __iomem *mbase = musb->mregs;
458 switch (musb->xceiv->state) {
459 case OTG_STATE_A_SUSPEND:
460 /* remote wakeup? later, GetPortStatus
461 * will stop RESUME signaling
464 power = musb_readb(musb->mregs, MUSB_POWER);
465 if (power & MUSB_POWER_SUSPENDM) {
467 musb->int_usb &= ~MUSB_INTR_SUSPEND;
468 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
472 power &= ~MUSB_POWER_SUSPENDM;
473 musb_writeb(mbase, MUSB_POWER,
474 power | MUSB_POWER_RESUME);
476 musb->port1_status |=
477 (USB_PORT_STAT_C_SUSPEND << 16)
478 | MUSB_PORT_STAT_RESUME;
479 musb->rh_timer = jiffies
480 + msecs_to_jiffies(20);
481 schedule_delayed_work(
482 &musb->finish_resume_work,
483 msecs_to_jiffies(20));
485 musb->xceiv->state = OTG_STATE_A_HOST;
487 musb_host_resume_root_hub(musb);
489 case OTG_STATE_B_WAIT_ACON:
490 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
495 WARNING("bogus %s RESUME (%s)\n",
497 usb_otg_state_string(musb->xceiv->state));
500 switch (musb->xceiv->state) {
501 case OTG_STATE_A_SUSPEND:
502 /* possibly DISCONNECT is upcoming */
503 musb->xceiv->state = OTG_STATE_A_HOST;
504 musb_host_resume_root_hub(musb);
506 case OTG_STATE_B_WAIT_ACON:
507 case OTG_STATE_B_PERIPHERAL:
508 /* disconnect while suspended? we may
509 * not get a disconnect irq...
511 if ((devctl & MUSB_DEVCTL_VBUS)
512 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
514 musb->int_usb |= MUSB_INTR_DISCONNECT;
515 musb->int_usb &= ~MUSB_INTR_SUSPEND;
520 case OTG_STATE_B_IDLE:
521 musb->int_usb &= ~MUSB_INTR_SUSPEND;
524 WARNING("bogus %s RESUME (%s)\n",
526 usb_otg_state_string(musb->xceiv->state));
531 /* see manual for the order of the tests */
532 if (int_usb & MUSB_INTR_SESSREQ) {
533 void __iomem *mbase = musb->mregs;
535 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536 && (devctl & MUSB_DEVCTL_BDEVICE)) {
537 dev_dbg(musb->controller, "SessReq while on B state\n");
541 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
542 usb_otg_state_string(musb->xceiv->state));
544 /* IRQ arrives from ID pin sense or (later, if VBUS power
545 * is removed) SRP. responses are time critical:
546 * - turn on VBUS (with silicon-specific mechanism)
547 * - go through A_WAIT_VRISE
548 * - ... to A_WAIT_BCON.
549 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
551 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552 musb->ep0_stage = MUSB_EP0_START;
553 musb->xceiv->state = OTG_STATE_A_IDLE;
555 musb_platform_set_vbus(musb, 1);
557 handled = IRQ_HANDLED;
560 if (int_usb & MUSB_INTR_VBUSERROR) {
563 /* During connection as an A-Device, we may see a short
564 * current spikes causing voltage drop, because of cable
565 * and peripheral capacitance combined with vbus draw.
566 * (So: less common with truly self-powered devices, where
567 * vbus doesn't act like a power supply.)
569 * Such spikes are short; usually less than ~500 usec, max
570 * of ~2 msec. That is, they're not sustained overcurrent
571 * errors, though they're reported using VBUSERROR irqs.
573 * Workarounds: (a) hardware: use self powered devices.
574 * (b) software: ignore non-repeated VBUS errors.
576 * REVISIT: do delays from lots of DEBUG_KERNEL checks
577 * make trouble here, keeping VBUS < 4.4V ?
579 switch (musb->xceiv->state) {
580 case OTG_STATE_A_HOST:
581 /* recovery is dicey once we've gotten past the
582 * initial stages of enumeration, but if VBUS
583 * stayed ok at the other end of the link, and
584 * another reset is due (at least for high speed,
585 * to redo the chirp etc), it might work OK...
587 case OTG_STATE_A_WAIT_BCON:
588 case OTG_STATE_A_WAIT_VRISE:
589 if (musb->vbuserr_retry) {
590 void __iomem *mbase = musb->mregs;
592 musb->vbuserr_retry--;
594 devctl |= MUSB_DEVCTL_SESSION;
595 musb_writeb(mbase, MUSB_DEVCTL, devctl);
597 musb->port1_status |=
598 USB_PORT_STAT_OVERCURRENT
599 | (USB_PORT_STAT_C_OVERCURRENT << 16);
606 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
608 usb_otg_state_string(musb->xceiv->state),
611 switch (devctl & MUSB_DEVCTL_VBUS) {
612 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613 s = "<SessEnd"; break;
614 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615 s = "<AValid"; break;
616 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617 s = "<VBusValid"; break;
618 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
622 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
625 /* go through A_WAIT_VFALL then start a new session */
627 musb_platform_set_vbus(musb, 0);
628 handled = IRQ_HANDLED;
631 if (int_usb & MUSB_INTR_SUSPEND) {
632 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
633 usb_otg_state_string(musb->xceiv->state), devctl);
634 handled = IRQ_HANDLED;
636 switch (musb->xceiv->state) {
637 case OTG_STATE_A_PERIPHERAL:
638 /* We also come here if the cable is removed, since
639 * this silicon doesn't report ID-no-longer-grounded.
641 * We depend on T(a_wait_bcon) to shut us down, and
642 * hope users don't do anything dicey during this
643 * undesired detour through A_WAIT_BCON.
646 musb_host_resume_root_hub(musb);
647 musb_root_disconnect(musb);
648 musb_platform_try_idle(musb, jiffies
649 + msecs_to_jiffies(musb->a_wait_bcon
650 ? : OTG_TIME_A_WAIT_BCON));
653 case OTG_STATE_B_IDLE:
654 if (!musb->is_active)
656 case OTG_STATE_B_PERIPHERAL:
657 musb_g_suspend(musb);
658 musb->is_active = musb->g.b_hnp_enable;
659 if (musb->is_active) {
660 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
661 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
662 mod_timer(&musb->otg_timer, jiffies
664 OTG_TIME_B_ASE0_BRST));
667 case OTG_STATE_A_WAIT_BCON:
668 if (musb->a_wait_bcon != 0)
669 musb_platform_try_idle(musb, jiffies
670 + msecs_to_jiffies(musb->a_wait_bcon));
672 case OTG_STATE_A_HOST:
673 musb->xceiv->state = OTG_STATE_A_SUSPEND;
674 musb->is_active = musb->hcd->self.b_hnp_enable;
676 case OTG_STATE_B_HOST:
677 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
678 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
681 /* "should not happen" */
687 if (int_usb & MUSB_INTR_CONNECT) {
688 struct usb_hcd *hcd = musb->hcd;
690 handled = IRQ_HANDLED;
693 musb->ep0_stage = MUSB_EP0_START;
695 /* flush endpoints when transitioning from Device Mode */
696 if (is_peripheral_active(musb)) {
697 /* REVISIT HNP; just force disconnect */
699 musb->intrtxe = musb->epmask;
700 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
701 musb->intrrxe = musb->epmask & 0xfffe;
702 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
703 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
704 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705 |USB_PORT_STAT_HIGH_SPEED
706 |USB_PORT_STAT_ENABLE
708 musb->port1_status |= USB_PORT_STAT_CONNECTION
709 |(USB_PORT_STAT_C_CONNECTION << 16);
711 /* high vs full speed is just a guess until after reset */
712 if (devctl & MUSB_DEVCTL_LSDEV)
713 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
715 /* indicate new connection to OTG machine */
716 switch (musb->xceiv->state) {
717 case OTG_STATE_B_PERIPHERAL:
718 if (int_usb & MUSB_INTR_SUSPEND) {
719 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
720 int_usb &= ~MUSB_INTR_SUSPEND;
723 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
725 case OTG_STATE_B_WAIT_ACON:
726 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
728 musb->xceiv->state = OTG_STATE_B_HOST;
730 musb->hcd->self.is_b_host = 1;
731 del_timer(&musb->otg_timer);
734 if ((devctl & MUSB_DEVCTL_VBUS)
735 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
736 musb->xceiv->state = OTG_STATE_A_HOST;
738 hcd->self.is_b_host = 0;
743 musb_host_poke_root_hub(musb);
745 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
746 usb_otg_state_string(musb->xceiv->state), devctl);
749 if (int_usb & MUSB_INTR_DISCONNECT) {
750 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
751 usb_otg_state_string(musb->xceiv->state),
752 MUSB_MODE(musb), devctl);
753 handled = IRQ_HANDLED;
755 switch (musb->xceiv->state) {
756 case OTG_STATE_A_HOST:
757 case OTG_STATE_A_SUSPEND:
758 musb_host_resume_root_hub(musb);
759 musb_root_disconnect(musb);
760 if (musb->a_wait_bcon != 0)
761 musb_platform_try_idle(musb, jiffies
762 + msecs_to_jiffies(musb->a_wait_bcon));
764 case OTG_STATE_B_HOST:
765 /* REVISIT this behaves for "real disconnect"
766 * cases; make sure the other transitions from
767 * from B_HOST act right too. The B_HOST code
768 * in hnp_stop() is currently not used...
770 musb_root_disconnect(musb);
772 musb->hcd->self.is_b_host = 0;
773 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
775 musb_g_disconnect(musb);
777 case OTG_STATE_A_PERIPHERAL:
779 musb_root_disconnect(musb);
781 case OTG_STATE_B_WAIT_ACON:
783 case OTG_STATE_B_PERIPHERAL:
784 case OTG_STATE_B_IDLE:
785 musb_g_disconnect(musb);
788 WARNING("unhandled DISCONNECT transition (%s)\n",
789 usb_otg_state_string(musb->xceiv->state));
794 /* mentor saves a bit: bus reset and babble share the same irq.
795 * only host sees babble; only peripheral sees bus reset.
797 if (int_usb & MUSB_INTR_RESET) {
798 handled = IRQ_HANDLED;
799 if ((devctl & MUSB_DEVCTL_HM) != 0) {
801 * Looks like non-HS BABBLE can be ignored, but
802 * HS BABBLE is an error condition. For HS the solution
803 * is to avoid babble in the first place and fix what
804 * caused BABBLE. When HS BABBLE happens we can only
807 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
808 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
810 ERR("Stopping host session -- babble\n");
811 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
814 dev_dbg(musb->controller, "BUS RESET as %s\n",
815 usb_otg_state_string(musb->xceiv->state));
816 switch (musb->xceiv->state) {
817 case OTG_STATE_A_SUSPEND:
820 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
821 /* never use invalid T(a_wait_bcon) */
822 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
823 usb_otg_state_string(musb->xceiv->state),
825 mod_timer(&musb->otg_timer, jiffies
826 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
828 case OTG_STATE_A_PERIPHERAL:
829 del_timer(&musb->otg_timer);
832 case OTG_STATE_B_WAIT_ACON:
833 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
834 usb_otg_state_string(musb->xceiv->state));
835 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
838 case OTG_STATE_B_IDLE:
839 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
841 case OTG_STATE_B_PERIPHERAL:
845 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
846 usb_otg_state_string(musb->xceiv->state));
851 /* handle babble condition */
852 if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb))
853 schedule_delayed_work(&musb->recover_work,
854 msecs_to_jiffies(100));
857 /* REVISIT ... this would be for multiplexing periodic endpoints, or
858 * supporting transfer phasing to prevent exceeding ISO bandwidth
859 * limits of a given frame or microframe.
861 * It's not needed for peripheral side, which dedicates endpoints;
862 * though it _might_ use SOF irqs for other purposes.
864 * And it's not currently needed for host side, which also dedicates
865 * endpoints, relies on TX/RX interval registers, and isn't claimed
866 * to support ISO transfers yet.
868 if (int_usb & MUSB_INTR_SOF) {
869 void __iomem *mbase = musb->mregs;
870 struct musb_hw_ep *ep;
874 dev_dbg(musb->controller, "START_OF_FRAME\n");
875 handled = IRQ_HANDLED;
877 /* start any periodic Tx transfers waiting for current frame */
878 frame = musb_readw(mbase, MUSB_FRAME);
879 ep = musb->endpoints;
880 for (epnum = 1; (epnum < musb->nr_endpoints)
881 && (musb->epmask >= (1 << epnum));
884 * FIXME handle framecounter wraps (12 bits)
885 * eliminate duplicated StartUrb logic
887 if (ep->dwWaitFrame >= frame) {
889 pr_debug("SOF --> periodic TX%s on %d\n",
890 ep->tx_channel ? " DMA" : "",
893 musb_h_tx_start(musb, epnum);
895 cppi_hostdma_start(musb, epnum);
897 } /* end of for loop */
901 schedule_work(&musb->irq_work);
906 /*-------------------------------------------------------------------------*/
908 static void musb_generic_disable(struct musb *musb)
910 void __iomem *mbase = musb->mregs;
913 /* disable interrupts */
914 musb_writeb(mbase, MUSB_INTRUSBE, 0);
916 musb_writew(mbase, MUSB_INTRTXE, 0);
918 musb_writew(mbase, MUSB_INTRRXE, 0);
921 musb_writeb(mbase, MUSB_DEVCTL, 0);
923 /* flush pending interrupts */
924 temp = musb_readb(mbase, MUSB_INTRUSB);
925 temp = musb_readw(mbase, MUSB_INTRTX);
926 temp = musb_readw(mbase, MUSB_INTRRX);
931 * Program the HDRC to start (enable interrupts, dma, etc.).
933 void musb_start(struct musb *musb)
935 void __iomem *regs = musb->mregs;
936 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
938 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
940 /* Set INT enable registers, enable interrupts */
941 musb->intrtxe = musb->epmask;
942 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
943 musb->intrrxe = musb->epmask & 0xfffe;
944 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
945 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
947 musb_writeb(regs, MUSB_TESTMODE, 0);
949 /* put into basic highspeed mode and start session */
950 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
952 /* ENSUSPEND wedges tusb */
953 /* | MUSB_POWER_ENSUSPEND */
957 devctl = musb_readb(regs, MUSB_DEVCTL);
958 devctl &= ~MUSB_DEVCTL_SESSION;
960 /* session started after:
961 * (a) ID-grounded irq, host mode;
962 * (b) vbus present/connect IRQ, peripheral mode;
963 * (c) peripheral initiates, using SRP
965 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
966 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
969 devctl |= MUSB_DEVCTL_SESSION;
972 musb_platform_enable(musb);
973 musb_writeb(regs, MUSB_DEVCTL, devctl);
977 * Make the HDRC stop (disable interrupts, etc.);
978 * reversible by musb_start
979 * called on gadget driver unregister
980 * with controller locked, irqs blocked
981 * acts as a NOP unless some role activated the hardware
983 void musb_stop(struct musb *musb)
985 /* stop IRQs, timers, ... */
986 musb_platform_disable(musb);
987 musb_generic_disable(musb);
988 dev_dbg(musb->controller, "HDRC disabled\n");
991 * - mark host and/or peripheral drivers unusable/inactive
992 * - disable DMA (and enable it in HdrcStart)
993 * - make sure we can musb_start() after musb_stop(); with
994 * OTG mode, gadget driver module rmmod/modprobe cycles that
997 musb_platform_try_idle(musb, 0);
1000 static void musb_shutdown(struct platform_device *pdev)
1002 struct musb *musb = dev_to_musb(&pdev->dev);
1003 unsigned long flags;
1005 pm_runtime_get_sync(musb->controller);
1007 musb_host_cleanup(musb);
1008 musb_gadget_cleanup(musb);
1010 spin_lock_irqsave(&musb->lock, flags);
1011 musb_platform_disable(musb);
1012 musb_generic_disable(musb);
1013 spin_unlock_irqrestore(&musb->lock, flags);
1015 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1016 musb_platform_exit(musb);
1018 pm_runtime_put(musb->controller);
1019 /* FIXME power down */
1023 /*-------------------------------------------------------------------------*/
1026 * The silicon either has hard-wired endpoint configurations, or else
1027 * "dynamic fifo" sizing. The driver has support for both, though at this
1028 * writing only the dynamic sizing is very well tested. Since we switched
1029 * away from compile-time hardware parameters, we can no longer rely on
1030 * dead code elimination to leave only the relevant one in the object file.
1032 * We don't currently use dynamic fifo setup capability to do anything
1033 * more than selecting one of a bunch of predefined configurations.
1035 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1036 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1037 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1038 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1039 || defined(CONFIG_USB_MUSB_AM35X) \
1040 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1041 || defined(CONFIG_USB_MUSB_DSPS) \
1042 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1043 static ushort fifo_mode = 4;
1044 #elif defined(CONFIG_USB_MUSB_UX500) \
1045 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1046 static ushort fifo_mode = 5;
1048 static ushort fifo_mode = 2;
1051 /* "modprobe ... fifo_mode=1" etc */
1052 module_param(fifo_mode, ushort, 0);
1053 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1056 * tables defining fifo_mode values. define more if you like.
1057 * for host side, make sure both halves of ep1 are set up.
1060 /* mode 0 - fits in 2KB */
1061 static struct musb_fifo_cfg mode_0_cfg[] = {
1062 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1063 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1064 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1065 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1066 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1069 /* mode 1 - fits in 4KB */
1070 static struct musb_fifo_cfg mode_1_cfg[] = {
1071 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1072 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1073 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1074 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1075 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1078 /* mode 2 - fits in 4KB */
1079 static struct musb_fifo_cfg mode_2_cfg[] = {
1080 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1085 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1088 /* mode 3 - fits in 4KB */
1089 static struct musb_fifo_cfg mode_3_cfg[] = {
1090 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1091 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1092 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1095 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1098 /* mode 4 - fits in 16KB */
1099 static struct musb_fifo_cfg mode_4_cfg[] = {
1100 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1107 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1108 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1109 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1110 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1111 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1112 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1113 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1114 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1117 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1118 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1119 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1120 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1121 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1122 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1123 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1124 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1125 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1126 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1129 /* mode 5 - fits in 8KB */
1130 static struct musb_fifo_cfg mode_5_cfg[] = {
1131 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1142 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1143 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1144 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1145 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1146 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1147 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1148 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1149 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1150 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1151 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1152 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1153 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1154 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1155 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1156 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1157 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1161 * configure a fifo; for non-shared endpoints, this may be called
1162 * once for a tx fifo and once for an rx fifo.
1164 * returns negative errno or offset for next fifo.
1167 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1168 const struct musb_fifo_cfg *cfg, u16 offset)
1170 void __iomem *mbase = musb->mregs;
1172 u16 maxpacket = cfg->maxpacket;
1173 u16 c_off = offset >> 3;
1176 /* expect hw_ep has already been zero-initialized */
1178 size = ffs(max(maxpacket, (u16) 8)) - 1;
1179 maxpacket = 1 << size;
1182 if (cfg->mode == BUF_DOUBLE) {
1183 if ((offset + (maxpacket << 1)) >
1184 (1 << (musb->config->ram_bits + 2)))
1186 c_size |= MUSB_FIFOSZ_DPB;
1188 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1192 /* configure the FIFO */
1193 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1195 /* EP0 reserved endpoint for control, bidirectional;
1196 * EP1 reserved for bulk, two unidirectional halves.
1198 if (hw_ep->epnum == 1)
1199 musb->bulk_ep = hw_ep;
1200 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1201 switch (cfg->style) {
1203 musb_write_txfifosz(mbase, c_size);
1204 musb_write_txfifoadd(mbase, c_off);
1205 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1206 hw_ep->max_packet_sz_tx = maxpacket;
1209 musb_write_rxfifosz(mbase, c_size);
1210 musb_write_rxfifoadd(mbase, c_off);
1211 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1212 hw_ep->max_packet_sz_rx = maxpacket;
1215 musb_write_txfifosz(mbase, c_size);
1216 musb_write_txfifoadd(mbase, c_off);
1217 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1218 hw_ep->max_packet_sz_rx = maxpacket;
1220 musb_write_rxfifosz(mbase, c_size);
1221 musb_write_rxfifoadd(mbase, c_off);
1222 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1223 hw_ep->max_packet_sz_tx = maxpacket;
1225 hw_ep->is_shared_fifo = true;
1229 /* NOTE rx and tx endpoint irqs aren't managed separately,
1230 * which happens to be ok
1232 musb->epmask |= (1 << hw_ep->epnum);
1234 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1237 static struct musb_fifo_cfg ep0_cfg = {
1238 .style = FIFO_RXTX, .maxpacket = 64,
1241 static int ep_config_from_table(struct musb *musb)
1243 const struct musb_fifo_cfg *cfg;
1246 struct musb_hw_ep *hw_ep = musb->endpoints;
1248 if (musb->config->fifo_cfg) {
1249 cfg = musb->config->fifo_cfg;
1250 n = musb->config->fifo_cfg_size;
1254 switch (fifo_mode) {
1260 n = ARRAY_SIZE(mode_0_cfg);
1264 n = ARRAY_SIZE(mode_1_cfg);
1268 n = ARRAY_SIZE(mode_2_cfg);
1272 n = ARRAY_SIZE(mode_3_cfg);
1276 n = ARRAY_SIZE(mode_4_cfg);
1280 n = ARRAY_SIZE(mode_5_cfg);
1284 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1285 musb_driver_name, fifo_mode);
1289 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1290 /* assert(offset > 0) */
1292 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1293 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1296 for (i = 0; i < n; i++) {
1297 u8 epn = cfg->hw_ep_num;
1299 if (epn >= musb->config->num_eps) {
1300 pr_debug("%s: invalid ep %d\n",
1301 musb_driver_name, epn);
1304 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1306 pr_debug("%s: mem overrun, ep %d\n",
1307 musb_driver_name, epn);
1311 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1314 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1316 n + 1, musb->config->num_eps * 2 - 1,
1317 offset, (1 << (musb->config->ram_bits + 2)));
1319 if (!musb->bulk_ep) {
1320 pr_debug("%s: missing bulk\n", musb_driver_name);
1329 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1330 * @param musb the controller
1332 static int ep_config_from_hw(struct musb *musb)
1335 struct musb_hw_ep *hw_ep;
1336 void __iomem *mbase = musb->mregs;
1339 dev_dbg(musb->controller, "<== static silicon ep config\n");
1341 /* FIXME pick up ep0 maxpacket size */
1343 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1344 musb_ep_select(mbase, epnum);
1345 hw_ep = musb->endpoints + epnum;
1347 ret = musb_read_fifosize(musb, hw_ep, epnum);
1351 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1353 /* pick an RX/TX endpoint for bulk */
1354 if (hw_ep->max_packet_sz_tx < 512
1355 || hw_ep->max_packet_sz_rx < 512)
1358 /* REVISIT: this algorithm is lazy, we should at least
1359 * try to pick a double buffered endpoint.
1363 musb->bulk_ep = hw_ep;
1366 if (!musb->bulk_ep) {
1367 pr_debug("%s: missing bulk\n", musb_driver_name);
1374 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1376 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1377 * configure endpoints, or take their config from silicon
1379 static int musb_core_init(u16 musb_type, struct musb *musb)
1383 char aInfo[90], aRevision[32], aDate[12];
1384 void __iomem *mbase = musb->mregs;
1388 /* log core options (read using indexed model) */
1389 reg = musb_read_configdata(mbase);
1391 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1392 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1393 strcat(aInfo, ", dyn FIFOs");
1394 musb->dyn_fifo = true;
1396 if (reg & MUSB_CONFIGDATA_MPRXE) {
1397 strcat(aInfo, ", bulk combine");
1398 musb->bulk_combine = true;
1400 if (reg & MUSB_CONFIGDATA_MPTXE) {
1401 strcat(aInfo, ", bulk split");
1402 musb->bulk_split = true;
1404 if (reg & MUSB_CONFIGDATA_HBRXE) {
1405 strcat(aInfo, ", HB-ISO Rx");
1406 musb->hb_iso_rx = true;
1408 if (reg & MUSB_CONFIGDATA_HBTXE) {
1409 strcat(aInfo, ", HB-ISO Tx");
1410 musb->hb_iso_tx = true;
1412 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1413 strcat(aInfo, ", SoftConn");
1415 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1416 musb_driver_name, reg, aInfo);
1419 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1420 musb->is_multipoint = 1;
1423 musb->is_multipoint = 0;
1425 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1427 "%s: kernel must blacklist external hubs\n",
1432 /* log release info */
1433 musb->hwvers = musb_read_hwvers(mbase);
1434 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1435 MUSB_HWVERS_MINOR(musb->hwvers),
1436 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1437 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1438 musb_driver_name, type, aRevision, aDate);
1441 musb_configure_ep0(musb);
1443 /* discover endpoint configuration */
1444 musb->nr_endpoints = 1;
1448 status = ep_config_from_table(musb);
1450 status = ep_config_from_hw(musb);
1455 /* finish init, and print endpoint config */
1456 for (i = 0; i < musb->nr_endpoints; i++) {
1457 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1459 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1460 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1461 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1462 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1463 hw_ep->fifo_sync_va =
1464 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1467 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1469 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1472 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1473 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1474 hw_ep->rx_reinit = 1;
1475 hw_ep->tx_reinit = 1;
1477 if (hw_ep->max_packet_sz_tx) {
1478 dev_dbg(musb->controller,
1479 "%s: hw_ep %d%s, %smax %d\n",
1480 musb_driver_name, i,
1481 hw_ep->is_shared_fifo ? "shared" : "tx",
1482 hw_ep->tx_double_buffered
1483 ? "doublebuffer, " : "",
1484 hw_ep->max_packet_sz_tx);
1486 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1487 dev_dbg(musb->controller,
1488 "%s: hw_ep %d%s, %smax %d\n",
1489 musb_driver_name, i,
1491 hw_ep->rx_double_buffered
1492 ? "doublebuffer, " : "",
1493 hw_ep->max_packet_sz_rx);
1495 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1496 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1502 /*-------------------------------------------------------------------------*/
1505 * handle all the irqs defined by the HDRC core. for now we expect: other
1506 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1507 * will be assigned, and the irq will already have been acked.
1509 * called in irq context with spinlock held, irqs blocked
1511 irqreturn_t musb_interrupt(struct musb *musb)
1513 irqreturn_t retval = IRQ_NONE;
1518 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1520 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1521 is_host_active(musb) ? "host" : "peripheral",
1522 musb->int_usb, musb->int_tx, musb->int_rx);
1524 /* the core can interrupt us for multiple reasons; docs have
1525 * a generic interrupt flowchart to follow
1528 retval |= musb_stage0_irq(musb, musb->int_usb,
1531 /* "stage 1" is handling endpoint irqs */
1533 /* handle endpoint 0 first */
1534 if (musb->int_tx & 1) {
1535 if (is_host_active(musb))
1536 retval |= musb_h_ep0_irq(musb);
1538 retval |= musb_g_ep0_irq(musb);
1541 /* RX on endpoints 1-15 */
1542 reg = musb->int_rx >> 1;
1546 /* musb_ep_select(musb->mregs, ep_num); */
1547 /* REVISIT just retval = ep->rx_irq(...) */
1548 retval = IRQ_HANDLED;
1549 if (is_host_active(musb))
1550 musb_host_rx(musb, ep_num);
1552 musb_g_rx(musb, ep_num);
1559 /* TX on endpoints 1-15 */
1560 reg = musb->int_tx >> 1;
1564 /* musb_ep_select(musb->mregs, ep_num); */
1565 /* REVISIT just retval |= ep->tx_irq(...) */
1566 retval = IRQ_HANDLED;
1567 if (is_host_active(musb))
1568 musb_host_tx(musb, ep_num);
1570 musb_g_tx(musb, ep_num);
1578 EXPORT_SYMBOL_GPL(musb_interrupt);
1580 #ifndef CONFIG_MUSB_PIO_ONLY
1581 static bool use_dma = 1;
1583 /* "modprobe ... use_dma=0" etc */
1584 module_param(use_dma, bool, 0);
1585 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1587 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1589 /* called with controller lock already held */
1592 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1593 if (!is_cppi_enabled()) {
1595 if (is_host_active(musb))
1596 musb_h_ep0_irq(musb);
1598 musb_g_ep0_irq(musb);
1602 /* endpoints 1..15 */
1604 if (is_host_active(musb))
1605 musb_host_tx(musb, epnum);
1607 musb_g_tx(musb, epnum);
1610 if (is_host_active(musb))
1611 musb_host_rx(musb, epnum);
1613 musb_g_rx(musb, epnum);
1617 EXPORT_SYMBOL_GPL(musb_dma_completion);
1623 /*-------------------------------------------------------------------------*/
1626 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1628 struct musb *musb = dev_to_musb(dev);
1629 unsigned long flags;
1632 spin_lock_irqsave(&musb->lock, flags);
1633 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
1634 spin_unlock_irqrestore(&musb->lock, flags);
1640 musb_mode_store(struct device *dev, struct device_attribute *attr,
1641 const char *buf, size_t n)
1643 struct musb *musb = dev_to_musb(dev);
1644 unsigned long flags;
1647 spin_lock_irqsave(&musb->lock, flags);
1648 if (sysfs_streq(buf, "host"))
1649 status = musb_platform_set_mode(musb, MUSB_HOST);
1650 else if (sysfs_streq(buf, "peripheral"))
1651 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1652 else if (sysfs_streq(buf, "otg"))
1653 status = musb_platform_set_mode(musb, MUSB_OTG);
1656 spin_unlock_irqrestore(&musb->lock, flags);
1658 return (status == 0) ? n : status;
1660 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1663 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1664 const char *buf, size_t n)
1666 struct musb *musb = dev_to_musb(dev);
1667 unsigned long flags;
1670 if (sscanf(buf, "%lu", &val) < 1) {
1671 dev_err(dev, "Invalid VBUS timeout ms value\n");
1675 spin_lock_irqsave(&musb->lock, flags);
1676 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1677 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1678 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1679 musb->is_active = 0;
1680 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1681 spin_unlock_irqrestore(&musb->lock, flags);
1687 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1689 struct musb *musb = dev_to_musb(dev);
1690 unsigned long flags;
1694 spin_lock_irqsave(&musb->lock, flags);
1695 val = musb->a_wait_bcon;
1696 /* FIXME get_vbus_status() is normally #defined as false...
1697 * and is effectively TUSB-specific.
1699 vbus = musb_platform_get_vbus_status(musb);
1700 spin_unlock_irqrestore(&musb->lock, flags);
1702 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1703 vbus ? "on" : "off", val);
1705 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1707 /* Gadget drivers can't know that a host is connected so they might want
1708 * to start SRP, but users can. This allows userspace to trigger SRP.
1711 musb_srp_store(struct device *dev, struct device_attribute *attr,
1712 const char *buf, size_t n)
1714 struct musb *musb = dev_to_musb(dev);
1717 if (sscanf(buf, "%hu", &srp) != 1
1719 dev_err(dev, "SRP: Value must be 1\n");
1724 musb_g_wakeup(musb);
1728 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1730 static struct attribute *musb_attributes[] = {
1731 &dev_attr_mode.attr,
1732 &dev_attr_vbus.attr,
1737 static const struct attribute_group musb_attr_group = {
1738 .attrs = musb_attributes,
1741 /* Only used to provide driver mode change events */
1742 static void musb_irq_work(struct work_struct *data)
1744 struct musb *musb = container_of(data, struct musb, irq_work);
1746 if (musb->xceiv->state != musb->xceiv_old_state) {
1747 musb->xceiv_old_state = musb->xceiv->state;
1748 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1752 /* Recover from babble interrupt conditions */
1753 static void musb_recover_work(struct work_struct *data)
1755 struct musb *musb = container_of(data, struct musb, recover_work.work);
1758 ret = musb_platform_reset(musb);
1762 usb_phy_vbus_off(musb->xceiv);
1763 usleep_range(100, 200);
1765 usb_phy_vbus_on(musb->xceiv);
1766 usleep_range(100, 200);
1769 * When a babble condition occurs, the musb controller
1770 * removes the session bit and the endpoint config is lost.
1773 status = ep_config_from_table(musb);
1775 status = ep_config_from_hw(musb);
1777 /* start the session again */
1782 /* --------------------------------------------------------------------------
1786 static struct musb *allocate_instance(struct device *dev,
1787 struct musb_hdrc_config *config, void __iomem *mbase)
1790 struct musb_hw_ep *ep;
1794 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1798 INIT_LIST_HEAD(&musb->control);
1799 INIT_LIST_HEAD(&musb->in_bulk);
1800 INIT_LIST_HEAD(&musb->out_bulk);
1802 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1803 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1804 musb->mregs = mbase;
1805 musb->ctrl_base = mbase;
1806 musb->nIrq = -ENODEV;
1807 musb->config = config;
1808 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1809 for (epnum = 0, ep = musb->endpoints;
1810 epnum < musb->config->num_eps;
1816 musb->controller = dev;
1818 ret = musb_host_alloc(musb);
1822 dev_set_drvdata(dev, musb);
1830 static void musb_free(struct musb *musb)
1832 /* this has multiple entry modes. it handles fault cleanup after
1833 * probe(), where things may be partially set up, as well as rmmod
1834 * cleanup after everything's been de-activated.
1838 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1841 if (musb->nIrq >= 0) {
1843 disable_irq_wake(musb->nIrq);
1844 free_irq(musb->nIrq, musb);
1847 musb_host_free(musb);
1850 static void musb_deassert_reset(struct work_struct *work)
1853 unsigned long flags;
1855 musb = container_of(work, struct musb, deassert_reset_work.work);
1857 spin_lock_irqsave(&musb->lock, flags);
1859 if (musb->port1_status & USB_PORT_STAT_RESET)
1860 musb_port_reset(musb, false);
1862 spin_unlock_irqrestore(&musb->lock, flags);
1866 * Perform generic per-controller initialization.
1868 * @dev: the controller (already clocked, etc)
1870 * @ctrl: virtual address of controller registers,
1871 * not yet corrected for platform-specific offsets
1874 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1878 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1880 /* The driver might handle more features than the board; OK.
1881 * Fail when the board needs a feature that's not enabled.
1884 dev_dbg(dev, "no platform_data?\n");
1890 musb = allocate_instance(dev, plat->config, ctrl);
1896 pm_runtime_use_autosuspend(musb->controller);
1897 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1898 pm_runtime_enable(musb->controller);
1900 spin_lock_init(&musb->lock);
1901 musb->board_set_power = plat->set_power;
1902 musb->min_power = plat->min_power;
1903 musb->ops = plat->platform_ops;
1904 musb->port_mode = plat->mode;
1906 /* The musb_platform_init() call:
1907 * - adjusts musb->mregs
1908 * - sets the musb->isr
1909 * - may initialize an integrated transceiver
1910 * - initializes musb->xceiv, usually by otg_get_phy()
1911 * - stops powering VBUS
1913 * There are various transceiver configurations. Blackfin,
1914 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1915 * external/discrete ones in various flavors (twl4030 family,
1916 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1918 status = musb_platform_init(musb);
1927 if (!musb->xceiv->io_ops) {
1928 musb->xceiv->io_dev = musb->controller;
1929 musb->xceiv->io_priv = musb->mregs;
1930 musb->xceiv->io_ops = &musb_ulpi_access;
1933 pm_runtime_get_sync(musb->controller);
1935 if (use_dma && dev->dma_mask) {
1936 musb->dma_controller = dma_controller_create(musb, musb->mregs);
1937 if (IS_ERR(musb->dma_controller)) {
1938 status = PTR_ERR(musb->dma_controller);
1943 /* be sure interrupts are disabled before connecting ISR */
1944 musb_platform_disable(musb);
1945 musb_generic_disable(musb);
1947 /* Init IRQ workqueue before request_irq */
1948 INIT_WORK(&musb->irq_work, musb_irq_work);
1949 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
1950 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
1951 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
1953 /* setup musb parts of the core (especially endpoints) */
1954 status = musb_core_init(plat->config->multipoint
1955 ? MUSB_CONTROLLER_MHDRC
1956 : MUSB_CONTROLLER_HDRC, musb);
1960 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1962 /* attach to the IRQ */
1963 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1964 dev_err(dev, "request_irq %d failed!\n", nIrq);
1969 /* FIXME this handles wakeup irqs wrong */
1970 if (enable_irq_wake(nIrq) == 0) {
1972 device_init_wakeup(dev, 1);
1977 /* program PHY to use external vBus if required */
1978 if (plat->extvbus) {
1979 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1980 busctl |= MUSB_ULPI_USE_EXTVBUS;
1981 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1984 if (musb->xceiv->otg->default_a) {
1985 MUSB_HST_MODE(musb);
1986 musb->xceiv->state = OTG_STATE_A_IDLE;
1988 MUSB_DEV_MODE(musb);
1989 musb->xceiv->state = OTG_STATE_B_IDLE;
1992 switch (musb->port_mode) {
1993 case MUSB_PORT_MODE_HOST:
1994 status = musb_host_setup(musb, plat->power);
1997 status = musb_platform_set_mode(musb, MUSB_HOST);
1999 case MUSB_PORT_MODE_GADGET:
2000 status = musb_gadget_setup(musb);
2003 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2005 case MUSB_PORT_MODE_DUAL_ROLE:
2006 status = musb_host_setup(musb, plat->power);
2009 status = musb_gadget_setup(musb);
2011 musb_host_cleanup(musb);
2014 status = musb_platform_set_mode(musb, MUSB_OTG);
2017 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2024 status = musb_init_debugfs(musb);
2028 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2032 pm_runtime_put(musb->controller);
2037 musb_exit_debugfs(musb);
2040 musb_gadget_cleanup(musb);
2041 musb_host_cleanup(musb);
2044 cancel_work_sync(&musb->irq_work);
2045 cancel_delayed_work_sync(&musb->recover_work);
2046 cancel_delayed_work_sync(&musb->finish_resume_work);
2047 cancel_delayed_work_sync(&musb->deassert_reset_work);
2048 if (musb->dma_controller)
2049 dma_controller_destroy(musb->dma_controller);
2051 pm_runtime_put_sync(musb->controller);
2055 device_init_wakeup(dev, 0);
2056 musb_platform_exit(musb);
2059 pm_runtime_disable(musb->controller);
2060 dev_err(musb->controller,
2061 "musb_init_controller failed with status %d\n", status);
2071 /*-------------------------------------------------------------------------*/
2073 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2074 * bridge to a platform device; this driver then suffices.
2076 static int musb_probe(struct platform_device *pdev)
2078 struct device *dev = &pdev->dev;
2079 int irq = platform_get_irq_byname(pdev, "mc");
2080 struct resource *iomem;
2086 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2087 base = devm_ioremap_resource(dev, iomem);
2089 return PTR_ERR(base);
2091 return musb_init_controller(dev, irq, base);
2094 static int musb_remove(struct platform_device *pdev)
2096 struct device *dev = &pdev->dev;
2097 struct musb *musb = dev_to_musb(dev);
2099 /* this gets called on rmmod.
2100 * - Host mode: host may still be active
2101 * - Peripheral mode: peripheral is deactivated (or never-activated)
2102 * - OTG mode: both roles are deactivated (or never-activated)
2104 musb_exit_debugfs(musb);
2105 musb_shutdown(pdev);
2107 if (musb->dma_controller)
2108 dma_controller_destroy(musb->dma_controller);
2110 cancel_work_sync(&musb->irq_work);
2111 cancel_delayed_work_sync(&musb->recover_work);
2112 cancel_delayed_work_sync(&musb->finish_resume_work);
2113 cancel_delayed_work_sync(&musb->deassert_reset_work);
2115 device_init_wakeup(dev, 0);
2121 static void musb_save_context(struct musb *musb)
2124 void __iomem *musb_base = musb->mregs;
2127 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2128 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2129 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2130 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2131 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2132 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2133 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2135 for (i = 0; i < musb->config->num_eps; ++i) {
2136 struct musb_hw_ep *hw_ep;
2138 hw_ep = &musb->endpoints[i];
2146 musb_writeb(musb_base, MUSB_INDEX, i);
2147 musb->context.index_regs[i].txmaxp =
2148 musb_readw(epio, MUSB_TXMAXP);
2149 musb->context.index_regs[i].txcsr =
2150 musb_readw(epio, MUSB_TXCSR);
2151 musb->context.index_regs[i].rxmaxp =
2152 musb_readw(epio, MUSB_RXMAXP);
2153 musb->context.index_regs[i].rxcsr =
2154 musb_readw(epio, MUSB_RXCSR);
2156 if (musb->dyn_fifo) {
2157 musb->context.index_regs[i].txfifoadd =
2158 musb_read_txfifoadd(musb_base);
2159 musb->context.index_regs[i].rxfifoadd =
2160 musb_read_rxfifoadd(musb_base);
2161 musb->context.index_regs[i].txfifosz =
2162 musb_read_txfifosz(musb_base);
2163 musb->context.index_regs[i].rxfifosz =
2164 musb_read_rxfifosz(musb_base);
2167 musb->context.index_regs[i].txtype =
2168 musb_readb(epio, MUSB_TXTYPE);
2169 musb->context.index_regs[i].txinterval =
2170 musb_readb(epio, MUSB_TXINTERVAL);
2171 musb->context.index_regs[i].rxtype =
2172 musb_readb(epio, MUSB_RXTYPE);
2173 musb->context.index_regs[i].rxinterval =
2174 musb_readb(epio, MUSB_RXINTERVAL);
2176 musb->context.index_regs[i].txfunaddr =
2177 musb_read_txfunaddr(musb_base, i);
2178 musb->context.index_regs[i].txhubaddr =
2179 musb_read_txhubaddr(musb_base, i);
2180 musb->context.index_regs[i].txhubport =
2181 musb_read_txhubport(musb_base, i);
2183 musb->context.index_regs[i].rxfunaddr =
2184 musb_read_rxfunaddr(musb_base, i);
2185 musb->context.index_regs[i].rxhubaddr =
2186 musb_read_rxhubaddr(musb_base, i);
2187 musb->context.index_regs[i].rxhubport =
2188 musb_read_rxhubport(musb_base, i);
2192 static void musb_restore_context(struct musb *musb)
2195 void __iomem *musb_base = musb->mregs;
2196 void __iomem *ep_target_regs;
2200 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2201 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2202 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2204 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2205 power = musb_readb(musb_base, MUSB_POWER);
2206 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2207 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2208 power |= musb->context.power;
2209 musb_writeb(musb_base, MUSB_POWER, power);
2211 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2212 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2213 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2214 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2216 for (i = 0; i < musb->config->num_eps; ++i) {
2217 struct musb_hw_ep *hw_ep;
2219 hw_ep = &musb->endpoints[i];
2227 musb_writeb(musb_base, MUSB_INDEX, i);
2228 musb_writew(epio, MUSB_TXMAXP,
2229 musb->context.index_regs[i].txmaxp);
2230 musb_writew(epio, MUSB_TXCSR,
2231 musb->context.index_regs[i].txcsr);
2232 musb_writew(epio, MUSB_RXMAXP,
2233 musb->context.index_regs[i].rxmaxp);
2234 musb_writew(epio, MUSB_RXCSR,
2235 musb->context.index_regs[i].rxcsr);
2237 if (musb->dyn_fifo) {
2238 musb_write_txfifosz(musb_base,
2239 musb->context.index_regs[i].txfifosz);
2240 musb_write_rxfifosz(musb_base,
2241 musb->context.index_regs[i].rxfifosz);
2242 musb_write_txfifoadd(musb_base,
2243 musb->context.index_regs[i].txfifoadd);
2244 musb_write_rxfifoadd(musb_base,
2245 musb->context.index_regs[i].rxfifoadd);
2248 musb_writeb(epio, MUSB_TXTYPE,
2249 musb->context.index_regs[i].txtype);
2250 musb_writeb(epio, MUSB_TXINTERVAL,
2251 musb->context.index_regs[i].txinterval);
2252 musb_writeb(epio, MUSB_RXTYPE,
2253 musb->context.index_regs[i].rxtype);
2254 musb_writeb(epio, MUSB_RXINTERVAL,
2256 musb->context.index_regs[i].rxinterval);
2257 musb_write_txfunaddr(musb_base, i,
2258 musb->context.index_regs[i].txfunaddr);
2259 musb_write_txhubaddr(musb_base, i,
2260 musb->context.index_regs[i].txhubaddr);
2261 musb_write_txhubport(musb_base, i,
2262 musb->context.index_regs[i].txhubport);
2265 musb_read_target_reg_base(i, musb_base);
2267 musb_write_rxfunaddr(ep_target_regs,
2268 musb->context.index_regs[i].rxfunaddr);
2269 musb_write_rxhubaddr(ep_target_regs,
2270 musb->context.index_regs[i].rxhubaddr);
2271 musb_write_rxhubport(ep_target_regs,
2272 musb->context.index_regs[i].rxhubport);
2274 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2277 static int musb_suspend(struct device *dev)
2279 struct musb *musb = dev_to_musb(dev);
2280 unsigned long flags;
2282 spin_lock_irqsave(&musb->lock, flags);
2284 if (is_peripheral_active(musb)) {
2285 /* FIXME force disconnect unless we know USB will wake
2286 * the system up quickly enough to respond ...
2288 } else if (is_host_active(musb)) {
2289 /* we know all the children are suspended; sometimes
2290 * they will even be wakeup-enabled.
2294 musb_save_context(musb);
2296 spin_unlock_irqrestore(&musb->lock, flags);
2300 static int musb_resume(struct device *dev)
2302 struct musb *musb = dev_to_musb(dev);
2305 * For static cmos like DaVinci, register values were preserved
2306 * unless for some reason the whole soc powered down or the USB
2307 * module got reset through the PSC (vs just being disabled).
2309 * For the DSPS glue layer though, a full register restore has to
2310 * be done. As it shouldn't harm other platforms, we do it
2314 musb_restore_context(musb);
2319 static int musb_runtime_suspend(struct device *dev)
2321 struct musb *musb = dev_to_musb(dev);
2323 musb_save_context(musb);
2328 static int musb_runtime_resume(struct device *dev)
2330 struct musb *musb = dev_to_musb(dev);
2331 static int first = 1;
2334 * When pm_runtime_get_sync called for the first time in driver
2335 * init, some of the structure is still not initialized which is
2336 * used in restore function. But clock needs to be
2337 * enabled before any register access, so
2338 * pm_runtime_get_sync has to be called.
2339 * Also context restore without save does not make
2343 musb_restore_context(musb);
2349 static const struct dev_pm_ops musb_dev_pm_ops = {
2350 .suspend = musb_suspend,
2351 .resume = musb_resume,
2352 .runtime_suspend = musb_runtime_suspend,
2353 .runtime_resume = musb_runtime_resume,
2356 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2358 #define MUSB_DEV_PM_OPS NULL
2361 static struct platform_driver musb_driver = {
2363 .name = (char *)musb_driver_name,
2364 .bus = &platform_bus_type,
2365 .owner = THIS_MODULE,
2366 .pm = MUSB_DEV_PM_OPS,
2368 .probe = musb_probe,
2369 .remove = musb_remove,
2370 .shutdown = musb_shutdown,
2373 module_platform_driver(musb_driver);