2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
125 #define MUSB_VERSION "6.0"
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
138 /*-------------------------------------------------------------------------*/
140 static inline struct musb *dev_to_musb(struct device *dev)
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
146 return dev_get_drvdata(dev);
150 /*-------------------------------------------------------------------------*/
152 #ifndef CONFIG_BLACKFIN
153 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
155 void __iomem *addr = otg->io_priv;
160 /* Make sure the transceiver is not in low power mode */
161 power = musb_readb(addr, MUSB_POWER);
162 power &= ~MUSB_POWER_SUSPENDM;
163 musb_writeb(addr, MUSB_POWER, power);
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
174 & MUSB_ULPI_REG_CMPLT)) {
177 DBG(3, "ULPI read timed out\n");
182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
183 r &= ~MUSB_ULPI_REG_CMPLT;
184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
186 return musb_readb(addr, MUSB_ULPI_REG_DATA);
189 static int musb_ulpi_write(struct otg_transceiver *otg,
190 u32 offset, u32 data)
192 void __iomem *addr = otg->io_priv;
197 /* Make sure the transceiver is not in low power mode */
198 power = musb_readb(addr, MUSB_POWER);
199 power &= ~MUSB_POWER_SUSPENDM;
200 musb_writeb(addr, MUSB_POWER, power);
202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
207 & MUSB_ULPI_REG_CMPLT)) {
210 DBG(3, "ULPI write timed out\n");
215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
216 r &= ~MUSB_ULPI_REG_CMPLT;
217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
222 #define musb_ulpi_read(a, b) NULL
223 #define musb_ulpi_write(a, b, c) NULL
226 static struct otg_io_access_ops musb_ulpi_access = {
227 .read = musb_ulpi_read,
228 .write = musb_ulpi_write,
231 /*-------------------------------------------------------------------------*/
233 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
236 * Load an endpoint's FIFO
238 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
240 void __iomem *fifo = hw_ep->fifo;
244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
268 musb_writeb(fifo, 0, src[index]);
271 writesb(fifo, src, len);
276 * Unload an endpoint's FIFO
278 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
280 void __iomem *fifo = hw_ep->fifo;
282 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
283 'R', hw_ep->epnum, fifo, len, dst);
285 /* we can't assume unaligned writes work */
286 if (likely((0x01 & (unsigned long) dst) == 0)) {
289 /* best case is 32bit-aligned destination address */
290 if ((0x02 & (unsigned long) dst) == 0) {
292 readsl(fifo, dst, len >> 2);
296 *(u16 *)&dst[index] = musb_readw(fifo, 0);
301 readsw(fifo, dst, len >> 1);
306 dst[index] = musb_readb(fifo, 0);
309 readsb(fifo, dst, len);
313 #endif /* normal PIO */
316 /*-------------------------------------------------------------------------*/
318 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
319 static const u8 musb_test_packet[53] = {
320 /* implicit SYNC then DATA0 to start */
323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
325 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
327 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
328 /* JJJJJJJKKKKKKK x8 */
329 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
331 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
332 /* JKKKKKKK x10, JK */
333 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
335 /* implicit CRC16 then EOP to end */
338 void musb_load_testpacket(struct musb *musb)
340 void __iomem *regs = musb->endpoints[0].regs;
342 musb_ep_select(musb->mregs, 0);
343 musb_write_fifo(musb->control_ep,
344 sizeof(musb_test_packet), musb_test_packet);
345 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
348 /*-------------------------------------------------------------------------*/
350 const char *otg_state_string(struct musb *musb)
352 switch (musb->xceiv->state) {
353 case OTG_STATE_A_IDLE: return "a_idle";
354 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
355 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
356 case OTG_STATE_A_HOST: return "a_host";
357 case OTG_STATE_A_SUSPEND: return "a_suspend";
358 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
359 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
360 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
361 case OTG_STATE_B_IDLE: return "b_idle";
362 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
363 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
364 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
365 case OTG_STATE_B_HOST: return "b_host";
366 default: return "UNDEFINED";
370 #ifdef CONFIG_USB_MUSB_OTG
373 * Handles OTG hnp timeouts, such as b_ase0_brst
375 void musb_otg_timer_func(unsigned long data)
377 struct musb *musb = (struct musb *)data;
380 spin_lock_irqsave(&musb->lock, flags);
381 switch (musb->xceiv->state) {
382 case OTG_STATE_B_WAIT_ACON:
383 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
384 musb_g_disconnect(musb);
385 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
388 case OTG_STATE_A_SUSPEND:
389 case OTG_STATE_A_WAIT_BCON:
390 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
391 musb_set_vbus(musb, 0);
392 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
395 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
397 musb->ignore_disconnect = 0;
398 spin_unlock_irqrestore(&musb->lock, flags);
402 * Stops the HNP transition. Caller must take care of locking.
404 void musb_hnp_stop(struct musb *musb)
406 struct usb_hcd *hcd = musb_to_hcd(musb);
407 void __iomem *mbase = musb->mregs;
410 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
412 switch (musb->xceiv->state) {
413 case OTG_STATE_A_PERIPHERAL:
414 musb_g_disconnect(musb);
415 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
417 case OTG_STATE_B_HOST:
418 DBG(1, "HNP: Disabling HR\n");
419 hcd->self.is_b_host = 0;
420 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
422 reg = musb_readb(mbase, MUSB_POWER);
423 reg |= MUSB_POWER_SUSPENDM;
424 musb_writeb(mbase, MUSB_POWER, reg);
425 /* REVISIT: Start SESSION_REQUEST here? */
428 DBG(1, "HNP: Stopping in unknown state %s\n",
429 otg_state_string(musb));
433 * When returning to A state after HNP, avoid hub_port_rebounce(),
434 * which cause occasional OPT A "Did not receive reset after connect"
437 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
443 * Interrupt Service Routine to record USB "global" interrupts.
444 * Since these do not happen often and signify things of
445 * paramount importance, it seems OK to check them individually;
446 * the order of the tests is specified in the manual
448 * @param musb instance pointer
449 * @param int_usb register contents
454 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
455 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
458 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
461 irqreturn_t handled = IRQ_NONE;
463 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
466 /* in host mode, the peripheral may issue remote wakeup.
467 * in peripheral mode, the host may resume the link.
468 * spurious RESUME irqs happen too, paired with SUSPEND.
470 if (int_usb & MUSB_INTR_RESUME) {
471 handled = IRQ_HANDLED;
472 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
474 if (devctl & MUSB_DEVCTL_HM) {
475 #ifdef CONFIG_USB_MUSB_HDRC_HCD
476 void __iomem *mbase = musb->mregs;
478 switch (musb->xceiv->state) {
479 case OTG_STATE_A_SUSPEND:
480 /* remote wakeup? later, GetPortStatus
481 * will stop RESUME signaling
484 if (power & MUSB_POWER_SUSPENDM) {
486 musb->int_usb &= ~MUSB_INTR_SUSPEND;
487 DBG(2, "Spurious SUSPENDM\n");
491 power &= ~MUSB_POWER_SUSPENDM;
492 musb_writeb(mbase, MUSB_POWER,
493 power | MUSB_POWER_RESUME);
495 musb->port1_status |=
496 (USB_PORT_STAT_C_SUSPEND << 16)
497 | MUSB_PORT_STAT_RESUME;
498 musb->rh_timer = jiffies
499 + msecs_to_jiffies(20);
501 musb->xceiv->state = OTG_STATE_A_HOST;
503 usb_hcd_resume_root_hub(musb_to_hcd(musb));
505 case OTG_STATE_B_WAIT_ACON:
506 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
511 WARNING("bogus %s RESUME (%s)\n",
513 otg_state_string(musb));
517 switch (musb->xceiv->state) {
518 #ifdef CONFIG_USB_MUSB_HDRC_HCD
519 case OTG_STATE_A_SUSPEND:
520 /* possibly DISCONNECT is upcoming */
521 musb->xceiv->state = OTG_STATE_A_HOST;
522 usb_hcd_resume_root_hub(musb_to_hcd(musb));
525 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
526 case OTG_STATE_B_WAIT_ACON:
527 case OTG_STATE_B_PERIPHERAL:
528 /* disconnect while suspended? we may
529 * not get a disconnect irq...
531 if ((devctl & MUSB_DEVCTL_VBUS)
532 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
534 musb->int_usb |= MUSB_INTR_DISCONNECT;
535 musb->int_usb &= ~MUSB_INTR_SUSPEND;
540 case OTG_STATE_B_IDLE:
541 musb->int_usb &= ~MUSB_INTR_SUSPEND;
545 WARNING("bogus %s RESUME (%s)\n",
547 otg_state_string(musb));
552 #ifdef CONFIG_USB_MUSB_HDRC_HCD
553 /* see manual for the order of the tests */
554 if (int_usb & MUSB_INTR_SESSREQ) {
555 void __iomem *mbase = musb->mregs;
557 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
559 /* IRQ arrives from ID pin sense or (later, if VBUS power
560 * is removed) SRP. responses are time critical:
561 * - turn on VBUS (with silicon-specific mechanism)
562 * - go through A_WAIT_VRISE
563 * - ... to A_WAIT_BCON.
564 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
566 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
567 musb->ep0_stage = MUSB_EP0_START;
568 musb->xceiv->state = OTG_STATE_A_IDLE;
570 musb_set_vbus(musb, 1);
572 handled = IRQ_HANDLED;
575 if (int_usb & MUSB_INTR_VBUSERROR) {
578 /* During connection as an A-Device, we may see a short
579 * current spikes causing voltage drop, because of cable
580 * and peripheral capacitance combined with vbus draw.
581 * (So: less common with truly self-powered devices, where
582 * vbus doesn't act like a power supply.)
584 * Such spikes are short; usually less than ~500 usec, max
585 * of ~2 msec. That is, they're not sustained overcurrent
586 * errors, though they're reported using VBUSERROR irqs.
588 * Workarounds: (a) hardware: use self powered devices.
589 * (b) software: ignore non-repeated VBUS errors.
591 * REVISIT: do delays from lots of DEBUG_KERNEL checks
592 * make trouble here, keeping VBUS < 4.4V ?
594 switch (musb->xceiv->state) {
595 case OTG_STATE_A_HOST:
596 /* recovery is dicey once we've gotten past the
597 * initial stages of enumeration, but if VBUS
598 * stayed ok at the other end of the link, and
599 * another reset is due (at least for high speed,
600 * to redo the chirp etc), it might work OK...
602 case OTG_STATE_A_WAIT_BCON:
603 case OTG_STATE_A_WAIT_VRISE:
604 if (musb->vbuserr_retry) {
605 void __iomem *mbase = musb->mregs;
607 musb->vbuserr_retry--;
609 devctl |= MUSB_DEVCTL_SESSION;
610 musb_writeb(mbase, MUSB_DEVCTL, devctl);
612 musb->port1_status |=
613 USB_PORT_STAT_OVERCURRENT
614 | (USB_PORT_STAT_C_OVERCURRENT << 16);
621 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
622 otg_state_string(musb),
625 switch (devctl & MUSB_DEVCTL_VBUS) {
626 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
627 s = "<SessEnd"; break;
628 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
629 s = "<AValid"; break;
630 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
631 s = "<VBusValid"; break;
632 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
636 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
639 /* go through A_WAIT_VFALL then start a new session */
641 musb_set_vbus(musb, 0);
642 handled = IRQ_HANDLED;
646 if (int_usb & MUSB_INTR_SUSPEND) {
647 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
648 otg_state_string(musb), devctl, power);
649 handled = IRQ_HANDLED;
651 switch (musb->xceiv->state) {
652 #ifdef CONFIG_USB_MUSB_OTG
653 case OTG_STATE_A_PERIPHERAL:
654 /* We also come here if the cable is removed, since
655 * this silicon doesn't report ID-no-longer-grounded.
657 * We depend on T(a_wait_bcon) to shut us down, and
658 * hope users don't do anything dicey during this
659 * undesired detour through A_WAIT_BCON.
662 usb_hcd_resume_root_hub(musb_to_hcd(musb));
663 musb_root_disconnect(musb);
664 musb_platform_try_idle(musb, jiffies
665 + msecs_to_jiffies(musb->a_wait_bcon
666 ? : OTG_TIME_A_WAIT_BCON));
670 case OTG_STATE_B_IDLE:
671 if (!musb->is_active)
673 case OTG_STATE_B_PERIPHERAL:
674 musb_g_suspend(musb);
675 musb->is_active = is_otg_enabled(musb)
676 && musb->xceiv->gadget->b_hnp_enable;
677 if (musb->is_active) {
678 #ifdef CONFIG_USB_MUSB_OTG
679 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
680 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
681 mod_timer(&musb->otg_timer, jiffies
683 OTG_TIME_B_ASE0_BRST));
687 case OTG_STATE_A_WAIT_BCON:
688 if (musb->a_wait_bcon != 0)
689 musb_platform_try_idle(musb, jiffies
690 + msecs_to_jiffies(musb->a_wait_bcon));
692 case OTG_STATE_A_HOST:
693 musb->xceiv->state = OTG_STATE_A_SUSPEND;
694 musb->is_active = is_otg_enabled(musb)
695 && musb->xceiv->host->b_hnp_enable;
697 case OTG_STATE_B_HOST:
698 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
699 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
702 /* "should not happen" */
708 if (int_usb & MUSB_INTR_CONNECT) {
709 struct usb_hcd *hcd = musb_to_hcd(musb);
710 void __iomem *mbase = musb->mregs;
712 handled = IRQ_HANDLED;
714 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
716 musb->ep0_stage = MUSB_EP0_START;
718 #ifdef CONFIG_USB_MUSB_OTG
719 /* flush endpoints when transitioning from Device Mode */
720 if (is_peripheral_active(musb)) {
721 /* REVISIT HNP; just force disconnect */
723 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
724 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
725 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
727 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
728 |USB_PORT_STAT_HIGH_SPEED
729 |USB_PORT_STAT_ENABLE
731 musb->port1_status |= USB_PORT_STAT_CONNECTION
732 |(USB_PORT_STAT_C_CONNECTION << 16);
734 /* high vs full speed is just a guess until after reset */
735 if (devctl & MUSB_DEVCTL_LSDEV)
736 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
738 /* indicate new connection to OTG machine */
739 switch (musb->xceiv->state) {
740 case OTG_STATE_B_PERIPHERAL:
741 if (int_usb & MUSB_INTR_SUSPEND) {
742 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
743 int_usb &= ~MUSB_INTR_SUSPEND;
746 DBG(1, "CONNECT as b_peripheral???\n");
748 case OTG_STATE_B_WAIT_ACON:
749 DBG(1, "HNP: CONNECT, now b_host\n");
751 musb->xceiv->state = OTG_STATE_B_HOST;
752 hcd->self.is_b_host = 1;
753 musb->ignore_disconnect = 0;
754 del_timer(&musb->otg_timer);
757 if ((devctl & MUSB_DEVCTL_VBUS)
758 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
759 musb->xceiv->state = OTG_STATE_A_HOST;
760 hcd->self.is_b_host = 0;
765 /* poke the root hub */
768 usb_hcd_poll_rh_status(hcd);
770 usb_hcd_resume_root_hub(hcd);
772 DBG(1, "CONNECT (%s) devctl %02x\n",
773 otg_state_string(musb), devctl);
775 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
777 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
778 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
779 otg_state_string(musb),
780 MUSB_MODE(musb), devctl);
781 handled = IRQ_HANDLED;
783 switch (musb->xceiv->state) {
784 #ifdef CONFIG_USB_MUSB_HDRC_HCD
785 case OTG_STATE_A_HOST:
786 case OTG_STATE_A_SUSPEND:
787 usb_hcd_resume_root_hub(musb_to_hcd(musb));
788 musb_root_disconnect(musb);
789 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
790 musb_platform_try_idle(musb, jiffies
791 + msecs_to_jiffies(musb->a_wait_bcon));
794 #ifdef CONFIG_USB_MUSB_OTG
795 case OTG_STATE_B_HOST:
796 /* REVISIT this behaves for "real disconnect"
797 * cases; make sure the other transitions from
798 * from B_HOST act right too. The B_HOST code
799 * in hnp_stop() is currently not used...
801 musb_root_disconnect(musb);
802 musb_to_hcd(musb)->self.is_b_host = 0;
803 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
805 musb_g_disconnect(musb);
807 case OTG_STATE_A_PERIPHERAL:
809 musb_root_disconnect(musb);
811 case OTG_STATE_B_WAIT_ACON:
814 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
815 case OTG_STATE_B_PERIPHERAL:
816 case OTG_STATE_B_IDLE:
817 musb_g_disconnect(musb);
821 WARNING("unhandled DISCONNECT transition (%s)\n",
822 otg_state_string(musb));
827 /* mentor saves a bit: bus reset and babble share the same irq.
828 * only host sees babble; only peripheral sees bus reset.
830 if (int_usb & MUSB_INTR_RESET) {
831 handled = IRQ_HANDLED;
832 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
834 * Looks like non-HS BABBLE can be ignored, but
835 * HS BABBLE is an error condition. For HS the solution
836 * is to avoid babble in the first place and fix what
837 * caused BABBLE. When HS BABBLE happens we can only
840 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
841 DBG(1, "BABBLE devctl: %02x\n", devctl);
843 ERR("Stopping host session -- babble\n");
844 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
846 } else if (is_peripheral_capable()) {
847 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
848 switch (musb->xceiv->state) {
849 #ifdef CONFIG_USB_OTG
850 case OTG_STATE_A_SUSPEND:
851 /* We need to ignore disconnect on suspend
852 * otherwise tusb 2.0 won't reconnect after a
853 * power cycle, which breaks otg compliance.
855 musb->ignore_disconnect = 1;
858 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
859 /* never use invalid T(a_wait_bcon) */
860 DBG(1, "HNP: in %s, %d msec timeout\n",
861 otg_state_string(musb),
863 mod_timer(&musb->otg_timer, jiffies
864 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
866 case OTG_STATE_A_PERIPHERAL:
867 musb->ignore_disconnect = 0;
868 del_timer(&musb->otg_timer);
871 case OTG_STATE_B_WAIT_ACON:
872 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
873 otg_state_string(musb));
874 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
878 case OTG_STATE_B_IDLE:
879 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
881 case OTG_STATE_B_PERIPHERAL:
885 DBG(1, "Unhandled BUS RESET as %s\n",
886 otg_state_string(musb));
892 /* REVISIT ... this would be for multiplexing periodic endpoints, or
893 * supporting transfer phasing to prevent exceeding ISO bandwidth
894 * limits of a given frame or microframe.
896 * It's not needed for peripheral side, which dedicates endpoints;
897 * though it _might_ use SOF irqs for other purposes.
899 * And it's not currently needed for host side, which also dedicates
900 * endpoints, relies on TX/RX interval registers, and isn't claimed
901 * to support ISO transfers yet.
903 if (int_usb & MUSB_INTR_SOF) {
904 void __iomem *mbase = musb->mregs;
905 struct musb_hw_ep *ep;
909 DBG(6, "START_OF_FRAME\n");
910 handled = IRQ_HANDLED;
912 /* start any periodic Tx transfers waiting for current frame */
913 frame = musb_readw(mbase, MUSB_FRAME);
914 ep = musb->endpoints;
915 for (epnum = 1; (epnum < musb->nr_endpoints)
916 && (musb->epmask >= (1 << epnum));
919 * FIXME handle framecounter wraps (12 bits)
920 * eliminate duplicated StartUrb logic
922 if (ep->dwWaitFrame >= frame) {
924 pr_debug("SOF --> periodic TX%s on %d\n",
925 ep->tx_channel ? " DMA" : "",
928 musb_h_tx_start(musb, epnum);
930 cppi_hostdma_start(musb, epnum);
932 } /* end of for loop */
936 schedule_work(&musb->irq_work);
941 /*-------------------------------------------------------------------------*/
944 * Program the HDRC to start (enable interrupts, dma, etc.).
946 void musb_start(struct musb *musb)
948 void __iomem *regs = musb->mregs;
949 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
951 DBG(2, "<== devctl %02x\n", devctl);
953 /* Set INT enable registers, enable interrupts */
954 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
955 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
956 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
958 musb_writeb(regs, MUSB_TESTMODE, 0);
960 /* put into basic highspeed mode and start session */
961 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
962 | MUSB_POWER_SOFTCONN
964 /* ENSUSPEND wedges tusb */
965 /* | MUSB_POWER_ENSUSPEND */
969 devctl = musb_readb(regs, MUSB_DEVCTL);
970 devctl &= ~MUSB_DEVCTL_SESSION;
972 if (is_otg_enabled(musb)) {
973 /* session started after:
974 * (a) ID-grounded irq, host mode;
975 * (b) vbus present/connect IRQ, peripheral mode;
976 * (c) peripheral initiates, using SRP
978 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
981 devctl |= MUSB_DEVCTL_SESSION;
983 } else if (is_host_enabled(musb)) {
984 /* assume ID pin is hard-wired to ground */
985 devctl |= MUSB_DEVCTL_SESSION;
987 } else /* peripheral is enabled */ {
988 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
991 musb_platform_enable(musb);
992 musb_writeb(regs, MUSB_DEVCTL, devctl);
996 static void musb_generic_disable(struct musb *musb)
998 void __iomem *mbase = musb->mregs;
1001 /* disable interrupts */
1002 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1003 musb_writew(mbase, MUSB_INTRTXE, 0);
1004 musb_writew(mbase, MUSB_INTRRXE, 0);
1007 musb_writeb(mbase, MUSB_DEVCTL, 0);
1009 /* flush pending interrupts */
1010 temp = musb_readb(mbase, MUSB_INTRUSB);
1011 temp = musb_readw(mbase, MUSB_INTRTX);
1012 temp = musb_readw(mbase, MUSB_INTRRX);
1017 * Make the HDRC stop (disable interrupts, etc.);
1018 * reversible by musb_start
1019 * called on gadget driver unregister
1020 * with controller locked, irqs blocked
1021 * acts as a NOP unless some role activated the hardware
1023 void musb_stop(struct musb *musb)
1025 /* stop IRQs, timers, ... */
1026 musb_platform_disable(musb);
1027 musb_generic_disable(musb);
1028 DBG(3, "HDRC disabled\n");
1031 * - mark host and/or peripheral drivers unusable/inactive
1032 * - disable DMA (and enable it in HdrcStart)
1033 * - make sure we can musb_start() after musb_stop(); with
1034 * OTG mode, gadget driver module rmmod/modprobe cycles that
1037 musb_platform_try_idle(musb, 0);
1040 static void musb_shutdown(struct platform_device *pdev)
1042 struct musb *musb = dev_to_musb(&pdev->dev);
1043 unsigned long flags;
1045 spin_lock_irqsave(&musb->lock, flags);
1046 musb_platform_disable(musb);
1047 musb_generic_disable(musb);
1049 clk_put(musb->clock);
1050 spin_unlock_irqrestore(&musb->lock, flags);
1052 /* FIXME power down */
1056 /*-------------------------------------------------------------------------*/
1059 * The silicon either has hard-wired endpoint configurations, or else
1060 * "dynamic fifo" sizing. The driver has support for both, though at this
1061 * writing only the dynamic sizing is very well tested. Since we switched
1062 * away from compile-time hardware parameters, we can no longer rely on
1063 * dead code elimination to leave only the relevant one in the object file.
1065 * We don't currently use dynamic fifo setup capability to do anything
1066 * more than selecting one of a bunch of predefined configurations.
1068 #if defined(CONFIG_USB_TUSB6010) || \
1069 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1070 || defined(CONFIG_ARCH_OMAP4)
1071 static ushort __initdata fifo_mode = 4;
1073 static ushort __initdata fifo_mode = 2;
1076 /* "modprobe ... fifo_mode=1" etc */
1077 module_param(fifo_mode, ushort, 0);
1078 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1081 * tables defining fifo_mode values. define more if you like.
1082 * for host side, make sure both halves of ep1 are set up.
1085 /* mode 0 - fits in 2KB */
1086 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1087 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1088 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1089 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1090 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1091 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1094 /* mode 1 - fits in 4KB */
1095 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1096 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1097 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1098 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1099 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1100 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1103 /* mode 2 - fits in 4KB */
1104 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1105 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1110 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1113 /* mode 3 - fits in 4KB */
1114 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1115 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1116 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1117 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1118 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1119 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1120 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1123 /* mode 4 - fits in 16KB */
1124 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1125 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1142 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1143 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1144 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1145 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1146 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1147 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1148 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1149 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1150 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1151 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1154 /* mode 5 - fits in 8KB */
1155 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1156 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1157 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1158 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1161 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1162 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1163 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1164 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1165 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1166 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1167 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1168 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1169 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1170 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1171 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1172 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1173 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1174 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1175 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1176 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1177 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1178 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1179 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1180 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1181 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1182 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1186 * configure a fifo; for non-shared endpoints, this may be called
1187 * once for a tx fifo and once for an rx fifo.
1189 * returns negative errno or offset for next fifo.
1192 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1193 const struct musb_fifo_cfg *cfg, u16 offset)
1195 void __iomem *mbase = musb->mregs;
1197 u16 maxpacket = cfg->maxpacket;
1198 u16 c_off = offset >> 3;
1201 /* expect hw_ep has already been zero-initialized */
1203 size = ffs(max(maxpacket, (u16) 8)) - 1;
1204 maxpacket = 1 << size;
1207 if (cfg->mode == BUF_DOUBLE) {
1208 if ((offset + (maxpacket << 1)) >
1209 (1 << (musb->config->ram_bits + 2)))
1211 c_size |= MUSB_FIFOSZ_DPB;
1213 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1217 /* configure the FIFO */
1218 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1220 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1221 /* EP0 reserved endpoint for control, bidirectional;
1222 * EP1 reserved for bulk, two unidirection halves.
1224 if (hw_ep->epnum == 1)
1225 musb->bulk_ep = hw_ep;
1226 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1228 switch (cfg->style) {
1230 musb_write_txfifosz(mbase, c_size);
1231 musb_write_txfifoadd(mbase, c_off);
1232 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1233 hw_ep->max_packet_sz_tx = maxpacket;
1236 musb_write_rxfifosz(mbase, c_size);
1237 musb_write_rxfifoadd(mbase, c_off);
1238 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1239 hw_ep->max_packet_sz_rx = maxpacket;
1242 musb_write_txfifosz(mbase, c_size);
1243 musb_write_txfifoadd(mbase, c_off);
1244 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1245 hw_ep->max_packet_sz_rx = maxpacket;
1247 musb_write_rxfifosz(mbase, c_size);
1248 musb_write_rxfifoadd(mbase, c_off);
1249 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1250 hw_ep->max_packet_sz_tx = maxpacket;
1252 hw_ep->is_shared_fifo = true;
1256 /* NOTE rx and tx endpoint irqs aren't managed separately,
1257 * which happens to be ok
1259 musb->epmask |= (1 << hw_ep->epnum);
1261 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1264 static struct musb_fifo_cfg __initdata ep0_cfg = {
1265 .style = FIFO_RXTX, .maxpacket = 64,
1268 static int __init ep_config_from_table(struct musb *musb)
1270 const struct musb_fifo_cfg *cfg;
1273 struct musb_hw_ep *hw_ep = musb->endpoints;
1275 if (musb->config->fifo_cfg) {
1276 cfg = musb->config->fifo_cfg;
1277 n = musb->config->fifo_cfg_size;
1281 switch (fifo_mode) {
1287 n = ARRAY_SIZE(mode_0_cfg);
1291 n = ARRAY_SIZE(mode_1_cfg);
1295 n = ARRAY_SIZE(mode_2_cfg);
1299 n = ARRAY_SIZE(mode_3_cfg);
1303 n = ARRAY_SIZE(mode_4_cfg);
1307 n = ARRAY_SIZE(mode_5_cfg);
1311 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1312 musb_driver_name, fifo_mode);
1316 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1317 /* assert(offset > 0) */
1319 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1320 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1323 for (i = 0; i < n; i++) {
1324 u8 epn = cfg->hw_ep_num;
1326 if (epn >= musb->config->num_eps) {
1327 pr_debug("%s: invalid ep %d\n",
1328 musb_driver_name, epn);
1331 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1333 pr_debug("%s: mem overrun, ep %d\n",
1334 musb_driver_name, epn);
1338 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1341 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1343 n + 1, musb->config->num_eps * 2 - 1,
1344 offset, (1 << (musb->config->ram_bits + 2)));
1346 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1347 if (!musb->bulk_ep) {
1348 pr_debug("%s: missing bulk\n", musb_driver_name);
1358 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1359 * @param musb the controller
1361 static int __init ep_config_from_hw(struct musb *musb)
1364 struct musb_hw_ep *hw_ep;
1365 void *mbase = musb->mregs;
1368 DBG(2, "<== static silicon ep config\n");
1370 /* FIXME pick up ep0 maxpacket size */
1372 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1373 musb_ep_select(mbase, epnum);
1374 hw_ep = musb->endpoints + epnum;
1376 ret = musb_read_fifosize(musb, hw_ep, epnum);
1380 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1382 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1383 /* pick an RX/TX endpoint for bulk */
1384 if (hw_ep->max_packet_sz_tx < 512
1385 || hw_ep->max_packet_sz_rx < 512)
1388 /* REVISIT: this algorithm is lazy, we should at least
1389 * try to pick a double buffered endpoint.
1393 musb->bulk_ep = hw_ep;
1397 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1398 if (!musb->bulk_ep) {
1399 pr_debug("%s: missing bulk\n", musb_driver_name);
1407 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1409 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1410 * configure endpoints, or take their config from silicon
1412 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1416 char aInfo[90], aRevision[32], aDate[12];
1417 void __iomem *mbase = musb->mregs;
1421 /* log core options (read using indexed model) */
1422 reg = musb_read_configdata(mbase);
1424 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1425 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1426 strcat(aInfo, ", dyn FIFOs");
1427 musb->dyn_fifo = true;
1429 if (reg & MUSB_CONFIGDATA_MPRXE) {
1430 strcat(aInfo, ", bulk combine");
1431 musb->bulk_combine = true;
1433 if (reg & MUSB_CONFIGDATA_MPTXE) {
1434 strcat(aInfo, ", bulk split");
1435 musb->bulk_split = true;
1437 if (reg & MUSB_CONFIGDATA_HBRXE) {
1438 strcat(aInfo, ", HB-ISO Rx");
1439 musb->hb_iso_rx = true;
1441 if (reg & MUSB_CONFIGDATA_HBTXE) {
1442 strcat(aInfo, ", HB-ISO Tx");
1443 musb->hb_iso_tx = true;
1445 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1446 strcat(aInfo, ", SoftConn");
1448 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1449 musb_driver_name, reg, aInfo);
1452 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1453 musb->is_multipoint = 1;
1456 musb->is_multipoint = 0;
1458 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1459 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1461 "%s: kernel must blacklist external hubs\n",
1467 /* log release info */
1468 musb->hwvers = musb_read_hwvers(mbase);
1469 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1470 MUSB_HWVERS_MINOR(musb->hwvers),
1471 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1472 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1473 musb_driver_name, type, aRevision, aDate);
1476 musb_configure_ep0(musb);
1478 /* discover endpoint configuration */
1479 musb->nr_endpoints = 1;
1483 status = ep_config_from_table(musb);
1485 status = ep_config_from_hw(musb);
1490 /* finish init, and print endpoint config */
1491 for (i = 0; i < musb->nr_endpoints; i++) {
1492 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1494 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1495 #ifdef CONFIG_USB_TUSB6010
1496 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1497 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1498 hw_ep->fifo_sync_va =
1499 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1502 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1504 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1507 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1508 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1509 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1510 hw_ep->rx_reinit = 1;
1511 hw_ep->tx_reinit = 1;
1514 if (hw_ep->max_packet_sz_tx) {
1516 "%s: hw_ep %d%s, %smax %d\n",
1517 musb_driver_name, i,
1518 hw_ep->is_shared_fifo ? "shared" : "tx",
1519 hw_ep->tx_double_buffered
1520 ? "doublebuffer, " : "",
1521 hw_ep->max_packet_sz_tx);
1523 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1525 "%s: hw_ep %d%s, %smax %d\n",
1526 musb_driver_name, i,
1528 hw_ep->rx_double_buffered
1529 ? "doublebuffer, " : "",
1530 hw_ep->max_packet_sz_rx);
1532 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1533 DBG(1, "hw_ep %d not configured\n", i);
1539 /*-------------------------------------------------------------------------*/
1541 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1542 defined(CONFIG_ARCH_OMAP4)
1544 static irqreturn_t generic_interrupt(int irq, void *__hci)
1546 unsigned long flags;
1547 irqreturn_t retval = IRQ_NONE;
1548 struct musb *musb = __hci;
1550 spin_lock_irqsave(&musb->lock, flags);
1552 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1553 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1554 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1556 if (musb->int_usb || musb->int_tx || musb->int_rx)
1557 retval = musb_interrupt(musb);
1559 spin_unlock_irqrestore(&musb->lock, flags);
1565 #define generic_interrupt NULL
1569 * handle all the irqs defined by the HDRC core. for now we expect: other
1570 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1571 * will be assigned, and the irq will already have been acked.
1573 * called in irq context with spinlock held, irqs blocked
1575 irqreturn_t musb_interrupt(struct musb *musb)
1577 irqreturn_t retval = IRQ_NONE;
1582 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1583 power = musb_readb(musb->mregs, MUSB_POWER);
1585 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1586 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1587 musb->int_usb, musb->int_tx, musb->int_rx);
1589 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1590 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1591 if (!musb->gadget_driver) {
1592 DBG(5, "No gadget driver loaded\n");
1597 /* the core can interrupt us for multiple reasons; docs have
1598 * a generic interrupt flowchart to follow
1600 if (musb->int_usb & STAGE0_MASK)
1601 retval |= musb_stage0_irq(musb, musb->int_usb,
1604 /* "stage 1" is handling endpoint irqs */
1606 /* handle endpoint 0 first */
1607 if (musb->int_tx & 1) {
1608 if (devctl & MUSB_DEVCTL_HM)
1609 retval |= musb_h_ep0_irq(musb);
1611 retval |= musb_g_ep0_irq(musb);
1614 /* RX on endpoints 1-15 */
1615 reg = musb->int_rx >> 1;
1619 /* musb_ep_select(musb->mregs, ep_num); */
1620 /* REVISIT just retval = ep->rx_irq(...) */
1621 retval = IRQ_HANDLED;
1622 if (devctl & MUSB_DEVCTL_HM) {
1623 if (is_host_capable())
1624 musb_host_rx(musb, ep_num);
1626 if (is_peripheral_capable())
1627 musb_g_rx(musb, ep_num);
1635 /* TX on endpoints 1-15 */
1636 reg = musb->int_tx >> 1;
1640 /* musb_ep_select(musb->mregs, ep_num); */
1641 /* REVISIT just retval |= ep->tx_irq(...) */
1642 retval = IRQ_HANDLED;
1643 if (devctl & MUSB_DEVCTL_HM) {
1644 if (is_host_capable())
1645 musb_host_tx(musb, ep_num);
1647 if (is_peripheral_capable())
1648 musb_g_tx(musb, ep_num);
1659 #ifndef CONFIG_MUSB_PIO_ONLY
1660 static int __initdata use_dma = 1;
1662 /* "modprobe ... use_dma=0" etc */
1663 module_param(use_dma, bool, 0);
1664 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1666 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1668 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1670 /* called with controller lock already held */
1673 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1674 if (!is_cppi_enabled()) {
1676 if (devctl & MUSB_DEVCTL_HM)
1677 musb_h_ep0_irq(musb);
1679 musb_g_ep0_irq(musb);
1683 /* endpoints 1..15 */
1685 if (devctl & MUSB_DEVCTL_HM) {
1686 if (is_host_capable())
1687 musb_host_tx(musb, epnum);
1689 if (is_peripheral_capable())
1690 musb_g_tx(musb, epnum);
1694 if (devctl & MUSB_DEVCTL_HM) {
1695 if (is_host_capable())
1696 musb_host_rx(musb, epnum);
1698 if (is_peripheral_capable())
1699 musb_g_rx(musb, epnum);
1709 /*-------------------------------------------------------------------------*/
1714 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1716 struct musb *musb = dev_to_musb(dev);
1717 unsigned long flags;
1720 spin_lock_irqsave(&musb->lock, flags);
1721 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1722 spin_unlock_irqrestore(&musb->lock, flags);
1728 musb_mode_store(struct device *dev, struct device_attribute *attr,
1729 const char *buf, size_t n)
1731 struct musb *musb = dev_to_musb(dev);
1732 unsigned long flags;
1735 spin_lock_irqsave(&musb->lock, flags);
1736 if (sysfs_streq(buf, "host"))
1737 status = musb_platform_set_mode(musb, MUSB_HOST);
1738 else if (sysfs_streq(buf, "peripheral"))
1739 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1740 else if (sysfs_streq(buf, "otg"))
1741 status = musb_platform_set_mode(musb, MUSB_OTG);
1744 spin_unlock_irqrestore(&musb->lock, flags);
1746 return (status == 0) ? n : status;
1748 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1751 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1752 const char *buf, size_t n)
1754 struct musb *musb = dev_to_musb(dev);
1755 unsigned long flags;
1758 if (sscanf(buf, "%lu", &val) < 1) {
1759 dev_err(dev, "Invalid VBUS timeout ms value\n");
1763 spin_lock_irqsave(&musb->lock, flags);
1764 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1765 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1766 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1767 musb->is_active = 0;
1768 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1769 spin_unlock_irqrestore(&musb->lock, flags);
1775 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1777 struct musb *musb = dev_to_musb(dev);
1778 unsigned long flags;
1782 spin_lock_irqsave(&musb->lock, flags);
1783 val = musb->a_wait_bcon;
1784 /* FIXME get_vbus_status() is normally #defined as false...
1785 * and is effectively TUSB-specific.
1787 vbus = musb_platform_get_vbus_status(musb);
1788 spin_unlock_irqrestore(&musb->lock, flags);
1790 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1791 vbus ? "on" : "off", val);
1793 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1795 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1797 /* Gadget drivers can't know that a host is connected so they might want
1798 * to start SRP, but users can. This allows userspace to trigger SRP.
1801 musb_srp_store(struct device *dev, struct device_attribute *attr,
1802 const char *buf, size_t n)
1804 struct musb *musb = dev_to_musb(dev);
1807 if (sscanf(buf, "%hu", &srp) != 1
1809 dev_err(dev, "SRP: Value must be 1\n");
1814 musb_g_wakeup(musb);
1818 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1820 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1822 static struct attribute *musb_attributes[] = {
1823 &dev_attr_mode.attr,
1824 &dev_attr_vbus.attr,
1825 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1831 static const struct attribute_group musb_attr_group = {
1832 .attrs = musb_attributes,
1837 /* Only used to provide driver mode change events */
1838 static void musb_irq_work(struct work_struct *data)
1840 struct musb *musb = container_of(data, struct musb, irq_work);
1841 static int old_state;
1843 if (musb->xceiv->state != old_state) {
1844 old_state = musb->xceiv->state;
1845 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1849 /* --------------------------------------------------------------------------
1853 static struct musb *__init
1854 allocate_instance(struct device *dev,
1855 struct musb_hdrc_config *config, void __iomem *mbase)
1858 struct musb_hw_ep *ep;
1860 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1861 struct usb_hcd *hcd;
1863 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1866 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1868 musb = hcd_to_musb(hcd);
1869 INIT_LIST_HEAD(&musb->control);
1870 INIT_LIST_HEAD(&musb->in_bulk);
1871 INIT_LIST_HEAD(&musb->out_bulk);
1873 hcd->uses_new_polling = 1;
1875 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1876 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1878 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1881 dev_set_drvdata(dev, musb);
1885 musb->mregs = mbase;
1886 musb->ctrl_base = mbase;
1887 musb->nIrq = -ENODEV;
1888 musb->config = config;
1889 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1890 for (epnum = 0, ep = musb->endpoints;
1891 epnum < musb->config->num_eps;
1897 musb->controller = dev;
1901 static void musb_free(struct musb *musb)
1903 /* this has multiple entry modes. it handles fault cleanup after
1904 * probe(), where things may be partially set up, as well as rmmod
1905 * cleanup after everything's been de-activated.
1909 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1912 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1913 musb_gadget_cleanup(musb);
1916 if (musb->nIrq >= 0) {
1918 disable_irq_wake(musb->nIrq);
1919 free_irq(musb->nIrq, musb);
1921 if (is_dma_capable() && musb->dma_controller) {
1922 struct dma_controller *c = musb->dma_controller;
1925 dma_controller_destroy(c);
1928 #ifdef CONFIG_USB_MUSB_OTG
1929 put_device(musb->xceiv->dev);
1932 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1933 usb_put_hcd(musb_to_hcd(musb));
1940 * Perform generic per-controller initialization.
1942 * @pDevice: the controller (already clocked, etc)
1944 * @mregs: virtual address of controller registers,
1945 * not yet corrected for platform-specific offsets
1948 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1952 struct musb_hdrc_platform_data *plat = dev->platform_data;
1954 /* The driver might handle more features than the board; OK.
1955 * Fail when the board needs a feature that's not enabled.
1958 dev_dbg(dev, "no platform_data?\n");
1963 switch (plat->mode) {
1965 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1970 case MUSB_PERIPHERAL:
1971 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1977 #ifdef CONFIG_USB_MUSB_OTG
1983 dev_err(dev, "incompatible Kconfig role setting\n");
1989 musb = allocate_instance(dev, plat->config, ctrl);
1995 spin_lock_init(&musb->lock);
1996 musb->board_mode = plat->mode;
1997 musb->board_set_power = plat->set_power;
1998 musb->set_clock = plat->set_clock;
1999 musb->min_power = plat->min_power;
2001 /* Clock usage is chip-specific ... functional clock (DaVinci,
2002 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2003 * code does is make sure a clock handle is available; platform
2004 * code manages it during start/stop and suspend/resume.
2007 musb->clock = clk_get(dev, plat->clock);
2008 if (IS_ERR(musb->clock)) {
2009 status = PTR_ERR(musb->clock);
2015 /* The musb_platform_init() call:
2016 * - adjusts musb->mregs and musb->isr if needed,
2017 * - may initialize an integrated tranceiver
2018 * - initializes musb->xceiv, usually by otg_get_transceiver()
2019 * - activates clocks.
2020 * - stops powering VBUS
2021 * - assigns musb->board_set_vbus if host mode is enabled
2023 * There are various transciever configurations. Blackfin,
2024 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2025 * external/discrete ones in various flavors (twl4030 family,
2026 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2028 musb->isr = generic_interrupt;
2029 status = musb_platform_init(musb, plat->board_data);
2038 if (!musb->xceiv->io_ops) {
2039 musb->xceiv->io_priv = musb->mregs;
2040 musb->xceiv->io_ops = &musb_ulpi_access;
2043 #ifndef CONFIG_MUSB_PIO_ONLY
2044 if (use_dma && dev->dma_mask) {
2045 struct dma_controller *c;
2047 c = dma_controller_create(musb, musb->mregs);
2048 musb->dma_controller = c;
2053 /* ideally this would be abstracted in platform setup */
2054 if (!is_dma_capable() || !musb->dma_controller)
2055 dev->dma_mask = NULL;
2057 /* be sure interrupts are disabled before connecting ISR */
2058 musb_platform_disable(musb);
2059 musb_generic_disable(musb);
2061 /* setup musb parts of the core (especially endpoints) */
2062 status = musb_core_init(plat->config->multipoint
2063 ? MUSB_CONTROLLER_MHDRC
2064 : MUSB_CONTROLLER_HDRC, musb);
2068 #ifdef CONFIG_USB_MUSB_OTG
2069 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2072 /* Init IRQ workqueue before request_irq */
2073 INIT_WORK(&musb->irq_work, musb_irq_work);
2075 /* attach to the IRQ */
2076 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2077 dev_err(dev, "request_irq %d failed!\n", nIrq);
2082 /* FIXME this handles wakeup irqs wrong */
2083 if (enable_irq_wake(nIrq) == 0) {
2085 device_init_wakeup(dev, 1);
2090 /* host side needs more setup */
2091 if (is_host_enabled(musb)) {
2092 struct usb_hcd *hcd = musb_to_hcd(musb);
2094 otg_set_host(musb->xceiv, &hcd->self);
2096 if (is_otg_enabled(musb))
2097 hcd->self.otg_port = 1;
2098 musb->xceiv->host = &hcd->self;
2099 hcd->power_budget = 2 * (plat->power ? : 250);
2101 /* program PHY to use external vBus if required */
2102 if (plat->extvbus) {
2103 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2104 busctl |= MUSB_ULPI_USE_EXTVBUS;
2105 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2109 /* For the host-only role, we can activate right away.
2110 * (We expect the ID pin to be forcibly grounded!!)
2111 * Otherwise, wait till the gadget driver hooks up.
2113 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2114 MUSB_HST_MODE(musb);
2115 musb->xceiv->default_a = 1;
2116 musb->xceiv->state = OTG_STATE_A_IDLE;
2118 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2120 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2122 musb_readb(musb->mregs, MUSB_DEVCTL),
2123 (musb_readb(musb->mregs, MUSB_DEVCTL)
2124 & MUSB_DEVCTL_BDEVICE
2127 } else /* peripheral is enabled */ {
2128 MUSB_DEV_MODE(musb);
2129 musb->xceiv->default_a = 0;
2130 musb->xceiv->state = OTG_STATE_B_IDLE;
2132 status = musb_gadget_setup(musb);
2134 DBG(1, "%s mode, status %d, dev%02x\n",
2135 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2137 musb_readb(musb->mregs, MUSB_DEVCTL));
2143 status = musb_init_debugfs(musb);
2148 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2153 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2155 switch (musb->board_mode) {
2156 case MUSB_HOST: s = "Host"; break;
2157 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2158 default: s = "OTG"; break;
2161 (is_dma_capable() && musb->dma_controller)
2168 musb_exit_debugfs(musb);
2171 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2172 usb_remove_hcd(musb_to_hcd(musb));
2174 musb_gadget_cleanup(musb);
2178 device_init_wakeup(dev, 0);
2179 musb_platform_exit(musb);
2183 clk_put(musb->clock);
2186 dev_err(musb->controller,
2187 "musb_init_controller failed with status %d\n", status);
2197 /*-------------------------------------------------------------------------*/
2199 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2200 * bridge to a platform device; this driver then suffices.
2203 #ifndef CONFIG_MUSB_PIO_ONLY
2204 static u64 *orig_dma_mask;
2207 static int __init musb_probe(struct platform_device *pdev)
2209 struct device *dev = &pdev->dev;
2210 int irq = platform_get_irq(pdev, 0);
2212 struct resource *iomem;
2215 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2216 if (!iomem || irq == 0)
2219 base = ioremap(iomem->start, resource_size(iomem));
2221 dev_err(dev, "ioremap failed\n");
2225 #ifndef CONFIG_MUSB_PIO_ONLY
2226 /* clobbered by use_dma=n */
2227 orig_dma_mask = dev->dma_mask;
2229 status = musb_init_controller(dev, irq, base);
2236 static int __exit musb_remove(struct platform_device *pdev)
2238 struct musb *musb = dev_to_musb(&pdev->dev);
2239 void __iomem *ctrl_base = musb->ctrl_base;
2241 /* this gets called on rmmod.
2242 * - Host mode: host may still be active
2243 * - Peripheral mode: peripheral is deactivated (or never-activated)
2244 * - OTG mode: both roles are deactivated (or never-activated)
2246 musb_exit_debugfs(musb);
2247 musb_shutdown(pdev);
2248 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2249 if (musb->board_mode == MUSB_HOST)
2250 usb_remove_hcd(musb_to_hcd(musb));
2252 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2253 musb_platform_exit(musb);
2254 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2258 device_init_wakeup(&pdev->dev, 0);
2259 #ifndef CONFIG_MUSB_PIO_ONLY
2260 pdev->dev.dma_mask = orig_dma_mask;
2267 static struct musb_context_registers musb_context;
2269 void musb_save_context(struct musb *musb)
2272 void __iomem *musb_base = musb->mregs;
2274 if (is_host_enabled(musb)) {
2275 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2276 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2277 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2279 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2280 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2281 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2282 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2283 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2284 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2286 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2287 musb_writeb(musb_base, MUSB_INDEX, i);
2288 musb_context.index_regs[i].txmaxp =
2289 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2290 musb_context.index_regs[i].txcsr =
2291 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2292 musb_context.index_regs[i].rxmaxp =
2293 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2294 musb_context.index_regs[i].rxcsr =
2295 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2297 if (musb->dyn_fifo) {
2298 musb_context.index_regs[i].txfifoadd =
2299 musb_read_txfifoadd(musb_base);
2300 musb_context.index_regs[i].rxfifoadd =
2301 musb_read_rxfifoadd(musb_base);
2302 musb_context.index_regs[i].txfifosz =
2303 musb_read_txfifosz(musb_base);
2304 musb_context.index_regs[i].rxfifosz =
2305 musb_read_rxfifosz(musb_base);
2307 if (is_host_enabled(musb)) {
2308 musb_context.index_regs[i].txtype =
2309 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2310 musb_context.index_regs[i].txinterval =
2311 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2312 musb_context.index_regs[i].rxtype =
2313 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2314 musb_context.index_regs[i].rxinterval =
2315 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2317 musb_context.index_regs[i].txfunaddr =
2318 musb_read_txfunaddr(musb_base, i);
2319 musb_context.index_regs[i].txhubaddr =
2320 musb_read_txhubaddr(musb_base, i);
2321 musb_context.index_regs[i].txhubport =
2322 musb_read_txhubport(musb_base, i);
2324 musb_context.index_regs[i].rxfunaddr =
2325 musb_read_rxfunaddr(musb_base, i);
2326 musb_context.index_regs[i].rxhubaddr =
2327 musb_read_rxhubaddr(musb_base, i);
2328 musb_context.index_regs[i].rxhubport =
2329 musb_read_rxhubport(musb_base, i);
2333 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2335 musb_platform_save_context(musb, &musb_context);
2338 void musb_restore_context(struct musb *musb)
2341 void __iomem *musb_base = musb->mregs;
2342 void __iomem *ep_target_regs;
2344 musb_platform_restore_context(musb, &musb_context);
2346 if (is_host_enabled(musb)) {
2347 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2348 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2349 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2351 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2352 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2353 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2354 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2355 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2357 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2358 musb_writeb(musb_base, MUSB_INDEX, i);
2359 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2360 musb_context.index_regs[i].txmaxp);
2361 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2362 musb_context.index_regs[i].txcsr);
2363 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2364 musb_context.index_regs[i].rxmaxp);
2365 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2366 musb_context.index_regs[i].rxcsr);
2368 if (musb->dyn_fifo) {
2369 musb_write_txfifosz(musb_base,
2370 musb_context.index_regs[i].txfifosz);
2371 musb_write_rxfifosz(musb_base,
2372 musb_context.index_regs[i].rxfifosz);
2373 musb_write_txfifoadd(musb_base,
2374 musb_context.index_regs[i].txfifoadd);
2375 musb_write_rxfifoadd(musb_base,
2376 musb_context.index_regs[i].rxfifoadd);
2379 if (is_host_enabled(musb)) {
2380 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2381 musb_context.index_regs[i].txtype);
2382 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2383 musb_context.index_regs[i].txinterval);
2384 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2385 musb_context.index_regs[i].rxtype);
2386 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2388 musb_context.index_regs[i].rxinterval);
2389 musb_write_txfunaddr(musb_base, i,
2390 musb_context.index_regs[i].txfunaddr);
2391 musb_write_txhubaddr(musb_base, i,
2392 musb_context.index_regs[i].txhubaddr);
2393 musb_write_txhubport(musb_base, i,
2394 musb_context.index_regs[i].txhubport);
2397 musb_read_target_reg_base(i, musb_base);
2399 musb_write_rxfunaddr(ep_target_regs,
2400 musb_context.index_regs[i].rxfunaddr);
2401 musb_write_rxhubaddr(ep_target_regs,
2402 musb_context.index_regs[i].rxhubaddr);
2403 musb_write_rxhubport(ep_target_regs,
2404 musb_context.index_regs[i].rxhubport);
2408 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2411 static int musb_suspend(struct device *dev)
2413 struct platform_device *pdev = to_platform_device(dev);
2414 unsigned long flags;
2415 struct musb *musb = dev_to_musb(&pdev->dev);
2420 spin_lock_irqsave(&musb->lock, flags);
2422 if (is_peripheral_active(musb)) {
2423 /* FIXME force disconnect unless we know USB will wake
2424 * the system up quickly enough to respond ...
2426 } else if (is_host_active(musb)) {
2427 /* we know all the children are suspended; sometimes
2428 * they will even be wakeup-enabled.
2432 musb_save_context(musb);
2434 if (musb->set_clock)
2435 musb->set_clock(musb->clock, 0);
2437 clk_disable(musb->clock);
2438 spin_unlock_irqrestore(&musb->lock, flags);
2442 static int musb_resume_noirq(struct device *dev)
2444 struct platform_device *pdev = to_platform_device(dev);
2445 struct musb *musb = dev_to_musb(&pdev->dev);
2450 if (musb->set_clock)
2451 musb->set_clock(musb->clock, 1);
2453 clk_enable(musb->clock);
2455 musb_restore_context(musb);
2457 /* for static cmos like DaVinci, register values were preserved
2458 * unless for some reason the whole soc powered down or the USB
2459 * module got reset through the PSC (vs just being disabled).
2464 static const struct dev_pm_ops musb_dev_pm_ops = {
2465 .suspend = musb_suspend,
2466 .resume_noirq = musb_resume_noirq,
2469 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2471 #define MUSB_DEV_PM_OPS NULL
2474 static struct platform_driver musb_driver = {
2476 .name = (char *)musb_driver_name,
2477 .bus = &platform_bus_type,
2478 .owner = THIS_MODULE,
2479 .pm = MUSB_DEV_PM_OPS,
2481 .remove = __exit_p(musb_remove),
2482 .shutdown = musb_shutdown,
2485 /*-------------------------------------------------------------------------*/
2487 static int __init musb_init(void)
2489 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2494 pr_info("%s: version " MUSB_VERSION ", "
2495 #ifdef CONFIG_MUSB_PIO_ONLY
2497 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2499 #elif defined(CONFIG_USB_INVENTRA_DMA)
2501 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2507 #ifdef CONFIG_USB_MUSB_OTG
2508 "otg (peripheral+host)"
2509 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2511 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2515 musb_driver_name, musb_debug);
2516 return platform_driver_probe(&musb_driver, musb_probe);
2519 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2520 * and before usb gadget and host-side drivers start to register
2522 fs_initcall(musb_init);
2524 static void __exit musb_cleanup(void)
2526 platform_driver_unregister(&musb_driver);
2528 module_exit(musb_cleanup);