drivers/usb/musb/musb_cppi41.c

   1 #include <linux/device.h>
   2 #include <linux/dma-mapping.h>
   3 #include <linux/dmaengine.h>
   4 #include <linux/sizes.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/of.h>
   7
   8 #include "musb_core.h"
   9
  10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
  11
  12 #define EP_MODE_AUTOREG_NONE            0
  13 #define EP_MODE_AUTOREG_ALL_NEOP        1
  14 #define EP_MODE_AUTOREG_ALWAYS          3
  15
  16 #define EP_MODE_DMA_TRANSPARENT         0
  17 #define EP_MODE_DMA_RNDIS               1
  18 #define EP_MODE_DMA_GEN_RNDIS           3
  19
  20 #define USB_CTRL_TX_MODE        0x70
  21 #define USB_CTRL_RX_MODE        0x74
  22 #define USB_CTRL_AUTOREQ        0xd0
  23 #define USB_TDOWN               0xd8
  24
  25 struct cppi41_dma_channel {
  26         struct dma_channel channel;
  27         struct cppi41_dma_controller *controller;
  28         struct musb_hw_ep *hw_ep;
  29         struct dma_chan *dc;
  30         dma_cookie_t cookie;
  31         u8 port_num;
  32         u8 is_tx;
  33         u8 is_allocated;
  34         u8 usb_toggle;
  35
  36         dma_addr_t buf_addr;
  37         u32 total_len;
  38         u32 prog_len;
  39         u32 transferred;
  40         u32 packet_sz;
  41         struct list_head tx_check;
  42 };
  43
  44 #define MUSB_DMA_NUM_CHANNELS 15
  45
  46 struct cppi41_dma_controller {
  47         struct dma_controller controller;
  48         struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
  49         struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
  50         struct musb *musb;
  51         struct hrtimer early_tx;
  52         struct list_head early_tx_list;
  53         u32 rx_mode;
  54         u32 tx_mode;
  55         u32 auto_req;
  56 };
  57
  58 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  59 {
  60         u16 csr;
  61         u8 toggle;
  62
  63         if (cppi41_channel->is_tx)
  64                 return;
  65         if (!is_host_active(cppi41_channel->controller->musb))
  66                 return;
  67
  68         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  69         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  70
  71         cppi41_channel->usb_toggle = toggle;
  72 }
  73
  74 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  75 {
  76         u16 csr;
  77         u8 toggle;
  78
  79         if (cppi41_channel->is_tx)
  80                 return;
  81         if (!is_host_active(cppi41_channel->controller->musb))
  82                 return;
  83
  84         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  85         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  86
  87         /*
  88          * AM335x Advisory 1.0.13: Due to internal synchronisation error the
  89          * data toggle may reset from DATA1 to DATA0 during receiving data from
  90          * more than one endpoint.
  91          */
  92         if (!toggle && toggle == cppi41_channel->usb_toggle) {
  93                 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
  94                 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
  95                 dev_dbg(cppi41_channel->controller->musb->controller,
  96                                 "Restoring DATA1 toggle.\n");
  97         }
  98
  99         cppi41_channel->usb_toggle = toggle;
 100 }
 101
 102 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
 103 {
 104         u8              epnum = hw_ep->epnum;
 105         struct musb     *musb = hw_ep->musb;
 106         void __iomem    *epio = musb->endpoints[epnum].regs;
 107         u16             csr;
 108
 109         csr = musb_readw(epio, MUSB_TXCSR);
 110         if (csr & MUSB_TXCSR_TXPKTRDY)
 111                 return false;
 112         return true;
 113 }
 114
 115 static void cppi41_dma_callback(void *private_data);
 116
 117 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
 118 {
 119         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 120         struct musb *musb = hw_ep->musb;
 121
 122         if (!cppi41_channel->prog_len) {
 123
 124                 /* done, complete */
 125                 cppi41_channel->channel.actual_len =
 126                         cppi41_channel->transferred;
 127                 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 128                 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
 129         } else {
 130                 /* next iteration, reload */
 131                 struct dma_chan *dc = cppi41_channel->dc;
 132                 struct dma_async_tx_descriptor *dma_desc;
 133                 enum dma_transfer_direction direction;
 134                 u16 csr;
 135                 u32 remain_bytes;
 136                 void __iomem *epio = cppi41_channel->hw_ep->regs;
 137
 138                 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
 139
 140                 remain_bytes = cppi41_channel->total_len;
 141                 remain_bytes -= cppi41_channel->transferred;
 142                 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
 143                 cppi41_channel->prog_len = remain_bytes;
 144
 145                 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
 146                         : DMA_DEV_TO_MEM;
 147                 dma_desc = dmaengine_prep_slave_single(dc,
 148                                 cppi41_channel->buf_addr,
 149                                 remain_bytes,
 150                                 direction,
 151                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 152                 if (WARN_ON(!dma_desc))
 153                         return;
 154
 155                 dma_desc->callback = cppi41_dma_callback;
 156                 dma_desc->callback_param = &cppi41_channel->channel;
 157                 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 158                 dma_async_issue_pending(dc);
 159
 160                 if (!cppi41_channel->is_tx) {
 161                         csr = musb_readw(epio, MUSB_RXCSR);
 162                         csr |= MUSB_RXCSR_H_REQPKT;
 163                         musb_writew(epio, MUSB_RXCSR, csr);
 164                 }
 165         }
 166 }
 167
 168 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
 169 {
 170         struct cppi41_dma_controller *controller;
 171         struct cppi41_dma_channel *cppi41_channel, *n;
 172         struct musb *musb;
 173         unsigned long flags;
 174         enum hrtimer_restart ret = HRTIMER_NORESTART;
 175
 176         controller = container_of(timer, struct cppi41_dma_controller,
 177                         early_tx);
 178         musb = controller->musb;
 179
 180         spin_lock_irqsave(&musb->lock, flags);
 181         list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
 182                         tx_check) {
 183                 bool empty;
 184                 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 185
 186                 empty = musb_is_tx_fifo_empty(hw_ep);
 187                 if (empty) {
 188                         list_del_init(&cppi41_channel->tx_check);
 189                         cppi41_trans_done(cppi41_channel);
 190                 }
 191         }
 192
 193         if (!list_empty(&controller->early_tx_list) &&
 194             !hrtimer_is_queued(&controller->early_tx)) {
 195                 ret = HRTIMER_RESTART;
 196                 hrtimer_forward_now(&controller->early_tx,
 197                                 ktime_set(0, 150 * NSEC_PER_USEC));
 198         }
 199
 200         spin_unlock_irqrestore(&musb->lock, flags);
 201         return ret;
 202 }
 203
 204 static void cppi41_dma_callback(void *private_data)
 205 {
 206         struct dma_channel *channel = private_data;
 207         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 208         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 209         struct musb *musb = hw_ep->musb;
 210         unsigned long flags;
 211         struct dma_tx_state txstate;
 212         u32 transferred;
 213         bool empty;
 214
 215         spin_lock_irqsave(&musb->lock, flags);
 216
 217         dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
 218                         &txstate);
 219         transferred = cppi41_channel->prog_len - txstate.residue;
 220         cppi41_channel->transferred += transferred;
 221
 222         dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
 223                 hw_ep->epnum, cppi41_channel->transferred,
 224                 cppi41_channel->total_len);
 225
 226         update_rx_toggle(cppi41_channel);
 227
 228         if (cppi41_channel->transferred == cppi41_channel->total_len ||
 229                         transferred < cppi41_channel->packet_sz)
 230                 cppi41_channel->prog_len = 0;
 231
 232         empty = musb_is_tx_fifo_empty(hw_ep);
 233         if (empty) {
 234                 cppi41_trans_done(cppi41_channel);
 235         } else {
 236                 struct cppi41_dma_controller *controller;
 237                 /*
 238                  * On AM335x it has been observed that the TX interrupt fires
 239                  * too early that means the TXFIFO is not yet empty but the DMA
 240                  * engine says that it is done with the transfer. We don't
 241                  * receive a FIFO empty interrupt so the only thing we can do is
 242                  * to poll for the bit. On HS it usually takes 2us, on FS around
 243                  * 110us - 150us depending on the transfer size.
 244                  * We spin on HS (no longer than than 25us and setup a timer on
 245                  * FS to check for the bit and complete the transfer.
 246                  */
 247                 controller = cppi41_channel->controller;
 248
 249                 if (musb->g.speed == USB_SPEED_HIGH) {
 250                         unsigned wait = 25;
 251
 252                         do {
 253                                 empty = musb_is_tx_fifo_empty(hw_ep);
 254                                 if (empty)
 255                                         break;
 256                                 wait--;
 257                                 if (!wait)
 258                                         break;
 259                                 udelay(1);
 260                         } while (1);
 261
 262                         empty = musb_is_tx_fifo_empty(hw_ep);
 263                         if (empty) {
 264                                 cppi41_trans_done(cppi41_channel);
 265                                 goto out;
 266                         }
 267                 }
 268                 list_add_tail(&cppi41_channel->tx_check,
 269                                 &controller->early_tx_list);
 270                 if (!hrtimer_is_queued(&controller->early_tx)) {
 271                         hrtimer_start_range_ns(&controller->early_tx,
 272                                 ktime_set(0, 140 * NSEC_PER_USEC),
 273                                 40 * NSEC_PER_USEC,
 274                                 HRTIMER_MODE_REL);
 275                 }
 276         }
 277 out:
 278         spin_unlock_irqrestore(&musb->lock, flags);
 279 }
 280
 281 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
 282 {
 283         unsigned shift;
 284
 285         shift = (ep - 1) * 2;
 286         old &= ~(3 << shift);
 287         old |= mode << shift;
 288         return old;
 289 }
 290
 291 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
 292                 unsigned mode)
 293 {
 294         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 295         u32 port;
 296         u32 new_mode;
 297         u32 old_mode;
 298
 299         if (cppi41_channel->is_tx)
 300                 old_mode = controller->tx_mode;
 301         else
 302                 old_mode = controller->rx_mode;
 303         port = cppi41_channel->port_num;
 304         new_mode = update_ep_mode(port, mode, old_mode);
 305
 306         if (new_mode == old_mode)
 307                 return;
 308         if (cppi41_channel->is_tx) {
 309                 controller->tx_mode = new_mode;
 310                 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
 311                                 new_mode);
 312         } else {
 313                 controller->rx_mode = new_mode;
 314                 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
 315                                 new_mode);
 316         }
 317 }
 318
 319 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
 320                 unsigned mode)
 321 {
 322         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 323         u32 port;
 324         u32 new_mode;
 325         u32 old_mode;
 326
 327         old_mode = controller->auto_req;
 328         port = cppi41_channel->port_num;
 329         new_mode = update_ep_mode(port, mode, old_mode);
 330
 331         if (new_mode == old_mode)
 332                 return;
 333         controller->auto_req = new_mode;
 334         musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
 335 }
 336
 337 static bool cppi41_configure_channel(struct dma_channel *channel,
 338                                 u16 packet_sz, u8 mode,
 339                                 dma_addr_t dma_addr, u32 len)
 340 {
 341         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 342         struct dma_chan *dc = cppi41_channel->dc;
 343         struct dma_async_tx_descriptor *dma_desc;
 344         enum dma_transfer_direction direction;
 345         struct musb *musb = cppi41_channel->controller->musb;
 346         unsigned use_gen_rndis = 0;
 347
 348         dev_dbg(musb->controller,
 349                 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
 350                 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
 351                 packet_sz, mode, (unsigned long long) dma_addr,
 352                 len, cppi41_channel->is_tx);
 353
 354         cppi41_channel->buf_addr = dma_addr;
 355         cppi41_channel->total_len = len;
 356         cppi41_channel->transferred = 0;
 357         cppi41_channel->packet_sz = packet_sz;
 358
 359         /*
 360          * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
 361          * than max packet size at a time.
 362          */
 363         if (cppi41_channel->is_tx)
 364                 use_gen_rndis = 1;
 365
 366         if (use_gen_rndis) {
 367                 /* RNDIS mode */
 368                 if (len > packet_sz) {
 369                         musb_writel(musb->ctrl_base,
 370                                 RNDIS_REG(cppi41_channel->port_num), len);
 371                         /* gen rndis */
 372                         cppi41_set_dma_mode(cppi41_channel,
 373                                         EP_MODE_DMA_GEN_RNDIS);
 374
 375                         /* auto req */
 376                         cppi41_set_autoreq_mode(cppi41_channel,
 377                                         EP_MODE_AUTOREG_ALL_NEOP);
 378                 } else {
 379                         musb_writel(musb->ctrl_base,
 380                                         RNDIS_REG(cppi41_channel->port_num), 0);
 381                         cppi41_set_dma_mode(cppi41_channel,
 382                                         EP_MODE_DMA_TRANSPARENT);
 383                         cppi41_set_autoreq_mode(cppi41_channel,
 384                                         EP_MODE_AUTOREG_NONE);
 385                 }
 386         } else {
 387                 /* fallback mode */
 388                 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
 389                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
 390                 len = min_t(u32, packet_sz, len);
 391         }
 392         cppi41_channel->prog_len = len;
 393         direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 394         dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
 395                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 396         if (!dma_desc)
 397                 return false;
 398
 399         dma_desc->callback = cppi41_dma_callback;
 400         dma_desc->callback_param = channel;
 401         cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 402
 403         save_rx_toggle(cppi41_channel);
 404         dma_async_issue_pending(dc);
 405         return true;
 406 }
 407
 408 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
 409                                 struct musb_hw_ep *hw_ep, u8 is_tx)
 410 {
 411         struct cppi41_dma_controller *controller = container_of(c,
 412                         struct cppi41_dma_controller, controller);
 413         struct cppi41_dma_channel *cppi41_channel = NULL;
 414         u8 ch_num = hw_ep->epnum - 1;
 415
 416         if (ch_num >= MUSB_DMA_NUM_CHANNELS)
 417                 return NULL;
 418
 419         if (is_tx)
 420                 cppi41_channel = &controller->tx_channel[ch_num];
 421         else
 422                 cppi41_channel = &controller->rx_channel[ch_num];
 423
 424         if (!cppi41_channel->dc)
 425                 return NULL;
 426
 427         if (cppi41_channel->is_allocated)
 428                 return NULL;
 429
 430         cppi41_channel->hw_ep = hw_ep;
 431         cppi41_channel->is_allocated = 1;
 432
 433         return &cppi41_channel->channel;
 434 }
 435
 436 static void cppi41_dma_channel_release(struct dma_channel *channel)
 437 {
 438         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 439
 440         if (cppi41_channel->is_allocated) {
 441                 cppi41_channel->is_allocated = 0;
 442                 channel->status = MUSB_DMA_STATUS_FREE;
 443                 channel->actual_len = 0;
 444         }
 445 }
 446
 447 static int cppi41_dma_channel_program(struct dma_channel *channel,
 448                                 u16 packet_sz, u8 mode,
 449                                 dma_addr_t dma_addr, u32 len)
 450 {
 451         int ret;
 452
 453         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 454                 channel->status == MUSB_DMA_STATUS_BUSY);
 455
 456         channel->status = MUSB_DMA_STATUS_BUSY;
 457         channel->actual_len = 0;
 458         ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
 459         if (!ret)
 460                 channel->status = MUSB_DMA_STATUS_FREE;
 461
 462         return ret;
 463 }
 464
 465 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
 466                 void *buf, u32 length)
 467 {
 468         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 469         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 470         struct musb *musb = controller->musb;
 471
 472         if (is_host_active(musb)) {
 473                 WARN_ON(1);
 474                 return 1;
 475         }
 476         if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
 477                 return 0;
 478         if (cppi41_channel->is_tx)
 479                 return 1;
 480         /* AM335x Advisory 1.0.13. No workaround for device RX mode */
 481         return 0;
 482 }
 483
 484 static int cppi41_dma_channel_abort(struct dma_channel *channel)
 485 {
 486         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 487         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 488         struct musb *musb = controller->musb;
 489         void __iomem *epio = cppi41_channel->hw_ep->regs;
 490         int tdbit;
 491         int ret;
 492         unsigned is_tx;
 493         u16 csr;
 494
 495         is_tx = cppi41_channel->is_tx;
 496         dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
 497                         cppi41_channel->port_num, is_tx);
 498
 499         if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
 500                 return 0;
 501
 502         list_del_init(&cppi41_channel->tx_check);
 503         if (is_tx) {
 504                 csr = musb_readw(epio, MUSB_TXCSR);
 505                 csr &= ~MUSB_TXCSR_DMAENAB;
 506                 musb_writew(epio, MUSB_TXCSR, csr);
 507         } else {
 508                 csr = musb_readw(epio, MUSB_RXCSR);
 509                 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
 510                 musb_writew(epio, MUSB_RXCSR, csr);
 511
 512                 csr = musb_readw(epio, MUSB_RXCSR);
 513                 if (csr & MUSB_RXCSR_RXPKTRDY) {
 514                         csr |= MUSB_RXCSR_FLUSHFIFO;
 515                         musb_writew(epio, MUSB_RXCSR, csr);
 516                         musb_writew(epio, MUSB_RXCSR, csr);
 517                 }
 518         }
 519
 520         tdbit = 1 << cppi41_channel->port_num;
 521         if (is_tx)
 522                 tdbit <<= 16;
 523
 524         do {
 525                 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 526                 ret = dmaengine_terminate_all(cppi41_channel->dc);
 527         } while (ret == -EAGAIN);
 528
 529         musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 530
 531         if (is_tx) {
 532                 csr = musb_readw(epio, MUSB_TXCSR);
 533                 if (csr & MUSB_TXCSR_TXPKTRDY) {
 534                         csr |= MUSB_TXCSR_FLUSHFIFO;
 535                         musb_writew(epio, MUSB_TXCSR, csr);
 536                 }
 537         }
 538
 539         cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 540         return 0;
 541 }
 542
 543 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
 544 {
 545         struct dma_chan *dc;
 546         int i;
 547
 548         for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
 549                 dc = ctrl->tx_channel[i].dc;
 550                 if (dc)
 551                         dma_release_channel(dc);
 552                 dc = ctrl->rx_channel[i].dc;
 553                 if (dc)
 554                         dma_release_channel(dc);
 555         }
 556 }
 557
 558 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
 559 {
 560         cppi41_release_all_dma_chans(controller);
 561 }
 562
 563 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 564 {
 565         struct musb *musb = controller->musb;
 566         struct device *dev = musb->controller;
 567         struct device_node *np = dev->of_node;
 568         struct cppi41_dma_channel *cppi41_channel;
 569         int count;
 570         int i;
 571         int ret;
 572
 573         count = of_property_count_strings(np, "dma-names");
 574         if (count < 0)
 575                 return count;
 576
 577         for (i = 0; i < count; i++) {
 578                 struct dma_chan *dc;
 579                 struct dma_channel *musb_dma;
 580                 const char *str;
 581                 unsigned is_tx;
 582                 unsigned int port;
 583
 584                 ret = of_property_read_string_index(np, "dma-names", i, &str);
 585                 if (ret)
 586                         goto err;
 587                 if (!strncmp(str, "tx", 2))
 588                         is_tx = 1;
 589                 else if (!strncmp(str, "rx", 2))
 590                         is_tx = 0;
 591                 else {
 592                         dev_err(dev, "Wrong dmatype %s\n", str);
 593                         goto err;
 594                 }
 595                 ret = kstrtouint(str + 2, 0, &port);
 596                 if (ret)
 597                         goto err;
 598
 599                 ret = -EINVAL;
 600                 if (port > MUSB_DMA_NUM_CHANNELS || !port)
 601                         goto err;
 602                 if (is_tx)
 603                         cppi41_channel = &controller->tx_channel[port - 1];
 604                 else
 605                         cppi41_channel = &controller->rx_channel[port - 1];
 606
 607                 cppi41_channel->controller = controller;
 608                 cppi41_channel->port_num = port;
 609                 cppi41_channel->is_tx = is_tx;
 610                 INIT_LIST_HEAD(&cppi41_channel->tx_check);
 611
 612                 musb_dma = &cppi41_channel->channel;
 613                 musb_dma->private_data = cppi41_channel;
 614                 musb_dma->status = MUSB_DMA_STATUS_FREE;
 615                 musb_dma->max_len = SZ_4M;
 616
 617                 dc = dma_request_slave_channel(dev, str);
 618                 if (!dc) {
 619                         dev_err(dev, "Failed to request %s.\n", str);
 620                         ret = -EPROBE_DEFER;
 621                         goto err;
 622                 }
 623                 cppi41_channel->dc = dc;
 624         }
 625         return 0;
 626 err:
 627         cppi41_release_all_dma_chans(controller);
 628         return ret;
 629 }
 630
 631 void dma_controller_destroy(struct dma_controller *c)
 632 {
 633         struct cppi41_dma_controller *controller = container_of(c,
 634                         struct cppi41_dma_controller, controller);
 635
 636         hrtimer_cancel(&controller->early_tx);
 637         cppi41_dma_controller_stop(controller);
 638         kfree(controller);
 639 }
 640
 641 struct dma_controller *dma_controller_create(struct musb *musb,
 642                                         void __iomem *base)
 643 {
 644         struct cppi41_dma_controller *controller;
 645         int ret = 0;
 646
 647         if (!musb->controller->of_node) {
 648                 dev_err(musb->controller, "Need DT for the DMA engine.\n");
 649                 return NULL;
 650         }
 651
 652         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 653         if (!controller)
 654                 goto kzalloc_fail;
 655
 656         hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 657         controller->early_tx.function = cppi41_recheck_tx_req;
 658         INIT_LIST_HEAD(&controller->early_tx_list);
 659         controller->musb = musb;
 660
 661         controller->controller.channel_alloc = cppi41_dma_channel_allocate;
 662         controller->controller.channel_release = cppi41_dma_channel_release;
 663         controller->controller.channel_program = cppi41_dma_channel_program;
 664         controller->controller.channel_abort = cppi41_dma_channel_abort;
 665         controller->controller.is_compatible = cppi41_is_compatible;
 666
 667         ret = cppi41_dma_controller_start(controller);
 668         if (ret)
 669                 goto plat_get_fail;
 670         return &controller->controller;
 671
 672 plat_get_fail:
 673         kfree(controller);
 674 kzalloc_fail:
 675         if (ret == -EPROBE_DEFER)
 676                 return ERR_PTR(ret);
 677         return NULL;
 678 }