2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
49 /* ----------------------------------------------------------------------- */
51 #define is_buffer_mapped(req) (is_dma_capable() && \
52 (req->map_state != UN_MAPPED))
54 /* Maps the buffer to dma */
56 static inline void map_dma_buffer(struct musb_request *request,
57 struct musb *musb, struct musb_ep *musb_ep)
59 int compatible = true;
60 struct dma_controller *dma = musb->dma_controller;
62 request->map_state = UN_MAPPED;
64 if (!is_dma_capable() || !musb_ep->dma)
67 /* Check if DMA engine can handle this request.
68 * DMA code must reject the USB request explicitly.
69 * Default behaviour is to map the request.
71 if (dma->is_compatible)
72 compatible = dma->is_compatible(musb_ep->dma,
73 musb_ep->packet_sz, request->request.buf,
74 request->request.length);
78 if (request->request.dma == DMA_ADDR_INVALID) {
79 request->request.dma = dma_map_single(
82 request->request.length,
86 request->map_state = MUSB_MAPPED;
88 dma_sync_single_for_device(musb->controller,
90 request->request.length,
94 request->map_state = PRE_MAPPED;
98 /* Unmap the buffer from dma and maps it back to cpu */
99 static inline void unmap_dma_buffer(struct musb_request *request,
102 struct musb_ep *musb_ep = request->ep;
104 if (!is_buffer_mapped(request) || !musb_ep->dma)
107 if (request->request.dma == DMA_ADDR_INVALID) {
108 dev_vdbg(musb->controller,
109 "not unmapping a never mapped buffer\n");
112 if (request->map_state == MUSB_MAPPED) {
113 dma_unmap_single(musb->controller,
114 request->request.dma,
115 request->request.length,
119 request->request.dma = DMA_ADDR_INVALID;
120 } else { /* PRE_MAPPED */
121 dma_sync_single_for_cpu(musb->controller,
122 request->request.dma,
123 request->request.length,
128 request->map_state = UN_MAPPED;
132 * Immediately complete a request.
134 * @param request the request to complete
135 * @param status the status to complete the request with
136 * Context: controller locked, IRQs blocked.
138 void musb_g_giveback(
140 struct usb_request *request,
142 __releases(ep->musb->lock)
143 __acquires(ep->musb->lock)
145 struct musb_request *req;
149 req = to_musb_request(request);
151 list_del(&req->list);
152 if (req->request.status == -EINPROGRESS)
153 req->request.status = status;
157 spin_unlock(&musb->lock);
159 if (!dma_mapping_error(&musb->g.dev, request->dma))
160 unmap_dma_buffer(req, musb);
162 if (request->status == 0)
163 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
164 ep->end_point.name, request,
165 req->request.actual, req->request.length);
167 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
168 ep->end_point.name, request,
169 req->request.actual, req->request.length,
171 req->request.complete(&req->ep->end_point, &req->request);
172 spin_lock(&musb->lock);
176 /* ----------------------------------------------------------------------- */
179 * Abort requests queued to an endpoint using the status. Synchronous.
180 * caller locked controller and blocked irqs, and selected this ep.
182 static void nuke(struct musb_ep *ep, const int status)
184 struct musb *musb = ep->musb;
185 struct musb_request *req = NULL;
186 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
190 if (is_dma_capable() && ep->dma) {
191 struct dma_controller *c = ep->musb->dma_controller;
196 * The programming guide says that we must not clear
197 * the DMAMODE bit before DMAENAB, so we only
198 * clear it in the second write...
200 musb_writew(epio, MUSB_TXCSR,
201 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
202 musb_writew(epio, MUSB_TXCSR,
203 0 | MUSB_TXCSR_FLUSHFIFO);
205 musb_writew(epio, MUSB_RXCSR,
206 0 | MUSB_RXCSR_FLUSHFIFO);
207 musb_writew(epio, MUSB_RXCSR,
208 0 | MUSB_RXCSR_FLUSHFIFO);
211 value = c->channel_abort(ep->dma);
212 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
214 c->channel_release(ep->dma);
218 while (!list_empty(&ep->req_list)) {
219 req = list_first_entry(&ep->req_list, struct musb_request, list);
220 musb_g_giveback(ep, &req->request, status);
224 /* ----------------------------------------------------------------------- */
226 /* Data transfers - pure PIO, pure DMA, or mixed mode */
229 * This assumes the separate CPPI engine is responding to DMA requests
230 * from the usb core ... sequenced a bit differently from mentor dma.
233 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
235 if (can_bulk_split(musb, ep->type))
236 return ep->hw_ep->max_packet_sz_tx;
238 return ep->packet_sz;
242 * An endpoint is transmitting data. This can be called either from
243 * the IRQ routine or from ep.queue() to kickstart a request on an
246 * Context: controller locked, IRQs blocked, endpoint selected
248 static void txstate(struct musb *musb, struct musb_request *req)
250 u8 epnum = req->epnum;
251 struct musb_ep *musb_ep;
252 void __iomem *epio = musb->endpoints[epnum].regs;
253 struct usb_request *request;
254 u16 fifo_count = 0, csr;
259 /* Check if EP is disabled */
260 if (!musb_ep->desc) {
261 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
262 musb_ep->end_point.name);
266 /* we shouldn't get here while DMA is active ... but we do ... */
267 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
268 dev_dbg(musb->controller, "dma pending...\n");
272 /* read TXCSR before */
273 csr = musb_readw(epio, MUSB_TXCSR);
275 request = &req->request;
276 fifo_count = min(max_ep_writesize(musb, musb_ep),
277 (int)(request->length - request->actual));
279 if (csr & MUSB_TXCSR_TXPKTRDY) {
280 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
281 musb_ep->end_point.name, csr);
285 if (csr & MUSB_TXCSR_P_SENDSTALL) {
286 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
287 musb_ep->end_point.name, csr);
291 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
292 epnum, musb_ep->packet_sz, fifo_count,
295 #ifndef CONFIG_MUSB_PIO_ONLY
296 if (is_buffer_mapped(req)) {
297 struct dma_controller *c = musb->dma_controller;
300 /* setup DMA, then program endpoint CSR */
301 request_size = min_t(size_t, request->length - request->actual,
302 musb_ep->dma->max_len);
304 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
306 /* MUSB_TXCSR_P_ISO is still set correctly */
308 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
310 if (request_size < musb_ep->packet_sz)
311 musb_ep->dma->desired_mode = 0;
313 musb_ep->dma->desired_mode = 1;
315 use_dma = use_dma && c->channel_program(
316 musb_ep->dma, musb_ep->packet_sz,
317 musb_ep->dma->desired_mode,
318 request->dma + request->actual, request_size);
320 if (musb_ep->dma->desired_mode == 0) {
322 * We must not clear the DMAMODE bit
323 * before the DMAENAB bit -- and the
324 * latter doesn't always get cleared
325 * before we get here...
327 csr &= ~(MUSB_TXCSR_AUTOSET
328 | MUSB_TXCSR_DMAENAB);
329 musb_writew(epio, MUSB_TXCSR, csr
330 | MUSB_TXCSR_P_WZC_BITS);
331 csr &= ~MUSB_TXCSR_DMAMODE;
332 csr |= (MUSB_TXCSR_DMAENAB |
334 /* against programming guide */
336 csr |= (MUSB_TXCSR_DMAENAB
340 * Enable Autoset according to table
342 * bulk_split hb_mult Autoset_Enable
344 * 0 >0 No(High BW ISO)
348 if (!musb_ep->hb_mult ||
352 csr |= MUSB_TXCSR_AUTOSET;
354 csr &= ~MUSB_TXCSR_P_UNDERRUN;
356 musb_writew(epio, MUSB_TXCSR, csr);
361 if (is_cppi_enabled()) {
362 /* program endpoint CSR first, then setup DMA */
363 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
364 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
366 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
367 ~MUSB_TXCSR_P_UNDERRUN) | csr);
369 /* ensure writebuffer is empty */
370 csr = musb_readw(epio, MUSB_TXCSR);
373 * NOTE host side sets DMAENAB later than this; both are
374 * OK since the transfer dma glue (between CPPI and
375 * Mentor fifos) just tells CPPI it could start. Data
376 * only moves to the USB TX fifo when both fifos are
380 * "mode" is irrelevant here; handle terminating ZLPs
381 * like PIO does, since the hardware RNDIS mode seems
382 * unreliable except for the
383 * last-packet-is-already-short case.
385 use_dma = use_dma && c->channel_program(
386 musb_ep->dma, musb_ep->packet_sz,
388 request->dma + request->actual,
391 c->channel_release(musb_ep->dma);
393 csr &= ~MUSB_TXCSR_DMAENAB;
394 musb_writew(epio, MUSB_TXCSR, csr);
395 /* invariant: prequest->buf is non-null */
397 } else if (tusb_dma_omap())
398 use_dma = use_dma && c->channel_program(
399 musb_ep->dma, musb_ep->packet_sz,
401 request->dma + request->actual,
408 * Unmap the dma buffer back to cpu if dma channel
411 unmap_dma_buffer(req, musb);
413 musb_write_fifo(musb_ep->hw_ep, fifo_count,
414 (u8 *) (request->buf + request->actual));
415 request->actual += fifo_count;
416 csr |= MUSB_TXCSR_TXPKTRDY;
417 csr &= ~MUSB_TXCSR_P_UNDERRUN;
418 musb_writew(epio, MUSB_TXCSR, csr);
421 /* host may already have the data when this message shows... */
422 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
423 musb_ep->end_point.name, use_dma ? "dma" : "pio",
424 request->actual, request->length,
425 musb_readw(epio, MUSB_TXCSR),
427 musb_readw(epio, MUSB_TXMAXP));
431 * FIFO state update (e.g. data ready).
432 * Called from IRQ, with controller locked.
434 void musb_g_tx(struct musb *musb, u8 epnum)
437 struct musb_request *req;
438 struct usb_request *request;
439 u8 __iomem *mbase = musb->mregs;
440 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
441 void __iomem *epio = musb->endpoints[epnum].regs;
442 struct dma_channel *dma;
444 musb_ep_select(mbase, epnum);
445 req = next_request(musb_ep);
446 request = &req->request;
448 csr = musb_readw(epio, MUSB_TXCSR);
449 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
451 dma = is_dma_capable() ? musb_ep->dma : NULL;
454 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
455 * probably rates reporting as a host error.
457 if (csr & MUSB_TXCSR_P_SENTSTALL) {
458 csr |= MUSB_TXCSR_P_WZC_BITS;
459 csr &= ~MUSB_TXCSR_P_SENTSTALL;
460 musb_writew(epio, MUSB_TXCSR, csr);
464 if (csr & MUSB_TXCSR_P_UNDERRUN) {
465 /* We NAKed, no big deal... little reason to care. */
466 csr |= MUSB_TXCSR_P_WZC_BITS;
467 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
468 musb_writew(epio, MUSB_TXCSR, csr);
469 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
473 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
475 * SHOULD NOT HAPPEN... has with CPPI though, after
476 * changing SENDSTALL (and other cases); harmless?
478 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
485 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
487 csr |= MUSB_TXCSR_P_WZC_BITS;
488 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
489 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
490 musb_writew(epio, MUSB_TXCSR, csr);
491 /* Ensure writebuffer is empty. */
492 csr = musb_readw(epio, MUSB_TXCSR);
493 request->actual += musb_ep->dma->actual_len;
494 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
495 epnum, csr, musb_ep->dma->actual_len, request);
499 * First, maybe a terminating short packet. Some DMA
500 * engines might handle this by themselves.
502 if ((request->zero && request->length
503 && (request->length % musb_ep->packet_sz == 0)
504 && (request->actual == request->length))
505 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
506 || (is_dma && (!dma->desired_mode ||
508 (musb_ep->packet_sz - 1))))
512 * On DMA completion, FIFO may not be
515 if (csr & MUSB_TXCSR_TXPKTRDY)
518 dev_dbg(musb->controller, "sending zero pkt\n");
519 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
520 | MUSB_TXCSR_TXPKTRDY);
524 if (request->actual == request->length) {
525 musb_g_giveback(musb_ep, request, 0);
527 * In the giveback function the MUSB lock is
528 * released and acquired after sometime. During
529 * this time period the INDEX register could get
530 * changed by the gadget_queue function especially
531 * on SMP systems. Reselect the INDEX to be sure
532 * we are reading/modifying the right registers
534 musb_ep_select(mbase, epnum);
535 req = musb_ep->desc ? next_request(musb_ep) : NULL;
537 dev_dbg(musb->controller, "%s idle now\n",
538 musb_ep->end_point.name);
547 /* ------------------------------------------------------------ */
550 * Context: controller locked, IRQs blocked, endpoint selected
552 static void rxstate(struct musb *musb, struct musb_request *req)
554 const u8 epnum = req->epnum;
555 struct usb_request *request = &req->request;
556 struct musb_ep *musb_ep;
557 void __iomem *epio = musb->endpoints[epnum].regs;
560 u16 csr = musb_readw(epio, MUSB_RXCSR);
561 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
564 if (hw_ep->is_shared_fifo)
565 musb_ep = &hw_ep->ep_in;
567 musb_ep = &hw_ep->ep_out;
569 fifo_count = musb_ep->packet_sz;
571 /* Check if EP is disabled */
572 if (!musb_ep->desc) {
573 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
574 musb_ep->end_point.name);
578 /* We shouldn't get here while DMA is active, but we do... */
579 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
580 dev_dbg(musb->controller, "DMA pending...\n");
584 if (csr & MUSB_RXCSR_P_SENDSTALL) {
585 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
586 musb_ep->end_point.name, csr);
590 if (is_cppi_enabled() && is_buffer_mapped(req)) {
591 struct dma_controller *c = musb->dma_controller;
592 struct dma_channel *channel = musb_ep->dma;
594 /* NOTE: CPPI won't actually stop advancing the DMA
595 * queue after short packet transfers, so this is almost
596 * always going to run as IRQ-per-packet DMA so that
597 * faults will be handled correctly.
599 if (c->channel_program(channel,
601 !request->short_not_ok,
602 request->dma + request->actual,
603 request->length - request->actual)) {
605 /* make sure that if an rxpkt arrived after the irq,
606 * the cppi engine will be ready to take it as soon
609 csr &= ~(MUSB_RXCSR_AUTOCLEAR
610 | MUSB_RXCSR_DMAMODE);
611 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
612 musb_writew(epio, MUSB_RXCSR, csr);
617 if (csr & MUSB_RXCSR_RXPKTRDY) {
618 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
621 * Enable Mode 1 on RX transfers only when short_not_ok flag
622 * is set. Currently short_not_ok flag is set only from
623 * file_storage and f_mass_storage drivers
626 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
631 if (request->actual < request->length) {
632 #ifdef CONFIG_USB_INVENTRA_DMA
633 if (is_buffer_mapped(req)) {
634 struct dma_controller *c;
635 struct dma_channel *channel;
637 unsigned int transfer_size;
639 c = musb->dma_controller;
640 channel = musb_ep->dma;
642 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
643 * mode 0 only. So we do not get endpoint interrupts due to DMA
644 * completion. We only get interrupts from DMA controller.
646 * We could operate in DMA mode 1 if we knew the size of the tranfer
647 * in advance. For mass storage class, request->length = what the host
648 * sends, so that'd work. But for pretty much everything else,
649 * request->length is routinely more than what the host sends. For
650 * most these gadgets, end of is signified either by a short packet,
651 * or filling the last byte of the buffer. (Sending extra data in
652 * that last pckate should trigger an overflow fault.) But in mode 1,
653 * we don't get DMA completion interrupt for short packets.
655 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
656 * to get endpoint interrupt on every DMA req, but that didn't seem
659 * REVISIT an updated g_file_storage can set req->short_not_ok, which
660 * then becomes usable as a runtime "use mode 1" hint...
663 /* Experimental: Mode1 works with mass storage use cases */
665 csr |= MUSB_RXCSR_AUTOCLEAR;
666 musb_writew(epio, MUSB_RXCSR, csr);
667 csr |= MUSB_RXCSR_DMAENAB;
668 musb_writew(epio, MUSB_RXCSR, csr);
671 * this special sequence (enabling and then
672 * disabling MUSB_RXCSR_DMAMODE) is required
673 * to get DMAReq to activate
675 musb_writew(epio, MUSB_RXCSR,
676 csr | MUSB_RXCSR_DMAMODE);
677 musb_writew(epio, MUSB_RXCSR, csr);
679 transfer_size = min_t(unsigned int,
683 musb_ep->dma->desired_mode = 1;
685 if (!musb_ep->hb_mult &&
686 musb_ep->hw_ep->rx_double_buffered)
687 csr |= MUSB_RXCSR_AUTOCLEAR;
688 csr |= MUSB_RXCSR_DMAENAB;
689 musb_writew(epio, MUSB_RXCSR, csr);
691 transfer_size = min(request->length - request->actual,
692 (unsigned)fifo_count);
693 musb_ep->dma->desired_mode = 0;
696 use_dma = c->channel_program(
699 channel->desired_mode,
707 #elif defined(CONFIG_USB_UX500_DMA)
708 if ((is_buffer_mapped(req)) &&
709 (request->actual < request->length)) {
711 struct dma_controller *c;
712 struct dma_channel *channel;
713 unsigned int transfer_size = 0;
715 c = musb->dma_controller;
716 channel = musb_ep->dma;
718 /* In case first packet is short */
719 if (fifo_count < musb_ep->packet_sz)
720 transfer_size = fifo_count;
721 else if (request->short_not_ok)
722 transfer_size = min_t(unsigned int,
727 transfer_size = min_t(unsigned int,
730 (unsigned)fifo_count);
732 csr &= ~MUSB_RXCSR_DMAMODE;
733 csr |= (MUSB_RXCSR_DMAENAB |
734 MUSB_RXCSR_AUTOCLEAR);
736 musb_writew(epio, MUSB_RXCSR, csr);
738 if (transfer_size <= musb_ep->packet_sz) {
739 musb_ep->dma->desired_mode = 0;
741 musb_ep->dma->desired_mode = 1;
742 /* Mode must be set after DMAENAB */
743 csr |= MUSB_RXCSR_DMAMODE;
744 musb_writew(epio, MUSB_RXCSR, csr);
747 if (c->channel_program(channel,
749 channel->desired_mode,
756 #endif /* Mentor's DMA */
758 len = request->length - request->actual;
759 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
760 musb_ep->end_point.name,
764 fifo_count = min_t(unsigned, len, fifo_count);
766 #ifdef CONFIG_USB_TUSB_OMAP_DMA
767 if (tusb_dma_omap() && is_buffer_mapped(req)) {
768 struct dma_controller *c = musb->dma_controller;
769 struct dma_channel *channel = musb_ep->dma;
770 u32 dma_addr = request->dma + request->actual;
773 ret = c->channel_program(channel,
775 channel->desired_mode,
783 * Unmap the dma buffer back to cpu if dma channel
784 * programming fails. This buffer is mapped if the
785 * channel allocation is successful
787 if (is_buffer_mapped(req)) {
788 unmap_dma_buffer(req, musb);
791 * Clear DMAENAB and AUTOCLEAR for the
794 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
795 musb_writew(epio, MUSB_RXCSR, csr);
798 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
799 (request->buf + request->actual));
800 request->actual += fifo_count;
802 /* REVISIT if we left anything in the fifo, flush
803 * it and report -EOVERFLOW
807 csr |= MUSB_RXCSR_P_WZC_BITS;
808 csr &= ~MUSB_RXCSR_RXPKTRDY;
809 musb_writew(epio, MUSB_RXCSR, csr);
813 /* reach the end or short packet detected */
814 if (request->actual == request->length ||
815 fifo_count < musb_ep->packet_sz)
816 musb_g_giveback(musb_ep, request, 0);
820 * Data ready for a request; called from IRQ
822 void musb_g_rx(struct musb *musb, u8 epnum)
825 struct musb_request *req;
826 struct usb_request *request;
827 void __iomem *mbase = musb->mregs;
828 struct musb_ep *musb_ep;
829 void __iomem *epio = musb->endpoints[epnum].regs;
830 struct dma_channel *dma;
831 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
833 if (hw_ep->is_shared_fifo)
834 musb_ep = &hw_ep->ep_in;
836 musb_ep = &hw_ep->ep_out;
838 musb_ep_select(mbase, epnum);
840 req = next_request(musb_ep);
844 request = &req->request;
846 csr = musb_readw(epio, MUSB_RXCSR);
847 dma = is_dma_capable() ? musb_ep->dma : NULL;
849 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
850 csr, dma ? " (dma)" : "", request);
852 if (csr & MUSB_RXCSR_P_SENTSTALL) {
853 csr |= MUSB_RXCSR_P_WZC_BITS;
854 csr &= ~MUSB_RXCSR_P_SENTSTALL;
855 musb_writew(epio, MUSB_RXCSR, csr);
859 if (csr & MUSB_RXCSR_P_OVERRUN) {
860 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
861 csr &= ~MUSB_RXCSR_P_OVERRUN;
862 musb_writew(epio, MUSB_RXCSR, csr);
864 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
865 if (request->status == -EINPROGRESS)
866 request->status = -EOVERFLOW;
868 if (csr & MUSB_RXCSR_INCOMPRX) {
869 /* REVISIT not necessarily an error */
870 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
873 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
874 /* "should not happen"; likely RXPKTRDY pending for DMA */
875 dev_dbg(musb->controller, "%s busy, csr %04x\n",
876 musb_ep->end_point.name, csr);
880 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
881 csr &= ~(MUSB_RXCSR_AUTOCLEAR
883 | MUSB_RXCSR_DMAMODE);
884 musb_writew(epio, MUSB_RXCSR,
885 MUSB_RXCSR_P_WZC_BITS | csr);
887 request->actual += musb_ep->dma->actual_len;
889 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
891 musb_readw(epio, MUSB_RXCSR),
892 musb_ep->dma->actual_len, request);
894 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
895 defined(CONFIG_USB_UX500_DMA)
896 /* Autoclear doesn't clear RxPktRdy for short packets */
897 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
899 & (musb_ep->packet_sz - 1))) {
901 csr &= ~MUSB_RXCSR_RXPKTRDY;
902 musb_writew(epio, MUSB_RXCSR, csr);
905 /* incomplete, and not short? wait for next IN packet */
906 if ((request->actual < request->length)
907 && (musb_ep->dma->actual_len
908 == musb_ep->packet_sz)) {
909 /* In double buffer case, continue to unload fifo if
910 * there is Rx packet in FIFO.
912 csr = musb_readw(epio, MUSB_RXCSR);
913 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
914 hw_ep->rx_double_buffered)
919 musb_g_giveback(musb_ep, request, 0);
921 * In the giveback function the MUSB lock is
922 * released and acquired after sometime. During
923 * this time period the INDEX register could get
924 * changed by the gadget_queue function especially
925 * on SMP systems. Reselect the INDEX to be sure
926 * we are reading/modifying the right registers
928 musb_ep_select(mbase, epnum);
930 req = next_request(musb_ep);
934 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
935 defined(CONFIG_USB_UX500_DMA)
938 /* Analyze request */
942 /* ------------------------------------------------------------ */
944 static int musb_gadget_enable(struct usb_ep *ep,
945 const struct usb_endpoint_descriptor *desc)
948 struct musb_ep *musb_ep;
949 struct musb_hw_ep *hw_ep;
956 int status = -EINVAL;
961 musb_ep = to_musb_ep(ep);
962 hw_ep = musb_ep->hw_ep;
964 musb = musb_ep->musb;
966 epnum = musb_ep->current_epnum;
968 spin_lock_irqsave(&musb->lock, flags);
974 musb_ep->type = usb_endpoint_type(desc);
976 /* check direction and (later) maxpacket size against endpoint */
977 if (usb_endpoint_num(desc) != epnum)
980 /* REVISIT this rules out high bandwidth periodic transfers */
981 tmp = usb_endpoint_maxp(desc);
985 if (usb_endpoint_dir_in(desc))
986 ok = musb->hb_iso_tx;
988 ok = musb->hb_iso_rx;
991 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
994 musb_ep->hb_mult = (tmp >> 11) & 3;
996 musb_ep->hb_mult = 0;
999 musb_ep->packet_sz = tmp & 0x7ff;
1000 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1002 /* enable the interrupts for the endpoint, set the endpoint
1003 * packet size (or fail), set the mode, clear the fifo
1005 musb_ep_select(mbase, epnum);
1006 if (usb_endpoint_dir_in(desc)) {
1008 if (hw_ep->is_shared_fifo)
1010 if (!musb_ep->is_in)
1013 if (tmp > hw_ep->max_packet_sz_tx) {
1014 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1018 musb->intrtxe |= (1 << epnum);
1019 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1021 /* REVISIT if can_bulk_split(), use by updating "tmp";
1022 * likewise high bandwidth periodic tx
1024 /* Set TXMAXP with the FIFO size of the endpoint
1025 * to disable double buffering mode.
1027 if (musb->double_buffer_not_ok) {
1028 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1030 if (can_bulk_split(musb, musb_ep->type))
1031 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1032 musb_ep->packet_sz) - 1;
1033 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1034 | (musb_ep->hb_mult << 11));
1037 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1038 if (musb_readw(regs, MUSB_TXCSR)
1039 & MUSB_TXCSR_FIFONOTEMPTY)
1040 csr |= MUSB_TXCSR_FLUSHFIFO;
1041 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1042 csr |= MUSB_TXCSR_P_ISO;
1044 /* set twice in case of double buffering */
1045 musb_writew(regs, MUSB_TXCSR, csr);
1046 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1047 musb_writew(regs, MUSB_TXCSR, csr);
1051 if (hw_ep->is_shared_fifo)
1056 if (tmp > hw_ep->max_packet_sz_rx) {
1057 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1061 musb->intrrxe |= (1 << epnum);
1062 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1064 /* REVISIT if can_bulk_combine() use by updating "tmp"
1065 * likewise high bandwidth periodic rx
1067 /* Set RXMAXP with the FIFO size of the endpoint
1068 * to disable double buffering mode.
1070 if (musb->double_buffer_not_ok)
1071 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1073 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1074 | (musb_ep->hb_mult << 11));
1076 /* force shared fifo to OUT-only mode */
1077 if (hw_ep->is_shared_fifo) {
1078 csr = musb_readw(regs, MUSB_TXCSR);
1079 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1080 musb_writew(regs, MUSB_TXCSR, csr);
1083 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1084 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1085 csr |= MUSB_RXCSR_P_ISO;
1086 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1087 csr |= MUSB_RXCSR_DISNYET;
1089 /* set twice in case of double buffering */
1090 musb_writew(regs, MUSB_RXCSR, csr);
1091 musb_writew(regs, MUSB_RXCSR, csr);
1094 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1095 * for some reason you run out of channels here.
1097 if (is_dma_capable() && musb->dma_controller) {
1098 struct dma_controller *c = musb->dma_controller;
1100 musb_ep->dma = c->channel_alloc(c, hw_ep,
1101 (desc->bEndpointAddress & USB_DIR_IN));
1103 musb_ep->dma = NULL;
1105 musb_ep->desc = desc;
1107 musb_ep->wedged = 0;
1110 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1111 musb_driver_name, musb_ep->end_point.name,
1112 ({ char *s; switch (musb_ep->type) {
1113 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1114 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1115 default: s = "iso"; break;
1117 musb_ep->is_in ? "IN" : "OUT",
1118 musb_ep->dma ? "dma, " : "",
1119 musb_ep->packet_sz);
1121 schedule_work(&musb->irq_work);
1124 spin_unlock_irqrestore(&musb->lock, flags);
1129 * Disable an endpoint flushing all requests queued.
1131 static int musb_gadget_disable(struct usb_ep *ep)
1133 unsigned long flags;
1136 struct musb_ep *musb_ep;
1140 musb_ep = to_musb_ep(ep);
1141 musb = musb_ep->musb;
1142 epnum = musb_ep->current_epnum;
1143 epio = musb->endpoints[epnum].regs;
1145 spin_lock_irqsave(&musb->lock, flags);
1146 musb_ep_select(musb->mregs, epnum);
1148 /* zero the endpoint sizes */
1149 if (musb_ep->is_in) {
1150 musb->intrtxe &= ~(1 << epnum);
1151 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1152 musb_writew(epio, MUSB_TXMAXP, 0);
1154 musb->intrrxe &= ~(1 << epnum);
1155 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1156 musb_writew(epio, MUSB_RXMAXP, 0);
1159 musb_ep->desc = NULL;
1160 musb_ep->end_point.desc = NULL;
1162 /* abort all pending DMA and requests */
1163 nuke(musb_ep, -ESHUTDOWN);
1165 schedule_work(&musb->irq_work);
1167 spin_unlock_irqrestore(&(musb->lock), flags);
1169 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1175 * Allocate a request for an endpoint.
1176 * Reused by ep0 code.
1178 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1180 struct musb_ep *musb_ep = to_musb_ep(ep);
1181 struct musb *musb = musb_ep->musb;
1182 struct musb_request *request = NULL;
1184 request = kzalloc(sizeof *request, gfp_flags);
1186 dev_dbg(musb->controller, "not enough memory\n");
1190 request->request.dma = DMA_ADDR_INVALID;
1191 request->epnum = musb_ep->current_epnum;
1192 request->ep = musb_ep;
1194 return &request->request;
1199 * Reused by ep0 code.
1201 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1203 kfree(to_musb_request(req));
1206 static LIST_HEAD(buffers);
1208 struct free_record {
1209 struct list_head list;
1216 * Context: controller locked, IRQs blocked.
1218 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1220 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1221 req->tx ? "TX/IN" : "RX/OUT",
1222 &req->request, req->request.length, req->epnum);
1224 musb_ep_select(musb->mregs, req->epnum);
1231 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1234 struct musb_ep *musb_ep;
1235 struct musb_request *request;
1238 unsigned long lockflags;
1245 musb_ep = to_musb_ep(ep);
1246 musb = musb_ep->musb;
1248 request = to_musb_request(req);
1249 request->musb = musb;
1251 if (request->ep != musb_ep)
1254 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1256 /* request is mine now... */
1257 request->request.actual = 0;
1258 request->request.status = -EINPROGRESS;
1259 request->epnum = musb_ep->current_epnum;
1260 request->tx = musb_ep->is_in;
1262 map_dma_buffer(request, musb, musb_ep);
1264 spin_lock_irqsave(&musb->lock, lockflags);
1266 /* don't queue if the ep is down */
1267 if (!musb_ep->desc) {
1268 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1269 req, ep->name, "disabled");
1270 status = -ESHUTDOWN;
1271 unmap_dma_buffer(request, musb);
1275 /* add request to the list */
1276 list_add_tail(&request->list, &musb_ep->req_list);
1278 /* it this is the head of the queue, start i/o ... */
1279 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1280 musb_ep_restart(musb, request);
1283 spin_unlock_irqrestore(&musb->lock, lockflags);
1287 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1289 struct musb_ep *musb_ep = to_musb_ep(ep);
1290 struct musb_request *req = to_musb_request(request);
1291 struct musb_request *r;
1292 unsigned long flags;
1294 struct musb *musb = musb_ep->musb;
1296 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1299 spin_lock_irqsave(&musb->lock, flags);
1301 list_for_each_entry(r, &musb_ep->req_list, list) {
1306 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1311 /* if the hardware doesn't have the request, easy ... */
1312 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1313 musb_g_giveback(musb_ep, request, -ECONNRESET);
1315 /* ... else abort the dma transfer ... */
1316 else if (is_dma_capable() && musb_ep->dma) {
1317 struct dma_controller *c = musb->dma_controller;
1319 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1320 if (c->channel_abort)
1321 status = c->channel_abort(musb_ep->dma);
1325 musb_g_giveback(musb_ep, request, -ECONNRESET);
1327 /* NOTE: by sticking to easily tested hardware/driver states,
1328 * we leave counting of in-flight packets imprecise.
1330 musb_g_giveback(musb_ep, request, -ECONNRESET);
1334 spin_unlock_irqrestore(&musb->lock, flags);
1339 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1340 * data but will queue requests.
1342 * exported to ep0 code
1344 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1346 struct musb_ep *musb_ep = to_musb_ep(ep);
1347 u8 epnum = musb_ep->current_epnum;
1348 struct musb *musb = musb_ep->musb;
1349 void __iomem *epio = musb->endpoints[epnum].regs;
1350 void __iomem *mbase;
1351 unsigned long flags;
1353 struct musb_request *request;
1358 mbase = musb->mregs;
1360 spin_lock_irqsave(&musb->lock, flags);
1362 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1367 musb_ep_select(mbase, epnum);
1369 request = next_request(musb_ep);
1372 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1377 /* Cannot portably stall with non-empty FIFO */
1378 if (musb_ep->is_in) {
1379 csr = musb_readw(epio, MUSB_TXCSR);
1380 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1381 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1387 musb_ep->wedged = 0;
1389 /* set/clear the stall and toggle bits */
1390 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1391 if (musb_ep->is_in) {
1392 csr = musb_readw(epio, MUSB_TXCSR);
1393 csr |= MUSB_TXCSR_P_WZC_BITS
1394 | MUSB_TXCSR_CLRDATATOG;
1396 csr |= MUSB_TXCSR_P_SENDSTALL;
1398 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1399 | MUSB_TXCSR_P_SENTSTALL);
1400 csr &= ~MUSB_TXCSR_TXPKTRDY;
1401 musb_writew(epio, MUSB_TXCSR, csr);
1403 csr = musb_readw(epio, MUSB_RXCSR);
1404 csr |= MUSB_RXCSR_P_WZC_BITS
1405 | MUSB_RXCSR_FLUSHFIFO
1406 | MUSB_RXCSR_CLRDATATOG;
1408 csr |= MUSB_RXCSR_P_SENDSTALL;
1410 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1411 | MUSB_RXCSR_P_SENTSTALL);
1412 musb_writew(epio, MUSB_RXCSR, csr);
1415 /* maybe start the first request in the queue */
1416 if (!musb_ep->busy && !value && request) {
1417 dev_dbg(musb->controller, "restarting the request\n");
1418 musb_ep_restart(musb, request);
1422 spin_unlock_irqrestore(&musb->lock, flags);
1427 * Sets the halt feature with the clear requests ignored
1429 static int musb_gadget_set_wedge(struct usb_ep *ep)
1431 struct musb_ep *musb_ep = to_musb_ep(ep);
1436 musb_ep->wedged = 1;
1438 return usb_ep_set_halt(ep);
1441 static int musb_gadget_fifo_status(struct usb_ep *ep)
1443 struct musb_ep *musb_ep = to_musb_ep(ep);
1444 void __iomem *epio = musb_ep->hw_ep->regs;
1445 int retval = -EINVAL;
1447 if (musb_ep->desc && !musb_ep->is_in) {
1448 struct musb *musb = musb_ep->musb;
1449 int epnum = musb_ep->current_epnum;
1450 void __iomem *mbase = musb->mregs;
1451 unsigned long flags;
1453 spin_lock_irqsave(&musb->lock, flags);
1455 musb_ep_select(mbase, epnum);
1456 /* FIXME return zero unless RXPKTRDY is set */
1457 retval = musb_readw(epio, MUSB_RXCOUNT);
1459 spin_unlock_irqrestore(&musb->lock, flags);
1464 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1466 struct musb_ep *musb_ep = to_musb_ep(ep);
1467 struct musb *musb = musb_ep->musb;
1468 u8 epnum = musb_ep->current_epnum;
1469 void __iomem *epio = musb->endpoints[epnum].regs;
1470 void __iomem *mbase;
1471 unsigned long flags;
1474 mbase = musb->mregs;
1476 spin_lock_irqsave(&musb->lock, flags);
1477 musb_ep_select(mbase, (u8) epnum);
1479 /* disable interrupts */
1480 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1482 if (musb_ep->is_in) {
1483 csr = musb_readw(epio, MUSB_TXCSR);
1484 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1485 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1487 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1488 * to interrupt current FIFO loading, but not flushing
1489 * the already loaded ones.
1491 csr &= ~MUSB_TXCSR_TXPKTRDY;
1492 musb_writew(epio, MUSB_TXCSR, csr);
1493 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1494 musb_writew(epio, MUSB_TXCSR, csr);
1497 csr = musb_readw(epio, MUSB_RXCSR);
1498 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1499 musb_writew(epio, MUSB_RXCSR, csr);
1500 musb_writew(epio, MUSB_RXCSR, csr);
1503 /* re-enable interrupt */
1504 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1505 spin_unlock_irqrestore(&musb->lock, flags);
1508 static const struct usb_ep_ops musb_ep_ops = {
1509 .enable = musb_gadget_enable,
1510 .disable = musb_gadget_disable,
1511 .alloc_request = musb_alloc_request,
1512 .free_request = musb_free_request,
1513 .queue = musb_gadget_queue,
1514 .dequeue = musb_gadget_dequeue,
1515 .set_halt = musb_gadget_set_halt,
1516 .set_wedge = musb_gadget_set_wedge,
1517 .fifo_status = musb_gadget_fifo_status,
1518 .fifo_flush = musb_gadget_fifo_flush
1521 /* ----------------------------------------------------------------------- */
1523 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1525 struct musb *musb = gadget_to_musb(gadget);
1527 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1530 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1532 struct musb *musb = gadget_to_musb(gadget);
1533 void __iomem *mregs = musb->mregs;
1534 unsigned long flags;
1535 int status = -EINVAL;
1539 spin_lock_irqsave(&musb->lock, flags);
1541 switch (musb->xceiv->state) {
1542 case OTG_STATE_B_PERIPHERAL:
1543 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1544 * that's part of the standard usb 1.1 state machine, and
1545 * doesn't affect OTG transitions.
1547 if (musb->may_wakeup && musb->is_suspended)
1550 case OTG_STATE_B_IDLE:
1551 /* Start SRP ... OTG not required. */
1552 devctl = musb_readb(mregs, MUSB_DEVCTL);
1553 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1554 devctl |= MUSB_DEVCTL_SESSION;
1555 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1556 devctl = musb_readb(mregs, MUSB_DEVCTL);
1558 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1559 devctl = musb_readb(mregs, MUSB_DEVCTL);
1564 while (devctl & MUSB_DEVCTL_SESSION) {
1565 devctl = musb_readb(mregs, MUSB_DEVCTL);
1570 spin_unlock_irqrestore(&musb->lock, flags);
1571 otg_start_srp(musb->xceiv->otg);
1572 spin_lock_irqsave(&musb->lock, flags);
1574 /* Block idling for at least 1s */
1575 musb_platform_try_idle(musb,
1576 jiffies + msecs_to_jiffies(1 * HZ));
1581 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1582 usb_otg_state_string(musb->xceiv->state));
1588 power = musb_readb(mregs, MUSB_POWER);
1589 power |= MUSB_POWER_RESUME;
1590 musb_writeb(mregs, MUSB_POWER, power);
1591 dev_dbg(musb->controller, "issue wakeup\n");
1593 /* FIXME do this next chunk in a timer callback, no udelay */
1596 power = musb_readb(mregs, MUSB_POWER);
1597 power &= ~MUSB_POWER_RESUME;
1598 musb_writeb(mregs, MUSB_POWER, power);
1600 spin_unlock_irqrestore(&musb->lock, flags);
1605 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1607 struct musb *musb = gadget_to_musb(gadget);
1609 musb->is_self_powered = !!is_selfpowered;
1613 static void musb_pullup(struct musb *musb, int is_on)
1617 power = musb_readb(musb->mregs, MUSB_POWER);
1619 power |= MUSB_POWER_SOFTCONN;
1621 power &= ~MUSB_POWER_SOFTCONN;
1623 /* FIXME if on, HdrcStart; if off, HdrcStop */
1625 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1626 is_on ? "on" : "off");
1627 musb_writeb(musb->mregs, MUSB_POWER, power);
1631 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1633 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1636 * FIXME iff driver's softconnect flag is set (as it is during probe,
1637 * though that can clear it), just musb_pullup().
1644 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1646 struct musb *musb = gadget_to_musb(gadget);
1648 if (!musb->xceiv->set_power)
1650 return usb_phy_set_power(musb->xceiv, mA);
1653 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1655 struct musb *musb = gadget_to_musb(gadget);
1656 unsigned long flags;
1660 pm_runtime_get_sync(musb->controller);
1662 /* NOTE: this assumes we are sensing vbus; we'd rather
1663 * not pullup unless the B-session is active.
1665 spin_lock_irqsave(&musb->lock, flags);
1666 if (is_on != musb->softconnect) {
1667 musb->softconnect = is_on;
1668 musb_pullup(musb, is_on);
1670 spin_unlock_irqrestore(&musb->lock, flags);
1672 pm_runtime_put(musb->controller);
1677 static int musb_gadget_start(struct usb_gadget *g,
1678 struct usb_gadget_driver *driver);
1679 static int musb_gadget_stop(struct usb_gadget *g,
1680 struct usb_gadget_driver *driver);
1682 static const struct usb_gadget_ops musb_gadget_operations = {
1683 .get_frame = musb_gadget_get_frame,
1684 .wakeup = musb_gadget_wakeup,
1685 .set_selfpowered = musb_gadget_set_self_powered,
1686 /* .vbus_session = musb_gadget_vbus_session, */
1687 .vbus_draw = musb_gadget_vbus_draw,
1688 .pullup = musb_gadget_pullup,
1689 .udc_start = musb_gadget_start,
1690 .udc_stop = musb_gadget_stop,
1693 /* ----------------------------------------------------------------------- */
1697 /* Only this registration code "knows" the rule (from USB standards)
1698 * about there being only one external upstream port. It assumes
1699 * all peripheral ports are external...
1703 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1705 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1707 memset(ep, 0, sizeof *ep);
1709 ep->current_epnum = epnum;
1714 INIT_LIST_HEAD(&ep->req_list);
1716 sprintf(ep->name, "ep%d%s", epnum,
1717 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1718 is_in ? "in" : "out"));
1719 ep->end_point.name = ep->name;
1720 INIT_LIST_HEAD(&ep->end_point.ep_list);
1722 ep->end_point.maxpacket = 64;
1723 ep->end_point.ops = &musb_g_ep0_ops;
1724 musb->g.ep0 = &ep->end_point;
1727 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1729 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1730 ep->end_point.ops = &musb_ep_ops;
1731 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1736 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1737 * to the rest of the driver state.
1739 static inline void musb_g_init_endpoints(struct musb *musb)
1742 struct musb_hw_ep *hw_ep;
1745 /* initialize endpoint list just once */
1746 INIT_LIST_HEAD(&(musb->g.ep_list));
1748 for (epnum = 0, hw_ep = musb->endpoints;
1749 epnum < musb->nr_endpoints;
1751 if (hw_ep->is_shared_fifo /* || !epnum */) {
1752 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1755 if (hw_ep->max_packet_sz_tx) {
1756 init_peripheral_ep(musb, &hw_ep->ep_in,
1760 if (hw_ep->max_packet_sz_rx) {
1761 init_peripheral_ep(musb, &hw_ep->ep_out,
1769 /* called once during driver setup to initialize and link into
1770 * the driver model; memory is zeroed.
1772 int musb_gadget_setup(struct musb *musb)
1776 /* REVISIT minor race: if (erroneously) setting up two
1777 * musb peripherals at the same time, only the bus lock
1781 musb->g.ops = &musb_gadget_operations;
1782 musb->g.max_speed = USB_SPEED_HIGH;
1783 musb->g.speed = USB_SPEED_UNKNOWN;
1785 /* this "gadget" abstracts/virtualizes the controller */
1786 musb->g.name = musb_driver_name;
1789 musb_g_init_endpoints(musb);
1791 musb->is_active = 0;
1792 musb_platform_try_idle(musb, 0);
1794 status = usb_add_gadget_udc(musb->controller, &musb->g);
1800 musb->g.dev.parent = NULL;
1801 device_unregister(&musb->g.dev);
1805 void musb_gadget_cleanup(struct musb *musb)
1807 usb_del_gadget_udc(&musb->g);
1811 * Register the gadget driver. Used by gadget drivers when
1812 * registering themselves with the controller.
1814 * -EINVAL something went wrong (not driver)
1815 * -EBUSY another gadget is already using the controller
1816 * -ENOMEM no memory to perform the operation
1818 * @param driver the gadget driver
1819 * @return <0 if error, 0 if everything is fine
1821 static int musb_gadget_start(struct usb_gadget *g,
1822 struct usb_gadget_driver *driver)
1824 struct musb *musb = gadget_to_musb(g);
1825 struct usb_otg *otg = musb->xceiv->otg;
1826 unsigned long flags;
1829 if (driver->max_speed < USB_SPEED_HIGH) {
1834 pm_runtime_get_sync(musb->controller);
1836 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1838 musb->softconnect = 0;
1839 musb->gadget_driver = driver;
1841 spin_lock_irqsave(&musb->lock, flags);
1842 musb->is_active = 1;
1844 otg_set_peripheral(otg, &musb->g);
1845 musb->xceiv->state = OTG_STATE_B_IDLE;
1846 spin_unlock_irqrestore(&musb->lock, flags);
1848 /* REVISIT: funcall to other code, which also
1849 * handles power budgeting ... this way also
1850 * ensures HdrcStart is indirectly called.
1852 if (musb->xceiv->last_event == USB_EVENT_ID)
1853 musb_platform_set_vbus(musb, 1);
1855 if (musb->xceiv->last_event == USB_EVENT_NONE)
1856 pm_runtime_put(musb->controller);
1864 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1867 struct musb_hw_ep *hw_ep;
1869 /* don't disconnect if it's not connected */
1870 if (musb->g.speed == USB_SPEED_UNKNOWN)
1873 musb->g.speed = USB_SPEED_UNKNOWN;
1875 /* deactivate the hardware */
1876 if (musb->softconnect) {
1877 musb->softconnect = 0;
1878 musb_pullup(musb, 0);
1882 /* killing any outstanding requests will quiesce the driver;
1883 * then report disconnect
1886 for (i = 0, hw_ep = musb->endpoints;
1887 i < musb->nr_endpoints;
1889 musb_ep_select(musb->mregs, i);
1890 if (hw_ep->is_shared_fifo /* || !epnum */) {
1891 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1893 if (hw_ep->max_packet_sz_tx)
1894 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1895 if (hw_ep->max_packet_sz_rx)
1896 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1903 * Unregister the gadget driver. Used by gadget drivers when
1904 * unregistering themselves from the controller.
1906 * @param driver the gadget driver to unregister
1908 static int musb_gadget_stop(struct usb_gadget *g,
1909 struct usb_gadget_driver *driver)
1911 struct musb *musb = gadget_to_musb(g);
1912 unsigned long flags;
1914 if (musb->xceiv->last_event == USB_EVENT_NONE)
1915 pm_runtime_get_sync(musb->controller);
1918 * REVISIT always use otg_set_peripheral() here too;
1919 * this needs to shut down the OTG engine.
1922 spin_lock_irqsave(&musb->lock, flags);
1924 musb_hnp_stop(musb);
1926 (void) musb_gadget_vbus_draw(&musb->g, 0);
1928 musb->xceiv->state = OTG_STATE_UNDEFINED;
1929 stop_activity(musb, driver);
1930 otg_set_peripheral(musb->xceiv->otg, NULL);
1932 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
1934 musb->is_active = 0;
1935 musb->gadget_driver = NULL;
1936 musb_platform_try_idle(musb, 0);
1937 spin_unlock_irqrestore(&musb->lock, flags);
1940 * FIXME we need to be able to register another
1941 * gadget driver here and have everything work;
1942 * that currently misbehaves.
1945 pm_runtime_put(musb->controller);
1950 /* ----------------------------------------------------------------------- */
1952 /* lifecycle operations called through plat_uds.c */
1954 void musb_g_resume(struct musb *musb)
1956 musb->is_suspended = 0;
1957 switch (musb->xceiv->state) {
1958 case OTG_STATE_B_IDLE:
1960 case OTG_STATE_B_WAIT_ACON:
1961 case OTG_STATE_B_PERIPHERAL:
1962 musb->is_active = 1;
1963 if (musb->gadget_driver && musb->gadget_driver->resume) {
1964 spin_unlock(&musb->lock);
1965 musb->gadget_driver->resume(&musb->g);
1966 spin_lock(&musb->lock);
1970 WARNING("unhandled RESUME transition (%s)\n",
1971 usb_otg_state_string(musb->xceiv->state));
1975 /* called when SOF packets stop for 3+ msec */
1976 void musb_g_suspend(struct musb *musb)
1980 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1981 dev_dbg(musb->controller, "devctl %02x\n", devctl);
1983 switch (musb->xceiv->state) {
1984 case OTG_STATE_B_IDLE:
1985 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1986 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1988 case OTG_STATE_B_PERIPHERAL:
1989 musb->is_suspended = 1;
1990 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1991 spin_unlock(&musb->lock);
1992 musb->gadget_driver->suspend(&musb->g);
1993 spin_lock(&musb->lock);
1997 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1998 * A_PERIPHERAL may need care too
2000 WARNING("unhandled SUSPEND transition (%s)\n",
2001 usb_otg_state_string(musb->xceiv->state));
2005 /* Called during SRP */
2006 void musb_g_wakeup(struct musb *musb)
2008 musb_gadget_wakeup(&musb->g);
2011 /* called when VBUS drops below session threshold, and in other cases */
2012 void musb_g_disconnect(struct musb *musb)
2014 void __iomem *mregs = musb->mregs;
2015 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2017 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2020 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2022 /* don't draw vbus until new b-default session */
2023 (void) musb_gadget_vbus_draw(&musb->g, 0);
2025 musb->g.speed = USB_SPEED_UNKNOWN;
2026 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2027 spin_unlock(&musb->lock);
2028 musb->gadget_driver->disconnect(&musb->g);
2029 spin_lock(&musb->lock);
2032 switch (musb->xceiv->state) {
2034 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2035 usb_otg_state_string(musb->xceiv->state));
2036 musb->xceiv->state = OTG_STATE_A_IDLE;
2037 MUSB_HST_MODE(musb);
2039 case OTG_STATE_A_PERIPHERAL:
2040 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2041 MUSB_HST_MODE(musb);
2043 case OTG_STATE_B_WAIT_ACON:
2044 case OTG_STATE_B_HOST:
2045 case OTG_STATE_B_PERIPHERAL:
2046 case OTG_STATE_B_IDLE:
2047 musb->xceiv->state = OTG_STATE_B_IDLE;
2049 case OTG_STATE_B_SRP_INIT:
2053 musb->is_active = 0;
2056 void musb_g_reset(struct musb *musb)
2057 __releases(musb->lock)
2058 __acquires(musb->lock)
2060 void __iomem *mbase = musb->mregs;
2061 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2064 dev_dbg(musb->controller, "<== %s driver '%s'\n",
2065 (devctl & MUSB_DEVCTL_BDEVICE)
2066 ? "B-Device" : "A-Device",
2068 ? musb->gadget_driver->driver.name
2072 /* report disconnect, if we didn't already (flushing EP state) */
2073 if (musb->g.speed != USB_SPEED_UNKNOWN)
2074 musb_g_disconnect(musb);
2077 else if (devctl & MUSB_DEVCTL_HR)
2078 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2081 /* what speed did we negotiate? */
2082 power = musb_readb(mbase, MUSB_POWER);
2083 musb->g.speed = (power & MUSB_POWER_HSMODE)
2084 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2086 /* start in USB_STATE_DEFAULT */
2087 musb->is_active = 1;
2088 musb->is_suspended = 0;
2089 MUSB_DEV_MODE(musb);
2091 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2093 musb->may_wakeup = 0;
2094 musb->g.b_hnp_enable = 0;
2095 musb->g.a_alt_hnp_support = 0;
2096 musb->g.a_hnp_support = 0;
2098 /* Normal reset, as B-Device;
2099 * or else after HNP, as A-Device
2101 if (devctl & MUSB_DEVCTL_BDEVICE) {
2102 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2103 musb->g.is_a_peripheral = 0;
2105 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2106 musb->g.is_a_peripheral = 1;
2109 /* start with default limits on VBUS power draw */
2110 (void) musb_gadget_vbus_draw(&musb->g, 8);