2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
49 /* MUSB PERIPHERAL status 3-mar-2006:
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
79 * - ISO not tested ... might work, but only weakly isochronous
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
91 /* ----------------------------------------------------------------------- */
93 #define is_buffer_mapped(req) (is_dma_capable() && \
94 (req->map_state != UN_MAPPED))
96 /* Maps the buffer to dma */
98 static inline void map_dma_buffer(struct musb_request *request,
99 struct musb *musb, struct musb_ep *musb_ep)
101 int compatible = true;
102 struct dma_controller *dma = musb->dma_controller;
104 request->map_state = UN_MAPPED;
106 if (!is_dma_capable() || !musb_ep->dma)
109 /* Check if DMA engine can handle this request.
110 * DMA code must reject the USB request explicitly.
111 * Default behaviour is to map the request.
113 if (dma->is_compatible)
114 compatible = dma->is_compatible(musb_ep->dma,
115 musb_ep->packet_sz, request->request.buf,
116 request->request.length);
120 if (request->request.dma == DMA_ADDR_INVALID) {
121 request->request.dma = dma_map_single(
123 request->request.buf,
124 request->request.length,
128 request->map_state = MUSB_MAPPED;
130 dma_sync_single_for_device(musb->controller,
131 request->request.dma,
132 request->request.length,
136 request->map_state = PRE_MAPPED;
140 /* Unmap the buffer from dma and maps it back to cpu */
141 static inline void unmap_dma_buffer(struct musb_request *request,
144 if (!is_buffer_mapped(request))
147 if (request->request.dma == DMA_ADDR_INVALID) {
148 dev_vdbg(musb->controller,
149 "not unmapping a never mapped buffer\n");
152 if (request->map_state == MUSB_MAPPED) {
153 dma_unmap_single(musb->controller,
154 request->request.dma,
155 request->request.length,
159 request->request.dma = DMA_ADDR_INVALID;
160 } else { /* PRE_MAPPED */
161 dma_sync_single_for_cpu(musb->controller,
162 request->request.dma,
163 request->request.length,
168 request->map_state = UN_MAPPED;
172 * Immediately complete a request.
174 * @param request the request to complete
175 * @param status the status to complete the request with
176 * Context: controller locked, IRQs blocked.
178 void musb_g_giveback(
180 struct usb_request *request,
182 __releases(ep->musb->lock)
183 __acquires(ep->musb->lock)
185 struct musb_request *req;
189 req = to_musb_request(request);
191 list_del(&req->list);
192 if (req->request.status == -EINPROGRESS)
193 req->request.status = status;
197 spin_unlock(&musb->lock);
198 unmap_dma_buffer(req, musb);
199 if (request->status == 0)
200 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
201 ep->end_point.name, request,
202 req->request.actual, req->request.length);
204 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
205 ep->end_point.name, request,
206 req->request.actual, req->request.length,
208 req->request.complete(&req->ep->end_point, &req->request);
209 spin_lock(&musb->lock);
213 /* ----------------------------------------------------------------------- */
216 * Abort requests queued to an endpoint using the status. Synchronous.
217 * caller locked controller and blocked irqs, and selected this ep.
219 static void nuke(struct musb_ep *ep, const int status)
221 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
248 value = c->channel_abort(ep->dma);
249 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
251 c->channel_release(ep->dma);
255 while (!list_empty(&ep->req_list)) {
256 req = list_first_entry(&ep->req_list, struct musb_request, list);
257 musb_g_giveback(ep, &req->request, status);
261 /* ----------------------------------------------------------------------- */
263 /* Data transfers - pure PIO, pure DMA, or mixed mode */
266 * This assumes the separate CPPI engine is responding to DMA requests
267 * from the usb core ... sequenced a bit differently from mentor dma.
270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
272 if (can_bulk_split(musb, ep->type))
273 return ep->hw_ep->max_packet_sz_tx;
275 return ep->packet_sz;
279 #ifdef CONFIG_USB_INVENTRA_DMA
281 /* Peripheral tx (IN) using Mentor DMA works as follows:
282 Only mode 0 is used for transfers <= wPktSize,
283 mode 1 is used for larger transfers,
285 One of the following happens:
286 - Host sends IN token which causes an endpoint interrupt
288 -> if DMA is currently busy, exit.
289 -> if queue is non-empty, txstate().
291 - Request is queued by the gadget driver.
292 -> if queue was previously empty, txstate()
297 | (data is transferred to the FIFO, then sent out when
298 | IN token(s) are recd from Host.
299 | -> DMA interrupt on completion
301 | -> stop DMA, ~DMAENAB,
302 | -> set TxPktRdy for last short pkt or zlp
303 | -> Complete Request
304 | -> Continue next request (call txstate)
305 |___________________________________|
307 * Non-Mentor DMA engines can of course work differently, such as by
308 * upleveling from irq-per-packet to irq-per-buffer.
314 * An endpoint is transmitting data. This can be called either from
315 * the IRQ routine or from ep.queue() to kickstart a request on an
318 * Context: controller locked, IRQs blocked, endpoint selected
320 static void txstate(struct musb *musb, struct musb_request *req)
322 u8 epnum = req->epnum;
323 struct musb_ep *musb_ep;
324 void __iomem *epio = musb->endpoints[epnum].regs;
325 struct usb_request *request;
326 u16 fifo_count = 0, csr;
331 /* Check if EP is disabled */
332 if (!musb_ep->desc) {
333 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
334 musb_ep->end_point.name);
338 /* we shouldn't get here while DMA is active ... but we do ... */
339 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
340 dev_dbg(musb->controller, "dma pending...\n");
344 /* read TXCSR before */
345 csr = musb_readw(epio, MUSB_TXCSR);
347 request = &req->request;
348 fifo_count = min(max_ep_writesize(musb, musb_ep),
349 (int)(request->length - request->actual));
351 if (csr & MUSB_TXCSR_TXPKTRDY) {
352 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
353 musb_ep->end_point.name, csr);
357 if (csr & MUSB_TXCSR_P_SENDSTALL) {
358 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
359 musb_ep->end_point.name, csr);
363 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
364 epnum, musb_ep->packet_sz, fifo_count,
367 #ifndef CONFIG_MUSB_PIO_ONLY
368 if (is_buffer_mapped(req)) {
369 struct dma_controller *c = musb->dma_controller;
372 /* setup DMA, then program endpoint CSR */
373 request_size = min_t(size_t, request->length - request->actual,
374 musb_ep->dma->max_len);
376 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
378 /* MUSB_TXCSR_P_ISO is still set correctly */
380 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
382 if (request_size < musb_ep->packet_sz)
383 musb_ep->dma->desired_mode = 0;
385 musb_ep->dma->desired_mode = 1;
387 use_dma = use_dma && c->channel_program(
388 musb_ep->dma, musb_ep->packet_sz,
389 musb_ep->dma->desired_mode,
390 request->dma + request->actual, request_size);
392 if (musb_ep->dma->desired_mode == 0) {
394 * We must not clear the DMAMODE bit
395 * before the DMAENAB bit -- and the
396 * latter doesn't always get cleared
397 * before we get here...
399 csr &= ~(MUSB_TXCSR_AUTOSET
400 | MUSB_TXCSR_DMAENAB);
401 musb_writew(epio, MUSB_TXCSR, csr
402 | MUSB_TXCSR_P_WZC_BITS);
403 csr &= ~MUSB_TXCSR_DMAMODE;
404 csr |= (MUSB_TXCSR_DMAENAB |
406 /* against programming guide */
408 csr |= (MUSB_TXCSR_DMAENAB
411 if (!musb_ep->hb_mult)
412 csr |= MUSB_TXCSR_AUTOSET;
414 csr &= ~MUSB_TXCSR_P_UNDERRUN;
416 musb_writew(epio, MUSB_TXCSR, csr);
420 #elif defined(CONFIG_USB_TI_CPPI_DMA)
421 /* program endpoint CSR first, then setup DMA */
422 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
423 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
425 musb_writew(epio, MUSB_TXCSR,
426 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
429 /* ensure writebuffer is empty */
430 csr = musb_readw(epio, MUSB_TXCSR);
432 /* NOTE host side sets DMAENAB later than this; both are
433 * OK since the transfer dma glue (between CPPI and Mentor
434 * fifos) just tells CPPI it could start. Data only moves
435 * to the USB TX fifo when both fifos are ready.
438 /* "mode" is irrelevant here; handle terminating ZLPs like
439 * PIO does, since the hardware RNDIS mode seems unreliable
440 * except for the last-packet-is-already-short case.
442 use_dma = use_dma && c->channel_program(
443 musb_ep->dma, musb_ep->packet_sz,
445 request->dma + request->actual,
448 c->channel_release(musb_ep->dma);
450 csr &= ~MUSB_TXCSR_DMAENAB;
451 musb_writew(epio, MUSB_TXCSR, csr);
452 /* invariant: prequest->buf is non-null */
454 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
455 use_dma = use_dma && c->channel_program(
456 musb_ep->dma, musb_ep->packet_sz,
458 request->dma + request->actual,
466 * Unmap the dma buffer back to cpu if dma channel
469 unmap_dma_buffer(req, musb);
471 musb_write_fifo(musb_ep->hw_ep, fifo_count,
472 (u8 *) (request->buf + request->actual));
473 request->actual += fifo_count;
474 csr |= MUSB_TXCSR_TXPKTRDY;
475 csr &= ~MUSB_TXCSR_P_UNDERRUN;
476 musb_writew(epio, MUSB_TXCSR, csr);
479 /* host may already have the data when this message shows... */
480 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
481 musb_ep->end_point.name, use_dma ? "dma" : "pio",
482 request->actual, request->length,
483 musb_readw(epio, MUSB_TXCSR),
485 musb_readw(epio, MUSB_TXMAXP));
489 * FIFO state update (e.g. data ready).
490 * Called from IRQ, with controller locked.
492 void musb_g_tx(struct musb *musb, u8 epnum)
495 struct musb_request *req;
496 struct usb_request *request;
497 u8 __iomem *mbase = musb->mregs;
498 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
499 void __iomem *epio = musb->endpoints[epnum].regs;
500 struct dma_channel *dma;
502 musb_ep_select(mbase, epnum);
503 req = next_request(musb_ep);
504 request = &req->request;
506 csr = musb_readw(epio, MUSB_TXCSR);
507 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
509 dma = is_dma_capable() ? musb_ep->dma : NULL;
512 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
513 * probably rates reporting as a host error.
515 if (csr & MUSB_TXCSR_P_SENTSTALL) {
516 csr |= MUSB_TXCSR_P_WZC_BITS;
517 csr &= ~MUSB_TXCSR_P_SENTSTALL;
518 musb_writew(epio, MUSB_TXCSR, csr);
522 if (csr & MUSB_TXCSR_P_UNDERRUN) {
523 /* We NAKed, no big deal... little reason to care. */
524 csr |= MUSB_TXCSR_P_WZC_BITS;
525 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
526 musb_writew(epio, MUSB_TXCSR, csr);
527 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
531 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
533 * SHOULD NOT HAPPEN... has with CPPI though, after
534 * changing SENDSTALL (and other cases); harmless?
536 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
543 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
545 csr |= MUSB_TXCSR_P_WZC_BITS;
546 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
547 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
548 musb_writew(epio, MUSB_TXCSR, csr);
549 /* Ensure writebuffer is empty. */
550 csr = musb_readw(epio, MUSB_TXCSR);
551 request->actual += musb_ep->dma->actual_len;
552 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
553 epnum, csr, musb_ep->dma->actual_len, request);
557 * First, maybe a terminating short packet. Some DMA
558 * engines might handle this by themselves.
560 if ((request->zero && request->length
561 && (request->length % musb_ep->packet_sz == 0)
562 && (request->actual == request->length))
563 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
564 || (is_dma && (!dma->desired_mode ||
566 (musb_ep->packet_sz - 1))))
570 * On DMA completion, FIFO may not be
573 if (csr & MUSB_TXCSR_TXPKTRDY)
576 dev_dbg(musb->controller, "sending zero pkt\n");
577 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
578 | MUSB_TXCSR_TXPKTRDY);
582 if (request->actual == request->length) {
583 musb_g_giveback(musb_ep, request, 0);
585 * In the giveback function the MUSB lock is
586 * released and acquired after sometime. During
587 * this time period the INDEX register could get
588 * changed by the gadget_queue function especially
589 * on SMP systems. Reselect the INDEX to be sure
590 * we are reading/modifying the right registers
592 musb_ep_select(mbase, epnum);
593 req = musb_ep->desc ? next_request(musb_ep) : NULL;
595 dev_dbg(musb->controller, "%s idle now\n",
596 musb_ep->end_point.name);
605 /* ------------------------------------------------------------ */
607 #ifdef CONFIG_USB_INVENTRA_DMA
609 /* Peripheral rx (OUT) using Mentor DMA works as follows:
610 - Only mode 0 is used.
612 - Request is queued by the gadget class driver.
613 -> if queue was previously empty, rxstate()
615 - Host sends OUT token which causes an endpoint interrupt
617 | -> if request queued, call rxstate
619 | | -> DMA interrupt on completion
623 | | -> if data recd = max expected
624 | | by the request, or host
625 | | sent a short packet,
626 | | complete the request,
627 | | and start the next one.
628 | |_____________________________________|
629 | else just wait for the host
630 | to send the next OUT token.
631 |__________________________________________________|
633 * Non-Mentor DMA engines can of course work differently.
639 * Context: controller locked, IRQs blocked, endpoint selected
641 static void rxstate(struct musb *musb, struct musb_request *req)
643 const u8 epnum = req->epnum;
644 struct usb_request *request = &req->request;
645 struct musb_ep *musb_ep;
646 void __iomem *epio = musb->endpoints[epnum].regs;
649 u16 csr = musb_readw(epio, MUSB_RXCSR);
650 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
653 if (hw_ep->is_shared_fifo)
654 musb_ep = &hw_ep->ep_in;
656 musb_ep = &hw_ep->ep_out;
658 fifo_count = musb_ep->packet_sz;
660 /* Check if EP is disabled */
661 if (!musb_ep->desc) {
662 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
663 musb_ep->end_point.name);
667 /* We shouldn't get here while DMA is active, but we do... */
668 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
669 dev_dbg(musb->controller, "DMA pending...\n");
673 if (csr & MUSB_RXCSR_P_SENDSTALL) {
674 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
675 musb_ep->end_point.name, csr);
679 if (is_cppi_enabled() && is_buffer_mapped(req)) {
680 struct dma_controller *c = musb->dma_controller;
681 struct dma_channel *channel = musb_ep->dma;
683 /* NOTE: CPPI won't actually stop advancing the DMA
684 * queue after short packet transfers, so this is almost
685 * always going to run as IRQ-per-packet DMA so that
686 * faults will be handled correctly.
688 if (c->channel_program(channel,
690 !request->short_not_ok,
691 request->dma + request->actual,
692 request->length - request->actual)) {
694 /* make sure that if an rxpkt arrived after the irq,
695 * the cppi engine will be ready to take it as soon
698 csr &= ~(MUSB_RXCSR_AUTOCLEAR
699 | MUSB_RXCSR_DMAMODE);
700 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
701 musb_writew(epio, MUSB_RXCSR, csr);
706 if (csr & MUSB_RXCSR_RXPKTRDY) {
707 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
710 * use mode 1 only if we expect data of at least ep packet_sz
711 * and have not yet received a short packet
713 if ((request->length - request->actual >= musb_ep->packet_sz) &&
714 (fifo_count >= musb_ep->packet_sz))
719 if (request->actual < request->length) {
720 #ifdef CONFIG_USB_INVENTRA_DMA
721 if (is_buffer_mapped(req)) {
722 struct dma_controller *c;
723 struct dma_channel *channel;
727 c = musb->dma_controller;
728 channel = musb_ep->dma;
730 /* Experimental: Mode1 works with mass storage use cases */
732 csr |= MUSB_RXCSR_AUTOCLEAR;
733 musb_writew(epio, MUSB_RXCSR, csr);
734 csr |= MUSB_RXCSR_DMAENAB;
735 musb_writew(epio, MUSB_RXCSR, csr);
738 * this special sequence (enabling and then
739 * disabling MUSB_RXCSR_DMAMODE) is required
740 * to get DMAReq to activate
742 musb_writew(epio, MUSB_RXCSR,
743 csr | MUSB_RXCSR_DMAMODE);
744 musb_writew(epio, MUSB_RXCSR, csr);
746 transfer_size = min(request->length - request->actual,
748 musb_ep->dma->desired_mode = 1;
751 if (!musb_ep->hb_mult &&
752 musb_ep->hw_ep->rx_double_buffered)
753 csr |= MUSB_RXCSR_AUTOCLEAR;
754 csr |= MUSB_RXCSR_DMAENAB;
755 musb_writew(epio, MUSB_RXCSR, csr);
757 transfer_size = min(request->length - request->actual,
758 (unsigned)fifo_count);
759 musb_ep->dma->desired_mode = 0;
762 use_dma = c->channel_program(
765 channel->desired_mode,
773 #elif defined(CONFIG_USB_UX500_DMA)
774 if ((is_buffer_mapped(req)) &&
775 (request->actual < request->length)) {
777 struct dma_controller *c;
778 struct dma_channel *channel;
779 int transfer_size = 0;
781 c = musb->dma_controller;
782 channel = musb_ep->dma;
784 /* In case first packet is short */
785 if (fifo_count < musb_ep->packet_sz)
786 transfer_size = fifo_count;
787 else if (request->short_not_ok)
788 transfer_size = min(request->length -
792 transfer_size = min(request->length -
794 (unsigned)fifo_count);
796 csr &= ~MUSB_RXCSR_DMAMODE;
797 csr |= (MUSB_RXCSR_DMAENAB |
798 MUSB_RXCSR_AUTOCLEAR);
800 musb_writew(epio, MUSB_RXCSR, csr);
802 if (transfer_size <= musb_ep->packet_sz) {
803 musb_ep->dma->desired_mode = 0;
805 musb_ep->dma->desired_mode = 1;
806 /* Mode must be set after DMAENAB */
807 csr |= MUSB_RXCSR_DMAMODE;
808 musb_writew(epio, MUSB_RXCSR, csr);
811 if (c->channel_program(channel,
813 channel->desired_mode,
820 #endif /* Mentor's DMA */
822 len = request->length - request->actual;
823 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
824 musb_ep->end_point.name,
828 fifo_count = min_t(unsigned, len, fifo_count);
830 #ifdef CONFIG_USB_TUSB_OMAP_DMA
831 if (tusb_dma_omap() && is_buffer_mapped(req)) {
832 struct dma_controller *c = musb->dma_controller;
833 struct dma_channel *channel = musb_ep->dma;
834 u32 dma_addr = request->dma + request->actual;
837 ret = c->channel_program(channel,
839 channel->desired_mode,
847 * Unmap the dma buffer back to cpu if dma channel
848 * programming fails. This buffer is mapped if the
849 * channel allocation is successful
851 if (is_buffer_mapped(req)) {
852 unmap_dma_buffer(req, musb);
855 * Clear DMAENAB and AUTOCLEAR for the
858 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
859 musb_writew(epio, MUSB_RXCSR, csr);
862 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
863 (request->buf + request->actual));
864 request->actual += fifo_count;
866 /* REVISIT if we left anything in the fifo, flush
867 * it and report -EOVERFLOW
871 csr |= MUSB_RXCSR_P_WZC_BITS;
872 csr &= ~MUSB_RXCSR_RXPKTRDY;
873 musb_writew(epio, MUSB_RXCSR, csr);
877 /* reach the end or short packet detected */
878 if (request->actual == request->length ||
879 fifo_count < musb_ep->packet_sz)
880 musb_g_giveback(musb_ep, request, 0);
884 * Data ready for a request; called from IRQ
886 void musb_g_rx(struct musb *musb, u8 epnum)
889 struct musb_request *req;
890 struct usb_request *request;
891 void __iomem *mbase = musb->mregs;
892 struct musb_ep *musb_ep;
893 void __iomem *epio = musb->endpoints[epnum].regs;
894 struct dma_channel *dma;
895 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
897 if (hw_ep->is_shared_fifo)
898 musb_ep = &hw_ep->ep_in;
900 musb_ep = &hw_ep->ep_out;
902 musb_ep_select(mbase, epnum);
904 req = next_request(musb_ep);
908 request = &req->request;
910 csr = musb_readw(epio, MUSB_RXCSR);
911 dma = is_dma_capable() ? musb_ep->dma : NULL;
913 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
914 csr, dma ? " (dma)" : "", request);
916 if (csr & MUSB_RXCSR_P_SENTSTALL) {
917 csr |= MUSB_RXCSR_P_WZC_BITS;
918 csr &= ~MUSB_RXCSR_P_SENTSTALL;
919 musb_writew(epio, MUSB_RXCSR, csr);
923 if (csr & MUSB_RXCSR_P_OVERRUN) {
924 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
925 csr &= ~MUSB_RXCSR_P_OVERRUN;
926 musb_writew(epio, MUSB_RXCSR, csr);
928 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
929 if (request->status == -EINPROGRESS)
930 request->status = -EOVERFLOW;
932 if (csr & MUSB_RXCSR_INCOMPRX) {
933 /* REVISIT not necessarily an error */
934 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
937 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
938 /* "should not happen"; likely RXPKTRDY pending for DMA */
939 dev_dbg(musb->controller, "%s busy, csr %04x\n",
940 musb_ep->end_point.name, csr);
944 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
945 csr &= ~(MUSB_RXCSR_AUTOCLEAR
947 | MUSB_RXCSR_DMAMODE);
948 musb_writew(epio, MUSB_RXCSR,
949 MUSB_RXCSR_P_WZC_BITS | csr);
951 request->actual += musb_ep->dma->actual_len;
953 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
955 musb_readw(epio, MUSB_RXCSR),
956 musb_ep->dma->actual_len, request);
958 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
959 defined(CONFIG_USB_UX500_DMA)
960 /* Autoclear doesn't clear RxPktRdy for short packets */
961 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
963 & (musb_ep->packet_sz - 1))) {
965 csr &= ~MUSB_RXCSR_RXPKTRDY;
966 musb_writew(epio, MUSB_RXCSR, csr);
969 /* incomplete, and not short? wait for next IN packet */
970 if ((request->actual < request->length)
971 && (musb_ep->dma->actual_len
972 == musb_ep->packet_sz)) {
973 /* In double buffer case, continue to unload fifo if
974 * there is Rx packet in FIFO.
976 csr = musb_readw(epio, MUSB_RXCSR);
977 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
978 hw_ep->rx_double_buffered)
983 musb_g_giveback(musb_ep, request, 0);
985 * In the giveback function the MUSB lock is
986 * released and acquired after sometime. During
987 * this time period the INDEX register could get
988 * changed by the gadget_queue function especially
989 * on SMP systems. Reselect the INDEX to be sure
990 * we are reading/modifying the right registers
992 musb_ep_select(mbase, epnum);
994 req = next_request(musb_ep);
998 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
999 defined(CONFIG_USB_UX500_DMA)
1002 /* Analyze request */
1006 /* ------------------------------------------------------------ */
1008 static int musb_gadget_enable(struct usb_ep *ep,
1009 const struct usb_endpoint_descriptor *desc)
1011 unsigned long flags;
1012 struct musb_ep *musb_ep;
1013 struct musb_hw_ep *hw_ep;
1016 void __iomem *mbase;
1020 int status = -EINVAL;
1025 musb_ep = to_musb_ep(ep);
1026 hw_ep = musb_ep->hw_ep;
1028 musb = musb_ep->musb;
1029 mbase = musb->mregs;
1030 epnum = musb_ep->current_epnum;
1032 spin_lock_irqsave(&musb->lock, flags);
1034 if (musb_ep->desc) {
1038 musb_ep->type = usb_endpoint_type(desc);
1040 /* check direction and (later) maxpacket size against endpoint */
1041 if (usb_endpoint_num(desc) != epnum)
1044 /* REVISIT this rules out high bandwidth periodic transfers */
1045 tmp = usb_endpoint_maxp(desc);
1046 if (tmp & ~0x07ff) {
1049 if (usb_endpoint_dir_in(desc))
1050 ok = musb->hb_iso_tx;
1052 ok = musb->hb_iso_rx;
1055 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1058 musb_ep->hb_mult = (tmp >> 11) & 3;
1060 musb_ep->hb_mult = 0;
1063 musb_ep->packet_sz = tmp & 0x7ff;
1064 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1066 /* enable the interrupts for the endpoint, set the endpoint
1067 * packet size (or fail), set the mode, clear the fifo
1069 musb_ep_select(mbase, epnum);
1070 if (usb_endpoint_dir_in(desc)) {
1071 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1073 if (hw_ep->is_shared_fifo)
1075 if (!musb_ep->is_in)
1078 if (tmp > hw_ep->max_packet_sz_tx) {
1079 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1083 int_txe |= (1 << epnum);
1084 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1086 /* REVISIT if can_bulk_split(), use by updating "tmp";
1087 * likewise high bandwidth periodic tx
1089 /* Set TXMAXP with the FIFO size of the endpoint
1090 * to disable double buffering mode.
1092 if (musb->double_buffer_not_ok)
1093 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1095 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1096 | (musb_ep->hb_mult << 11));
1098 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1099 if (musb_readw(regs, MUSB_TXCSR)
1100 & MUSB_TXCSR_FIFONOTEMPTY)
1101 csr |= MUSB_TXCSR_FLUSHFIFO;
1102 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1103 csr |= MUSB_TXCSR_P_ISO;
1105 /* set twice in case of double buffering */
1106 musb_writew(regs, MUSB_TXCSR, csr);
1107 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1108 musb_writew(regs, MUSB_TXCSR, csr);
1111 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1113 if (hw_ep->is_shared_fifo)
1118 if (tmp > hw_ep->max_packet_sz_rx) {
1119 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1123 int_rxe |= (1 << epnum);
1124 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1126 /* REVISIT if can_bulk_combine() use by updating "tmp"
1127 * likewise high bandwidth periodic rx
1129 /* Set RXMAXP with the FIFO size of the endpoint
1130 * to disable double buffering mode.
1132 if (musb->double_buffer_not_ok)
1133 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1135 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1136 | (musb_ep->hb_mult << 11));
1138 /* force shared fifo to OUT-only mode */
1139 if (hw_ep->is_shared_fifo) {
1140 csr = musb_readw(regs, MUSB_TXCSR);
1141 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1142 musb_writew(regs, MUSB_TXCSR, csr);
1145 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1146 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1147 csr |= MUSB_RXCSR_P_ISO;
1148 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1149 csr |= MUSB_RXCSR_DISNYET;
1151 /* set twice in case of double buffering */
1152 musb_writew(regs, MUSB_RXCSR, csr);
1153 musb_writew(regs, MUSB_RXCSR, csr);
1156 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1157 * for some reason you run out of channels here.
1159 if (is_dma_capable() && musb->dma_controller) {
1160 struct dma_controller *c = musb->dma_controller;
1162 musb_ep->dma = c->channel_alloc(c, hw_ep,
1163 (desc->bEndpointAddress & USB_DIR_IN));
1165 musb_ep->dma = NULL;
1167 musb_ep->desc = desc;
1169 musb_ep->wedged = 0;
1172 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1173 musb_driver_name, musb_ep->end_point.name,
1174 ({ char *s; switch (musb_ep->type) {
1175 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1176 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1177 default: s = "iso"; break;
1179 musb_ep->is_in ? "IN" : "OUT",
1180 musb_ep->dma ? "dma, " : "",
1181 musb_ep->packet_sz);
1183 schedule_work(&musb->irq_work);
1186 spin_unlock_irqrestore(&musb->lock, flags);
1191 * Disable an endpoint flushing all requests queued.
1193 static int musb_gadget_disable(struct usb_ep *ep)
1195 unsigned long flags;
1198 struct musb_ep *musb_ep;
1202 musb_ep = to_musb_ep(ep);
1203 musb = musb_ep->musb;
1204 epnum = musb_ep->current_epnum;
1205 epio = musb->endpoints[epnum].regs;
1207 spin_lock_irqsave(&musb->lock, flags);
1208 musb_ep_select(musb->mregs, epnum);
1210 /* zero the endpoint sizes */
1211 if (musb_ep->is_in) {
1212 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1213 int_txe &= ~(1 << epnum);
1214 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1215 musb_writew(epio, MUSB_TXMAXP, 0);
1217 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1218 int_rxe &= ~(1 << epnum);
1219 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1220 musb_writew(epio, MUSB_RXMAXP, 0);
1223 musb_ep->desc = NULL;
1224 musb_ep->end_point.desc = NULL;
1226 /* abort all pending DMA and requests */
1227 nuke(musb_ep, -ESHUTDOWN);
1229 schedule_work(&musb->irq_work);
1231 spin_unlock_irqrestore(&(musb->lock), flags);
1233 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1239 * Allocate a request for an endpoint.
1240 * Reused by ep0 code.
1242 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1244 struct musb_ep *musb_ep = to_musb_ep(ep);
1245 struct musb *musb = musb_ep->musb;
1246 struct musb_request *request = NULL;
1248 request = kzalloc(sizeof *request, gfp_flags);
1250 dev_dbg(musb->controller, "not enough memory\n");
1254 request->request.dma = DMA_ADDR_INVALID;
1255 request->epnum = musb_ep->current_epnum;
1256 request->ep = musb_ep;
1258 return &request->request;
1263 * Reused by ep0 code.
1265 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1267 kfree(to_musb_request(req));
1270 static LIST_HEAD(buffers);
1272 struct free_record {
1273 struct list_head list;
1280 * Context: controller locked, IRQs blocked.
1282 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1284 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1285 req->tx ? "TX/IN" : "RX/OUT",
1286 &req->request, req->request.length, req->epnum);
1288 musb_ep_select(musb->mregs, req->epnum);
1295 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1298 struct musb_ep *musb_ep;
1299 struct musb_request *request;
1302 unsigned long lockflags;
1309 musb_ep = to_musb_ep(ep);
1310 musb = musb_ep->musb;
1312 request = to_musb_request(req);
1313 request->musb = musb;
1315 if (request->ep != musb_ep)
1318 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1320 /* request is mine now... */
1321 request->request.actual = 0;
1322 request->request.status = -EINPROGRESS;
1323 request->epnum = musb_ep->current_epnum;
1324 request->tx = musb_ep->is_in;
1326 map_dma_buffer(request, musb, musb_ep);
1328 spin_lock_irqsave(&musb->lock, lockflags);
1330 /* don't queue if the ep is down */
1331 if (!musb_ep->desc) {
1332 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1333 req, ep->name, "disabled");
1334 status = -ESHUTDOWN;
1338 /* add request to the list */
1339 list_add_tail(&request->list, &musb_ep->req_list);
1341 /* it this is the head of the queue, start i/o ... */
1342 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1343 musb_ep_restart(musb, request);
1346 spin_unlock_irqrestore(&musb->lock, lockflags);
1350 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1352 struct musb_ep *musb_ep = to_musb_ep(ep);
1353 struct musb_request *req = to_musb_request(request);
1354 struct musb_request *r;
1355 unsigned long flags;
1357 struct musb *musb = musb_ep->musb;
1359 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1362 spin_lock_irqsave(&musb->lock, flags);
1364 list_for_each_entry(r, &musb_ep->req_list, list) {
1369 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1374 /* if the hardware doesn't have the request, easy ... */
1375 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1376 musb_g_giveback(musb_ep, request, -ECONNRESET);
1378 /* ... else abort the dma transfer ... */
1379 else if (is_dma_capable() && musb_ep->dma) {
1380 struct dma_controller *c = musb->dma_controller;
1382 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1383 if (c->channel_abort)
1384 status = c->channel_abort(musb_ep->dma);
1388 musb_g_giveback(musb_ep, request, -ECONNRESET);
1390 /* NOTE: by sticking to easily tested hardware/driver states,
1391 * we leave counting of in-flight packets imprecise.
1393 musb_g_giveback(musb_ep, request, -ECONNRESET);
1397 spin_unlock_irqrestore(&musb->lock, flags);
1402 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1403 * data but will queue requests.
1405 * exported to ep0 code
1407 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1409 struct musb_ep *musb_ep = to_musb_ep(ep);
1410 u8 epnum = musb_ep->current_epnum;
1411 struct musb *musb = musb_ep->musb;
1412 void __iomem *epio = musb->endpoints[epnum].regs;
1413 void __iomem *mbase;
1414 unsigned long flags;
1416 struct musb_request *request;
1421 mbase = musb->mregs;
1423 spin_lock_irqsave(&musb->lock, flags);
1425 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1430 musb_ep_select(mbase, epnum);
1432 request = next_request(musb_ep);
1435 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1440 /* Cannot portably stall with non-empty FIFO */
1441 if (musb_ep->is_in) {
1442 csr = musb_readw(epio, MUSB_TXCSR);
1443 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1444 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1450 musb_ep->wedged = 0;
1452 /* set/clear the stall and toggle bits */
1453 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1454 if (musb_ep->is_in) {
1455 csr = musb_readw(epio, MUSB_TXCSR);
1456 csr |= MUSB_TXCSR_P_WZC_BITS
1457 | MUSB_TXCSR_CLRDATATOG;
1459 csr |= MUSB_TXCSR_P_SENDSTALL;
1461 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1462 | MUSB_TXCSR_P_SENTSTALL);
1463 csr &= ~MUSB_TXCSR_TXPKTRDY;
1464 musb_writew(epio, MUSB_TXCSR, csr);
1466 csr = musb_readw(epio, MUSB_RXCSR);
1467 csr |= MUSB_RXCSR_P_WZC_BITS
1468 | MUSB_RXCSR_FLUSHFIFO
1469 | MUSB_RXCSR_CLRDATATOG;
1471 csr |= MUSB_RXCSR_P_SENDSTALL;
1473 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1474 | MUSB_RXCSR_P_SENTSTALL);
1475 musb_writew(epio, MUSB_RXCSR, csr);
1478 /* maybe start the first request in the queue */
1479 if (!musb_ep->busy && !value && request) {
1480 dev_dbg(musb->controller, "restarting the request\n");
1481 musb_ep_restart(musb, request);
1485 spin_unlock_irqrestore(&musb->lock, flags);
1490 * Sets the halt feature with the clear requests ignored
1492 static int musb_gadget_set_wedge(struct usb_ep *ep)
1494 struct musb_ep *musb_ep = to_musb_ep(ep);
1499 musb_ep->wedged = 1;
1501 return usb_ep_set_halt(ep);
1504 static int musb_gadget_fifo_status(struct usb_ep *ep)
1506 struct musb_ep *musb_ep = to_musb_ep(ep);
1507 void __iomem *epio = musb_ep->hw_ep->regs;
1508 int retval = -EINVAL;
1510 if (musb_ep->desc && !musb_ep->is_in) {
1511 struct musb *musb = musb_ep->musb;
1512 int epnum = musb_ep->current_epnum;
1513 void __iomem *mbase = musb->mregs;
1514 unsigned long flags;
1516 spin_lock_irqsave(&musb->lock, flags);
1518 musb_ep_select(mbase, epnum);
1519 /* FIXME return zero unless RXPKTRDY is set */
1520 retval = musb_readw(epio, MUSB_RXCOUNT);
1522 spin_unlock_irqrestore(&musb->lock, flags);
1527 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1529 struct musb_ep *musb_ep = to_musb_ep(ep);
1530 struct musb *musb = musb_ep->musb;
1531 u8 epnum = musb_ep->current_epnum;
1532 void __iomem *epio = musb->endpoints[epnum].regs;
1533 void __iomem *mbase;
1534 unsigned long flags;
1537 mbase = musb->mregs;
1539 spin_lock_irqsave(&musb->lock, flags);
1540 musb_ep_select(mbase, (u8) epnum);
1542 /* disable interrupts */
1543 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1544 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1546 if (musb_ep->is_in) {
1547 csr = musb_readw(epio, MUSB_TXCSR);
1548 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1549 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1551 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1552 * to interrupt current FIFO loading, but not flushing
1553 * the already loaded ones.
1555 csr &= ~MUSB_TXCSR_TXPKTRDY;
1556 musb_writew(epio, MUSB_TXCSR, csr);
1557 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1558 musb_writew(epio, MUSB_TXCSR, csr);
1561 csr = musb_readw(epio, MUSB_RXCSR);
1562 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1563 musb_writew(epio, MUSB_RXCSR, csr);
1564 musb_writew(epio, MUSB_RXCSR, csr);
1567 /* re-enable interrupt */
1568 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1569 spin_unlock_irqrestore(&musb->lock, flags);
1572 static const struct usb_ep_ops musb_ep_ops = {
1573 .enable = musb_gadget_enable,
1574 .disable = musb_gadget_disable,
1575 .alloc_request = musb_alloc_request,
1576 .free_request = musb_free_request,
1577 .queue = musb_gadget_queue,
1578 .dequeue = musb_gadget_dequeue,
1579 .set_halt = musb_gadget_set_halt,
1580 .set_wedge = musb_gadget_set_wedge,
1581 .fifo_status = musb_gadget_fifo_status,
1582 .fifo_flush = musb_gadget_fifo_flush
1585 /* ----------------------------------------------------------------------- */
1587 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1589 struct musb *musb = gadget_to_musb(gadget);
1591 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1594 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1596 struct musb *musb = gadget_to_musb(gadget);
1597 void __iomem *mregs = musb->mregs;
1598 unsigned long flags;
1599 int status = -EINVAL;
1603 spin_lock_irqsave(&musb->lock, flags);
1605 switch (musb->xceiv->state) {
1606 case OTG_STATE_B_PERIPHERAL:
1607 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1608 * that's part of the standard usb 1.1 state machine, and
1609 * doesn't affect OTG transitions.
1611 if (musb->may_wakeup && musb->is_suspended)
1614 case OTG_STATE_B_IDLE:
1615 /* Start SRP ... OTG not required. */
1616 devctl = musb_readb(mregs, MUSB_DEVCTL);
1617 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1618 devctl |= MUSB_DEVCTL_SESSION;
1619 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1620 devctl = musb_readb(mregs, MUSB_DEVCTL);
1622 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1623 devctl = musb_readb(mregs, MUSB_DEVCTL);
1628 while (devctl & MUSB_DEVCTL_SESSION) {
1629 devctl = musb_readb(mregs, MUSB_DEVCTL);
1634 spin_unlock_irqrestore(&musb->lock, flags);
1635 otg_start_srp(musb->xceiv->otg);
1636 spin_lock_irqsave(&musb->lock, flags);
1638 /* Block idling for at least 1s */
1639 musb_platform_try_idle(musb,
1640 jiffies + msecs_to_jiffies(1 * HZ));
1645 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1646 otg_state_string(musb->xceiv->state));
1652 power = musb_readb(mregs, MUSB_POWER);
1653 power |= MUSB_POWER_RESUME;
1654 musb_writeb(mregs, MUSB_POWER, power);
1655 dev_dbg(musb->controller, "issue wakeup\n");
1657 /* FIXME do this next chunk in a timer callback, no udelay */
1660 power = musb_readb(mregs, MUSB_POWER);
1661 power &= ~MUSB_POWER_RESUME;
1662 musb_writeb(mregs, MUSB_POWER, power);
1664 spin_unlock_irqrestore(&musb->lock, flags);
1669 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1671 struct musb *musb = gadget_to_musb(gadget);
1673 musb->is_self_powered = !!is_selfpowered;
1677 static void musb_pullup(struct musb *musb, int is_on)
1681 power = musb_readb(musb->mregs, MUSB_POWER);
1683 power |= MUSB_POWER_SOFTCONN;
1685 power &= ~MUSB_POWER_SOFTCONN;
1687 /* FIXME if on, HdrcStart; if off, HdrcStop */
1689 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1690 is_on ? "on" : "off");
1691 musb_writeb(musb->mregs, MUSB_POWER, power);
1695 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1697 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1700 * FIXME iff driver's softconnect flag is set (as it is during probe,
1701 * though that can clear it), just musb_pullup().
1708 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1710 struct musb *musb = gadget_to_musb(gadget);
1712 if (!musb->xceiv->set_power)
1714 return usb_phy_set_power(musb->xceiv, mA);
1717 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1719 struct musb *musb = gadget_to_musb(gadget);
1720 unsigned long flags;
1724 pm_runtime_get_sync(musb->controller);
1726 /* NOTE: this assumes we are sensing vbus; we'd rather
1727 * not pullup unless the B-session is active.
1729 spin_lock_irqsave(&musb->lock, flags);
1730 if (is_on != musb->softconnect) {
1731 musb->softconnect = is_on;
1732 musb_pullup(musb, is_on);
1734 spin_unlock_irqrestore(&musb->lock, flags);
1736 pm_runtime_put(musb->controller);
1741 static int musb_gadget_start(struct usb_gadget *g,
1742 struct usb_gadget_driver *driver);
1743 static int musb_gadget_stop(struct usb_gadget *g,
1744 struct usb_gadget_driver *driver);
1746 static const struct usb_gadget_ops musb_gadget_operations = {
1747 .get_frame = musb_gadget_get_frame,
1748 .wakeup = musb_gadget_wakeup,
1749 .set_selfpowered = musb_gadget_set_self_powered,
1750 /* .vbus_session = musb_gadget_vbus_session, */
1751 .vbus_draw = musb_gadget_vbus_draw,
1752 .pullup = musb_gadget_pullup,
1753 .udc_start = musb_gadget_start,
1754 .udc_stop = musb_gadget_stop,
1757 /* ----------------------------------------------------------------------- */
1761 /* Only this registration code "knows" the rule (from USB standards)
1762 * about there being only one external upstream port. It assumes
1763 * all peripheral ports are external...
1766 static void musb_gadget_release(struct device *dev)
1768 /* kref_put(WHAT) */
1769 dev_dbg(dev, "%s\n", __func__);
1773 static void __devinit
1774 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1776 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1778 memset(ep, 0, sizeof *ep);
1780 ep->current_epnum = epnum;
1785 INIT_LIST_HEAD(&ep->req_list);
1787 sprintf(ep->name, "ep%d%s", epnum,
1788 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1789 is_in ? "in" : "out"));
1790 ep->end_point.name = ep->name;
1791 INIT_LIST_HEAD(&ep->end_point.ep_list);
1793 ep->end_point.maxpacket = 64;
1794 ep->end_point.ops = &musb_g_ep0_ops;
1795 musb->g.ep0 = &ep->end_point;
1798 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1800 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1801 ep->end_point.ops = &musb_ep_ops;
1802 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1807 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1808 * to the rest of the driver state.
1810 static inline void __devinit musb_g_init_endpoints(struct musb *musb)
1813 struct musb_hw_ep *hw_ep;
1816 /* initialize endpoint list just once */
1817 INIT_LIST_HEAD(&(musb->g.ep_list));
1819 for (epnum = 0, hw_ep = musb->endpoints;
1820 epnum < musb->nr_endpoints;
1822 if (hw_ep->is_shared_fifo /* || !epnum */) {
1823 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1826 if (hw_ep->max_packet_sz_tx) {
1827 init_peripheral_ep(musb, &hw_ep->ep_in,
1831 if (hw_ep->max_packet_sz_rx) {
1832 init_peripheral_ep(musb, &hw_ep->ep_out,
1840 /* called once during driver setup to initialize and link into
1841 * the driver model; memory is zeroed.
1843 int __devinit musb_gadget_setup(struct musb *musb)
1847 /* REVISIT minor race: if (erroneously) setting up two
1848 * musb peripherals at the same time, only the bus lock
1852 musb->g.ops = &musb_gadget_operations;
1853 musb->g.max_speed = USB_SPEED_HIGH;
1854 musb->g.speed = USB_SPEED_UNKNOWN;
1856 /* this "gadget" abstracts/virtualizes the controller */
1857 dev_set_name(&musb->g.dev, "gadget");
1858 musb->g.dev.parent = musb->controller;
1859 musb->g.dev.dma_mask = musb->controller->dma_mask;
1860 musb->g.dev.release = musb_gadget_release;
1861 musb->g.name = musb_driver_name;
1865 musb_g_init_endpoints(musb);
1867 musb->is_active = 0;
1868 musb_platform_try_idle(musb, 0);
1870 status = device_register(&musb->g.dev);
1872 put_device(&musb->g.dev);
1875 status = usb_add_gadget_udc(musb->controller, &musb->g);
1881 musb->g.dev.parent = NULL;
1882 device_unregister(&musb->g.dev);
1886 void musb_gadget_cleanup(struct musb *musb)
1888 usb_del_gadget_udc(&musb->g);
1889 if (musb->g.dev.parent)
1890 device_unregister(&musb->g.dev);
1894 * Register the gadget driver. Used by gadget drivers when
1895 * registering themselves with the controller.
1897 * -EINVAL something went wrong (not driver)
1898 * -EBUSY another gadget is already using the controller
1899 * -ENOMEM no memory to perform the operation
1901 * @param driver the gadget driver
1902 * @return <0 if error, 0 if everything is fine
1904 static int musb_gadget_start(struct usb_gadget *g,
1905 struct usb_gadget_driver *driver)
1907 struct musb *musb = gadget_to_musb(g);
1908 struct usb_otg *otg = musb->xceiv->otg;
1909 struct usb_hcd *hcd = musb_to_hcd(musb);
1910 unsigned long flags;
1913 if (driver->max_speed < USB_SPEED_HIGH) {
1918 pm_runtime_get_sync(musb->controller);
1920 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1922 musb->softconnect = 0;
1923 musb->gadget_driver = driver;
1925 spin_lock_irqsave(&musb->lock, flags);
1926 musb->is_active = 1;
1928 otg_set_peripheral(otg, &musb->g);
1929 musb->xceiv->state = OTG_STATE_B_IDLE;
1930 spin_unlock_irqrestore(&musb->lock, flags);
1932 /* REVISIT: funcall to other code, which also
1933 * handles power budgeting ... this way also
1934 * ensures HdrcStart is indirectly called.
1936 retval = usb_add_hcd(hcd, 0, 0);
1938 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1942 if ((musb->xceiv->last_event == USB_EVENT_ID)
1944 otg_set_vbus(otg, 1);
1946 hcd->self.uses_pio_for_control = 1;
1948 if (musb->xceiv->last_event == USB_EVENT_NONE)
1949 pm_runtime_put(musb->controller);
1957 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1960 struct musb_hw_ep *hw_ep;
1962 /* don't disconnect if it's not connected */
1963 if (musb->g.speed == USB_SPEED_UNKNOWN)
1966 musb->g.speed = USB_SPEED_UNKNOWN;
1968 /* deactivate the hardware */
1969 if (musb->softconnect) {
1970 musb->softconnect = 0;
1971 musb_pullup(musb, 0);
1975 /* killing any outstanding requests will quiesce the driver;
1976 * then report disconnect
1979 for (i = 0, hw_ep = musb->endpoints;
1980 i < musb->nr_endpoints;
1982 musb_ep_select(musb->mregs, i);
1983 if (hw_ep->is_shared_fifo /* || !epnum */) {
1984 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1986 if (hw_ep->max_packet_sz_tx)
1987 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1988 if (hw_ep->max_packet_sz_rx)
1989 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1996 * Unregister the gadget driver. Used by gadget drivers when
1997 * unregistering themselves from the controller.
1999 * @param driver the gadget driver to unregister
2001 static int musb_gadget_stop(struct usb_gadget *g,
2002 struct usb_gadget_driver *driver)
2004 struct musb *musb = gadget_to_musb(g);
2005 unsigned long flags;
2007 if (musb->xceiv->last_event == USB_EVENT_NONE)
2008 pm_runtime_get_sync(musb->controller);
2011 * REVISIT always use otg_set_peripheral() here too;
2012 * this needs to shut down the OTG engine.
2015 spin_lock_irqsave(&musb->lock, flags);
2017 musb_hnp_stop(musb);
2019 (void) musb_gadget_vbus_draw(&musb->g, 0);
2021 musb->xceiv->state = OTG_STATE_UNDEFINED;
2022 stop_activity(musb, driver);
2023 otg_set_peripheral(musb->xceiv->otg, NULL);
2025 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2027 musb->is_active = 0;
2028 musb_platform_try_idle(musb, 0);
2029 spin_unlock_irqrestore(&musb->lock, flags);
2031 usb_remove_hcd(musb_to_hcd(musb));
2033 * FIXME we need to be able to register another
2034 * gadget driver here and have everything work;
2035 * that currently misbehaves.
2038 pm_runtime_put(musb->controller);
2043 /* ----------------------------------------------------------------------- */
2045 /* lifecycle operations called through plat_uds.c */
2047 void musb_g_resume(struct musb *musb)
2049 musb->is_suspended = 0;
2050 switch (musb->xceiv->state) {
2051 case OTG_STATE_B_IDLE:
2053 case OTG_STATE_B_WAIT_ACON:
2054 case OTG_STATE_B_PERIPHERAL:
2055 musb->is_active = 1;
2056 if (musb->gadget_driver && musb->gadget_driver->resume) {
2057 spin_unlock(&musb->lock);
2058 musb->gadget_driver->resume(&musb->g);
2059 spin_lock(&musb->lock);
2063 WARNING("unhandled RESUME transition (%s)\n",
2064 otg_state_string(musb->xceiv->state));
2068 /* called when SOF packets stop for 3+ msec */
2069 void musb_g_suspend(struct musb *musb)
2073 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2074 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2076 switch (musb->xceiv->state) {
2077 case OTG_STATE_B_IDLE:
2078 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2079 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2081 case OTG_STATE_B_PERIPHERAL:
2082 musb->is_suspended = 1;
2083 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2084 spin_unlock(&musb->lock);
2085 musb->gadget_driver->suspend(&musb->g);
2086 spin_lock(&musb->lock);
2090 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2091 * A_PERIPHERAL may need care too
2093 WARNING("unhandled SUSPEND transition (%s)\n",
2094 otg_state_string(musb->xceiv->state));
2098 /* Called during SRP */
2099 void musb_g_wakeup(struct musb *musb)
2101 musb_gadget_wakeup(&musb->g);
2104 /* called when VBUS drops below session threshold, and in other cases */
2105 void musb_g_disconnect(struct musb *musb)
2107 void __iomem *mregs = musb->mregs;
2108 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2110 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2113 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2115 /* don't draw vbus until new b-default session */
2116 (void) musb_gadget_vbus_draw(&musb->g, 0);
2118 musb->g.speed = USB_SPEED_UNKNOWN;
2119 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2120 spin_unlock(&musb->lock);
2121 musb->gadget_driver->disconnect(&musb->g);
2122 spin_lock(&musb->lock);
2125 switch (musb->xceiv->state) {
2127 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2128 otg_state_string(musb->xceiv->state));
2129 musb->xceiv->state = OTG_STATE_A_IDLE;
2130 MUSB_HST_MODE(musb);
2132 case OTG_STATE_A_PERIPHERAL:
2133 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2134 MUSB_HST_MODE(musb);
2136 case OTG_STATE_B_WAIT_ACON:
2137 case OTG_STATE_B_HOST:
2138 case OTG_STATE_B_PERIPHERAL:
2139 case OTG_STATE_B_IDLE:
2140 musb->xceiv->state = OTG_STATE_B_IDLE;
2142 case OTG_STATE_B_SRP_INIT:
2146 musb->is_active = 0;
2149 void musb_g_reset(struct musb *musb)
2150 __releases(musb->lock)
2151 __acquires(musb->lock)
2153 void __iomem *mbase = musb->mregs;
2154 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2157 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2158 (devctl & MUSB_DEVCTL_BDEVICE)
2159 ? "B-Device" : "A-Device",
2160 musb_readb(mbase, MUSB_FADDR),
2162 ? musb->gadget_driver->driver.name
2166 /* report disconnect, if we didn't already (flushing EP state) */
2167 if (musb->g.speed != USB_SPEED_UNKNOWN)
2168 musb_g_disconnect(musb);
2171 else if (devctl & MUSB_DEVCTL_HR)
2172 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2175 /* what speed did we negotiate? */
2176 power = musb_readb(mbase, MUSB_POWER);
2177 musb->g.speed = (power & MUSB_POWER_HSMODE)
2178 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2180 /* start in USB_STATE_DEFAULT */
2181 musb->is_active = 1;
2182 musb->is_suspended = 0;
2183 MUSB_DEV_MODE(musb);
2185 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2187 musb->may_wakeup = 0;
2188 musb->g.b_hnp_enable = 0;
2189 musb->g.a_alt_hnp_support = 0;
2190 musb->g.a_hnp_support = 0;
2192 /* Normal reset, as B-Device;
2193 * or else after HNP, as A-Device
2195 if (devctl & MUSB_DEVCTL_BDEVICE) {
2196 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2197 musb->g.is_a_peripheral = 0;
2199 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2200 musb->g.is_a_peripheral = 1;
2203 /* start with default limits on VBUS power draw */
2204 (void) musb_gadget_vbus_draw(&musb->g, 8);