2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
95 /* Maps the buffer to dma */
97 static inline void map_dma_buffer(struct musb_request *request,
100 if (request->request.dma == DMA_ADDR_INVALID) {
101 request->request.dma = dma_map_single(
103 request->request.buf,
104 request->request.length,
110 dma_sync_single_for_device(musb->controller,
111 request->request.dma,
112 request->request.length,
120 /* Unmap the buffer from dma and maps it back to cpu */
121 static inline void unmap_dma_buffer(struct musb_request *request,
124 if (request->request.dma == DMA_ADDR_INVALID) {
125 DBG(20, "not unmapping a never mapped buffer\n");
128 if (request->mapped) {
129 dma_unmap_single(musb->controller,
130 request->request.dma,
131 request->request.length,
135 request->request.dma = DMA_ADDR_INVALID;
138 dma_sync_single_for_cpu(musb->controller,
139 request->request.dma,
140 request->request.length,
149 * Immediately complete a request.
151 * @param request the request to complete
152 * @param status the status to complete the request with
153 * Context: controller locked, IRQs blocked.
155 void musb_g_giveback(
157 struct usb_request *request,
159 __releases(ep->musb->lock)
160 __acquires(ep->musb->lock)
162 struct musb_request *req;
166 req = to_musb_request(request);
168 list_del(&request->list);
169 if (req->request.status == -EINPROGRESS)
170 req->request.status = status;
174 spin_unlock(&musb->lock);
175 if (is_dma_capable() && ep->dma)
176 unmap_dma_buffer(req, musb);
177 if (request->status == 0)
178 DBG(5, "%s done request %p, %d/%d\n",
179 ep->end_point.name, request,
180 req->request.actual, req->request.length);
182 DBG(2, "%s request %p, %d/%d fault %d\n",
183 ep->end_point.name, request,
184 req->request.actual, req->request.length,
186 req->request.complete(&req->ep->end_point, &req->request);
187 spin_lock(&musb->lock);
191 /* ----------------------------------------------------------------------- */
194 * Abort requests queued to an endpoint using the status. Synchronous.
195 * caller locked controller and blocked irqs, and selected this ep.
197 static void nuke(struct musb_ep *ep, const int status)
199 struct musb_request *req = NULL;
200 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
204 if (is_dma_capable() && ep->dma) {
205 struct dma_controller *c = ep->musb->dma_controller;
210 * The programming guide says that we must not clear
211 * the DMAMODE bit before DMAENAB, so we only
212 * clear it in the second write...
214 musb_writew(epio, MUSB_TXCSR,
215 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
216 musb_writew(epio, MUSB_TXCSR,
217 0 | MUSB_TXCSR_FLUSHFIFO);
219 musb_writew(epio, MUSB_RXCSR,
220 0 | MUSB_RXCSR_FLUSHFIFO);
221 musb_writew(epio, MUSB_RXCSR,
222 0 | MUSB_RXCSR_FLUSHFIFO);
225 value = c->channel_abort(ep->dma);
226 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
227 c->channel_release(ep->dma);
231 while (!list_empty(&(ep->req_list))) {
232 req = container_of(ep->req_list.next, struct musb_request,
234 musb_g_giveback(ep, &req->request, status);
238 /* ----------------------------------------------------------------------- */
240 /* Data transfers - pure PIO, pure DMA, or mixed mode */
243 * This assumes the separate CPPI engine is responding to DMA requests
244 * from the usb core ... sequenced a bit differently from mentor dma.
247 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
249 if (can_bulk_split(musb, ep->type))
250 return ep->hw_ep->max_packet_sz_tx;
252 return ep->packet_sz;
256 #ifdef CONFIG_USB_INVENTRA_DMA
258 /* Peripheral tx (IN) using Mentor DMA works as follows:
259 Only mode 0 is used for transfers <= wPktSize,
260 mode 1 is used for larger transfers,
262 One of the following happens:
263 - Host sends IN token which causes an endpoint interrupt
265 -> if DMA is currently busy, exit.
266 -> if queue is non-empty, txstate().
268 - Request is queued by the gadget driver.
269 -> if queue was previously empty, txstate()
274 | (data is transferred to the FIFO, then sent out when
275 | IN token(s) are recd from Host.
276 | -> DMA interrupt on completion
278 | -> stop DMA, ~DMAENAB,
279 | -> set TxPktRdy for last short pkt or zlp
280 | -> Complete Request
281 | -> Continue next request (call txstate)
282 |___________________________________|
284 * Non-Mentor DMA engines can of course work differently, such as by
285 * upleveling from irq-per-packet to irq-per-buffer.
291 * An endpoint is transmitting data. This can be called either from
292 * the IRQ routine or from ep.queue() to kickstart a request on an
295 * Context: controller locked, IRQs blocked, endpoint selected
297 static void txstate(struct musb *musb, struct musb_request *req)
299 u8 epnum = req->epnum;
300 struct musb_ep *musb_ep;
301 void __iomem *epio = musb->endpoints[epnum].regs;
302 struct usb_request *request;
303 u16 fifo_count = 0, csr;
308 /* we shouldn't get here while DMA is active ... but we do ... */
309 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
310 DBG(4, "dma pending...\n");
314 /* read TXCSR before */
315 csr = musb_readw(epio, MUSB_TXCSR);
317 request = &req->request;
318 fifo_count = min(max_ep_writesize(musb, musb_ep),
319 (int)(request->length - request->actual));
321 if (csr & MUSB_TXCSR_TXPKTRDY) {
322 DBG(5, "%s old packet still ready , txcsr %03x\n",
323 musb_ep->end_point.name, csr);
327 if (csr & MUSB_TXCSR_P_SENDSTALL) {
328 DBG(5, "%s stalling, txcsr %03x\n",
329 musb_ep->end_point.name, csr);
333 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
334 epnum, musb_ep->packet_sz, fifo_count,
337 #ifndef CONFIG_MUSB_PIO_ONLY
338 if (is_dma_capable() && musb_ep->dma) {
339 struct dma_controller *c = musb->dma_controller;
342 /* setup DMA, then program endpoint CSR */
343 request_size = min_t(size_t, request->length - request->actual,
344 musb_ep->dma->max_len);
346 use_dma = (request->dma != DMA_ADDR_INVALID);
348 /* MUSB_TXCSR_P_ISO is still set correctly */
350 #ifdef CONFIG_USB_INVENTRA_DMA
352 if (request_size < musb_ep->packet_sz)
353 musb_ep->dma->desired_mode = 0;
355 musb_ep->dma->desired_mode = 1;
357 use_dma = use_dma && c->channel_program(
358 musb_ep->dma, musb_ep->packet_sz,
359 musb_ep->dma->desired_mode,
360 request->dma + request->actual, request_size);
362 if (musb_ep->dma->desired_mode == 0) {
364 * We must not clear the DMAMODE bit
365 * before the DMAENAB bit -- and the
366 * latter doesn't always get cleared
367 * before we get here...
369 csr &= ~(MUSB_TXCSR_AUTOSET
370 | MUSB_TXCSR_DMAENAB);
371 musb_writew(epio, MUSB_TXCSR, csr
372 | MUSB_TXCSR_P_WZC_BITS);
373 csr &= ~MUSB_TXCSR_DMAMODE;
374 csr |= (MUSB_TXCSR_DMAENAB |
376 /* against programming guide */
378 csr |= (MUSB_TXCSR_DMAENAB
381 if (!musb_ep->hb_mult)
382 csr |= MUSB_TXCSR_AUTOSET;
384 csr &= ~MUSB_TXCSR_P_UNDERRUN;
386 musb_writew(epio, MUSB_TXCSR, csr);
390 #elif defined(CONFIG_USB_TI_CPPI_DMA)
391 /* program endpoint CSR first, then setup DMA */
392 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
393 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
395 musb_writew(epio, MUSB_TXCSR,
396 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
399 /* ensure writebuffer is empty */
400 csr = musb_readw(epio, MUSB_TXCSR);
402 /* NOTE host side sets DMAENAB later than this; both are
403 * OK since the transfer dma glue (between CPPI and Mentor
404 * fifos) just tells CPPI it could start. Data only moves
405 * to the USB TX fifo when both fifos are ready.
408 /* "mode" is irrelevant here; handle terminating ZLPs like
409 * PIO does, since the hardware RNDIS mode seems unreliable
410 * except for the last-packet-is-already-short case.
412 use_dma = use_dma && c->channel_program(
413 musb_ep->dma, musb_ep->packet_sz,
415 request->dma + request->actual,
418 c->channel_release(musb_ep->dma);
420 csr &= ~MUSB_TXCSR_DMAENAB;
421 musb_writew(epio, MUSB_TXCSR, csr);
422 /* invariant: prequest->buf is non-null */
424 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
425 use_dma = use_dma && c->channel_program(
426 musb_ep->dma, musb_ep->packet_sz,
428 request->dma + request->actual,
436 * Unmap the dma buffer back to cpu if dma channel
439 if (is_dma_capable() && musb_ep->dma)
440 unmap_dma_buffer(req, musb);
442 musb_write_fifo(musb_ep->hw_ep, fifo_count,
443 (u8 *) (request->buf + request->actual));
444 request->actual += fifo_count;
445 csr |= MUSB_TXCSR_TXPKTRDY;
446 csr &= ~MUSB_TXCSR_P_UNDERRUN;
447 musb_writew(epio, MUSB_TXCSR, csr);
450 /* host may already have the data when this message shows... */
451 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
452 musb_ep->end_point.name, use_dma ? "dma" : "pio",
453 request->actual, request->length,
454 musb_readw(epio, MUSB_TXCSR),
456 musb_readw(epio, MUSB_TXMAXP));
460 * FIFO state update (e.g. data ready).
461 * Called from IRQ, with controller locked.
463 void musb_g_tx(struct musb *musb, u8 epnum)
466 struct usb_request *request;
467 u8 __iomem *mbase = musb->mregs;
468 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
469 void __iomem *epio = musb->endpoints[epnum].regs;
470 struct dma_channel *dma;
472 musb_ep_select(mbase, epnum);
473 request = next_request(musb_ep);
475 csr = musb_readw(epio, MUSB_TXCSR);
476 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
478 dma = is_dma_capable() ? musb_ep->dma : NULL;
481 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
482 * probably rates reporting as a host error.
484 if (csr & MUSB_TXCSR_P_SENTSTALL) {
485 csr |= MUSB_TXCSR_P_WZC_BITS;
486 csr &= ~MUSB_TXCSR_P_SENTSTALL;
487 musb_writew(epio, MUSB_TXCSR, csr);
491 if (csr & MUSB_TXCSR_P_UNDERRUN) {
492 /* We NAKed, no big deal... little reason to care. */
493 csr |= MUSB_TXCSR_P_WZC_BITS;
494 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
495 musb_writew(epio, MUSB_TXCSR, csr);
496 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
499 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
501 * SHOULD NOT HAPPEN... has with CPPI though, after
502 * changing SENDSTALL (and other cases); harmless?
504 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
511 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
513 csr |= MUSB_TXCSR_P_WZC_BITS;
514 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
515 MUSB_TXCSR_TXPKTRDY);
516 musb_writew(epio, MUSB_TXCSR, csr);
517 /* Ensure writebuffer is empty. */
518 csr = musb_readw(epio, MUSB_TXCSR);
519 request->actual += musb_ep->dma->actual_len;
520 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
521 epnum, csr, musb_ep->dma->actual_len, request);
525 * First, maybe a terminating short packet. Some DMA
526 * engines might handle this by themselves.
528 if ((request->zero && request->length
529 && (request->length % musb_ep->packet_sz == 0)
530 && (request->actual == request->length))
531 #ifdef CONFIG_USB_INVENTRA_DMA
532 || (is_dma && (!dma->desired_mode ||
534 (musb_ep->packet_sz - 1))))
538 * On DMA completion, FIFO may not be
541 if (csr & MUSB_TXCSR_TXPKTRDY)
544 DBG(4, "sending zero pkt\n");
545 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
546 | MUSB_TXCSR_TXPKTRDY);
550 if (request->actual == request->length) {
551 musb_g_giveback(musb_ep, request, 0);
552 request = musb_ep->desc ? next_request(musb_ep) : NULL;
554 DBG(4, "%s idle now\n",
555 musb_ep->end_point.name);
560 txstate(musb, to_musb_request(request));
564 /* ------------------------------------------------------------ */
566 #ifdef CONFIG_USB_INVENTRA_DMA
568 /* Peripheral rx (OUT) using Mentor DMA works as follows:
569 - Only mode 0 is used.
571 - Request is queued by the gadget class driver.
572 -> if queue was previously empty, rxstate()
574 - Host sends OUT token which causes an endpoint interrupt
576 | -> if request queued, call rxstate
578 | | -> DMA interrupt on completion
582 | | -> if data recd = max expected
583 | | by the request, or host
584 | | sent a short packet,
585 | | complete the request,
586 | | and start the next one.
587 | |_____________________________________|
588 | else just wait for the host
589 | to send the next OUT token.
590 |__________________________________________________|
592 * Non-Mentor DMA engines can of course work differently.
598 * Context: controller locked, IRQs blocked, endpoint selected
600 static void rxstate(struct musb *musb, struct musb_request *req)
602 const u8 epnum = req->epnum;
603 struct usb_request *request = &req->request;
604 struct musb_ep *musb_ep;
605 void __iomem *epio = musb->endpoints[epnum].regs;
606 unsigned fifo_count = 0;
608 u16 csr = musb_readw(epio, MUSB_RXCSR);
609 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
611 if (hw_ep->is_shared_fifo)
612 musb_ep = &hw_ep->ep_in;
614 musb_ep = &hw_ep->ep_out;
616 len = musb_ep->packet_sz;
618 /* We shouldn't get here while DMA is active, but we do... */
619 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
620 DBG(4, "DMA pending...\n");
624 if (csr & MUSB_RXCSR_P_SENDSTALL) {
625 DBG(5, "%s stalling, RXCSR %04x\n",
626 musb_ep->end_point.name, csr);
630 if (is_cppi_enabled() && musb_ep->dma) {
631 struct dma_controller *c = musb->dma_controller;
632 struct dma_channel *channel = musb_ep->dma;
634 /* NOTE: CPPI won't actually stop advancing the DMA
635 * queue after short packet transfers, so this is almost
636 * always going to run as IRQ-per-packet DMA so that
637 * faults will be handled correctly.
639 if (c->channel_program(channel,
641 !request->short_not_ok,
642 request->dma + request->actual,
643 request->length - request->actual)) {
645 /* make sure that if an rxpkt arrived after the irq,
646 * the cppi engine will be ready to take it as soon
649 csr &= ~(MUSB_RXCSR_AUTOCLEAR
650 | MUSB_RXCSR_DMAMODE);
651 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
652 musb_writew(epio, MUSB_RXCSR, csr);
657 if (csr & MUSB_RXCSR_RXPKTRDY) {
658 len = musb_readw(epio, MUSB_RXCOUNT);
659 if (request->actual < request->length) {
660 #ifdef CONFIG_USB_INVENTRA_DMA
661 if (is_dma_capable() && musb_ep->dma) {
662 struct dma_controller *c;
663 struct dma_channel *channel;
666 c = musb->dma_controller;
667 channel = musb_ep->dma;
669 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
670 * mode 0 only. So we do not get endpoint interrupts due to DMA
671 * completion. We only get interrupts from DMA controller.
673 * We could operate in DMA mode 1 if we knew the size of the tranfer
674 * in advance. For mass storage class, request->length = what the host
675 * sends, so that'd work. But for pretty much everything else,
676 * request->length is routinely more than what the host sends. For
677 * most these gadgets, end of is signified either by a short packet,
678 * or filling the last byte of the buffer. (Sending extra data in
679 * that last pckate should trigger an overflow fault.) But in mode 1,
680 * we don't get DMA completion interrrupt for short packets.
682 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
683 * to get endpoint interrupt on every DMA req, but that didn't seem
686 * REVISIT an updated g_file_storage can set req->short_not_ok, which
687 * then becomes usable as a runtime "use mode 1" hint...
690 csr |= MUSB_RXCSR_DMAENAB;
692 csr |= MUSB_RXCSR_AUTOCLEAR;
693 /* csr |= MUSB_RXCSR_DMAMODE; */
695 /* this special sequence (enabling and then
696 * disabling MUSB_RXCSR_DMAMODE) is required
697 * to get DMAReq to activate
699 musb_writew(epio, MUSB_RXCSR,
700 csr | MUSB_RXCSR_DMAMODE);
702 if (!musb_ep->hb_mult &&
703 musb_ep->hw_ep->rx_double_buffered)
704 csr |= MUSB_RXCSR_AUTOCLEAR;
706 musb_writew(epio, MUSB_RXCSR, csr);
708 if (request->actual < request->length) {
709 int transfer_size = 0;
711 transfer_size = min(request->length - request->actual,
714 transfer_size = min(request->length - request->actual,
717 if (transfer_size <= musb_ep->packet_sz)
718 musb_ep->dma->desired_mode = 0;
720 musb_ep->dma->desired_mode = 1;
722 use_dma = c->channel_program(
725 channel->desired_mode,
734 #endif /* Mentor's DMA */
736 fifo_count = request->length - request->actual;
737 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
738 musb_ep->end_point.name,
742 fifo_count = min_t(unsigned, len, fifo_count);
744 #ifdef CONFIG_USB_TUSB_OMAP_DMA
745 if (tusb_dma_omap() && musb_ep->dma) {
746 struct dma_controller *c = musb->dma_controller;
747 struct dma_channel *channel = musb_ep->dma;
748 u32 dma_addr = request->dma + request->actual;
751 ret = c->channel_program(channel,
753 channel->desired_mode,
761 * Unmap the dma buffer back to cpu if dma channel
762 * programming fails. This buffer is mapped if the
763 * channel allocation is successful
765 if (is_dma_capable() && musb_ep->dma) {
766 unmap_dma_buffer(req, musb);
769 * Clear DMAENAB and AUTOCLEAR for the
772 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
773 musb_writew(epio, MUSB_RXCSR, csr);
776 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
777 (request->buf + request->actual));
778 request->actual += fifo_count;
780 /* REVISIT if we left anything in the fifo, flush
781 * it and report -EOVERFLOW
785 csr |= MUSB_RXCSR_P_WZC_BITS;
786 csr &= ~MUSB_RXCSR_RXPKTRDY;
787 musb_writew(epio, MUSB_RXCSR, csr);
791 /* reach the end or short packet detected */
792 if (request->actual == request->length || len < musb_ep->packet_sz)
793 musb_g_giveback(musb_ep, request, 0);
797 * Data ready for a request; called from IRQ
799 void musb_g_rx(struct musb *musb, u8 epnum)
802 struct usb_request *request;
803 void __iomem *mbase = musb->mregs;
804 struct musb_ep *musb_ep;
805 void __iomem *epio = musb->endpoints[epnum].regs;
806 struct dma_channel *dma;
807 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
809 if (hw_ep->is_shared_fifo)
810 musb_ep = &hw_ep->ep_in;
812 musb_ep = &hw_ep->ep_out;
814 musb_ep_select(mbase, epnum);
816 request = next_request(musb_ep);
820 csr = musb_readw(epio, MUSB_RXCSR);
821 dma = is_dma_capable() ? musb_ep->dma : NULL;
823 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
824 csr, dma ? " (dma)" : "", request);
826 if (csr & MUSB_RXCSR_P_SENTSTALL) {
827 csr |= MUSB_RXCSR_P_WZC_BITS;
828 csr &= ~MUSB_RXCSR_P_SENTSTALL;
829 musb_writew(epio, MUSB_RXCSR, csr);
833 if (csr & MUSB_RXCSR_P_OVERRUN) {
834 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
835 csr &= ~MUSB_RXCSR_P_OVERRUN;
836 musb_writew(epio, MUSB_RXCSR, csr);
838 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
839 if (request->status == -EINPROGRESS)
840 request->status = -EOVERFLOW;
842 if (csr & MUSB_RXCSR_INCOMPRX) {
843 /* REVISIT not necessarily an error */
844 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
847 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
848 /* "should not happen"; likely RXPKTRDY pending for DMA */
849 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
850 "%s busy, csr %04x\n",
851 musb_ep->end_point.name, csr);
855 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
856 csr &= ~(MUSB_RXCSR_AUTOCLEAR
858 | MUSB_RXCSR_DMAMODE);
859 musb_writew(epio, MUSB_RXCSR,
860 MUSB_RXCSR_P_WZC_BITS | csr);
862 request->actual += musb_ep->dma->actual_len;
864 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
866 musb_readw(epio, MUSB_RXCSR),
867 musb_ep->dma->actual_len, request);
869 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
870 /* Autoclear doesn't clear RxPktRdy for short packets */
871 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
873 & (musb_ep->packet_sz - 1))) {
875 csr &= ~MUSB_RXCSR_RXPKTRDY;
876 musb_writew(epio, MUSB_RXCSR, csr);
879 /* incomplete, and not short? wait for next IN packet */
880 if ((request->actual < request->length)
881 && (musb_ep->dma->actual_len
882 == musb_ep->packet_sz)) {
883 /* In double buffer case, continue to unload fifo if
884 * there is Rx packet in FIFO.
886 csr = musb_readw(epio, MUSB_RXCSR);
887 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
888 hw_ep->rx_double_buffered)
893 musb_g_giveback(musb_ep, request, 0);
895 request = next_request(musb_ep);
899 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
902 /* Analyze request */
903 rxstate(musb, to_musb_request(request));
906 /* ------------------------------------------------------------ */
908 static int musb_gadget_enable(struct usb_ep *ep,
909 const struct usb_endpoint_descriptor *desc)
912 struct musb_ep *musb_ep;
913 struct musb_hw_ep *hw_ep;
920 int status = -EINVAL;
925 musb_ep = to_musb_ep(ep);
926 hw_ep = musb_ep->hw_ep;
928 musb = musb_ep->musb;
930 epnum = musb_ep->current_epnum;
932 spin_lock_irqsave(&musb->lock, flags);
938 musb_ep->type = usb_endpoint_type(desc);
940 /* check direction and (later) maxpacket size against endpoint */
941 if (usb_endpoint_num(desc) != epnum)
944 /* REVISIT this rules out high bandwidth periodic transfers */
945 tmp = le16_to_cpu(desc->wMaxPacketSize);
949 if (usb_endpoint_dir_in(desc))
950 ok = musb->hb_iso_tx;
952 ok = musb->hb_iso_rx;
955 DBG(4, "%s: not support ISO high bandwidth\n", __func__);
958 musb_ep->hb_mult = (tmp >> 11) & 3;
960 musb_ep->hb_mult = 0;
963 musb_ep->packet_sz = tmp & 0x7ff;
964 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
966 /* enable the interrupts for the endpoint, set the endpoint
967 * packet size (or fail), set the mode, clear the fifo
969 musb_ep_select(mbase, epnum);
970 if (usb_endpoint_dir_in(desc)) {
971 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
973 if (hw_ep->is_shared_fifo)
978 if (tmp > hw_ep->max_packet_sz_tx) {
979 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
983 int_txe |= (1 << epnum);
984 musb_writew(mbase, MUSB_INTRTXE, int_txe);
986 /* REVISIT if can_bulk_split(), use by updating "tmp";
987 * likewise high bandwidth periodic tx
989 /* Set TXMAXP with the FIFO size of the endpoint
990 * to disable double buffering mode.
992 if (musb->double_buffer_not_ok)
993 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
995 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
996 | (musb_ep->hb_mult << 11));
998 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
999 if (musb_readw(regs, MUSB_TXCSR)
1000 & MUSB_TXCSR_FIFONOTEMPTY)
1001 csr |= MUSB_TXCSR_FLUSHFIFO;
1002 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1003 csr |= MUSB_TXCSR_P_ISO;
1005 /* set twice in case of double buffering */
1006 musb_writew(regs, MUSB_TXCSR, csr);
1007 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1008 musb_writew(regs, MUSB_TXCSR, csr);
1011 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1013 if (hw_ep->is_shared_fifo)
1018 if (tmp > hw_ep->max_packet_sz_rx) {
1019 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
1023 int_rxe |= (1 << epnum);
1024 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1026 /* REVISIT if can_bulk_combine() use by updating "tmp"
1027 * likewise high bandwidth periodic rx
1029 /* Set RXMAXP with the FIFO size of the endpoint
1030 * to disable double buffering mode.
1032 if (musb->double_buffer_not_ok)
1033 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1035 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1036 | (musb_ep->hb_mult << 11));
1038 /* force shared fifo to OUT-only mode */
1039 if (hw_ep->is_shared_fifo) {
1040 csr = musb_readw(regs, MUSB_TXCSR);
1041 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1042 musb_writew(regs, MUSB_TXCSR, csr);
1045 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1046 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1047 csr |= MUSB_RXCSR_P_ISO;
1048 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1049 csr |= MUSB_RXCSR_DISNYET;
1051 /* set twice in case of double buffering */
1052 musb_writew(regs, MUSB_RXCSR, csr);
1053 musb_writew(regs, MUSB_RXCSR, csr);
1056 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1057 * for some reason you run out of channels here.
1059 if (is_dma_capable() && musb->dma_controller) {
1060 struct dma_controller *c = musb->dma_controller;
1062 musb_ep->dma = c->channel_alloc(c, hw_ep,
1063 (desc->bEndpointAddress & USB_DIR_IN));
1065 musb_ep->dma = NULL;
1067 musb_ep->desc = desc;
1069 musb_ep->wedged = 0;
1072 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1073 musb_driver_name, musb_ep->end_point.name,
1074 ({ char *s; switch (musb_ep->type) {
1075 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1076 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1077 default: s = "iso"; break;
1079 musb_ep->is_in ? "IN" : "OUT",
1080 musb_ep->dma ? "dma, " : "",
1081 musb_ep->packet_sz);
1083 schedule_work(&musb->irq_work);
1086 spin_unlock_irqrestore(&musb->lock, flags);
1091 * Disable an endpoint flushing all requests queued.
1093 static int musb_gadget_disable(struct usb_ep *ep)
1095 unsigned long flags;
1098 struct musb_ep *musb_ep;
1102 musb_ep = to_musb_ep(ep);
1103 musb = musb_ep->musb;
1104 epnum = musb_ep->current_epnum;
1105 epio = musb->endpoints[epnum].regs;
1107 spin_lock_irqsave(&musb->lock, flags);
1108 musb_ep_select(musb->mregs, epnum);
1110 /* zero the endpoint sizes */
1111 if (musb_ep->is_in) {
1112 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1113 int_txe &= ~(1 << epnum);
1114 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1115 musb_writew(epio, MUSB_TXMAXP, 0);
1117 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1118 int_rxe &= ~(1 << epnum);
1119 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1120 musb_writew(epio, MUSB_RXMAXP, 0);
1123 musb_ep->desc = NULL;
1125 /* abort all pending DMA and requests */
1126 nuke(musb_ep, -ESHUTDOWN);
1128 schedule_work(&musb->irq_work);
1130 spin_unlock_irqrestore(&(musb->lock), flags);
1132 DBG(2, "%s\n", musb_ep->end_point.name);
1138 * Allocate a request for an endpoint.
1139 * Reused by ep0 code.
1141 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1143 struct musb_ep *musb_ep = to_musb_ep(ep);
1144 struct musb_request *request = NULL;
1146 request = kzalloc(sizeof *request, gfp_flags);
1148 DBG(4, "not enough memory\n");
1152 INIT_LIST_HEAD(&request->request.list);
1153 request->request.dma = DMA_ADDR_INVALID;
1154 request->epnum = musb_ep->current_epnum;
1155 request->ep = musb_ep;
1157 return &request->request;
1162 * Reused by ep0 code.
1164 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1166 kfree(to_musb_request(req));
1169 static LIST_HEAD(buffers);
1171 struct free_record {
1172 struct list_head list;
1179 * Context: controller locked, IRQs blocked.
1181 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1183 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1184 req->tx ? "TX/IN" : "RX/OUT",
1185 &req->request, req->request.length, req->epnum);
1187 musb_ep_select(musb->mregs, req->epnum);
1194 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1197 struct musb_ep *musb_ep;
1198 struct musb_request *request;
1201 unsigned long lockflags;
1208 musb_ep = to_musb_ep(ep);
1209 musb = musb_ep->musb;
1211 request = to_musb_request(req);
1212 request->musb = musb;
1214 if (request->ep != musb_ep)
1217 DBG(4, "<== to %s request=%p\n", ep->name, req);
1219 /* request is mine now... */
1220 request->request.actual = 0;
1221 request->request.status = -EINPROGRESS;
1222 request->epnum = musb_ep->current_epnum;
1223 request->tx = musb_ep->is_in;
1225 if (is_dma_capable() && musb_ep->dma)
1226 map_dma_buffer(request, musb);
1228 request->mapped = 0;
1230 spin_lock_irqsave(&musb->lock, lockflags);
1232 /* don't queue if the ep is down */
1233 if (!musb_ep->desc) {
1234 DBG(4, "req %p queued to %s while ep %s\n",
1235 req, ep->name, "disabled");
1236 status = -ESHUTDOWN;
1240 /* add request to the list */
1241 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1243 /* it this is the head of the queue, start i/o ... */
1244 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1245 musb_ep_restart(musb, request);
1248 spin_unlock_irqrestore(&musb->lock, lockflags);
1252 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1254 struct musb_ep *musb_ep = to_musb_ep(ep);
1255 struct usb_request *r;
1256 unsigned long flags;
1258 struct musb *musb = musb_ep->musb;
1260 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1263 spin_lock_irqsave(&musb->lock, flags);
1265 list_for_each_entry(r, &musb_ep->req_list, list) {
1270 DBG(3, "request %p not queued to %s\n", request, ep->name);
1275 /* if the hardware doesn't have the request, easy ... */
1276 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1277 musb_g_giveback(musb_ep, request, -ECONNRESET);
1279 /* ... else abort the dma transfer ... */
1280 else if (is_dma_capable() && musb_ep->dma) {
1281 struct dma_controller *c = musb->dma_controller;
1283 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1284 if (c->channel_abort)
1285 status = c->channel_abort(musb_ep->dma);
1289 musb_g_giveback(musb_ep, request, -ECONNRESET);
1291 /* NOTE: by sticking to easily tested hardware/driver states,
1292 * we leave counting of in-flight packets imprecise.
1294 musb_g_giveback(musb_ep, request, -ECONNRESET);
1298 spin_unlock_irqrestore(&musb->lock, flags);
1303 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1304 * data but will queue requests.
1306 * exported to ep0 code
1308 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1310 struct musb_ep *musb_ep = to_musb_ep(ep);
1311 u8 epnum = musb_ep->current_epnum;
1312 struct musb *musb = musb_ep->musb;
1313 void __iomem *epio = musb->endpoints[epnum].regs;
1314 void __iomem *mbase;
1315 unsigned long flags;
1317 struct musb_request *request;
1322 mbase = musb->mregs;
1324 spin_lock_irqsave(&musb->lock, flags);
1326 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1331 musb_ep_select(mbase, epnum);
1333 request = to_musb_request(next_request(musb_ep));
1336 DBG(3, "request in progress, cannot halt %s\n",
1341 /* Cannot portably stall with non-empty FIFO */
1342 if (musb_ep->is_in) {
1343 csr = musb_readw(epio, MUSB_TXCSR);
1344 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1345 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1351 musb_ep->wedged = 0;
1353 /* set/clear the stall and toggle bits */
1354 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1355 if (musb_ep->is_in) {
1356 csr = musb_readw(epio, MUSB_TXCSR);
1357 csr |= MUSB_TXCSR_P_WZC_BITS
1358 | MUSB_TXCSR_CLRDATATOG;
1360 csr |= MUSB_TXCSR_P_SENDSTALL;
1362 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1363 | MUSB_TXCSR_P_SENTSTALL);
1364 csr &= ~MUSB_TXCSR_TXPKTRDY;
1365 musb_writew(epio, MUSB_TXCSR, csr);
1367 csr = musb_readw(epio, MUSB_RXCSR);
1368 csr |= MUSB_RXCSR_P_WZC_BITS
1369 | MUSB_RXCSR_FLUSHFIFO
1370 | MUSB_RXCSR_CLRDATATOG;
1372 csr |= MUSB_RXCSR_P_SENDSTALL;
1374 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1375 | MUSB_RXCSR_P_SENTSTALL);
1376 musb_writew(epio, MUSB_RXCSR, csr);
1379 /* maybe start the first request in the queue */
1380 if (!musb_ep->busy && !value && request) {
1381 DBG(3, "restarting the request\n");
1382 musb_ep_restart(musb, request);
1386 spin_unlock_irqrestore(&musb->lock, flags);
1391 * Sets the halt feature with the clear requests ignored
1393 static int musb_gadget_set_wedge(struct usb_ep *ep)
1395 struct musb_ep *musb_ep = to_musb_ep(ep);
1400 musb_ep->wedged = 1;
1402 return usb_ep_set_halt(ep);
1405 static int musb_gadget_fifo_status(struct usb_ep *ep)
1407 struct musb_ep *musb_ep = to_musb_ep(ep);
1408 void __iomem *epio = musb_ep->hw_ep->regs;
1409 int retval = -EINVAL;
1411 if (musb_ep->desc && !musb_ep->is_in) {
1412 struct musb *musb = musb_ep->musb;
1413 int epnum = musb_ep->current_epnum;
1414 void __iomem *mbase = musb->mregs;
1415 unsigned long flags;
1417 spin_lock_irqsave(&musb->lock, flags);
1419 musb_ep_select(mbase, epnum);
1420 /* FIXME return zero unless RXPKTRDY is set */
1421 retval = musb_readw(epio, MUSB_RXCOUNT);
1423 spin_unlock_irqrestore(&musb->lock, flags);
1428 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1430 struct musb_ep *musb_ep = to_musb_ep(ep);
1431 struct musb *musb = musb_ep->musb;
1432 u8 epnum = musb_ep->current_epnum;
1433 void __iomem *epio = musb->endpoints[epnum].regs;
1434 void __iomem *mbase;
1435 unsigned long flags;
1438 mbase = musb->mregs;
1440 spin_lock_irqsave(&musb->lock, flags);
1441 musb_ep_select(mbase, (u8) epnum);
1443 /* disable interrupts */
1444 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1445 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1447 if (musb_ep->is_in) {
1448 csr = musb_readw(epio, MUSB_TXCSR);
1449 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1450 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1451 musb_writew(epio, MUSB_TXCSR, csr);
1452 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1453 musb_writew(epio, MUSB_TXCSR, csr);
1456 csr = musb_readw(epio, MUSB_RXCSR);
1457 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1458 musb_writew(epio, MUSB_RXCSR, csr);
1459 musb_writew(epio, MUSB_RXCSR, csr);
1462 /* re-enable interrupt */
1463 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1464 spin_unlock_irqrestore(&musb->lock, flags);
1467 static const struct usb_ep_ops musb_ep_ops = {
1468 .enable = musb_gadget_enable,
1469 .disable = musb_gadget_disable,
1470 .alloc_request = musb_alloc_request,
1471 .free_request = musb_free_request,
1472 .queue = musb_gadget_queue,
1473 .dequeue = musb_gadget_dequeue,
1474 .set_halt = musb_gadget_set_halt,
1475 .set_wedge = musb_gadget_set_wedge,
1476 .fifo_status = musb_gadget_fifo_status,
1477 .fifo_flush = musb_gadget_fifo_flush
1480 /* ----------------------------------------------------------------------- */
1482 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1484 struct musb *musb = gadget_to_musb(gadget);
1486 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1489 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1491 struct musb *musb = gadget_to_musb(gadget);
1492 void __iomem *mregs = musb->mregs;
1493 unsigned long flags;
1494 int status = -EINVAL;
1498 spin_lock_irqsave(&musb->lock, flags);
1500 switch (musb->xceiv->state) {
1501 case OTG_STATE_B_PERIPHERAL:
1502 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1503 * that's part of the standard usb 1.1 state machine, and
1504 * doesn't affect OTG transitions.
1506 if (musb->may_wakeup && musb->is_suspended)
1509 case OTG_STATE_B_IDLE:
1510 /* Start SRP ... OTG not required. */
1511 devctl = musb_readb(mregs, MUSB_DEVCTL);
1512 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1513 devctl |= MUSB_DEVCTL_SESSION;
1514 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1515 devctl = musb_readb(mregs, MUSB_DEVCTL);
1517 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1518 devctl = musb_readb(mregs, MUSB_DEVCTL);
1523 while (devctl & MUSB_DEVCTL_SESSION) {
1524 devctl = musb_readb(mregs, MUSB_DEVCTL);
1529 /* Block idling for at least 1s */
1530 musb_platform_try_idle(musb,
1531 jiffies + msecs_to_jiffies(1 * HZ));
1536 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1542 power = musb_readb(mregs, MUSB_POWER);
1543 power |= MUSB_POWER_RESUME;
1544 musb_writeb(mregs, MUSB_POWER, power);
1545 DBG(2, "issue wakeup\n");
1547 /* FIXME do this next chunk in a timer callback, no udelay */
1550 power = musb_readb(mregs, MUSB_POWER);
1551 power &= ~MUSB_POWER_RESUME;
1552 musb_writeb(mregs, MUSB_POWER, power);
1554 spin_unlock_irqrestore(&musb->lock, flags);
1559 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1561 struct musb *musb = gadget_to_musb(gadget);
1563 musb->is_self_powered = !!is_selfpowered;
1567 static void musb_pullup(struct musb *musb, int is_on)
1571 power = musb_readb(musb->mregs, MUSB_POWER);
1573 power |= MUSB_POWER_SOFTCONN;
1575 power &= ~MUSB_POWER_SOFTCONN;
1577 /* FIXME if on, HdrcStart; if off, HdrcStop */
1579 DBG(3, "gadget %s D+ pullup %s\n",
1580 musb->gadget_driver->function, is_on ? "on" : "off");
1581 musb_writeb(musb->mregs, MUSB_POWER, power);
1585 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1587 DBG(2, "<= %s =>\n", __func__);
1590 * FIXME iff driver's softconnect flag is set (as it is during probe,
1591 * though that can clear it), just musb_pullup().
1598 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1600 struct musb *musb = gadget_to_musb(gadget);
1602 if (!musb->xceiv->set_power)
1604 return otg_set_power(musb->xceiv, mA);
1607 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1609 struct musb *musb = gadget_to_musb(gadget);
1610 unsigned long flags;
1614 /* NOTE: this assumes we are sensing vbus; we'd rather
1615 * not pullup unless the B-session is active.
1617 spin_lock_irqsave(&musb->lock, flags);
1618 if (is_on != musb->softconnect) {
1619 musb->softconnect = is_on;
1620 musb_pullup(musb, is_on);
1622 spin_unlock_irqrestore(&musb->lock, flags);
1626 static const struct usb_gadget_ops musb_gadget_operations = {
1627 .get_frame = musb_gadget_get_frame,
1628 .wakeup = musb_gadget_wakeup,
1629 .set_selfpowered = musb_gadget_set_self_powered,
1630 /* .vbus_session = musb_gadget_vbus_session, */
1631 .vbus_draw = musb_gadget_vbus_draw,
1632 .pullup = musb_gadget_pullup,
1635 /* ----------------------------------------------------------------------- */
1639 /* Only this registration code "knows" the rule (from USB standards)
1640 * about there being only one external upstream port. It assumes
1641 * all peripheral ports are external...
1643 static struct musb *the_gadget;
1645 static void musb_gadget_release(struct device *dev)
1647 /* kref_put(WHAT) */
1648 dev_dbg(dev, "%s\n", __func__);
1653 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1655 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1657 memset(ep, 0, sizeof *ep);
1659 ep->current_epnum = epnum;
1664 INIT_LIST_HEAD(&ep->req_list);
1666 sprintf(ep->name, "ep%d%s", epnum,
1667 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1668 is_in ? "in" : "out"));
1669 ep->end_point.name = ep->name;
1670 INIT_LIST_HEAD(&ep->end_point.ep_list);
1672 ep->end_point.maxpacket = 64;
1673 ep->end_point.ops = &musb_g_ep0_ops;
1674 musb->g.ep0 = &ep->end_point;
1677 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1679 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1680 ep->end_point.ops = &musb_ep_ops;
1681 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1686 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1687 * to the rest of the driver state.
1689 static inline void __init musb_g_init_endpoints(struct musb *musb)
1692 struct musb_hw_ep *hw_ep;
1695 /* initialize endpoint list just once */
1696 INIT_LIST_HEAD(&(musb->g.ep_list));
1698 for (epnum = 0, hw_ep = musb->endpoints;
1699 epnum < musb->nr_endpoints;
1701 if (hw_ep->is_shared_fifo /* || !epnum */) {
1702 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1705 if (hw_ep->max_packet_sz_tx) {
1706 init_peripheral_ep(musb, &hw_ep->ep_in,
1710 if (hw_ep->max_packet_sz_rx) {
1711 init_peripheral_ep(musb, &hw_ep->ep_out,
1719 /* called once during driver setup to initialize and link into
1720 * the driver model; memory is zeroed.
1722 int __init musb_gadget_setup(struct musb *musb)
1726 /* REVISIT minor race: if (erroneously) setting up two
1727 * musb peripherals at the same time, only the bus lock
1734 musb->g.ops = &musb_gadget_operations;
1735 musb->g.is_dualspeed = 1;
1736 musb->g.speed = USB_SPEED_UNKNOWN;
1738 /* this "gadget" abstracts/virtualizes the controller */
1739 dev_set_name(&musb->g.dev, "gadget");
1740 musb->g.dev.parent = musb->controller;
1741 musb->g.dev.dma_mask = musb->controller->dma_mask;
1742 musb->g.dev.release = musb_gadget_release;
1743 musb->g.name = musb_driver_name;
1745 if (is_otg_enabled(musb))
1748 musb_g_init_endpoints(musb);
1750 musb->is_active = 0;
1751 musb_platform_try_idle(musb, 0);
1753 status = device_register(&musb->g.dev);
1755 put_device(&musb->g.dev);
1761 void musb_gadget_cleanup(struct musb *musb)
1763 if (musb != the_gadget)
1766 device_unregister(&musb->g.dev);
1771 * Register the gadget driver. Used by gadget drivers when
1772 * registering themselves with the controller.
1774 * -EINVAL something went wrong (not driver)
1775 * -EBUSY another gadget is already using the controller
1776 * -ENOMEM no memory to perform the operation
1778 * @param driver the gadget driver
1779 * @param bind the driver's bind function
1780 * @return <0 if error, 0 if everything is fine
1782 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1783 int (*bind)(struct usb_gadget *))
1786 unsigned long flags;
1787 struct musb *musb = the_gadget;
1790 || driver->speed != USB_SPEED_HIGH
1791 || !bind || !driver->setup)
1794 /* driver must be initialized to support peripheral mode */
1796 DBG(1, "%s, no dev??\n", __func__);
1800 DBG(3, "registering driver %s\n", driver->function);
1801 spin_lock_irqsave(&musb->lock, flags);
1803 if (musb->gadget_driver) {
1804 DBG(1, "%s is already bound to %s\n",
1806 musb->gadget_driver->driver.name);
1809 musb->gadget_driver = driver;
1810 musb->g.dev.driver = &driver->driver;
1811 driver->driver.bus = NULL;
1812 musb->softconnect = 1;
1816 spin_unlock_irqrestore(&musb->lock, flags);
1819 retval = bind(&musb->g);
1821 DBG(3, "bind to driver %s failed --> %d\n",
1822 driver->driver.name, retval);
1823 musb->gadget_driver = NULL;
1824 musb->g.dev.driver = NULL;
1827 spin_lock_irqsave(&musb->lock, flags);
1829 otg_set_peripheral(musb->xceiv, &musb->g);
1830 musb->xceiv->state = OTG_STATE_B_IDLE;
1831 musb->is_active = 1;
1833 /* FIXME this ignores the softconnect flag. Drivers are
1834 * allowed hold the peripheral inactive until for example
1835 * userspace hooks up printer hardware or DSP codecs, so
1836 * hosts only see fully functional devices.
1839 if (!is_otg_enabled(musb))
1842 otg_set_peripheral(musb->xceiv, &musb->g);
1844 spin_unlock_irqrestore(&musb->lock, flags);
1846 if (is_otg_enabled(musb)) {
1847 struct usb_hcd *hcd = musb_to_hcd(musb);
1849 DBG(3, "OTG startup...\n");
1851 /* REVISIT: funcall to other code, which also
1852 * handles power budgeting ... this way also
1853 * ensures HdrcStart is indirectly called.
1855 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1857 DBG(1, "add_hcd failed, %d\n", retval);
1858 spin_lock_irqsave(&musb->lock, flags);
1859 otg_set_peripheral(musb->xceiv, NULL);
1860 musb->gadget_driver = NULL;
1861 musb->g.dev.driver = NULL;
1862 spin_unlock_irqrestore(&musb->lock, flags);
1864 hcd->self.uses_pio_for_control = 1;
1871 EXPORT_SYMBOL(usb_gadget_probe_driver);
1873 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1876 struct musb_hw_ep *hw_ep;
1878 /* don't disconnect if it's not connected */
1879 if (musb->g.speed == USB_SPEED_UNKNOWN)
1882 musb->g.speed = USB_SPEED_UNKNOWN;
1884 /* deactivate the hardware */
1885 if (musb->softconnect) {
1886 musb->softconnect = 0;
1887 musb_pullup(musb, 0);
1891 /* killing any outstanding requests will quiesce the driver;
1892 * then report disconnect
1895 for (i = 0, hw_ep = musb->endpoints;
1896 i < musb->nr_endpoints;
1898 musb_ep_select(musb->mregs, i);
1899 if (hw_ep->is_shared_fifo /* || !epnum */) {
1900 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1902 if (hw_ep->max_packet_sz_tx)
1903 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1904 if (hw_ep->max_packet_sz_rx)
1905 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1909 spin_unlock(&musb->lock);
1910 driver->disconnect(&musb->g);
1911 spin_lock(&musb->lock);
1916 * Unregister the gadget driver. Used by gadget drivers when
1917 * unregistering themselves from the controller.
1919 * @param driver the gadget driver to unregister
1921 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1923 unsigned long flags;
1925 struct musb *musb = the_gadget;
1927 if (!driver || !driver->unbind || !musb)
1930 /* REVISIT always use otg_set_peripheral() here too;
1931 * this needs to shut down the OTG engine.
1934 spin_lock_irqsave(&musb->lock, flags);
1936 #ifdef CONFIG_USB_MUSB_OTG
1937 musb_hnp_stop(musb);
1940 if (musb->gadget_driver == driver) {
1942 (void) musb_gadget_vbus_draw(&musb->g, 0);
1944 musb->xceiv->state = OTG_STATE_UNDEFINED;
1945 stop_activity(musb, driver);
1946 otg_set_peripheral(musb->xceiv, NULL);
1948 DBG(3, "unregistering driver %s\n", driver->function);
1949 spin_unlock_irqrestore(&musb->lock, flags);
1950 driver->unbind(&musb->g);
1951 spin_lock_irqsave(&musb->lock, flags);
1953 musb->gadget_driver = NULL;
1954 musb->g.dev.driver = NULL;
1956 musb->is_active = 0;
1957 musb_platform_try_idle(musb, 0);
1960 spin_unlock_irqrestore(&musb->lock, flags);
1962 if (is_otg_enabled(musb) && retval == 0) {
1963 usb_remove_hcd(musb_to_hcd(musb));
1964 /* FIXME we need to be able to register another
1965 * gadget driver here and have everything work;
1966 * that currently misbehaves.
1972 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1975 /* ----------------------------------------------------------------------- */
1977 /* lifecycle operations called through plat_uds.c */
1979 void musb_g_resume(struct musb *musb)
1981 musb->is_suspended = 0;
1982 switch (musb->xceiv->state) {
1983 case OTG_STATE_B_IDLE:
1985 case OTG_STATE_B_WAIT_ACON:
1986 case OTG_STATE_B_PERIPHERAL:
1987 musb->is_active = 1;
1988 if (musb->gadget_driver && musb->gadget_driver->resume) {
1989 spin_unlock(&musb->lock);
1990 musb->gadget_driver->resume(&musb->g);
1991 spin_lock(&musb->lock);
1995 WARNING("unhandled RESUME transition (%s)\n",
1996 otg_state_string(musb));
2000 /* called when SOF packets stop for 3+ msec */
2001 void musb_g_suspend(struct musb *musb)
2005 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2006 DBG(3, "devctl %02x\n", devctl);
2008 switch (musb->xceiv->state) {
2009 case OTG_STATE_B_IDLE:
2010 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2011 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2013 case OTG_STATE_B_PERIPHERAL:
2014 musb->is_suspended = 1;
2015 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2016 spin_unlock(&musb->lock);
2017 musb->gadget_driver->suspend(&musb->g);
2018 spin_lock(&musb->lock);
2022 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2023 * A_PERIPHERAL may need care too
2025 WARNING("unhandled SUSPEND transition (%s)\n",
2026 otg_state_string(musb));
2030 /* Called during SRP */
2031 void musb_g_wakeup(struct musb *musb)
2033 musb_gadget_wakeup(&musb->g);
2036 /* called when VBUS drops below session threshold, and in other cases */
2037 void musb_g_disconnect(struct musb *musb)
2039 void __iomem *mregs = musb->mregs;
2040 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2042 DBG(3, "devctl %02x\n", devctl);
2045 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2047 /* don't draw vbus until new b-default session */
2048 (void) musb_gadget_vbus_draw(&musb->g, 0);
2050 musb->g.speed = USB_SPEED_UNKNOWN;
2051 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2052 spin_unlock(&musb->lock);
2053 musb->gadget_driver->disconnect(&musb->g);
2054 spin_lock(&musb->lock);
2057 switch (musb->xceiv->state) {
2059 #ifdef CONFIG_USB_MUSB_OTG
2060 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
2061 otg_state_string(musb));
2062 musb->xceiv->state = OTG_STATE_A_IDLE;
2063 MUSB_HST_MODE(musb);
2065 case OTG_STATE_A_PERIPHERAL:
2066 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2067 MUSB_HST_MODE(musb);
2069 case OTG_STATE_B_WAIT_ACON:
2070 case OTG_STATE_B_HOST:
2072 case OTG_STATE_B_PERIPHERAL:
2073 case OTG_STATE_B_IDLE:
2074 musb->xceiv->state = OTG_STATE_B_IDLE;
2076 case OTG_STATE_B_SRP_INIT:
2080 musb->is_active = 0;
2083 void musb_g_reset(struct musb *musb)
2084 __releases(musb->lock)
2085 __acquires(musb->lock)
2087 void __iomem *mbase = musb->mregs;
2088 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2091 DBG(3, "<== %s addr=%x driver '%s'\n",
2092 (devctl & MUSB_DEVCTL_BDEVICE)
2093 ? "B-Device" : "A-Device",
2094 musb_readb(mbase, MUSB_FADDR),
2096 ? musb->gadget_driver->driver.name
2100 /* report disconnect, if we didn't already (flushing EP state) */
2101 if (musb->g.speed != USB_SPEED_UNKNOWN)
2102 musb_g_disconnect(musb);
2105 else if (devctl & MUSB_DEVCTL_HR)
2106 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2109 /* what speed did we negotiate? */
2110 power = musb_readb(mbase, MUSB_POWER);
2111 musb->g.speed = (power & MUSB_POWER_HSMODE)
2112 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2114 /* start in USB_STATE_DEFAULT */
2115 musb->is_active = 1;
2116 musb->is_suspended = 0;
2117 MUSB_DEV_MODE(musb);
2119 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2121 musb->may_wakeup = 0;
2122 musb->g.b_hnp_enable = 0;
2123 musb->g.a_alt_hnp_support = 0;
2124 musb->g.a_hnp_support = 0;
2126 /* Normal reset, as B-Device;
2127 * or else after HNP, as A-Device
2129 if (devctl & MUSB_DEVCTL_BDEVICE) {
2130 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2131 musb->g.is_a_peripheral = 0;
2132 } else if (is_otg_enabled(musb)) {
2133 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2134 musb->g.is_a_peripheral = 1;
2138 /* start with default limits on VBUS power draw */
2139 (void) musb_gadget_vbus_draw(&musb->g,
2140 is_otg_enabled(musb) ? 8 : 100);