2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
96 * Immediately complete a request.
98 * @param request the request to complete
99 * @param status the status to complete the request with
100 * Context: controller locked, IRQs blocked.
102 void musb_g_giveback(
104 struct usb_request *request,
106 __releases(ep->musb->lock)
107 __acquires(ep->musb->lock)
109 struct musb_request *req;
113 req = to_musb_request(request);
115 list_del(&request->list);
116 if (req->request.status == -EINPROGRESS)
117 req->request.status = status;
121 spin_unlock(&musb->lock);
122 if (is_dma_capable()) {
124 dma_unmap_single(musb->controller,
130 req->request.dma = DMA_ADDR_INVALID;
132 } else if (req->request.dma != DMA_ADDR_INVALID)
133 dma_sync_single_for_cpu(musb->controller,
140 if (request->status == 0)
141 DBG(5, "%s done request %p, %d/%d\n",
142 ep->end_point.name, request,
143 req->request.actual, req->request.length);
145 DBG(2, "%s request %p, %d/%d fault %d\n",
146 ep->end_point.name, request,
147 req->request.actual, req->request.length,
149 req->request.complete(&req->ep->end_point, &req->request);
150 spin_lock(&musb->lock);
154 /* ----------------------------------------------------------------------- */
157 * Abort requests queued to an endpoint using the status. Synchronous.
158 * caller locked controller and blocked irqs, and selected this ep.
160 static void nuke(struct musb_ep *ep, const int status)
162 struct musb_request *req = NULL;
163 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
167 if (is_dma_capable() && ep->dma) {
168 struct dma_controller *c = ep->musb->dma_controller;
173 * The programming guide says that we must not clear
174 * the DMAMODE bit before DMAENAB, so we only
175 * clear it in the second write...
177 musb_writew(epio, MUSB_TXCSR,
178 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
179 musb_writew(epio, MUSB_TXCSR,
180 0 | MUSB_TXCSR_FLUSHFIFO);
182 musb_writew(epio, MUSB_RXCSR,
183 0 | MUSB_RXCSR_FLUSHFIFO);
184 musb_writew(epio, MUSB_RXCSR,
185 0 | MUSB_RXCSR_FLUSHFIFO);
188 value = c->channel_abort(ep->dma);
189 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
190 c->channel_release(ep->dma);
194 while (!list_empty(&(ep->req_list))) {
195 req = container_of(ep->req_list.next, struct musb_request,
197 musb_g_giveback(ep, &req->request, status);
201 /* ----------------------------------------------------------------------- */
203 /* Data transfers - pure PIO, pure DMA, or mixed mode */
206 * This assumes the separate CPPI engine is responding to DMA requests
207 * from the usb core ... sequenced a bit differently from mentor dma.
210 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
212 if (can_bulk_split(musb, ep->type))
213 return ep->hw_ep->max_packet_sz_tx;
215 return ep->packet_sz;
219 #ifdef CONFIG_USB_INVENTRA_DMA
221 /* Peripheral tx (IN) using Mentor DMA works as follows:
222 Only mode 0 is used for transfers <= wPktSize,
223 mode 1 is used for larger transfers,
225 One of the following happens:
226 - Host sends IN token which causes an endpoint interrupt
228 -> if DMA is currently busy, exit.
229 -> if queue is non-empty, txstate().
231 - Request is queued by the gadget driver.
232 -> if queue was previously empty, txstate()
237 | (data is transferred to the FIFO, then sent out when
238 | IN token(s) are recd from Host.
239 | -> DMA interrupt on completion
241 | -> stop DMA, ~DMAENAB,
242 | -> set TxPktRdy for last short pkt or zlp
243 | -> Complete Request
244 | -> Continue next request (call txstate)
245 |___________________________________|
247 * Non-Mentor DMA engines can of course work differently, such as by
248 * upleveling from irq-per-packet to irq-per-buffer.
254 * An endpoint is transmitting data. This can be called either from
255 * the IRQ routine or from ep.queue() to kickstart a request on an
258 * Context: controller locked, IRQs blocked, endpoint selected
260 static void txstate(struct musb *musb, struct musb_request *req)
262 u8 epnum = req->epnum;
263 struct musb_ep *musb_ep;
264 void __iomem *epio = musb->endpoints[epnum].regs;
265 struct usb_request *request;
266 u16 fifo_count = 0, csr;
271 /* we shouldn't get here while DMA is active ... but we do ... */
272 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
273 DBG(4, "dma pending...\n");
277 /* read TXCSR before */
278 csr = musb_readw(epio, MUSB_TXCSR);
280 request = &req->request;
281 fifo_count = min(max_ep_writesize(musb, musb_ep),
282 (int)(request->length - request->actual));
284 if (csr & MUSB_TXCSR_TXPKTRDY) {
285 DBG(5, "%s old packet still ready , txcsr %03x\n",
286 musb_ep->end_point.name, csr);
290 if (csr & MUSB_TXCSR_P_SENDSTALL) {
291 DBG(5, "%s stalling, txcsr %03x\n",
292 musb_ep->end_point.name, csr);
296 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
297 epnum, musb_ep->packet_sz, fifo_count,
300 #ifndef CONFIG_MUSB_PIO_ONLY
301 if (is_dma_capable() && musb_ep->dma) {
302 struct dma_controller *c = musb->dma_controller;
305 /* setup DMA, then program endpoint CSR */
306 request_size = min_t(size_t, request->length - request->actual,
307 musb_ep->dma->max_len);
309 use_dma = (request->dma != DMA_ADDR_INVALID);
311 /* MUSB_TXCSR_P_ISO is still set correctly */
313 #ifdef CONFIG_USB_INVENTRA_DMA
315 if (request_size < musb_ep->packet_sz)
316 musb_ep->dma->desired_mode = 0;
318 musb_ep->dma->desired_mode = 1;
320 use_dma = use_dma && c->channel_program(
321 musb_ep->dma, musb_ep->packet_sz,
322 musb_ep->dma->desired_mode,
323 request->dma + request->actual, request_size);
325 if (musb_ep->dma->desired_mode == 0) {
327 * We must not clear the DMAMODE bit
328 * before the DMAENAB bit -- and the
329 * latter doesn't always get cleared
330 * before we get here...
332 csr &= ~(MUSB_TXCSR_AUTOSET
333 | MUSB_TXCSR_DMAENAB);
334 musb_writew(epio, MUSB_TXCSR, csr
335 | MUSB_TXCSR_P_WZC_BITS);
336 csr &= ~MUSB_TXCSR_DMAMODE;
337 csr |= (MUSB_TXCSR_DMAENAB |
339 /* against programming guide */
341 csr |= (MUSB_TXCSR_DMAENAB
344 if (!musb_ep->hb_mult)
345 csr |= MUSB_TXCSR_AUTOSET;
347 csr &= ~MUSB_TXCSR_P_UNDERRUN;
349 musb_writew(epio, MUSB_TXCSR, csr);
353 #elif defined(CONFIG_USB_TI_CPPI_DMA)
354 /* program endpoint CSR first, then setup DMA */
355 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
356 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
358 musb_writew(epio, MUSB_TXCSR,
359 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
362 /* ensure writebuffer is empty */
363 csr = musb_readw(epio, MUSB_TXCSR);
365 /* NOTE host side sets DMAENAB later than this; both are
366 * OK since the transfer dma glue (between CPPI and Mentor
367 * fifos) just tells CPPI it could start. Data only moves
368 * to the USB TX fifo when both fifos are ready.
371 /* "mode" is irrelevant here; handle terminating ZLPs like
372 * PIO does, since the hardware RNDIS mode seems unreliable
373 * except for the last-packet-is-already-short case.
375 use_dma = use_dma && c->channel_program(
376 musb_ep->dma, musb_ep->packet_sz,
378 request->dma + request->actual,
381 c->channel_release(musb_ep->dma);
383 csr &= ~MUSB_TXCSR_DMAENAB;
384 musb_writew(epio, MUSB_TXCSR, csr);
385 /* invariant: prequest->buf is non-null */
387 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
388 use_dma = use_dma && c->channel_program(
389 musb_ep->dma, musb_ep->packet_sz,
391 request->dma + request->actual,
398 musb_write_fifo(musb_ep->hw_ep, fifo_count,
399 (u8 *) (request->buf + request->actual));
400 request->actual += fifo_count;
401 csr |= MUSB_TXCSR_TXPKTRDY;
402 csr &= ~MUSB_TXCSR_P_UNDERRUN;
403 musb_writew(epio, MUSB_TXCSR, csr);
406 /* host may already have the data when this message shows... */
407 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
408 musb_ep->end_point.name, use_dma ? "dma" : "pio",
409 request->actual, request->length,
410 musb_readw(epio, MUSB_TXCSR),
412 musb_readw(epio, MUSB_TXMAXP));
416 * FIFO state update (e.g. data ready).
417 * Called from IRQ, with controller locked.
419 void musb_g_tx(struct musb *musb, u8 epnum)
422 struct usb_request *request;
423 u8 __iomem *mbase = musb->mregs;
424 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
425 void __iomem *epio = musb->endpoints[epnum].regs;
426 struct dma_channel *dma;
428 musb_ep_select(mbase, epnum);
429 request = next_request(musb_ep);
431 csr = musb_readw(epio, MUSB_TXCSR);
432 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
434 dma = is_dma_capable() ? musb_ep->dma : NULL;
437 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
438 * probably rates reporting as a host error.
440 if (csr & MUSB_TXCSR_P_SENTSTALL) {
441 csr |= MUSB_TXCSR_P_WZC_BITS;
442 csr &= ~MUSB_TXCSR_P_SENTSTALL;
443 musb_writew(epio, MUSB_TXCSR, csr);
447 if (csr & MUSB_TXCSR_P_UNDERRUN) {
448 /* We NAKed, no big deal... little reason to care. */
449 csr |= MUSB_TXCSR_P_WZC_BITS;
450 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
451 musb_writew(epio, MUSB_TXCSR, csr);
452 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
455 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
457 * SHOULD NOT HAPPEN... has with CPPI though, after
458 * changing SENDSTALL (and other cases); harmless?
460 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
467 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
469 csr |= MUSB_TXCSR_P_WZC_BITS;
470 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
471 MUSB_TXCSR_TXPKTRDY);
472 musb_writew(epio, MUSB_TXCSR, csr);
473 /* Ensure writebuffer is empty. */
474 csr = musb_readw(epio, MUSB_TXCSR);
475 request->actual += musb_ep->dma->actual_len;
476 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
477 epnum, csr, musb_ep->dma->actual_len, request);
481 * First, maybe a terminating short packet. Some DMA
482 * engines might handle this by themselves.
484 if ((request->zero && request->length
485 && (request->length % musb_ep->packet_sz == 0)
486 && (request->actual == request->length))
487 #ifdef CONFIG_USB_INVENTRA_DMA
488 || (is_dma && (!dma->desired_mode ||
490 (musb_ep->packet_sz - 1))))
494 * On DMA completion, FIFO may not be
497 if (csr & MUSB_TXCSR_TXPKTRDY)
500 DBG(4, "sending zero pkt\n");
501 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
502 | MUSB_TXCSR_TXPKTRDY);
506 if (request->actual == request->length) {
507 musb_g_giveback(musb_ep, request, 0);
508 request = musb_ep->desc ? next_request(musb_ep) : NULL;
510 DBG(4, "%s idle now\n",
511 musb_ep->end_point.name);
516 txstate(musb, to_musb_request(request));
520 /* ------------------------------------------------------------ */
522 #ifdef CONFIG_USB_INVENTRA_DMA
524 /* Peripheral rx (OUT) using Mentor DMA works as follows:
525 - Only mode 0 is used.
527 - Request is queued by the gadget class driver.
528 -> if queue was previously empty, rxstate()
530 - Host sends OUT token which causes an endpoint interrupt
532 | -> if request queued, call rxstate
534 | | -> DMA interrupt on completion
538 | | -> if data recd = max expected
539 | | by the request, or host
540 | | sent a short packet,
541 | | complete the request,
542 | | and start the next one.
543 | |_____________________________________|
544 | else just wait for the host
545 | to send the next OUT token.
546 |__________________________________________________|
548 * Non-Mentor DMA engines can of course work differently.
554 * Context: controller locked, IRQs blocked, endpoint selected
556 static void rxstate(struct musb *musb, struct musb_request *req)
558 const u8 epnum = req->epnum;
559 struct usb_request *request = &req->request;
560 struct musb_ep *musb_ep;
561 void __iomem *epio = musb->endpoints[epnum].regs;
562 unsigned fifo_count = 0;
564 u16 csr = musb_readw(epio, MUSB_RXCSR);
565 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
567 if (hw_ep->is_shared_fifo)
568 musb_ep = &hw_ep->ep_in;
570 musb_ep = &hw_ep->ep_out;
572 len = musb_ep->packet_sz;
574 /* We shouldn't get here while DMA is active, but we do... */
575 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
576 DBG(4, "DMA pending...\n");
580 if (csr & MUSB_RXCSR_P_SENDSTALL) {
581 DBG(5, "%s stalling, RXCSR %04x\n",
582 musb_ep->end_point.name, csr);
586 if (is_cppi_enabled() && musb_ep->dma) {
587 struct dma_controller *c = musb->dma_controller;
588 struct dma_channel *channel = musb_ep->dma;
590 /* NOTE: CPPI won't actually stop advancing the DMA
591 * queue after short packet transfers, so this is almost
592 * always going to run as IRQ-per-packet DMA so that
593 * faults will be handled correctly.
595 if (c->channel_program(channel,
597 !request->short_not_ok,
598 request->dma + request->actual,
599 request->length - request->actual)) {
601 /* make sure that if an rxpkt arrived after the irq,
602 * the cppi engine will be ready to take it as soon
605 csr &= ~(MUSB_RXCSR_AUTOCLEAR
606 | MUSB_RXCSR_DMAMODE);
607 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
608 musb_writew(epio, MUSB_RXCSR, csr);
613 if (csr & MUSB_RXCSR_RXPKTRDY) {
614 len = musb_readw(epio, MUSB_RXCOUNT);
615 if (request->actual < request->length) {
616 #ifdef CONFIG_USB_INVENTRA_DMA
617 if (is_dma_capable() && musb_ep->dma) {
618 struct dma_controller *c;
619 struct dma_channel *channel;
622 c = musb->dma_controller;
623 channel = musb_ep->dma;
625 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
626 * mode 0 only. So we do not get endpoint interrupts due to DMA
627 * completion. We only get interrupts from DMA controller.
629 * We could operate in DMA mode 1 if we knew the size of the tranfer
630 * in advance. For mass storage class, request->length = what the host
631 * sends, so that'd work. But for pretty much everything else,
632 * request->length is routinely more than what the host sends. For
633 * most these gadgets, end of is signified either by a short packet,
634 * or filling the last byte of the buffer. (Sending extra data in
635 * that last pckate should trigger an overflow fault.) But in mode 1,
636 * we don't get DMA completion interrrupt for short packets.
638 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
639 * to get endpoint interrupt on every DMA req, but that didn't seem
642 * REVISIT an updated g_file_storage can set req->short_not_ok, which
643 * then becomes usable as a runtime "use mode 1" hint...
646 csr |= MUSB_RXCSR_DMAENAB;
647 if (!musb_ep->hb_mult &&
648 musb_ep->hw_ep->rx_double_buffered)
649 csr |= MUSB_RXCSR_AUTOCLEAR;
651 /* csr |= MUSB_RXCSR_DMAMODE; */
653 /* this special sequence (enabling and then
654 * disabling MUSB_RXCSR_DMAMODE) is required
655 * to get DMAReq to activate
657 musb_writew(epio, MUSB_RXCSR,
658 csr | MUSB_RXCSR_DMAMODE);
660 musb_writew(epio, MUSB_RXCSR, csr);
662 if (request->actual < request->length) {
663 int transfer_size = 0;
665 transfer_size = min(request->length - request->actual,
668 transfer_size = min(request->length - request->actual,
671 if (transfer_size <= musb_ep->packet_sz)
672 musb_ep->dma->desired_mode = 0;
674 musb_ep->dma->desired_mode = 1;
676 use_dma = c->channel_program(
679 channel->desired_mode,
688 #endif /* Mentor's DMA */
690 fifo_count = request->length - request->actual;
691 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
692 musb_ep->end_point.name,
696 fifo_count = min_t(unsigned, len, fifo_count);
698 #ifdef CONFIG_USB_TUSB_OMAP_DMA
699 if (tusb_dma_omap() && musb_ep->dma) {
700 struct dma_controller *c = musb->dma_controller;
701 struct dma_channel *channel = musb_ep->dma;
702 u32 dma_addr = request->dma + request->actual;
705 ret = c->channel_program(channel,
707 channel->desired_mode,
715 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
716 (request->buf + request->actual));
717 request->actual += fifo_count;
719 /* REVISIT if we left anything in the fifo, flush
720 * it and report -EOVERFLOW
724 csr |= MUSB_RXCSR_P_WZC_BITS;
725 csr &= ~MUSB_RXCSR_RXPKTRDY;
726 musb_writew(epio, MUSB_RXCSR, csr);
730 /* reach the end or short packet detected */
731 if (request->actual == request->length || len < musb_ep->packet_sz)
732 musb_g_giveback(musb_ep, request, 0);
736 * Data ready for a request; called from IRQ
738 void musb_g_rx(struct musb *musb, u8 epnum)
741 struct usb_request *request;
742 void __iomem *mbase = musb->mregs;
743 struct musb_ep *musb_ep;
744 void __iomem *epio = musb->endpoints[epnum].regs;
745 struct dma_channel *dma;
746 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
748 if (hw_ep->is_shared_fifo)
749 musb_ep = &hw_ep->ep_in;
751 musb_ep = &hw_ep->ep_out;
753 musb_ep_select(mbase, epnum);
755 request = next_request(musb_ep);
759 csr = musb_readw(epio, MUSB_RXCSR);
760 dma = is_dma_capable() ? musb_ep->dma : NULL;
762 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
763 csr, dma ? " (dma)" : "", request);
765 if (csr & MUSB_RXCSR_P_SENTSTALL) {
766 csr |= MUSB_RXCSR_P_WZC_BITS;
767 csr &= ~MUSB_RXCSR_P_SENTSTALL;
768 musb_writew(epio, MUSB_RXCSR, csr);
772 if (csr & MUSB_RXCSR_P_OVERRUN) {
773 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
774 csr &= ~MUSB_RXCSR_P_OVERRUN;
775 musb_writew(epio, MUSB_RXCSR, csr);
777 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
778 if (request->status == -EINPROGRESS)
779 request->status = -EOVERFLOW;
781 if (csr & MUSB_RXCSR_INCOMPRX) {
782 /* REVISIT not necessarily an error */
783 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
786 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
787 /* "should not happen"; likely RXPKTRDY pending for DMA */
788 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
789 "%s busy, csr %04x\n",
790 musb_ep->end_point.name, csr);
794 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
795 csr &= ~(MUSB_RXCSR_AUTOCLEAR
797 | MUSB_RXCSR_DMAMODE);
798 musb_writew(epio, MUSB_RXCSR,
799 MUSB_RXCSR_P_WZC_BITS | csr);
801 request->actual += musb_ep->dma->actual_len;
803 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
805 musb_readw(epio, MUSB_RXCSR),
806 musb_ep->dma->actual_len, request);
808 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
809 /* Autoclear doesn't clear RxPktRdy for short packets */
810 if ((dma->desired_mode == 0)
812 & (musb_ep->packet_sz - 1))) {
814 csr &= ~MUSB_RXCSR_RXPKTRDY;
815 musb_writew(epio, MUSB_RXCSR, csr);
818 /* incomplete, and not short? wait for next IN packet */
819 if ((request->actual < request->length)
820 && (musb_ep->dma->actual_len
821 == musb_ep->packet_sz))
824 musb_g_giveback(musb_ep, request, 0);
826 request = next_request(musb_ep);
831 /* Analyze request */
832 rxstate(musb, to_musb_request(request));
835 /* ------------------------------------------------------------ */
837 static int musb_gadget_enable(struct usb_ep *ep,
838 const struct usb_endpoint_descriptor *desc)
841 struct musb_ep *musb_ep;
842 struct musb_hw_ep *hw_ep;
849 int status = -EINVAL;
854 musb_ep = to_musb_ep(ep);
855 hw_ep = musb_ep->hw_ep;
857 musb = musb_ep->musb;
859 epnum = musb_ep->current_epnum;
861 spin_lock_irqsave(&musb->lock, flags);
867 musb_ep->type = usb_endpoint_type(desc);
869 /* check direction and (later) maxpacket size against endpoint */
870 if (usb_endpoint_num(desc) != epnum)
873 /* REVISIT this rules out high bandwidth periodic transfers */
874 tmp = le16_to_cpu(desc->wMaxPacketSize);
878 if (usb_endpoint_dir_in(desc))
879 ok = musb->hb_iso_tx;
881 ok = musb->hb_iso_rx;
884 DBG(4, "%s: not support ISO high bandwidth\n", __func__);
887 musb_ep->hb_mult = (tmp >> 11) & 3;
889 musb_ep->hb_mult = 0;
892 musb_ep->packet_sz = tmp & 0x7ff;
893 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
895 /* enable the interrupts for the endpoint, set the endpoint
896 * packet size (or fail), set the mode, clear the fifo
898 musb_ep_select(mbase, epnum);
899 if (usb_endpoint_dir_in(desc)) {
900 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
902 if (hw_ep->is_shared_fifo)
907 if (tmp > hw_ep->max_packet_sz_tx) {
908 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
912 int_txe |= (1 << epnum);
913 musb_writew(mbase, MUSB_INTRTXE, int_txe);
915 /* REVISIT if can_bulk_split(), use by updating "tmp";
916 * likewise high bandwidth periodic tx
918 /* Set TXMAXP with the FIFO size of the endpoint
919 * to disable double buffering mode. Currently, It seems that double
920 * buffering has problem if musb RTL revision number < 2.0.
922 if (musb->hwvers < MUSB_HWVERS_2000)
923 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
925 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11));
927 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
928 if (musb_readw(regs, MUSB_TXCSR)
929 & MUSB_TXCSR_FIFONOTEMPTY)
930 csr |= MUSB_TXCSR_FLUSHFIFO;
931 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
932 csr |= MUSB_TXCSR_P_ISO;
934 /* set twice in case of double buffering */
935 musb_writew(regs, MUSB_TXCSR, csr);
936 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
937 musb_writew(regs, MUSB_TXCSR, csr);
940 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
942 if (hw_ep->is_shared_fifo)
947 if (tmp > hw_ep->max_packet_sz_rx) {
948 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
952 int_rxe |= (1 << epnum);
953 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
955 /* REVISIT if can_bulk_combine() use by updating "tmp"
956 * likewise high bandwidth periodic rx
958 /* Set RXMAXP with the FIFO size of the endpoint
959 * to disable double buffering mode.
961 if (musb->hwvers < MUSB_HWVERS_2000)
962 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_rx);
964 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11));
966 /* force shared fifo to OUT-only mode */
967 if (hw_ep->is_shared_fifo) {
968 csr = musb_readw(regs, MUSB_TXCSR);
969 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
970 musb_writew(regs, MUSB_TXCSR, csr);
973 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
974 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
975 csr |= MUSB_RXCSR_P_ISO;
976 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
977 csr |= MUSB_RXCSR_DISNYET;
979 /* set twice in case of double buffering */
980 musb_writew(regs, MUSB_RXCSR, csr);
981 musb_writew(regs, MUSB_RXCSR, csr);
984 /* NOTE: all the I/O code _should_ work fine without DMA, in case
985 * for some reason you run out of channels here.
987 if (is_dma_capable() && musb->dma_controller) {
988 struct dma_controller *c = musb->dma_controller;
990 musb_ep->dma = c->channel_alloc(c, hw_ep,
991 (desc->bEndpointAddress & USB_DIR_IN));
995 musb_ep->desc = desc;
1000 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1001 musb_driver_name, musb_ep->end_point.name,
1002 ({ char *s; switch (musb_ep->type) {
1003 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1004 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1005 default: s = "iso"; break;
1007 musb_ep->is_in ? "IN" : "OUT",
1008 musb_ep->dma ? "dma, " : "",
1009 musb_ep->packet_sz);
1011 schedule_work(&musb->irq_work);
1014 spin_unlock_irqrestore(&musb->lock, flags);
1019 * Disable an endpoint flushing all requests queued.
1021 static int musb_gadget_disable(struct usb_ep *ep)
1023 unsigned long flags;
1026 struct musb_ep *musb_ep;
1030 musb_ep = to_musb_ep(ep);
1031 musb = musb_ep->musb;
1032 epnum = musb_ep->current_epnum;
1033 epio = musb->endpoints[epnum].regs;
1035 spin_lock_irqsave(&musb->lock, flags);
1036 musb_ep_select(musb->mregs, epnum);
1038 /* zero the endpoint sizes */
1039 if (musb_ep->is_in) {
1040 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1041 int_txe &= ~(1 << epnum);
1042 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1043 musb_writew(epio, MUSB_TXMAXP, 0);
1045 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1046 int_rxe &= ~(1 << epnum);
1047 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1048 musb_writew(epio, MUSB_RXMAXP, 0);
1051 musb_ep->desc = NULL;
1053 /* abort all pending DMA and requests */
1054 nuke(musb_ep, -ESHUTDOWN);
1056 schedule_work(&musb->irq_work);
1058 spin_unlock_irqrestore(&(musb->lock), flags);
1060 DBG(2, "%s\n", musb_ep->end_point.name);
1066 * Allocate a request for an endpoint.
1067 * Reused by ep0 code.
1069 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1071 struct musb_ep *musb_ep = to_musb_ep(ep);
1072 struct musb_request *request = NULL;
1074 request = kzalloc(sizeof *request, gfp_flags);
1076 INIT_LIST_HEAD(&request->request.list);
1077 request->request.dma = DMA_ADDR_INVALID;
1078 request->epnum = musb_ep->current_epnum;
1079 request->ep = musb_ep;
1082 return &request->request;
1087 * Reused by ep0 code.
1089 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1091 kfree(to_musb_request(req));
1094 static LIST_HEAD(buffers);
1096 struct free_record {
1097 struct list_head list;
1104 * Context: controller locked, IRQs blocked.
1106 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1108 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1109 req->tx ? "TX/IN" : "RX/OUT",
1110 &req->request, req->request.length, req->epnum);
1112 musb_ep_select(musb->mregs, req->epnum);
1119 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1122 struct musb_ep *musb_ep;
1123 struct musb_request *request;
1126 unsigned long lockflags;
1133 musb_ep = to_musb_ep(ep);
1134 musb = musb_ep->musb;
1136 request = to_musb_request(req);
1137 request->musb = musb;
1139 if (request->ep != musb_ep)
1142 DBG(4, "<== to %s request=%p\n", ep->name, req);
1144 /* request is mine now... */
1145 request->request.actual = 0;
1146 request->request.status = -EINPROGRESS;
1147 request->epnum = musb_ep->current_epnum;
1148 request->tx = musb_ep->is_in;
1150 if (is_dma_capable() && musb_ep->dma) {
1151 if (request->request.dma == DMA_ADDR_INVALID) {
1152 request->request.dma = dma_map_single(
1154 request->request.buf,
1155 request->request.length,
1159 request->mapped = 1;
1161 dma_sync_single_for_device(musb->controller,
1162 request->request.dma,
1163 request->request.length,
1167 request->mapped = 0;
1169 } else if (!req->buf) {
1172 request->mapped = 0;
1174 spin_lock_irqsave(&musb->lock, lockflags);
1176 /* don't queue if the ep is down */
1177 if (!musb_ep->desc) {
1178 DBG(4, "req %p queued to %s while ep %s\n",
1179 req, ep->name, "disabled");
1180 status = -ESHUTDOWN;
1184 /* add request to the list */
1185 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1187 /* it this is the head of the queue, start i/o ... */
1188 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1189 musb_ep_restart(musb, request);
1192 spin_unlock_irqrestore(&musb->lock, lockflags);
1196 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1198 struct musb_ep *musb_ep = to_musb_ep(ep);
1199 struct usb_request *r;
1200 unsigned long flags;
1202 struct musb *musb = musb_ep->musb;
1204 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1207 spin_lock_irqsave(&musb->lock, flags);
1209 list_for_each_entry(r, &musb_ep->req_list, list) {
1214 DBG(3, "request %p not queued to %s\n", request, ep->name);
1219 /* if the hardware doesn't have the request, easy ... */
1220 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1221 musb_g_giveback(musb_ep, request, -ECONNRESET);
1223 /* ... else abort the dma transfer ... */
1224 else if (is_dma_capable() && musb_ep->dma) {
1225 struct dma_controller *c = musb->dma_controller;
1227 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1228 if (c->channel_abort)
1229 status = c->channel_abort(musb_ep->dma);
1233 musb_g_giveback(musb_ep, request, -ECONNRESET);
1235 /* NOTE: by sticking to easily tested hardware/driver states,
1236 * we leave counting of in-flight packets imprecise.
1238 musb_g_giveback(musb_ep, request, -ECONNRESET);
1242 spin_unlock_irqrestore(&musb->lock, flags);
1247 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1248 * data but will queue requests.
1250 * exported to ep0 code
1252 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1254 struct musb_ep *musb_ep = to_musb_ep(ep);
1255 u8 epnum = musb_ep->current_epnum;
1256 struct musb *musb = musb_ep->musb;
1257 void __iomem *epio = musb->endpoints[epnum].regs;
1258 void __iomem *mbase;
1259 unsigned long flags;
1261 struct musb_request *request;
1266 mbase = musb->mregs;
1268 spin_lock_irqsave(&musb->lock, flags);
1270 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1275 musb_ep_select(mbase, epnum);
1277 request = to_musb_request(next_request(musb_ep));
1280 DBG(3, "request in progress, cannot halt %s\n",
1285 /* Cannot portably stall with non-empty FIFO */
1286 if (musb_ep->is_in) {
1287 csr = musb_readw(epio, MUSB_TXCSR);
1288 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1289 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1295 musb_ep->wedged = 0;
1297 /* set/clear the stall and toggle bits */
1298 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1299 if (musb_ep->is_in) {
1300 csr = musb_readw(epio, MUSB_TXCSR);
1301 csr |= MUSB_TXCSR_P_WZC_BITS
1302 | MUSB_TXCSR_CLRDATATOG;
1304 csr |= MUSB_TXCSR_P_SENDSTALL;
1306 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1307 | MUSB_TXCSR_P_SENTSTALL);
1308 csr &= ~MUSB_TXCSR_TXPKTRDY;
1309 musb_writew(epio, MUSB_TXCSR, csr);
1311 csr = musb_readw(epio, MUSB_RXCSR);
1312 csr |= MUSB_RXCSR_P_WZC_BITS
1313 | MUSB_RXCSR_FLUSHFIFO
1314 | MUSB_RXCSR_CLRDATATOG;
1316 csr |= MUSB_RXCSR_P_SENDSTALL;
1318 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1319 | MUSB_RXCSR_P_SENTSTALL);
1320 musb_writew(epio, MUSB_RXCSR, csr);
1323 /* maybe start the first request in the queue */
1324 if (!musb_ep->busy && !value && request) {
1325 DBG(3, "restarting the request\n");
1326 musb_ep_restart(musb, request);
1330 spin_unlock_irqrestore(&musb->lock, flags);
1335 * Sets the halt feature with the clear requests ignored
1337 static int musb_gadget_set_wedge(struct usb_ep *ep)
1339 struct musb_ep *musb_ep = to_musb_ep(ep);
1344 musb_ep->wedged = 1;
1346 return usb_ep_set_halt(ep);
1349 static int musb_gadget_fifo_status(struct usb_ep *ep)
1351 struct musb_ep *musb_ep = to_musb_ep(ep);
1352 void __iomem *epio = musb_ep->hw_ep->regs;
1353 int retval = -EINVAL;
1355 if (musb_ep->desc && !musb_ep->is_in) {
1356 struct musb *musb = musb_ep->musb;
1357 int epnum = musb_ep->current_epnum;
1358 void __iomem *mbase = musb->mregs;
1359 unsigned long flags;
1361 spin_lock_irqsave(&musb->lock, flags);
1363 musb_ep_select(mbase, epnum);
1364 /* FIXME return zero unless RXPKTRDY is set */
1365 retval = musb_readw(epio, MUSB_RXCOUNT);
1367 spin_unlock_irqrestore(&musb->lock, flags);
1372 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1374 struct musb_ep *musb_ep = to_musb_ep(ep);
1375 struct musb *musb = musb_ep->musb;
1376 u8 epnum = musb_ep->current_epnum;
1377 void __iomem *epio = musb->endpoints[epnum].regs;
1378 void __iomem *mbase;
1379 unsigned long flags;
1382 mbase = musb->mregs;
1384 spin_lock_irqsave(&musb->lock, flags);
1385 musb_ep_select(mbase, (u8) epnum);
1387 /* disable interrupts */
1388 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1389 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1391 if (musb_ep->is_in) {
1392 csr = musb_readw(epio, MUSB_TXCSR);
1393 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1394 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1395 musb_writew(epio, MUSB_TXCSR, csr);
1396 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1397 musb_writew(epio, MUSB_TXCSR, csr);
1400 csr = musb_readw(epio, MUSB_RXCSR);
1401 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1402 musb_writew(epio, MUSB_RXCSR, csr);
1403 musb_writew(epio, MUSB_RXCSR, csr);
1406 /* re-enable interrupt */
1407 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1408 spin_unlock_irqrestore(&musb->lock, flags);
1411 static const struct usb_ep_ops musb_ep_ops = {
1412 .enable = musb_gadget_enable,
1413 .disable = musb_gadget_disable,
1414 .alloc_request = musb_alloc_request,
1415 .free_request = musb_free_request,
1416 .queue = musb_gadget_queue,
1417 .dequeue = musb_gadget_dequeue,
1418 .set_halt = musb_gadget_set_halt,
1419 .set_wedge = musb_gadget_set_wedge,
1420 .fifo_status = musb_gadget_fifo_status,
1421 .fifo_flush = musb_gadget_fifo_flush
1424 /* ----------------------------------------------------------------------- */
1426 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1428 struct musb *musb = gadget_to_musb(gadget);
1430 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1433 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1435 struct musb *musb = gadget_to_musb(gadget);
1436 void __iomem *mregs = musb->mregs;
1437 unsigned long flags;
1438 int status = -EINVAL;
1442 spin_lock_irqsave(&musb->lock, flags);
1444 switch (musb->xceiv->state) {
1445 case OTG_STATE_B_PERIPHERAL:
1446 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1447 * that's part of the standard usb 1.1 state machine, and
1448 * doesn't affect OTG transitions.
1450 if (musb->may_wakeup && musb->is_suspended)
1453 case OTG_STATE_B_IDLE:
1454 /* Start SRP ... OTG not required. */
1455 devctl = musb_readb(mregs, MUSB_DEVCTL);
1456 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1457 devctl |= MUSB_DEVCTL_SESSION;
1458 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1459 devctl = musb_readb(mregs, MUSB_DEVCTL);
1461 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1462 devctl = musb_readb(mregs, MUSB_DEVCTL);
1467 while (devctl & MUSB_DEVCTL_SESSION) {
1468 devctl = musb_readb(mregs, MUSB_DEVCTL);
1473 /* Block idling for at least 1s */
1474 musb_platform_try_idle(musb,
1475 jiffies + msecs_to_jiffies(1 * HZ));
1480 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1486 power = musb_readb(mregs, MUSB_POWER);
1487 power |= MUSB_POWER_RESUME;
1488 musb_writeb(mregs, MUSB_POWER, power);
1489 DBG(2, "issue wakeup\n");
1491 /* FIXME do this next chunk in a timer callback, no udelay */
1494 power = musb_readb(mregs, MUSB_POWER);
1495 power &= ~MUSB_POWER_RESUME;
1496 musb_writeb(mregs, MUSB_POWER, power);
1498 spin_unlock_irqrestore(&musb->lock, flags);
1503 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1505 struct musb *musb = gadget_to_musb(gadget);
1507 musb->is_self_powered = !!is_selfpowered;
1511 static void musb_pullup(struct musb *musb, int is_on)
1515 power = musb_readb(musb->mregs, MUSB_POWER);
1517 power |= MUSB_POWER_SOFTCONN;
1519 power &= ~MUSB_POWER_SOFTCONN;
1521 /* FIXME if on, HdrcStart; if off, HdrcStop */
1523 DBG(3, "gadget %s D+ pullup %s\n",
1524 musb->gadget_driver->function, is_on ? "on" : "off");
1525 musb_writeb(musb->mregs, MUSB_POWER, power);
1529 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1531 DBG(2, "<= %s =>\n", __func__);
1534 * FIXME iff driver's softconnect flag is set (as it is during probe,
1535 * though that can clear it), just musb_pullup().
1542 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1544 struct musb *musb = gadget_to_musb(gadget);
1546 if (!musb->xceiv->set_power)
1548 return otg_set_power(musb->xceiv, mA);
1551 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1553 struct musb *musb = gadget_to_musb(gadget);
1554 unsigned long flags;
1558 /* NOTE: this assumes we are sensing vbus; we'd rather
1559 * not pullup unless the B-session is active.
1561 spin_lock_irqsave(&musb->lock, flags);
1562 if (is_on != musb->softconnect) {
1563 musb->softconnect = is_on;
1564 musb_pullup(musb, is_on);
1566 spin_unlock_irqrestore(&musb->lock, flags);
1570 static const struct usb_gadget_ops musb_gadget_operations = {
1571 .get_frame = musb_gadget_get_frame,
1572 .wakeup = musb_gadget_wakeup,
1573 .set_selfpowered = musb_gadget_set_self_powered,
1574 /* .vbus_session = musb_gadget_vbus_session, */
1575 .vbus_draw = musb_gadget_vbus_draw,
1576 .pullup = musb_gadget_pullup,
1579 /* ----------------------------------------------------------------------- */
1583 /* Only this registration code "knows" the rule (from USB standards)
1584 * about there being only one external upstream port. It assumes
1585 * all peripheral ports are external...
1587 static struct musb *the_gadget;
1589 static void musb_gadget_release(struct device *dev)
1591 /* kref_put(WHAT) */
1592 dev_dbg(dev, "%s\n", __func__);
1597 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1599 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1601 memset(ep, 0, sizeof *ep);
1603 ep->current_epnum = epnum;
1608 INIT_LIST_HEAD(&ep->req_list);
1610 sprintf(ep->name, "ep%d%s", epnum,
1611 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1612 is_in ? "in" : "out"));
1613 ep->end_point.name = ep->name;
1614 INIT_LIST_HEAD(&ep->end_point.ep_list);
1616 ep->end_point.maxpacket = 64;
1617 ep->end_point.ops = &musb_g_ep0_ops;
1618 musb->g.ep0 = &ep->end_point;
1621 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1623 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1624 ep->end_point.ops = &musb_ep_ops;
1625 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1630 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1631 * to the rest of the driver state.
1633 static inline void __init musb_g_init_endpoints(struct musb *musb)
1636 struct musb_hw_ep *hw_ep;
1639 /* intialize endpoint list just once */
1640 INIT_LIST_HEAD(&(musb->g.ep_list));
1642 for (epnum = 0, hw_ep = musb->endpoints;
1643 epnum < musb->nr_endpoints;
1645 if (hw_ep->is_shared_fifo /* || !epnum */) {
1646 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1649 if (hw_ep->max_packet_sz_tx) {
1650 init_peripheral_ep(musb, &hw_ep->ep_in,
1654 if (hw_ep->max_packet_sz_rx) {
1655 init_peripheral_ep(musb, &hw_ep->ep_out,
1663 /* called once during driver setup to initialize and link into
1664 * the driver model; memory is zeroed.
1666 int __init musb_gadget_setup(struct musb *musb)
1670 /* REVISIT minor race: if (erroneously) setting up two
1671 * musb peripherals at the same time, only the bus lock
1678 musb->g.ops = &musb_gadget_operations;
1679 musb->g.is_dualspeed = 1;
1680 musb->g.speed = USB_SPEED_UNKNOWN;
1682 /* this "gadget" abstracts/virtualizes the controller */
1683 dev_set_name(&musb->g.dev, "gadget");
1684 musb->g.dev.parent = musb->controller;
1685 musb->g.dev.dma_mask = musb->controller->dma_mask;
1686 musb->g.dev.release = musb_gadget_release;
1687 musb->g.name = musb_driver_name;
1689 if (is_otg_enabled(musb))
1692 musb_g_init_endpoints(musb);
1694 musb->is_active = 0;
1695 musb_platform_try_idle(musb, 0);
1697 status = device_register(&musb->g.dev);
1703 void musb_gadget_cleanup(struct musb *musb)
1705 if (musb != the_gadget)
1708 device_unregister(&musb->g.dev);
1713 * Register the gadget driver. Used by gadget drivers when
1714 * registering themselves with the controller.
1716 * -EINVAL something went wrong (not driver)
1717 * -EBUSY another gadget is already using the controller
1718 * -ENOMEM no memeory to perform the operation
1720 * @param driver the gadget driver
1721 * @param bind the driver's bind function
1722 * @return <0 if error, 0 if everything is fine
1724 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1725 int (*bind)(struct usb_gadget *))
1728 unsigned long flags;
1729 struct musb *musb = the_gadget;
1732 || driver->speed != USB_SPEED_HIGH
1733 || !bind || !driver->setup)
1736 /* driver must be initialized to support peripheral mode */
1738 DBG(1, "%s, no dev??\n", __func__);
1742 DBG(3, "registering driver %s\n", driver->function);
1743 spin_lock_irqsave(&musb->lock, flags);
1745 if (musb->gadget_driver) {
1746 DBG(1, "%s is already bound to %s\n",
1748 musb->gadget_driver->driver.name);
1751 musb->gadget_driver = driver;
1752 musb->g.dev.driver = &driver->driver;
1753 driver->driver.bus = NULL;
1754 musb->softconnect = 1;
1758 spin_unlock_irqrestore(&musb->lock, flags);
1761 retval = bind(&musb->g);
1763 DBG(3, "bind to driver %s failed --> %d\n",
1764 driver->driver.name, retval);
1765 musb->gadget_driver = NULL;
1766 musb->g.dev.driver = NULL;
1769 spin_lock_irqsave(&musb->lock, flags);
1771 otg_set_peripheral(musb->xceiv, &musb->g);
1772 musb->xceiv->state = OTG_STATE_B_IDLE;
1773 musb->is_active = 1;
1775 /* FIXME this ignores the softconnect flag. Drivers are
1776 * allowed hold the peripheral inactive until for example
1777 * userspace hooks up printer hardware or DSP codecs, so
1778 * hosts only see fully functional devices.
1781 if (!is_otg_enabled(musb))
1784 otg_set_peripheral(musb->xceiv, &musb->g);
1786 spin_unlock_irqrestore(&musb->lock, flags);
1788 if (is_otg_enabled(musb)) {
1789 DBG(3, "OTG startup...\n");
1791 /* REVISIT: funcall to other code, which also
1792 * handles power budgeting ... this way also
1793 * ensures HdrcStart is indirectly called.
1795 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1797 DBG(1, "add_hcd failed, %d\n", retval);
1798 spin_lock_irqsave(&musb->lock, flags);
1799 otg_set_peripheral(musb->xceiv, NULL);
1800 musb->gadget_driver = NULL;
1801 musb->g.dev.driver = NULL;
1802 spin_unlock_irqrestore(&musb->lock, flags);
1809 EXPORT_SYMBOL(usb_gadget_probe_driver);
1811 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1814 struct musb_hw_ep *hw_ep;
1816 /* don't disconnect if it's not connected */
1817 if (musb->g.speed == USB_SPEED_UNKNOWN)
1820 musb->g.speed = USB_SPEED_UNKNOWN;
1822 /* deactivate the hardware */
1823 if (musb->softconnect) {
1824 musb->softconnect = 0;
1825 musb_pullup(musb, 0);
1829 /* killing any outstanding requests will quiesce the driver;
1830 * then report disconnect
1833 for (i = 0, hw_ep = musb->endpoints;
1834 i < musb->nr_endpoints;
1836 musb_ep_select(musb->mregs, i);
1837 if (hw_ep->is_shared_fifo /* || !epnum */) {
1838 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1840 if (hw_ep->max_packet_sz_tx)
1841 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1842 if (hw_ep->max_packet_sz_rx)
1843 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1847 spin_unlock(&musb->lock);
1848 driver->disconnect(&musb->g);
1849 spin_lock(&musb->lock);
1854 * Unregister the gadget driver. Used by gadget drivers when
1855 * unregistering themselves from the controller.
1857 * @param driver the gadget driver to unregister
1859 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1861 unsigned long flags;
1863 struct musb *musb = the_gadget;
1865 if (!driver || !driver->unbind || !musb)
1868 /* REVISIT always use otg_set_peripheral() here too;
1869 * this needs to shut down the OTG engine.
1872 spin_lock_irqsave(&musb->lock, flags);
1874 #ifdef CONFIG_USB_MUSB_OTG
1875 musb_hnp_stop(musb);
1878 if (musb->gadget_driver == driver) {
1880 (void) musb_gadget_vbus_draw(&musb->g, 0);
1882 musb->xceiv->state = OTG_STATE_UNDEFINED;
1883 stop_activity(musb, driver);
1884 otg_set_peripheral(musb->xceiv, NULL);
1886 DBG(3, "unregistering driver %s\n", driver->function);
1887 spin_unlock_irqrestore(&musb->lock, flags);
1888 driver->unbind(&musb->g);
1889 spin_lock_irqsave(&musb->lock, flags);
1891 musb->gadget_driver = NULL;
1892 musb->g.dev.driver = NULL;
1894 musb->is_active = 0;
1895 musb_platform_try_idle(musb, 0);
1898 spin_unlock_irqrestore(&musb->lock, flags);
1900 if (is_otg_enabled(musb) && retval == 0) {
1901 usb_remove_hcd(musb_to_hcd(musb));
1902 /* FIXME we need to be able to register another
1903 * gadget driver here and have everything work;
1904 * that currently misbehaves.
1910 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1913 /* ----------------------------------------------------------------------- */
1915 /* lifecycle operations called through plat_uds.c */
1917 void musb_g_resume(struct musb *musb)
1919 musb->is_suspended = 0;
1920 switch (musb->xceiv->state) {
1921 case OTG_STATE_B_IDLE:
1923 case OTG_STATE_B_WAIT_ACON:
1924 case OTG_STATE_B_PERIPHERAL:
1925 musb->is_active = 1;
1926 if (musb->gadget_driver && musb->gadget_driver->resume) {
1927 spin_unlock(&musb->lock);
1928 musb->gadget_driver->resume(&musb->g);
1929 spin_lock(&musb->lock);
1933 WARNING("unhandled RESUME transition (%s)\n",
1934 otg_state_string(musb));
1938 /* called when SOF packets stop for 3+ msec */
1939 void musb_g_suspend(struct musb *musb)
1943 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1944 DBG(3, "devctl %02x\n", devctl);
1946 switch (musb->xceiv->state) {
1947 case OTG_STATE_B_IDLE:
1948 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1949 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1951 case OTG_STATE_B_PERIPHERAL:
1952 musb->is_suspended = 1;
1953 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1954 spin_unlock(&musb->lock);
1955 musb->gadget_driver->suspend(&musb->g);
1956 spin_lock(&musb->lock);
1960 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1961 * A_PERIPHERAL may need care too
1963 WARNING("unhandled SUSPEND transition (%s)\n",
1964 otg_state_string(musb));
1968 /* Called during SRP */
1969 void musb_g_wakeup(struct musb *musb)
1971 musb_gadget_wakeup(&musb->g);
1974 /* called when VBUS drops below session threshold, and in other cases */
1975 void musb_g_disconnect(struct musb *musb)
1977 void __iomem *mregs = musb->mregs;
1978 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1980 DBG(3, "devctl %02x\n", devctl);
1983 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1985 /* don't draw vbus until new b-default session */
1986 (void) musb_gadget_vbus_draw(&musb->g, 0);
1988 musb->g.speed = USB_SPEED_UNKNOWN;
1989 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1990 spin_unlock(&musb->lock);
1991 musb->gadget_driver->disconnect(&musb->g);
1992 spin_lock(&musb->lock);
1995 switch (musb->xceiv->state) {
1997 #ifdef CONFIG_USB_MUSB_OTG
1998 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1999 otg_state_string(musb));
2000 musb->xceiv->state = OTG_STATE_A_IDLE;
2001 MUSB_HST_MODE(musb);
2003 case OTG_STATE_A_PERIPHERAL:
2004 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2005 MUSB_HST_MODE(musb);
2007 case OTG_STATE_B_WAIT_ACON:
2008 case OTG_STATE_B_HOST:
2010 case OTG_STATE_B_PERIPHERAL:
2011 case OTG_STATE_B_IDLE:
2012 musb->xceiv->state = OTG_STATE_B_IDLE;
2014 case OTG_STATE_B_SRP_INIT:
2018 musb->is_active = 0;
2021 void musb_g_reset(struct musb *musb)
2022 __releases(musb->lock)
2023 __acquires(musb->lock)
2025 void __iomem *mbase = musb->mregs;
2026 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2029 DBG(3, "<== %s addr=%x driver '%s'\n",
2030 (devctl & MUSB_DEVCTL_BDEVICE)
2031 ? "B-Device" : "A-Device",
2032 musb_readb(mbase, MUSB_FADDR),
2034 ? musb->gadget_driver->driver.name
2038 /* report disconnect, if we didn't already (flushing EP state) */
2039 if (musb->g.speed != USB_SPEED_UNKNOWN)
2040 musb_g_disconnect(musb);
2043 else if (devctl & MUSB_DEVCTL_HR)
2044 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2047 /* what speed did we negotiate? */
2048 power = musb_readb(mbase, MUSB_POWER);
2049 musb->g.speed = (power & MUSB_POWER_HSMODE)
2050 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2052 /* start in USB_STATE_DEFAULT */
2053 musb->is_active = 1;
2054 musb->is_suspended = 0;
2055 MUSB_DEV_MODE(musb);
2057 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2059 musb->may_wakeup = 0;
2060 musb->g.b_hnp_enable = 0;
2061 musb->g.a_alt_hnp_support = 0;
2062 musb->g.a_hnp_support = 0;
2064 /* Normal reset, as B-Device;
2065 * or else after HNP, as A-Device
2067 if (devctl & MUSB_DEVCTL_BDEVICE) {
2068 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2069 musb->g.is_a_peripheral = 0;
2070 } else if (is_otg_enabled(musb)) {
2071 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2072 musb->g.is_a_peripheral = 1;
2076 /* start with default limits on VBUS power draw */
2077 (void) musb_gadget_vbus_draw(&musb->g,
2078 is_otg_enabled(musb) ? 8 : 100);