2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
47 #include "musb_core.h"
50 /* MUSB PERIPHERAL status 3-mar-2006:
52 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
55 * + remote wakeup to Linux hosts work, but saw USBCV failures;
56 * in one test run (operator error?)
57 * + endpoint halt tests -- in both usbtest and usbcv -- seem
58 * to break when dma is enabled ... is something wrongly
61 * - Mass storage behaved ok when last tested. Network traffic patterns
62 * (with lots of short transfers etc) need retesting; they turn up the
63 * worst cases of the DMA, since short packets are typical but are not
67 * + both pio and dma behave in with network and g_zero tests
68 * + no cppi throughput issues other than no-hw-queueing
69 * + failed with FLAT_REG (DaVinci)
70 * + seems to behave with double buffering, PIO -and- CPPI
71 * + with gadgetfs + AIO, requests got lost?
74 * + both pio and dma behave in with network and g_zero tests
75 * + dma is slow in typical case (short_not_ok is clear)
76 * + double buffering ok with PIO
77 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
78 * + request lossage observed with gadgetfs
80 * - ISO not tested ... might work, but only weakly isochronous
82 * - Gadget driver disabling of softconnect during bind() is ignored; so
83 * drivers can't hold off host requests until userspace is ready.
84 * (Workaround: they can turn it off later.)
86 * - PORTABILITY (assumes PIO works):
87 * + DaVinci, basically works with cppi dma
88 * + OMAP 2430, ditto with mentor dma
89 * + TUSB 6010, platform-specific dma in the works
92 /* ----------------------------------------------------------------------- */
95 * Immediately complete a request.
97 * @param request the request to complete
98 * @param status the status to complete the request with
99 * Context: controller locked, IRQs blocked.
101 void musb_g_giveback(
103 struct usb_request *request,
105 __releases(ep->musb->lock)
106 __acquires(ep->musb->lock)
108 struct musb_request *req;
112 req = to_musb_request(request);
114 list_del(&request->list);
115 if (req->request.status == -EINPROGRESS)
116 req->request.status = status;
120 spin_unlock(&musb->lock);
121 if (is_dma_capable()) {
123 dma_unmap_single(musb->controller,
129 req->request.dma = DMA_ADDR_INVALID;
131 } else if (req->request.dma != DMA_ADDR_INVALID)
132 dma_sync_single_for_cpu(musb->controller,
139 if (request->status == 0)
140 DBG(5, "%s done request %p, %d/%d\n",
141 ep->end_point.name, request,
142 req->request.actual, req->request.length);
144 DBG(2, "%s request %p, %d/%d fault %d\n",
145 ep->end_point.name, request,
146 req->request.actual, req->request.length,
148 req->request.complete(&req->ep->end_point, &req->request);
149 spin_lock(&musb->lock);
153 /* ----------------------------------------------------------------------- */
156 * Abort requests queued to an endpoint using the status. Synchronous.
157 * caller locked controller and blocked irqs, and selected this ep.
159 static void nuke(struct musb_ep *ep, const int status)
161 struct musb_request *req = NULL;
162 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
166 if (is_dma_capable() && ep->dma) {
167 struct dma_controller *c = ep->musb->dma_controller;
172 * The programming guide says that we must not clear
173 * the DMAMODE bit before DMAENAB, so we only
174 * clear it in the second write...
176 musb_writew(epio, MUSB_TXCSR,
177 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
178 musb_writew(epio, MUSB_TXCSR,
179 0 | MUSB_TXCSR_FLUSHFIFO);
181 musb_writew(epio, MUSB_RXCSR,
182 0 | MUSB_RXCSR_FLUSHFIFO);
183 musb_writew(epio, MUSB_RXCSR,
184 0 | MUSB_RXCSR_FLUSHFIFO);
187 value = c->channel_abort(ep->dma);
188 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
189 c->channel_release(ep->dma);
193 while (!list_empty(&(ep->req_list))) {
194 req = container_of(ep->req_list.next, struct musb_request,
196 musb_g_giveback(ep, &req->request, status);
200 /* ----------------------------------------------------------------------- */
202 /* Data transfers - pure PIO, pure DMA, or mixed mode */
205 * This assumes the separate CPPI engine is responding to DMA requests
206 * from the usb core ... sequenced a bit differently from mentor dma.
209 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
211 if (can_bulk_split(musb, ep->type))
212 return ep->hw_ep->max_packet_sz_tx;
214 return ep->packet_sz;
218 #ifdef CONFIG_USB_INVENTRA_DMA
220 /* Peripheral tx (IN) using Mentor DMA works as follows:
221 Only mode 0 is used for transfers <= wPktSize,
222 mode 1 is used for larger transfers,
224 One of the following happens:
225 - Host sends IN token which causes an endpoint interrupt
227 -> if DMA is currently busy, exit.
228 -> if queue is non-empty, txstate().
230 - Request is queued by the gadget driver.
231 -> if queue was previously empty, txstate()
236 | (data is transferred to the FIFO, then sent out when
237 | IN token(s) are recd from Host.
238 | -> DMA interrupt on completion
240 | -> stop DMA, ~DMAENAB,
241 | -> set TxPktRdy for last short pkt or zlp
242 | -> Complete Request
243 | -> Continue next request (call txstate)
244 |___________________________________|
246 * Non-Mentor DMA engines can of course work differently, such as by
247 * upleveling from irq-per-packet to irq-per-buffer.
253 * An endpoint is transmitting data. This can be called either from
254 * the IRQ routine or from ep.queue() to kickstart a request on an
257 * Context: controller locked, IRQs blocked, endpoint selected
259 static void txstate(struct musb *musb, struct musb_request *req)
261 u8 epnum = req->epnum;
262 struct musb_ep *musb_ep;
263 void __iomem *epio = musb->endpoints[epnum].regs;
264 struct usb_request *request;
265 u16 fifo_count = 0, csr;
270 /* we shouldn't get here while DMA is active ... but we do ... */
271 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
272 DBG(4, "dma pending...\n");
276 /* read TXCSR before */
277 csr = musb_readw(epio, MUSB_TXCSR);
279 request = &req->request;
280 fifo_count = min(max_ep_writesize(musb, musb_ep),
281 (int)(request->length - request->actual));
283 if (csr & MUSB_TXCSR_TXPKTRDY) {
284 DBG(5, "%s old packet still ready , txcsr %03x\n",
285 musb_ep->end_point.name, csr);
289 if (csr & MUSB_TXCSR_P_SENDSTALL) {
290 DBG(5, "%s stalling, txcsr %03x\n",
291 musb_ep->end_point.name, csr);
295 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
296 epnum, musb_ep->packet_sz, fifo_count,
299 #ifndef CONFIG_MUSB_PIO_ONLY
300 if (is_dma_capable() && musb_ep->dma) {
301 struct dma_controller *c = musb->dma_controller;
303 use_dma = (request->dma != DMA_ADDR_INVALID);
305 /* MUSB_TXCSR_P_ISO is still set correctly */
307 #ifdef CONFIG_USB_INVENTRA_DMA
311 /* setup DMA, then program endpoint CSR */
312 request_size = min_t(size_t, request->length,
313 musb_ep->dma->max_len);
314 if (request_size < musb_ep->packet_sz)
315 musb_ep->dma->desired_mode = 0;
317 musb_ep->dma->desired_mode = 1;
319 use_dma = use_dma && c->channel_program(
320 musb_ep->dma, musb_ep->packet_sz,
321 musb_ep->dma->desired_mode,
322 request->dma + request->actual, request_size);
324 if (musb_ep->dma->desired_mode == 0) {
326 * We must not clear the DMAMODE bit
327 * before the DMAENAB bit -- and the
328 * latter doesn't always get cleared
329 * before we get here...
331 csr &= ~(MUSB_TXCSR_AUTOSET
332 | MUSB_TXCSR_DMAENAB);
333 musb_writew(epio, MUSB_TXCSR, csr
334 | MUSB_TXCSR_P_WZC_BITS);
335 csr &= ~MUSB_TXCSR_DMAMODE;
336 csr |= (MUSB_TXCSR_DMAENAB |
338 /* against programming guide */
340 csr |= (MUSB_TXCSR_AUTOSET
345 csr &= ~MUSB_TXCSR_P_UNDERRUN;
346 musb_writew(epio, MUSB_TXCSR, csr);
350 #elif defined(CONFIG_USB_TI_CPPI_DMA)
351 /* program endpoint CSR first, then setup DMA */
352 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
353 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
355 musb_writew(epio, MUSB_TXCSR,
356 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
359 /* ensure writebuffer is empty */
360 csr = musb_readw(epio, MUSB_TXCSR);
362 /* NOTE host side sets DMAENAB later than this; both are
363 * OK since the transfer dma glue (between CPPI and Mentor
364 * fifos) just tells CPPI it could start. Data only moves
365 * to the USB TX fifo when both fifos are ready.
368 /* "mode" is irrelevant here; handle terminating ZLPs like
369 * PIO does, since the hardware RNDIS mode seems unreliable
370 * except for the last-packet-is-already-short case.
372 use_dma = use_dma && c->channel_program(
373 musb_ep->dma, musb_ep->packet_sz,
378 c->channel_release(musb_ep->dma);
380 csr &= ~MUSB_TXCSR_DMAENAB;
381 musb_writew(epio, MUSB_TXCSR, csr);
382 /* invariant: prequest->buf is non-null */
384 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
385 use_dma = use_dma && c->channel_program(
386 musb_ep->dma, musb_ep->packet_sz,
395 musb_write_fifo(musb_ep->hw_ep, fifo_count,
396 (u8 *) (request->buf + request->actual));
397 request->actual += fifo_count;
398 csr |= MUSB_TXCSR_TXPKTRDY;
399 csr &= ~MUSB_TXCSR_P_UNDERRUN;
400 musb_writew(epio, MUSB_TXCSR, csr);
403 /* host may already have the data when this message shows... */
404 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
405 musb_ep->end_point.name, use_dma ? "dma" : "pio",
406 request->actual, request->length,
407 musb_readw(epio, MUSB_TXCSR),
409 musb_readw(epio, MUSB_TXMAXP));
413 * FIFO state update (e.g. data ready).
414 * Called from IRQ, with controller locked.
416 void musb_g_tx(struct musb *musb, u8 epnum)
419 struct usb_request *request;
420 u8 __iomem *mbase = musb->mregs;
421 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
422 void __iomem *epio = musb->endpoints[epnum].regs;
423 struct dma_channel *dma;
425 musb_ep_select(mbase, epnum);
426 request = next_request(musb_ep);
428 csr = musb_readw(epio, MUSB_TXCSR);
429 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
431 dma = is_dma_capable() ? musb_ep->dma : NULL;
434 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
435 * probably rates reporting as a host error.
437 if (csr & MUSB_TXCSR_P_SENTSTALL) {
438 csr |= MUSB_TXCSR_P_WZC_BITS;
439 csr &= ~MUSB_TXCSR_P_SENTSTALL;
440 musb_writew(epio, MUSB_TXCSR, csr);
444 if (csr & MUSB_TXCSR_P_UNDERRUN) {
445 /* We NAKed, no big deal... little reason to care. */
446 csr |= MUSB_TXCSR_P_WZC_BITS;
447 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
448 musb_writew(epio, MUSB_TXCSR, csr);
449 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
452 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
454 * SHOULD NOT HAPPEN... has with CPPI though, after
455 * changing SENDSTALL (and other cases); harmless?
457 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
464 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
466 csr |= MUSB_TXCSR_P_WZC_BITS;
467 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
468 MUSB_TXCSR_TXPKTRDY);
469 musb_writew(epio, MUSB_TXCSR, csr);
470 /* Ensure writebuffer is empty. */
471 csr = musb_readw(epio, MUSB_TXCSR);
472 request->actual += musb_ep->dma->actual_len;
473 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
474 epnum, csr, musb_ep->dma->actual_len, request);
477 if (is_dma || request->actual == request->length) {
479 * First, maybe a terminating short packet. Some DMA
480 * engines might handle this by themselves.
482 if ((request->zero && request->length
483 && request->length % musb_ep->packet_sz == 0)
484 #ifdef CONFIG_USB_INVENTRA_DMA
485 || (is_dma && (!dma->desired_mode ||
487 (musb_ep->packet_sz - 1))))
491 * On DMA completion, FIFO may not be
494 if (csr & MUSB_TXCSR_TXPKTRDY)
497 DBG(4, "sending zero pkt\n");
498 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
499 | MUSB_TXCSR_TXPKTRDY);
503 /* ... or if not, then complete it. */
504 musb_g_giveback(musb_ep, request, 0);
507 * Kickstart next transfer if appropriate;
508 * the packet that just completed might not
509 * be transmitted for hours or days.
510 * REVISIT for double buffering...
511 * FIXME revisit for stalls too...
513 musb_ep_select(mbase, epnum);
514 csr = musb_readw(epio, MUSB_TXCSR);
515 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
518 request = musb_ep->desc ? next_request(musb_ep) : NULL;
520 DBG(4, "%s idle now\n",
521 musb_ep->end_point.name);
526 txstate(musb, to_musb_request(request));
530 /* ------------------------------------------------------------ */
532 #ifdef CONFIG_USB_INVENTRA_DMA
534 /* Peripheral rx (OUT) using Mentor DMA works as follows:
535 - Only mode 0 is used.
537 - Request is queued by the gadget class driver.
538 -> if queue was previously empty, rxstate()
540 - Host sends OUT token which causes an endpoint interrupt
542 | -> if request queued, call rxstate
544 | | -> DMA interrupt on completion
548 | | -> if data recd = max expected
549 | | by the request, or host
550 | | sent a short packet,
551 | | complete the request,
552 | | and start the next one.
553 | |_____________________________________|
554 | else just wait for the host
555 | to send the next OUT token.
556 |__________________________________________________|
558 * Non-Mentor DMA engines can of course work differently.
564 * Context: controller locked, IRQs blocked, endpoint selected
566 static void rxstate(struct musb *musb, struct musb_request *req)
568 const u8 epnum = req->epnum;
569 struct usb_request *request = &req->request;
570 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
571 void __iomem *epio = musb->endpoints[epnum].regs;
572 unsigned fifo_count = 0;
573 u16 len = musb_ep->packet_sz;
574 u16 csr = musb_readw(epio, MUSB_RXCSR);
576 /* We shouldn't get here while DMA is active, but we do... */
577 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
578 DBG(4, "DMA pending...\n");
582 if (csr & MUSB_RXCSR_P_SENDSTALL) {
583 DBG(5, "%s stalling, RXCSR %04x\n",
584 musb_ep->end_point.name, csr);
588 if (is_cppi_enabled() && musb_ep->dma) {
589 struct dma_controller *c = musb->dma_controller;
590 struct dma_channel *channel = musb_ep->dma;
592 /* NOTE: CPPI won't actually stop advancing the DMA
593 * queue after short packet transfers, so this is almost
594 * always going to run as IRQ-per-packet DMA so that
595 * faults will be handled correctly.
597 if (c->channel_program(channel,
599 !request->short_not_ok,
600 request->dma + request->actual,
601 request->length - request->actual)) {
603 /* make sure that if an rxpkt arrived after the irq,
604 * the cppi engine will be ready to take it as soon
607 csr &= ~(MUSB_RXCSR_AUTOCLEAR
608 | MUSB_RXCSR_DMAMODE);
609 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
610 musb_writew(epio, MUSB_RXCSR, csr);
615 if (csr & MUSB_RXCSR_RXPKTRDY) {
616 len = musb_readw(epio, MUSB_RXCOUNT);
617 if (request->actual < request->length) {
618 #ifdef CONFIG_USB_INVENTRA_DMA
619 if (is_dma_capable() && musb_ep->dma) {
620 struct dma_controller *c;
621 struct dma_channel *channel;
624 c = musb->dma_controller;
625 channel = musb_ep->dma;
627 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
628 * mode 0 only. So we do not get endpoint interrupts due to DMA
629 * completion. We only get interrupts from DMA controller.
631 * We could operate in DMA mode 1 if we knew the size of the tranfer
632 * in advance. For mass storage class, request->length = what the host
633 * sends, so that'd work. But for pretty much everything else,
634 * request->length is routinely more than what the host sends. For
635 * most these gadgets, end of is signified either by a short packet,
636 * or filling the last byte of the buffer. (Sending extra data in
637 * that last pckate should trigger an overflow fault.) But in mode 1,
638 * we don't get DMA completion interrrupt for short packets.
640 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
641 * to get endpoint interrupt on every DMA req, but that didn't seem
644 * REVISIT an updated g_file_storage can set req->short_not_ok, which
645 * then becomes usable as a runtime "use mode 1" hint...
648 csr |= MUSB_RXCSR_DMAENAB;
650 csr |= MUSB_RXCSR_AUTOCLEAR;
651 /* csr |= MUSB_RXCSR_DMAMODE; */
653 /* this special sequence (enabling and then
654 * disabling MUSB_RXCSR_DMAMODE) is required
655 * to get DMAReq to activate
657 musb_writew(epio, MUSB_RXCSR,
658 csr | MUSB_RXCSR_DMAMODE);
660 musb_writew(epio, MUSB_RXCSR, csr);
662 if (request->actual < request->length) {
663 int transfer_size = 0;
665 transfer_size = min(request->length,
670 if (transfer_size <= musb_ep->packet_sz)
671 musb_ep->dma->desired_mode = 0;
673 musb_ep->dma->desired_mode = 1;
675 use_dma = c->channel_program(
678 channel->desired_mode,
687 #endif /* Mentor's DMA */
689 fifo_count = request->length - request->actual;
690 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
691 musb_ep->end_point.name,
695 fifo_count = min_t(unsigned, len, fifo_count);
697 #ifdef CONFIG_USB_TUSB_OMAP_DMA
698 if (tusb_dma_omap() && musb_ep->dma) {
699 struct dma_controller *c = musb->dma_controller;
700 struct dma_channel *channel = musb_ep->dma;
701 u32 dma_addr = request->dma + request->actual;
704 ret = c->channel_program(channel,
706 channel->desired_mode,
714 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
715 (request->buf + request->actual));
716 request->actual += fifo_count;
718 /* REVISIT if we left anything in the fifo, flush
719 * it and report -EOVERFLOW
723 csr |= MUSB_RXCSR_P_WZC_BITS;
724 csr &= ~MUSB_RXCSR_RXPKTRDY;
725 musb_writew(epio, MUSB_RXCSR, csr);
729 /* reach the end or short packet detected */
730 if (request->actual == request->length || len < musb_ep->packet_sz)
731 musb_g_giveback(musb_ep, request, 0);
735 * Data ready for a request; called from IRQ
737 void musb_g_rx(struct musb *musb, u8 epnum)
740 struct usb_request *request;
741 void __iomem *mbase = musb->mregs;
742 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
743 void __iomem *epio = musb->endpoints[epnum].regs;
744 struct dma_channel *dma;
746 musb_ep_select(mbase, epnum);
748 request = next_request(musb_ep);
752 csr = musb_readw(epio, MUSB_RXCSR);
753 dma = is_dma_capable() ? musb_ep->dma : NULL;
755 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
756 csr, dma ? " (dma)" : "", request);
758 if (csr & MUSB_RXCSR_P_SENTSTALL) {
759 csr |= MUSB_RXCSR_P_WZC_BITS;
760 csr &= ~MUSB_RXCSR_P_SENTSTALL;
761 musb_writew(epio, MUSB_RXCSR, csr);
765 if (csr & MUSB_RXCSR_P_OVERRUN) {
766 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
767 csr &= ~MUSB_RXCSR_P_OVERRUN;
768 musb_writew(epio, MUSB_RXCSR, csr);
770 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
771 if (request && request->status == -EINPROGRESS)
772 request->status = -EOVERFLOW;
774 if (csr & MUSB_RXCSR_INCOMPRX) {
775 /* REVISIT not necessarily an error */
776 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
779 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
780 /* "should not happen"; likely RXPKTRDY pending for DMA */
781 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
782 "%s busy, csr %04x\n",
783 musb_ep->end_point.name, csr);
787 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
788 csr &= ~(MUSB_RXCSR_AUTOCLEAR
790 | MUSB_RXCSR_DMAMODE);
791 musb_writew(epio, MUSB_RXCSR,
792 MUSB_RXCSR_P_WZC_BITS | csr);
794 request->actual += musb_ep->dma->actual_len;
796 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
798 musb_readw(epio, MUSB_RXCSR),
799 musb_ep->dma->actual_len, request);
801 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
802 /* Autoclear doesn't clear RxPktRdy for short packets */
803 if ((dma->desired_mode == 0)
805 & (musb_ep->packet_sz - 1))) {
807 csr &= ~MUSB_RXCSR_RXPKTRDY;
808 musb_writew(epio, MUSB_RXCSR, csr);
811 /* incomplete, and not short? wait for next IN packet */
812 if ((request->actual < request->length)
813 && (musb_ep->dma->actual_len
814 == musb_ep->packet_sz))
817 musb_g_giveback(musb_ep, request, 0);
819 request = next_request(musb_ep);
824 /* analyze request if the ep is hot */
826 rxstate(musb, to_musb_request(request));
828 DBG(3, "packet waiting for %s%s request\n",
829 musb_ep->desc ? "" : "inactive ",
830 musb_ep->end_point.name);
834 /* ------------------------------------------------------------ */
836 static int musb_gadget_enable(struct usb_ep *ep,
837 const struct usb_endpoint_descriptor *desc)
840 struct musb_ep *musb_ep;
841 struct musb_hw_ep *hw_ep;
848 int status = -EINVAL;
853 musb_ep = to_musb_ep(ep);
854 hw_ep = musb_ep->hw_ep;
856 musb = musb_ep->musb;
858 epnum = musb_ep->current_epnum;
860 spin_lock_irqsave(&musb->lock, flags);
866 musb_ep->type = usb_endpoint_type(desc);
868 /* check direction and (later) maxpacket size against endpoint */
869 if (usb_endpoint_num(desc) != epnum)
872 /* REVISIT this rules out high bandwidth periodic transfers */
873 tmp = le16_to_cpu(desc->wMaxPacketSize);
876 musb_ep->packet_sz = tmp;
878 /* enable the interrupts for the endpoint, set the endpoint
879 * packet size (or fail), set the mode, clear the fifo
881 musb_ep_select(mbase, epnum);
882 if (usb_endpoint_dir_in(desc)) {
883 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
885 if (hw_ep->is_shared_fifo)
889 if (tmp > hw_ep->max_packet_sz_tx)
892 int_txe |= (1 << epnum);
893 musb_writew(mbase, MUSB_INTRTXE, int_txe);
895 /* REVISIT if can_bulk_split(), use by updating "tmp";
896 * likewise high bandwidth periodic tx
898 musb_writew(regs, MUSB_TXMAXP, tmp);
900 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
901 if (musb_readw(regs, MUSB_TXCSR)
902 & MUSB_TXCSR_FIFONOTEMPTY)
903 csr |= MUSB_TXCSR_FLUSHFIFO;
904 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
905 csr |= MUSB_TXCSR_P_ISO;
907 /* set twice in case of double buffering */
908 musb_writew(regs, MUSB_TXCSR, csr);
909 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
910 musb_writew(regs, MUSB_TXCSR, csr);
913 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
915 if (hw_ep->is_shared_fifo)
919 if (tmp > hw_ep->max_packet_sz_rx)
922 int_rxe |= (1 << epnum);
923 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
925 /* REVISIT if can_bulk_combine() use by updating "tmp"
926 * likewise high bandwidth periodic rx
928 musb_writew(regs, MUSB_RXMAXP, tmp);
930 /* force shared fifo to OUT-only mode */
931 if (hw_ep->is_shared_fifo) {
932 csr = musb_readw(regs, MUSB_TXCSR);
933 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
934 musb_writew(regs, MUSB_TXCSR, csr);
937 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
938 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
939 csr |= MUSB_RXCSR_P_ISO;
940 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
941 csr |= MUSB_RXCSR_DISNYET;
943 /* set twice in case of double buffering */
944 musb_writew(regs, MUSB_RXCSR, csr);
945 musb_writew(regs, MUSB_RXCSR, csr);
948 /* NOTE: all the I/O code _should_ work fine without DMA, in case
949 * for some reason you run out of channels here.
951 if (is_dma_capable() && musb->dma_controller) {
952 struct dma_controller *c = musb->dma_controller;
954 musb_ep->dma = c->channel_alloc(c, hw_ep,
955 (desc->bEndpointAddress & USB_DIR_IN));
959 musb_ep->desc = desc;
964 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
965 musb_driver_name, musb_ep->end_point.name,
966 ({ char *s; switch (musb_ep->type) {
967 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
968 case USB_ENDPOINT_XFER_INT: s = "int"; break;
969 default: s = "iso"; break;
971 musb_ep->is_in ? "IN" : "OUT",
972 musb_ep->dma ? "dma, " : "",
975 schedule_work(&musb->irq_work);
978 spin_unlock_irqrestore(&musb->lock, flags);
983 * Disable an endpoint flushing all requests queued.
985 static int musb_gadget_disable(struct usb_ep *ep)
990 struct musb_ep *musb_ep;
994 musb_ep = to_musb_ep(ep);
995 musb = musb_ep->musb;
996 epnum = musb_ep->current_epnum;
997 epio = musb->endpoints[epnum].regs;
999 spin_lock_irqsave(&musb->lock, flags);
1000 musb_ep_select(musb->mregs, epnum);
1002 /* zero the endpoint sizes */
1003 if (musb_ep->is_in) {
1004 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1005 int_txe &= ~(1 << epnum);
1006 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1007 musb_writew(epio, MUSB_TXMAXP, 0);
1009 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1010 int_rxe &= ~(1 << epnum);
1011 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1012 musb_writew(epio, MUSB_RXMAXP, 0);
1015 musb_ep->desc = NULL;
1017 /* abort all pending DMA and requests */
1018 nuke(musb_ep, -ESHUTDOWN);
1020 schedule_work(&musb->irq_work);
1022 spin_unlock_irqrestore(&(musb->lock), flags);
1024 DBG(2, "%s\n", musb_ep->end_point.name);
1030 * Allocate a request for an endpoint.
1031 * Reused by ep0 code.
1033 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1035 struct musb_ep *musb_ep = to_musb_ep(ep);
1036 struct musb_request *request = NULL;
1038 request = kzalloc(sizeof *request, gfp_flags);
1040 INIT_LIST_HEAD(&request->request.list);
1041 request->request.dma = DMA_ADDR_INVALID;
1042 request->epnum = musb_ep->current_epnum;
1043 request->ep = musb_ep;
1046 return &request->request;
1051 * Reused by ep0 code.
1053 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1055 kfree(to_musb_request(req));
1058 static LIST_HEAD(buffers);
1060 struct free_record {
1061 struct list_head list;
1068 * Context: controller locked, IRQs blocked.
1070 static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1072 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1073 req->tx ? "TX/IN" : "RX/OUT",
1074 &req->request, req->request.length, req->epnum);
1076 musb_ep_select(musb->mregs, req->epnum);
1083 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1086 struct musb_ep *musb_ep;
1087 struct musb_request *request;
1090 unsigned long lockflags;
1097 musb_ep = to_musb_ep(ep);
1098 musb = musb_ep->musb;
1100 request = to_musb_request(req);
1101 request->musb = musb;
1103 if (request->ep != musb_ep)
1106 DBG(4, "<== to %s request=%p\n", ep->name, req);
1108 /* request is mine now... */
1109 request->request.actual = 0;
1110 request->request.status = -EINPROGRESS;
1111 request->epnum = musb_ep->current_epnum;
1112 request->tx = musb_ep->is_in;
1114 if (is_dma_capable() && musb_ep->dma) {
1115 if (request->request.dma == DMA_ADDR_INVALID) {
1116 request->request.dma = dma_map_single(
1118 request->request.buf,
1119 request->request.length,
1123 request->mapped = 1;
1125 dma_sync_single_for_device(musb->controller,
1126 request->request.dma,
1127 request->request.length,
1131 request->mapped = 0;
1133 } else if (!req->buf) {
1136 request->mapped = 0;
1138 spin_lock_irqsave(&musb->lock, lockflags);
1140 /* don't queue if the ep is down */
1141 if (!musb_ep->desc) {
1142 DBG(4, "req %p queued to %s while ep %s\n",
1143 req, ep->name, "disabled");
1144 status = -ESHUTDOWN;
1148 /* add request to the list */
1149 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1151 /* it this is the head of the queue, start i/o ... */
1152 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1153 musb_ep_restart(musb, request);
1156 spin_unlock_irqrestore(&musb->lock, lockflags);
1160 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1162 struct musb_ep *musb_ep = to_musb_ep(ep);
1163 struct usb_request *r;
1164 unsigned long flags;
1166 struct musb *musb = musb_ep->musb;
1168 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1171 spin_lock_irqsave(&musb->lock, flags);
1173 list_for_each_entry(r, &musb_ep->req_list, list) {
1178 DBG(3, "request %p not queued to %s\n", request, ep->name);
1183 /* if the hardware doesn't have the request, easy ... */
1184 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1185 musb_g_giveback(musb_ep, request, -ECONNRESET);
1187 /* ... else abort the dma transfer ... */
1188 else if (is_dma_capable() && musb_ep->dma) {
1189 struct dma_controller *c = musb->dma_controller;
1191 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1192 if (c->channel_abort)
1193 status = c->channel_abort(musb_ep->dma);
1197 musb_g_giveback(musb_ep, request, -ECONNRESET);
1199 /* NOTE: by sticking to easily tested hardware/driver states,
1200 * we leave counting of in-flight packets imprecise.
1202 musb_g_giveback(musb_ep, request, -ECONNRESET);
1206 spin_unlock_irqrestore(&musb->lock, flags);
1211 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1212 * data but will queue requests.
1214 * exported to ep0 code
1216 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1218 struct musb_ep *musb_ep = to_musb_ep(ep);
1219 u8 epnum = musb_ep->current_epnum;
1220 struct musb *musb = musb_ep->musb;
1221 void __iomem *epio = musb->endpoints[epnum].regs;
1222 void __iomem *mbase;
1223 unsigned long flags;
1225 struct musb_request *request;
1230 mbase = musb->mregs;
1232 spin_lock_irqsave(&musb->lock, flags);
1234 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1239 musb_ep_select(mbase, epnum);
1241 request = to_musb_request(next_request(musb_ep));
1244 DBG(3, "request in progress, cannot halt %s\n",
1249 /* Cannot portably stall with non-empty FIFO */
1250 if (musb_ep->is_in) {
1251 csr = musb_readw(epio, MUSB_TXCSR);
1252 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1253 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1259 musb_ep->wedged = 0;
1261 /* set/clear the stall and toggle bits */
1262 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1263 if (musb_ep->is_in) {
1264 csr = musb_readw(epio, MUSB_TXCSR);
1265 csr |= MUSB_TXCSR_P_WZC_BITS
1266 | MUSB_TXCSR_CLRDATATOG;
1268 csr |= MUSB_TXCSR_P_SENDSTALL;
1270 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1271 | MUSB_TXCSR_P_SENTSTALL);
1272 csr &= ~MUSB_TXCSR_TXPKTRDY;
1273 musb_writew(epio, MUSB_TXCSR, csr);
1275 csr = musb_readw(epio, MUSB_RXCSR);
1276 csr |= MUSB_RXCSR_P_WZC_BITS
1277 | MUSB_RXCSR_FLUSHFIFO
1278 | MUSB_RXCSR_CLRDATATOG;
1280 csr |= MUSB_RXCSR_P_SENDSTALL;
1282 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1283 | MUSB_RXCSR_P_SENTSTALL);
1284 musb_writew(epio, MUSB_RXCSR, csr);
1287 /* maybe start the first request in the queue */
1288 if (!musb_ep->busy && !value && request) {
1289 DBG(3, "restarting the request\n");
1290 musb_ep_restart(musb, request);
1294 spin_unlock_irqrestore(&musb->lock, flags);
1299 * Sets the halt feature with the clear requests ignored
1301 static int musb_gadget_set_wedge(struct usb_ep *ep)
1303 struct musb_ep *musb_ep = to_musb_ep(ep);
1308 musb_ep->wedged = 1;
1310 return usb_ep_set_halt(ep);
1313 static int musb_gadget_fifo_status(struct usb_ep *ep)
1315 struct musb_ep *musb_ep = to_musb_ep(ep);
1316 void __iomem *epio = musb_ep->hw_ep->regs;
1317 int retval = -EINVAL;
1319 if (musb_ep->desc && !musb_ep->is_in) {
1320 struct musb *musb = musb_ep->musb;
1321 int epnum = musb_ep->current_epnum;
1322 void __iomem *mbase = musb->mregs;
1323 unsigned long flags;
1325 spin_lock_irqsave(&musb->lock, flags);
1327 musb_ep_select(mbase, epnum);
1328 /* FIXME return zero unless RXPKTRDY is set */
1329 retval = musb_readw(epio, MUSB_RXCOUNT);
1331 spin_unlock_irqrestore(&musb->lock, flags);
1336 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1338 struct musb_ep *musb_ep = to_musb_ep(ep);
1339 struct musb *musb = musb_ep->musb;
1340 u8 epnum = musb_ep->current_epnum;
1341 void __iomem *epio = musb->endpoints[epnum].regs;
1342 void __iomem *mbase;
1343 unsigned long flags;
1346 mbase = musb->mregs;
1348 spin_lock_irqsave(&musb->lock, flags);
1349 musb_ep_select(mbase, (u8) epnum);
1351 /* disable interrupts */
1352 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1353 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1355 if (musb_ep->is_in) {
1356 csr = musb_readw(epio, MUSB_TXCSR);
1357 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1358 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1359 musb_writew(epio, MUSB_TXCSR, csr);
1360 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1361 musb_writew(epio, MUSB_TXCSR, csr);
1364 csr = musb_readw(epio, MUSB_RXCSR);
1365 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1366 musb_writew(epio, MUSB_RXCSR, csr);
1367 musb_writew(epio, MUSB_RXCSR, csr);
1370 /* re-enable interrupt */
1371 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1372 spin_unlock_irqrestore(&musb->lock, flags);
1375 static const struct usb_ep_ops musb_ep_ops = {
1376 .enable = musb_gadget_enable,
1377 .disable = musb_gadget_disable,
1378 .alloc_request = musb_alloc_request,
1379 .free_request = musb_free_request,
1380 .queue = musb_gadget_queue,
1381 .dequeue = musb_gadget_dequeue,
1382 .set_halt = musb_gadget_set_halt,
1383 .set_wedge = musb_gadget_set_wedge,
1384 .fifo_status = musb_gadget_fifo_status,
1385 .fifo_flush = musb_gadget_fifo_flush
1388 /* ----------------------------------------------------------------------- */
1390 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1392 struct musb *musb = gadget_to_musb(gadget);
1394 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1397 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1399 struct musb *musb = gadget_to_musb(gadget);
1400 void __iomem *mregs = musb->mregs;
1401 unsigned long flags;
1402 int status = -EINVAL;
1406 spin_lock_irqsave(&musb->lock, flags);
1408 switch (musb->xceiv->state) {
1409 case OTG_STATE_B_PERIPHERAL:
1410 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1411 * that's part of the standard usb 1.1 state machine, and
1412 * doesn't affect OTG transitions.
1414 if (musb->may_wakeup && musb->is_suspended)
1417 case OTG_STATE_B_IDLE:
1418 /* Start SRP ... OTG not required. */
1419 devctl = musb_readb(mregs, MUSB_DEVCTL);
1420 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1421 devctl |= MUSB_DEVCTL_SESSION;
1422 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1423 devctl = musb_readb(mregs, MUSB_DEVCTL);
1425 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1426 devctl = musb_readb(mregs, MUSB_DEVCTL);
1431 while (devctl & MUSB_DEVCTL_SESSION) {
1432 devctl = musb_readb(mregs, MUSB_DEVCTL);
1437 /* Block idling for at least 1s */
1438 musb_platform_try_idle(musb,
1439 jiffies + msecs_to_jiffies(1 * HZ));
1444 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1450 power = musb_readb(mregs, MUSB_POWER);
1451 power |= MUSB_POWER_RESUME;
1452 musb_writeb(mregs, MUSB_POWER, power);
1453 DBG(2, "issue wakeup\n");
1455 /* FIXME do this next chunk in a timer callback, no udelay */
1458 power = musb_readb(mregs, MUSB_POWER);
1459 power &= ~MUSB_POWER_RESUME;
1460 musb_writeb(mregs, MUSB_POWER, power);
1462 spin_unlock_irqrestore(&musb->lock, flags);
1467 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1469 struct musb *musb = gadget_to_musb(gadget);
1471 musb->is_self_powered = !!is_selfpowered;
1475 static void musb_pullup(struct musb *musb, int is_on)
1479 power = musb_readb(musb->mregs, MUSB_POWER);
1481 power |= MUSB_POWER_SOFTCONN;
1483 power &= ~MUSB_POWER_SOFTCONN;
1485 /* FIXME if on, HdrcStart; if off, HdrcStop */
1487 DBG(3, "gadget %s D+ pullup %s\n",
1488 musb->gadget_driver->function, is_on ? "on" : "off");
1489 musb_writeb(musb->mregs, MUSB_POWER, power);
1493 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1495 DBG(2, "<= %s =>\n", __func__);
1498 * FIXME iff driver's softconnect flag is set (as it is during probe,
1499 * though that can clear it), just musb_pullup().
1506 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1508 struct musb *musb = gadget_to_musb(gadget);
1510 if (!musb->xceiv->set_power)
1512 return otg_set_power(musb->xceiv, mA);
1515 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1517 struct musb *musb = gadget_to_musb(gadget);
1518 unsigned long flags;
1522 /* NOTE: this assumes we are sensing vbus; we'd rather
1523 * not pullup unless the B-session is active.
1525 spin_lock_irqsave(&musb->lock, flags);
1526 if (is_on != musb->softconnect) {
1527 musb->softconnect = is_on;
1528 musb_pullup(musb, is_on);
1530 spin_unlock_irqrestore(&musb->lock, flags);
1534 static const struct usb_gadget_ops musb_gadget_operations = {
1535 .get_frame = musb_gadget_get_frame,
1536 .wakeup = musb_gadget_wakeup,
1537 .set_selfpowered = musb_gadget_set_self_powered,
1538 /* .vbus_session = musb_gadget_vbus_session, */
1539 .vbus_draw = musb_gadget_vbus_draw,
1540 .pullup = musb_gadget_pullup,
1543 /* ----------------------------------------------------------------------- */
1547 /* Only this registration code "knows" the rule (from USB standards)
1548 * about there being only one external upstream port. It assumes
1549 * all peripheral ports are external...
1551 static struct musb *the_gadget;
1553 static void musb_gadget_release(struct device *dev)
1555 /* kref_put(WHAT) */
1556 dev_dbg(dev, "%s\n", __func__);
1561 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1563 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1565 memset(ep, 0, sizeof *ep);
1567 ep->current_epnum = epnum;
1572 INIT_LIST_HEAD(&ep->req_list);
1574 sprintf(ep->name, "ep%d%s", epnum,
1575 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1576 is_in ? "in" : "out"));
1577 ep->end_point.name = ep->name;
1578 INIT_LIST_HEAD(&ep->end_point.ep_list);
1580 ep->end_point.maxpacket = 64;
1581 ep->end_point.ops = &musb_g_ep0_ops;
1582 musb->g.ep0 = &ep->end_point;
1585 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1587 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1588 ep->end_point.ops = &musb_ep_ops;
1589 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1594 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1595 * to the rest of the driver state.
1597 static inline void __init musb_g_init_endpoints(struct musb *musb)
1600 struct musb_hw_ep *hw_ep;
1603 /* intialize endpoint list just once */
1604 INIT_LIST_HEAD(&(musb->g.ep_list));
1606 for (epnum = 0, hw_ep = musb->endpoints;
1607 epnum < musb->nr_endpoints;
1609 if (hw_ep->is_shared_fifo /* || !epnum */) {
1610 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1613 if (hw_ep->max_packet_sz_tx) {
1614 init_peripheral_ep(musb, &hw_ep->ep_in,
1618 if (hw_ep->max_packet_sz_rx) {
1619 init_peripheral_ep(musb, &hw_ep->ep_out,
1627 /* called once during driver setup to initialize and link into
1628 * the driver model; memory is zeroed.
1630 int __init musb_gadget_setup(struct musb *musb)
1634 /* REVISIT minor race: if (erroneously) setting up two
1635 * musb peripherals at the same time, only the bus lock
1642 musb->g.ops = &musb_gadget_operations;
1643 musb->g.is_dualspeed = 1;
1644 musb->g.speed = USB_SPEED_UNKNOWN;
1646 /* this "gadget" abstracts/virtualizes the controller */
1647 dev_set_name(&musb->g.dev, "gadget");
1648 musb->g.dev.parent = musb->controller;
1649 musb->g.dev.dma_mask = musb->controller->dma_mask;
1650 musb->g.dev.release = musb_gadget_release;
1651 musb->g.name = musb_driver_name;
1653 if (is_otg_enabled(musb))
1656 musb_g_init_endpoints(musb);
1658 musb->is_active = 0;
1659 musb_platform_try_idle(musb, 0);
1661 status = device_register(&musb->g.dev);
1667 void musb_gadget_cleanup(struct musb *musb)
1669 if (musb != the_gadget)
1672 device_unregister(&musb->g.dev);
1677 * Register the gadget driver. Used by gadget drivers when
1678 * registering themselves with the controller.
1680 * -EINVAL something went wrong (not driver)
1681 * -EBUSY another gadget is already using the controller
1682 * -ENOMEM no memeory to perform the operation
1684 * @param driver the gadget driver
1685 * @return <0 if error, 0 if everything is fine
1687 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1690 unsigned long flags;
1691 struct musb *musb = the_gadget;
1694 || driver->speed != USB_SPEED_HIGH
1699 /* driver must be initialized to support peripheral mode */
1700 if (!musb || !(musb->board_mode == MUSB_OTG
1701 || musb->board_mode != MUSB_OTG)) {
1702 DBG(1, "%s, no dev??\n", __func__);
1706 DBG(3, "registering driver %s\n", driver->function);
1707 spin_lock_irqsave(&musb->lock, flags);
1709 if (musb->gadget_driver) {
1710 DBG(1, "%s is already bound to %s\n",
1712 musb->gadget_driver->driver.name);
1715 musb->gadget_driver = driver;
1716 musb->g.dev.driver = &driver->driver;
1717 driver->driver.bus = NULL;
1718 musb->softconnect = 1;
1722 spin_unlock_irqrestore(&musb->lock, flags);
1725 retval = driver->bind(&musb->g);
1727 DBG(3, "bind to driver %s failed --> %d\n",
1728 driver->driver.name, retval);
1729 musb->gadget_driver = NULL;
1730 musb->g.dev.driver = NULL;
1733 spin_lock_irqsave(&musb->lock, flags);
1735 otg_set_peripheral(musb->xceiv, &musb->g);
1736 musb->xceiv->state = OTG_STATE_B_IDLE;
1737 musb->is_active = 1;
1739 /* FIXME this ignores the softconnect flag. Drivers are
1740 * allowed hold the peripheral inactive until for example
1741 * userspace hooks up printer hardware or DSP codecs, so
1742 * hosts only see fully functional devices.
1745 if (!is_otg_enabled(musb))
1748 otg_set_peripheral(musb->xceiv, &musb->g);
1750 spin_unlock_irqrestore(&musb->lock, flags);
1752 if (is_otg_enabled(musb)) {
1753 DBG(3, "OTG startup...\n");
1755 /* REVISIT: funcall to other code, which also
1756 * handles power budgeting ... this way also
1757 * ensures HdrcStart is indirectly called.
1759 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1761 DBG(1, "add_hcd failed, %d\n", retval);
1762 spin_lock_irqsave(&musb->lock, flags);
1763 otg_set_peripheral(musb->xceiv, NULL);
1764 musb->gadget_driver = NULL;
1765 musb->g.dev.driver = NULL;
1766 spin_unlock_irqrestore(&musb->lock, flags);
1773 EXPORT_SYMBOL(usb_gadget_register_driver);
1775 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1778 struct musb_hw_ep *hw_ep;
1780 /* don't disconnect if it's not connected */
1781 if (musb->g.speed == USB_SPEED_UNKNOWN)
1784 musb->g.speed = USB_SPEED_UNKNOWN;
1786 /* deactivate the hardware */
1787 if (musb->softconnect) {
1788 musb->softconnect = 0;
1789 musb_pullup(musb, 0);
1793 /* killing any outstanding requests will quiesce the driver;
1794 * then report disconnect
1797 for (i = 0, hw_ep = musb->endpoints;
1798 i < musb->nr_endpoints;
1800 musb_ep_select(musb->mregs, i);
1801 if (hw_ep->is_shared_fifo /* || !epnum */) {
1802 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1804 if (hw_ep->max_packet_sz_tx)
1805 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1806 if (hw_ep->max_packet_sz_rx)
1807 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1811 spin_unlock(&musb->lock);
1812 driver->disconnect(&musb->g);
1813 spin_lock(&musb->lock);
1818 * Unregister the gadget driver. Used by gadget drivers when
1819 * unregistering themselves from the controller.
1821 * @param driver the gadget driver to unregister
1823 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1825 unsigned long flags;
1827 struct musb *musb = the_gadget;
1829 if (!driver || !driver->unbind || !musb)
1832 /* REVISIT always use otg_set_peripheral() here too;
1833 * this needs to shut down the OTG engine.
1836 spin_lock_irqsave(&musb->lock, flags);
1838 #ifdef CONFIG_USB_MUSB_OTG
1839 musb_hnp_stop(musb);
1842 if (musb->gadget_driver == driver) {
1844 (void) musb_gadget_vbus_draw(&musb->g, 0);
1846 musb->xceiv->state = OTG_STATE_UNDEFINED;
1847 stop_activity(musb, driver);
1848 otg_set_peripheral(musb->xceiv, NULL);
1850 DBG(3, "unregistering driver %s\n", driver->function);
1851 spin_unlock_irqrestore(&musb->lock, flags);
1852 driver->unbind(&musb->g);
1853 spin_lock_irqsave(&musb->lock, flags);
1855 musb->gadget_driver = NULL;
1856 musb->g.dev.driver = NULL;
1858 musb->is_active = 0;
1859 musb_platform_try_idle(musb, 0);
1862 spin_unlock_irqrestore(&musb->lock, flags);
1864 if (is_otg_enabled(musb) && retval == 0) {
1865 usb_remove_hcd(musb_to_hcd(musb));
1866 /* FIXME we need to be able to register another
1867 * gadget driver here and have everything work;
1868 * that currently misbehaves.
1874 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1877 /* ----------------------------------------------------------------------- */
1879 /* lifecycle operations called through plat_uds.c */
1881 void musb_g_resume(struct musb *musb)
1883 musb->is_suspended = 0;
1884 switch (musb->xceiv->state) {
1885 case OTG_STATE_B_IDLE:
1887 case OTG_STATE_B_WAIT_ACON:
1888 case OTG_STATE_B_PERIPHERAL:
1889 musb->is_active = 1;
1890 if (musb->gadget_driver && musb->gadget_driver->resume) {
1891 spin_unlock(&musb->lock);
1892 musb->gadget_driver->resume(&musb->g);
1893 spin_lock(&musb->lock);
1897 WARNING("unhandled RESUME transition (%s)\n",
1898 otg_state_string(musb));
1902 /* called when SOF packets stop for 3+ msec */
1903 void musb_g_suspend(struct musb *musb)
1907 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1908 DBG(3, "devctl %02x\n", devctl);
1910 switch (musb->xceiv->state) {
1911 case OTG_STATE_B_IDLE:
1912 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1913 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1915 case OTG_STATE_B_PERIPHERAL:
1916 musb->is_suspended = 1;
1917 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1918 spin_unlock(&musb->lock);
1919 musb->gadget_driver->suspend(&musb->g);
1920 spin_lock(&musb->lock);
1924 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1925 * A_PERIPHERAL may need care too
1927 WARNING("unhandled SUSPEND transition (%s)\n",
1928 otg_state_string(musb));
1932 /* Called during SRP */
1933 void musb_g_wakeup(struct musb *musb)
1935 musb_gadget_wakeup(&musb->g);
1938 /* called when VBUS drops below session threshold, and in other cases */
1939 void musb_g_disconnect(struct musb *musb)
1941 void __iomem *mregs = musb->mregs;
1942 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1944 DBG(3, "devctl %02x\n", devctl);
1947 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1949 /* don't draw vbus until new b-default session */
1950 (void) musb_gadget_vbus_draw(&musb->g, 0);
1952 musb->g.speed = USB_SPEED_UNKNOWN;
1953 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1954 spin_unlock(&musb->lock);
1955 musb->gadget_driver->disconnect(&musb->g);
1956 spin_lock(&musb->lock);
1959 switch (musb->xceiv->state) {
1961 #ifdef CONFIG_USB_MUSB_OTG
1962 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1963 otg_state_string(musb));
1964 musb->xceiv->state = OTG_STATE_A_IDLE;
1965 MUSB_HST_MODE(musb);
1967 case OTG_STATE_A_PERIPHERAL:
1968 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
1969 MUSB_HST_MODE(musb);
1971 case OTG_STATE_B_WAIT_ACON:
1972 case OTG_STATE_B_HOST:
1974 case OTG_STATE_B_PERIPHERAL:
1975 case OTG_STATE_B_IDLE:
1976 musb->xceiv->state = OTG_STATE_B_IDLE;
1978 case OTG_STATE_B_SRP_INIT:
1982 musb->is_active = 0;
1985 void musb_g_reset(struct musb *musb)
1986 __releases(musb->lock)
1987 __acquires(musb->lock)
1989 void __iomem *mbase = musb->mregs;
1990 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
1993 DBG(3, "<== %s addr=%x driver '%s'\n",
1994 (devctl & MUSB_DEVCTL_BDEVICE)
1995 ? "B-Device" : "A-Device",
1996 musb_readb(mbase, MUSB_FADDR),
1998 ? musb->gadget_driver->driver.name
2002 /* report disconnect, if we didn't already (flushing EP state) */
2003 if (musb->g.speed != USB_SPEED_UNKNOWN)
2004 musb_g_disconnect(musb);
2007 else if (devctl & MUSB_DEVCTL_HR)
2008 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2011 /* what speed did we negotiate? */
2012 power = musb_readb(mbase, MUSB_POWER);
2013 musb->g.speed = (power & MUSB_POWER_HSMODE)
2014 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2016 /* start in USB_STATE_DEFAULT */
2017 musb->is_active = 1;
2018 musb->is_suspended = 0;
2019 MUSB_DEV_MODE(musb);
2021 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2023 musb->may_wakeup = 0;
2024 musb->g.b_hnp_enable = 0;
2025 musb->g.a_alt_hnp_support = 0;
2026 musb->g.a_hnp_support = 0;
2028 /* Normal reset, as B-Device;
2029 * or else after HNP, as A-Device
2031 if (devctl & MUSB_DEVCTL_BDEVICE) {
2032 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2033 musb->g.is_a_peripheral = 0;
2034 } else if (is_otg_enabled(musb)) {
2035 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2036 musb->g.is_a_peripheral = 1;
2040 /* start with default limits on VBUS power draw */
2041 (void) musb_gadget_vbus_draw(&musb->g,
2042 is_otg_enabled(musb) ? 8 : 100);