2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
95 #define is_buffer_mapped(req) (is_dma_capable() && \
96 (req->map_state != UN_MAPPED))
98 /* Maps the buffer to dma */
100 static inline void map_dma_buffer(struct musb_request *request,
101 struct musb *musb, struct musb_ep *musb_ep)
103 request->map_state = UN_MAPPED;
105 if (!is_dma_capable() || !musb_ep->dma)
108 if (request->request.dma == DMA_ADDR_INVALID) {
109 request->request.dma = dma_map_single(
111 request->request.buf,
112 request->request.length,
116 request->map_state = MUSB_MAPPED;
118 dma_sync_single_for_device(musb->controller,
119 request->request.dma,
120 request->request.length,
124 request->map_state = PRE_MAPPED;
128 /* Unmap the buffer from dma and maps it back to cpu */
129 static inline void unmap_dma_buffer(struct musb_request *request,
132 if (!is_buffer_mapped(request))
135 if (request->request.dma == DMA_ADDR_INVALID) {
136 DBG(20, "not unmapping a never mapped buffer\n");
139 if (request->map_state == MUSB_MAPPED) {
140 dma_unmap_single(musb->controller,
141 request->request.dma,
142 request->request.length,
146 request->request.dma = DMA_ADDR_INVALID;
147 } else { /* PRE_MAPPED */
148 dma_sync_single_for_cpu(musb->controller,
149 request->request.dma,
150 request->request.length,
155 request->map_state = UN_MAPPED;
159 * Immediately complete a request.
161 * @param request the request to complete
162 * @param status the status to complete the request with
163 * Context: controller locked, IRQs blocked.
165 void musb_g_giveback(
167 struct usb_request *request,
169 __releases(ep->musb->lock)
170 __acquires(ep->musb->lock)
172 struct musb_request *req;
176 req = to_musb_request(request);
178 list_del(&request->list);
179 if (req->request.status == -EINPROGRESS)
180 req->request.status = status;
184 spin_unlock(&musb->lock);
185 unmap_dma_buffer(req, musb);
186 if (request->status == 0)
187 DBG(5, "%s done request %p, %d/%d\n",
188 ep->end_point.name, request,
189 req->request.actual, req->request.length);
191 DBG(2, "%s request %p, %d/%d fault %d\n",
192 ep->end_point.name, request,
193 req->request.actual, req->request.length,
195 req->request.complete(&req->ep->end_point, &req->request);
196 spin_lock(&musb->lock);
200 /* ----------------------------------------------------------------------- */
203 * Abort requests queued to an endpoint using the status. Synchronous.
204 * caller locked controller and blocked irqs, and selected this ep.
206 static void nuke(struct musb_ep *ep, const int status)
208 struct musb_request *req = NULL;
209 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
213 if (is_dma_capable() && ep->dma) {
214 struct dma_controller *c = ep->musb->dma_controller;
219 * The programming guide says that we must not clear
220 * the DMAMODE bit before DMAENAB, so we only
221 * clear it in the second write...
223 musb_writew(epio, MUSB_TXCSR,
224 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
225 musb_writew(epio, MUSB_TXCSR,
226 0 | MUSB_TXCSR_FLUSHFIFO);
228 musb_writew(epio, MUSB_RXCSR,
229 0 | MUSB_RXCSR_FLUSHFIFO);
230 musb_writew(epio, MUSB_RXCSR,
231 0 | MUSB_RXCSR_FLUSHFIFO);
234 value = c->channel_abort(ep->dma);
235 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
236 c->channel_release(ep->dma);
240 while (!list_empty(&(ep->req_list))) {
241 req = container_of(ep->req_list.next, struct musb_request,
243 musb_g_giveback(ep, &req->request, status);
247 /* ----------------------------------------------------------------------- */
249 /* Data transfers - pure PIO, pure DMA, or mixed mode */
252 * This assumes the separate CPPI engine is responding to DMA requests
253 * from the usb core ... sequenced a bit differently from mentor dma.
256 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
258 if (can_bulk_split(musb, ep->type))
259 return ep->hw_ep->max_packet_sz_tx;
261 return ep->packet_sz;
265 #ifdef CONFIG_USB_INVENTRA_DMA
267 /* Peripheral tx (IN) using Mentor DMA works as follows:
268 Only mode 0 is used for transfers <= wPktSize,
269 mode 1 is used for larger transfers,
271 One of the following happens:
272 - Host sends IN token which causes an endpoint interrupt
274 -> if DMA is currently busy, exit.
275 -> if queue is non-empty, txstate().
277 - Request is queued by the gadget driver.
278 -> if queue was previously empty, txstate()
283 | (data is transferred to the FIFO, then sent out when
284 | IN token(s) are recd from Host.
285 | -> DMA interrupt on completion
287 | -> stop DMA, ~DMAENAB,
288 | -> set TxPktRdy for last short pkt or zlp
289 | -> Complete Request
290 | -> Continue next request (call txstate)
291 |___________________________________|
293 * Non-Mentor DMA engines can of course work differently, such as by
294 * upleveling from irq-per-packet to irq-per-buffer.
300 * An endpoint is transmitting data. This can be called either from
301 * the IRQ routine or from ep.queue() to kickstart a request on an
304 * Context: controller locked, IRQs blocked, endpoint selected
306 static void txstate(struct musb *musb, struct musb_request *req)
308 u8 epnum = req->epnum;
309 struct musb_ep *musb_ep;
310 void __iomem *epio = musb->endpoints[epnum].regs;
311 struct usb_request *request;
312 u16 fifo_count = 0, csr;
317 /* we shouldn't get here while DMA is active ... but we do ... */
318 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
319 DBG(4, "dma pending...\n");
323 /* read TXCSR before */
324 csr = musb_readw(epio, MUSB_TXCSR);
326 request = &req->request;
327 fifo_count = min(max_ep_writesize(musb, musb_ep),
328 (int)(request->length - request->actual));
330 if (csr & MUSB_TXCSR_TXPKTRDY) {
331 DBG(5, "%s old packet still ready , txcsr %03x\n",
332 musb_ep->end_point.name, csr);
336 if (csr & MUSB_TXCSR_P_SENDSTALL) {
337 DBG(5, "%s stalling, txcsr %03x\n",
338 musb_ep->end_point.name, csr);
342 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
343 epnum, musb_ep->packet_sz, fifo_count,
346 #ifndef CONFIG_MUSB_PIO_ONLY
347 if (is_buffer_mapped(req)) {
348 struct dma_controller *c = musb->dma_controller;
351 /* setup DMA, then program endpoint CSR */
352 request_size = min_t(size_t, request->length - request->actual,
353 musb_ep->dma->max_len);
355 use_dma = (request->dma != DMA_ADDR_INVALID);
357 /* MUSB_TXCSR_P_ISO is still set correctly */
359 #ifdef CONFIG_USB_INVENTRA_DMA
361 if (request_size < musb_ep->packet_sz)
362 musb_ep->dma->desired_mode = 0;
364 musb_ep->dma->desired_mode = 1;
366 use_dma = use_dma && c->channel_program(
367 musb_ep->dma, musb_ep->packet_sz,
368 musb_ep->dma->desired_mode,
369 request->dma + request->actual, request_size);
371 if (musb_ep->dma->desired_mode == 0) {
373 * We must not clear the DMAMODE bit
374 * before the DMAENAB bit -- and the
375 * latter doesn't always get cleared
376 * before we get here...
378 csr &= ~(MUSB_TXCSR_AUTOSET
379 | MUSB_TXCSR_DMAENAB);
380 musb_writew(epio, MUSB_TXCSR, csr
381 | MUSB_TXCSR_P_WZC_BITS);
382 csr &= ~MUSB_TXCSR_DMAMODE;
383 csr |= (MUSB_TXCSR_DMAENAB |
385 /* against programming guide */
387 csr |= (MUSB_TXCSR_DMAENAB
390 if (!musb_ep->hb_mult)
391 csr |= MUSB_TXCSR_AUTOSET;
393 csr &= ~MUSB_TXCSR_P_UNDERRUN;
395 musb_writew(epio, MUSB_TXCSR, csr);
399 #elif defined(CONFIG_USB_TI_CPPI_DMA)
400 /* program endpoint CSR first, then setup DMA */
401 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
402 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
404 musb_writew(epio, MUSB_TXCSR,
405 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
408 /* ensure writebuffer is empty */
409 csr = musb_readw(epio, MUSB_TXCSR);
411 /* NOTE host side sets DMAENAB later than this; both are
412 * OK since the transfer dma glue (between CPPI and Mentor
413 * fifos) just tells CPPI it could start. Data only moves
414 * to the USB TX fifo when both fifos are ready.
417 /* "mode" is irrelevant here; handle terminating ZLPs like
418 * PIO does, since the hardware RNDIS mode seems unreliable
419 * except for the last-packet-is-already-short case.
421 use_dma = use_dma && c->channel_program(
422 musb_ep->dma, musb_ep->packet_sz,
424 request->dma + request->actual,
427 c->channel_release(musb_ep->dma);
429 csr &= ~MUSB_TXCSR_DMAENAB;
430 musb_writew(epio, MUSB_TXCSR, csr);
431 /* invariant: prequest->buf is non-null */
433 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
434 use_dma = use_dma && c->channel_program(
435 musb_ep->dma, musb_ep->packet_sz,
437 request->dma + request->actual,
445 * Unmap the dma buffer back to cpu if dma channel
448 unmap_dma_buffer(req, musb);
450 musb_write_fifo(musb_ep->hw_ep, fifo_count,
451 (u8 *) (request->buf + request->actual));
452 request->actual += fifo_count;
453 csr |= MUSB_TXCSR_TXPKTRDY;
454 csr &= ~MUSB_TXCSR_P_UNDERRUN;
455 musb_writew(epio, MUSB_TXCSR, csr);
458 /* host may already have the data when this message shows... */
459 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
460 musb_ep->end_point.name, use_dma ? "dma" : "pio",
461 request->actual, request->length,
462 musb_readw(epio, MUSB_TXCSR),
464 musb_readw(epio, MUSB_TXMAXP));
468 * FIFO state update (e.g. data ready).
469 * Called from IRQ, with controller locked.
471 void musb_g_tx(struct musb *musb, u8 epnum)
474 struct usb_request *request;
475 u8 __iomem *mbase = musb->mregs;
476 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
477 void __iomem *epio = musb->endpoints[epnum].regs;
478 struct dma_channel *dma;
480 musb_ep_select(mbase, epnum);
481 request = next_request(musb_ep);
483 csr = musb_readw(epio, MUSB_TXCSR);
484 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
486 dma = is_dma_capable() ? musb_ep->dma : NULL;
489 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
490 * probably rates reporting as a host error.
492 if (csr & MUSB_TXCSR_P_SENTSTALL) {
493 csr |= MUSB_TXCSR_P_WZC_BITS;
494 csr &= ~MUSB_TXCSR_P_SENTSTALL;
495 musb_writew(epio, MUSB_TXCSR, csr);
499 if (csr & MUSB_TXCSR_P_UNDERRUN) {
500 /* We NAKed, no big deal... little reason to care. */
501 csr |= MUSB_TXCSR_P_WZC_BITS;
502 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
503 musb_writew(epio, MUSB_TXCSR, csr);
504 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
507 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
509 * SHOULD NOT HAPPEN... has with CPPI though, after
510 * changing SENDSTALL (and other cases); harmless?
512 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
519 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
521 csr |= MUSB_TXCSR_P_WZC_BITS;
522 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
523 MUSB_TXCSR_TXPKTRDY);
524 musb_writew(epio, MUSB_TXCSR, csr);
525 /* Ensure writebuffer is empty. */
526 csr = musb_readw(epio, MUSB_TXCSR);
527 request->actual += musb_ep->dma->actual_len;
528 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
529 epnum, csr, musb_ep->dma->actual_len, request);
533 * First, maybe a terminating short packet. Some DMA
534 * engines might handle this by themselves.
536 if ((request->zero && request->length
537 && (request->length % musb_ep->packet_sz == 0)
538 && (request->actual == request->length))
539 #ifdef CONFIG_USB_INVENTRA_DMA
540 || (is_dma && (!dma->desired_mode ||
542 (musb_ep->packet_sz - 1))))
546 * On DMA completion, FIFO may not be
549 if (csr & MUSB_TXCSR_TXPKTRDY)
552 DBG(4, "sending zero pkt\n");
553 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
554 | MUSB_TXCSR_TXPKTRDY);
558 if (request->actual == request->length) {
559 musb_g_giveback(musb_ep, request, 0);
560 request = musb_ep->desc ? next_request(musb_ep) : NULL;
562 DBG(4, "%s idle now\n",
563 musb_ep->end_point.name);
568 txstate(musb, to_musb_request(request));
572 /* ------------------------------------------------------------ */
574 #ifdef CONFIG_USB_INVENTRA_DMA
576 /* Peripheral rx (OUT) using Mentor DMA works as follows:
577 - Only mode 0 is used.
579 - Request is queued by the gadget class driver.
580 -> if queue was previously empty, rxstate()
582 - Host sends OUT token which causes an endpoint interrupt
584 | -> if request queued, call rxstate
586 | | -> DMA interrupt on completion
590 | | -> if data recd = max expected
591 | | by the request, or host
592 | | sent a short packet,
593 | | complete the request,
594 | | and start the next one.
595 | |_____________________________________|
596 | else just wait for the host
597 | to send the next OUT token.
598 |__________________________________________________|
600 * Non-Mentor DMA engines can of course work differently.
606 * Context: controller locked, IRQs blocked, endpoint selected
608 static void rxstate(struct musb *musb, struct musb_request *req)
610 const u8 epnum = req->epnum;
611 struct usb_request *request = &req->request;
612 struct musb_ep *musb_ep;
613 void __iomem *epio = musb->endpoints[epnum].regs;
614 unsigned fifo_count = 0;
616 u16 csr = musb_readw(epio, MUSB_RXCSR);
617 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
619 if (hw_ep->is_shared_fifo)
620 musb_ep = &hw_ep->ep_in;
622 musb_ep = &hw_ep->ep_out;
624 len = musb_ep->packet_sz;
626 /* We shouldn't get here while DMA is active, but we do... */
627 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
628 DBG(4, "DMA pending...\n");
632 if (csr & MUSB_RXCSR_P_SENDSTALL) {
633 DBG(5, "%s stalling, RXCSR %04x\n",
634 musb_ep->end_point.name, csr);
638 if (is_cppi_enabled() && is_buffer_mapped(req)) {
639 struct dma_controller *c = musb->dma_controller;
640 struct dma_channel *channel = musb_ep->dma;
642 /* NOTE: CPPI won't actually stop advancing the DMA
643 * queue after short packet transfers, so this is almost
644 * always going to run as IRQ-per-packet DMA so that
645 * faults will be handled correctly.
647 if (c->channel_program(channel,
649 !request->short_not_ok,
650 request->dma + request->actual,
651 request->length - request->actual)) {
653 /* make sure that if an rxpkt arrived after the irq,
654 * the cppi engine will be ready to take it as soon
657 csr &= ~(MUSB_RXCSR_AUTOCLEAR
658 | MUSB_RXCSR_DMAMODE);
659 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
660 musb_writew(epio, MUSB_RXCSR, csr);
665 if (csr & MUSB_RXCSR_RXPKTRDY) {
666 len = musb_readw(epio, MUSB_RXCOUNT);
667 if (request->actual < request->length) {
668 #ifdef CONFIG_USB_INVENTRA_DMA
669 if (is_buffer_mapped(req)) {
670 struct dma_controller *c;
671 struct dma_channel *channel;
674 c = musb->dma_controller;
675 channel = musb_ep->dma;
677 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
678 * mode 0 only. So we do not get endpoint interrupts due to DMA
679 * completion. We only get interrupts from DMA controller.
681 * We could operate in DMA mode 1 if we knew the size of the tranfer
682 * in advance. For mass storage class, request->length = what the host
683 * sends, so that'd work. But for pretty much everything else,
684 * request->length is routinely more than what the host sends. For
685 * most these gadgets, end of is signified either by a short packet,
686 * or filling the last byte of the buffer. (Sending extra data in
687 * that last pckate should trigger an overflow fault.) But in mode 1,
688 * we don't get DMA completion interrrupt for short packets.
690 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
691 * to get endpoint interrupt on every DMA req, but that didn't seem
694 * REVISIT an updated g_file_storage can set req->short_not_ok, which
695 * then becomes usable as a runtime "use mode 1" hint...
698 csr |= MUSB_RXCSR_DMAENAB;
700 csr |= MUSB_RXCSR_AUTOCLEAR;
701 /* csr |= MUSB_RXCSR_DMAMODE; */
703 /* this special sequence (enabling and then
704 * disabling MUSB_RXCSR_DMAMODE) is required
705 * to get DMAReq to activate
707 musb_writew(epio, MUSB_RXCSR,
708 csr | MUSB_RXCSR_DMAMODE);
710 if (!musb_ep->hb_mult &&
711 musb_ep->hw_ep->rx_double_buffered)
712 csr |= MUSB_RXCSR_AUTOCLEAR;
714 musb_writew(epio, MUSB_RXCSR, csr);
716 if (request->actual < request->length) {
717 int transfer_size = 0;
719 transfer_size = min(request->length - request->actual,
722 transfer_size = min(request->length - request->actual,
725 if (transfer_size <= musb_ep->packet_sz)
726 musb_ep->dma->desired_mode = 0;
728 musb_ep->dma->desired_mode = 1;
730 use_dma = c->channel_program(
733 channel->desired_mode,
742 #endif /* Mentor's DMA */
744 fifo_count = request->length - request->actual;
745 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
746 musb_ep->end_point.name,
750 fifo_count = min_t(unsigned, len, fifo_count);
752 #ifdef CONFIG_USB_TUSB_OMAP_DMA
753 if (tusb_dma_omap() && is_buffer_mapped(req)) {
754 struct dma_controller *c = musb->dma_controller;
755 struct dma_channel *channel = musb_ep->dma;
756 u32 dma_addr = request->dma + request->actual;
759 ret = c->channel_program(channel,
761 channel->desired_mode,
769 * Unmap the dma buffer back to cpu if dma channel
770 * programming fails. This buffer is mapped if the
771 * channel allocation is successful
773 if (is_buffer_mapped(req)) {
774 unmap_dma_buffer(req, musb);
777 * Clear DMAENAB and AUTOCLEAR for the
780 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
781 musb_writew(epio, MUSB_RXCSR, csr);
784 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
785 (request->buf + request->actual));
786 request->actual += fifo_count;
788 /* REVISIT if we left anything in the fifo, flush
789 * it and report -EOVERFLOW
793 csr |= MUSB_RXCSR_P_WZC_BITS;
794 csr &= ~MUSB_RXCSR_RXPKTRDY;
795 musb_writew(epio, MUSB_RXCSR, csr);
799 /* reach the end or short packet detected */
800 if (request->actual == request->length || len < musb_ep->packet_sz)
801 musb_g_giveback(musb_ep, request, 0);
805 * Data ready for a request; called from IRQ
807 void musb_g_rx(struct musb *musb, u8 epnum)
810 struct usb_request *request;
811 void __iomem *mbase = musb->mregs;
812 struct musb_ep *musb_ep;
813 void __iomem *epio = musb->endpoints[epnum].regs;
814 struct dma_channel *dma;
815 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
817 if (hw_ep->is_shared_fifo)
818 musb_ep = &hw_ep->ep_in;
820 musb_ep = &hw_ep->ep_out;
822 musb_ep_select(mbase, epnum);
824 request = next_request(musb_ep);
828 csr = musb_readw(epio, MUSB_RXCSR);
829 dma = is_dma_capable() ? musb_ep->dma : NULL;
831 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
832 csr, dma ? " (dma)" : "", request);
834 if (csr & MUSB_RXCSR_P_SENTSTALL) {
835 csr |= MUSB_RXCSR_P_WZC_BITS;
836 csr &= ~MUSB_RXCSR_P_SENTSTALL;
837 musb_writew(epio, MUSB_RXCSR, csr);
841 if (csr & MUSB_RXCSR_P_OVERRUN) {
842 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
843 csr &= ~MUSB_RXCSR_P_OVERRUN;
844 musb_writew(epio, MUSB_RXCSR, csr);
846 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
847 if (request->status == -EINPROGRESS)
848 request->status = -EOVERFLOW;
850 if (csr & MUSB_RXCSR_INCOMPRX) {
851 /* REVISIT not necessarily an error */
852 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
855 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
856 /* "should not happen"; likely RXPKTRDY pending for DMA */
857 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
858 "%s busy, csr %04x\n",
859 musb_ep->end_point.name, csr);
863 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
864 csr &= ~(MUSB_RXCSR_AUTOCLEAR
866 | MUSB_RXCSR_DMAMODE);
867 musb_writew(epio, MUSB_RXCSR,
868 MUSB_RXCSR_P_WZC_BITS | csr);
870 request->actual += musb_ep->dma->actual_len;
872 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
874 musb_readw(epio, MUSB_RXCSR),
875 musb_ep->dma->actual_len, request);
877 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
878 /* Autoclear doesn't clear RxPktRdy for short packets */
879 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
881 & (musb_ep->packet_sz - 1))) {
883 csr &= ~MUSB_RXCSR_RXPKTRDY;
884 musb_writew(epio, MUSB_RXCSR, csr);
887 /* incomplete, and not short? wait for next IN packet */
888 if ((request->actual < request->length)
889 && (musb_ep->dma->actual_len
890 == musb_ep->packet_sz)) {
891 /* In double buffer case, continue to unload fifo if
892 * there is Rx packet in FIFO.
894 csr = musb_readw(epio, MUSB_RXCSR);
895 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
896 hw_ep->rx_double_buffered)
901 musb_g_giveback(musb_ep, request, 0);
903 request = next_request(musb_ep);
907 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
910 /* Analyze request */
911 rxstate(musb, to_musb_request(request));
914 /* ------------------------------------------------------------ */
916 static int musb_gadget_enable(struct usb_ep *ep,
917 const struct usb_endpoint_descriptor *desc)
920 struct musb_ep *musb_ep;
921 struct musb_hw_ep *hw_ep;
928 int status = -EINVAL;
933 musb_ep = to_musb_ep(ep);
934 hw_ep = musb_ep->hw_ep;
936 musb = musb_ep->musb;
938 epnum = musb_ep->current_epnum;
940 spin_lock_irqsave(&musb->lock, flags);
946 musb_ep->type = usb_endpoint_type(desc);
948 /* check direction and (later) maxpacket size against endpoint */
949 if (usb_endpoint_num(desc) != epnum)
952 /* REVISIT this rules out high bandwidth periodic transfers */
953 tmp = le16_to_cpu(desc->wMaxPacketSize);
957 if (usb_endpoint_dir_in(desc))
958 ok = musb->hb_iso_tx;
960 ok = musb->hb_iso_rx;
963 DBG(4, "%s: not support ISO high bandwidth\n", __func__);
966 musb_ep->hb_mult = (tmp >> 11) & 3;
968 musb_ep->hb_mult = 0;
971 musb_ep->packet_sz = tmp & 0x7ff;
972 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
974 /* enable the interrupts for the endpoint, set the endpoint
975 * packet size (or fail), set the mode, clear the fifo
977 musb_ep_select(mbase, epnum);
978 if (usb_endpoint_dir_in(desc)) {
979 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
981 if (hw_ep->is_shared_fifo)
986 if (tmp > hw_ep->max_packet_sz_tx) {
987 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
991 int_txe |= (1 << epnum);
992 musb_writew(mbase, MUSB_INTRTXE, int_txe);
994 /* REVISIT if can_bulk_split(), use by updating "tmp";
995 * likewise high bandwidth periodic tx
997 /* Set TXMAXP with the FIFO size of the endpoint
998 * to disable double buffering mode.
1000 if (musb->double_buffer_not_ok)
1001 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1003 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1004 | (musb_ep->hb_mult << 11));
1006 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1007 if (musb_readw(regs, MUSB_TXCSR)
1008 & MUSB_TXCSR_FIFONOTEMPTY)
1009 csr |= MUSB_TXCSR_FLUSHFIFO;
1010 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1011 csr |= MUSB_TXCSR_P_ISO;
1013 /* set twice in case of double buffering */
1014 musb_writew(regs, MUSB_TXCSR, csr);
1015 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1016 musb_writew(regs, MUSB_TXCSR, csr);
1019 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1021 if (hw_ep->is_shared_fifo)
1026 if (tmp > hw_ep->max_packet_sz_rx) {
1027 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
1031 int_rxe |= (1 << epnum);
1032 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1034 /* REVISIT if can_bulk_combine() use by updating "tmp"
1035 * likewise high bandwidth periodic rx
1037 /* Set RXMAXP with the FIFO size of the endpoint
1038 * to disable double buffering mode.
1040 if (musb->double_buffer_not_ok)
1041 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1043 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1044 | (musb_ep->hb_mult << 11));
1046 /* force shared fifo to OUT-only mode */
1047 if (hw_ep->is_shared_fifo) {
1048 csr = musb_readw(regs, MUSB_TXCSR);
1049 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1050 musb_writew(regs, MUSB_TXCSR, csr);
1053 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1054 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1055 csr |= MUSB_RXCSR_P_ISO;
1056 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1057 csr |= MUSB_RXCSR_DISNYET;
1059 /* set twice in case of double buffering */
1060 musb_writew(regs, MUSB_RXCSR, csr);
1061 musb_writew(regs, MUSB_RXCSR, csr);
1064 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1065 * for some reason you run out of channels here.
1067 if (is_dma_capable() && musb->dma_controller) {
1068 struct dma_controller *c = musb->dma_controller;
1070 musb_ep->dma = c->channel_alloc(c, hw_ep,
1071 (desc->bEndpointAddress & USB_DIR_IN));
1073 musb_ep->dma = NULL;
1075 musb_ep->desc = desc;
1077 musb_ep->wedged = 0;
1080 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1081 musb_driver_name, musb_ep->end_point.name,
1082 ({ char *s; switch (musb_ep->type) {
1083 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1084 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1085 default: s = "iso"; break;
1087 musb_ep->is_in ? "IN" : "OUT",
1088 musb_ep->dma ? "dma, " : "",
1089 musb_ep->packet_sz);
1091 schedule_work(&musb->irq_work);
1094 spin_unlock_irqrestore(&musb->lock, flags);
1099 * Disable an endpoint flushing all requests queued.
1101 static int musb_gadget_disable(struct usb_ep *ep)
1103 unsigned long flags;
1106 struct musb_ep *musb_ep;
1110 musb_ep = to_musb_ep(ep);
1111 musb = musb_ep->musb;
1112 epnum = musb_ep->current_epnum;
1113 epio = musb->endpoints[epnum].regs;
1115 spin_lock_irqsave(&musb->lock, flags);
1116 musb_ep_select(musb->mregs, epnum);
1118 /* zero the endpoint sizes */
1119 if (musb_ep->is_in) {
1120 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1121 int_txe &= ~(1 << epnum);
1122 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1123 musb_writew(epio, MUSB_TXMAXP, 0);
1125 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1126 int_rxe &= ~(1 << epnum);
1127 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1128 musb_writew(epio, MUSB_RXMAXP, 0);
1131 musb_ep->desc = NULL;
1133 /* abort all pending DMA and requests */
1134 nuke(musb_ep, -ESHUTDOWN);
1136 schedule_work(&musb->irq_work);
1138 spin_unlock_irqrestore(&(musb->lock), flags);
1140 DBG(2, "%s\n", musb_ep->end_point.name);
1146 * Allocate a request for an endpoint.
1147 * Reused by ep0 code.
1149 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1151 struct musb_ep *musb_ep = to_musb_ep(ep);
1152 struct musb_request *request = NULL;
1154 request = kzalloc(sizeof *request, gfp_flags);
1156 DBG(4, "not enough memory\n");
1160 INIT_LIST_HEAD(&request->request.list);
1161 request->request.dma = DMA_ADDR_INVALID;
1162 request->epnum = musb_ep->current_epnum;
1163 request->ep = musb_ep;
1165 return &request->request;
1170 * Reused by ep0 code.
1172 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1174 kfree(to_musb_request(req));
1177 static LIST_HEAD(buffers);
1179 struct free_record {
1180 struct list_head list;
1187 * Context: controller locked, IRQs blocked.
1189 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1191 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1192 req->tx ? "TX/IN" : "RX/OUT",
1193 &req->request, req->request.length, req->epnum);
1195 musb_ep_select(musb->mregs, req->epnum);
1202 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1205 struct musb_ep *musb_ep;
1206 struct musb_request *request;
1209 unsigned long lockflags;
1216 musb_ep = to_musb_ep(ep);
1217 musb = musb_ep->musb;
1219 request = to_musb_request(req);
1220 request->musb = musb;
1222 if (request->ep != musb_ep)
1225 DBG(4, "<== to %s request=%p\n", ep->name, req);
1227 /* request is mine now... */
1228 request->request.actual = 0;
1229 request->request.status = -EINPROGRESS;
1230 request->epnum = musb_ep->current_epnum;
1231 request->tx = musb_ep->is_in;
1233 map_dma_buffer(request, musb, musb_ep);
1235 spin_lock_irqsave(&musb->lock, lockflags);
1237 /* don't queue if the ep is down */
1238 if (!musb_ep->desc) {
1239 DBG(4, "req %p queued to %s while ep %s\n",
1240 req, ep->name, "disabled");
1241 status = -ESHUTDOWN;
1245 /* add request to the list */
1246 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1248 /* it this is the head of the queue, start i/o ... */
1249 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1250 musb_ep_restart(musb, request);
1253 spin_unlock_irqrestore(&musb->lock, lockflags);
1257 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1259 struct musb_ep *musb_ep = to_musb_ep(ep);
1260 struct usb_request *r;
1261 unsigned long flags;
1263 struct musb *musb = musb_ep->musb;
1265 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1268 spin_lock_irqsave(&musb->lock, flags);
1270 list_for_each_entry(r, &musb_ep->req_list, list) {
1275 DBG(3, "request %p not queued to %s\n", request, ep->name);
1280 /* if the hardware doesn't have the request, easy ... */
1281 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1282 musb_g_giveback(musb_ep, request, -ECONNRESET);
1284 /* ... else abort the dma transfer ... */
1285 else if (is_dma_capable() && musb_ep->dma) {
1286 struct dma_controller *c = musb->dma_controller;
1288 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1289 if (c->channel_abort)
1290 status = c->channel_abort(musb_ep->dma);
1294 musb_g_giveback(musb_ep, request, -ECONNRESET);
1296 /* NOTE: by sticking to easily tested hardware/driver states,
1297 * we leave counting of in-flight packets imprecise.
1299 musb_g_giveback(musb_ep, request, -ECONNRESET);
1303 spin_unlock_irqrestore(&musb->lock, flags);
1308 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1309 * data but will queue requests.
1311 * exported to ep0 code
1313 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1315 struct musb_ep *musb_ep = to_musb_ep(ep);
1316 u8 epnum = musb_ep->current_epnum;
1317 struct musb *musb = musb_ep->musb;
1318 void __iomem *epio = musb->endpoints[epnum].regs;
1319 void __iomem *mbase;
1320 unsigned long flags;
1322 struct musb_request *request;
1327 mbase = musb->mregs;
1329 spin_lock_irqsave(&musb->lock, flags);
1331 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1336 musb_ep_select(mbase, epnum);
1338 request = to_musb_request(next_request(musb_ep));
1341 DBG(3, "request in progress, cannot halt %s\n",
1346 /* Cannot portably stall with non-empty FIFO */
1347 if (musb_ep->is_in) {
1348 csr = musb_readw(epio, MUSB_TXCSR);
1349 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1350 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1356 musb_ep->wedged = 0;
1358 /* set/clear the stall and toggle bits */
1359 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1360 if (musb_ep->is_in) {
1361 csr = musb_readw(epio, MUSB_TXCSR);
1362 csr |= MUSB_TXCSR_P_WZC_BITS
1363 | MUSB_TXCSR_CLRDATATOG;
1365 csr |= MUSB_TXCSR_P_SENDSTALL;
1367 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1368 | MUSB_TXCSR_P_SENTSTALL);
1369 csr &= ~MUSB_TXCSR_TXPKTRDY;
1370 musb_writew(epio, MUSB_TXCSR, csr);
1372 csr = musb_readw(epio, MUSB_RXCSR);
1373 csr |= MUSB_RXCSR_P_WZC_BITS
1374 | MUSB_RXCSR_FLUSHFIFO
1375 | MUSB_RXCSR_CLRDATATOG;
1377 csr |= MUSB_RXCSR_P_SENDSTALL;
1379 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1380 | MUSB_RXCSR_P_SENTSTALL);
1381 musb_writew(epio, MUSB_RXCSR, csr);
1384 /* maybe start the first request in the queue */
1385 if (!musb_ep->busy && !value && request) {
1386 DBG(3, "restarting the request\n");
1387 musb_ep_restart(musb, request);
1391 spin_unlock_irqrestore(&musb->lock, flags);
1396 * Sets the halt feature with the clear requests ignored
1398 static int musb_gadget_set_wedge(struct usb_ep *ep)
1400 struct musb_ep *musb_ep = to_musb_ep(ep);
1405 musb_ep->wedged = 1;
1407 return usb_ep_set_halt(ep);
1410 static int musb_gadget_fifo_status(struct usb_ep *ep)
1412 struct musb_ep *musb_ep = to_musb_ep(ep);
1413 void __iomem *epio = musb_ep->hw_ep->regs;
1414 int retval = -EINVAL;
1416 if (musb_ep->desc && !musb_ep->is_in) {
1417 struct musb *musb = musb_ep->musb;
1418 int epnum = musb_ep->current_epnum;
1419 void __iomem *mbase = musb->mregs;
1420 unsigned long flags;
1422 spin_lock_irqsave(&musb->lock, flags);
1424 musb_ep_select(mbase, epnum);
1425 /* FIXME return zero unless RXPKTRDY is set */
1426 retval = musb_readw(epio, MUSB_RXCOUNT);
1428 spin_unlock_irqrestore(&musb->lock, flags);
1433 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1435 struct musb_ep *musb_ep = to_musb_ep(ep);
1436 struct musb *musb = musb_ep->musb;
1437 u8 epnum = musb_ep->current_epnum;
1438 void __iomem *epio = musb->endpoints[epnum].regs;
1439 void __iomem *mbase;
1440 unsigned long flags;
1443 mbase = musb->mregs;
1445 spin_lock_irqsave(&musb->lock, flags);
1446 musb_ep_select(mbase, (u8) epnum);
1448 /* disable interrupts */
1449 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1450 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1452 if (musb_ep->is_in) {
1453 csr = musb_readw(epio, MUSB_TXCSR);
1454 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1455 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1456 musb_writew(epio, MUSB_TXCSR, csr);
1457 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1458 musb_writew(epio, MUSB_TXCSR, csr);
1461 csr = musb_readw(epio, MUSB_RXCSR);
1462 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1463 musb_writew(epio, MUSB_RXCSR, csr);
1464 musb_writew(epio, MUSB_RXCSR, csr);
1467 /* re-enable interrupt */
1468 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1469 spin_unlock_irqrestore(&musb->lock, flags);
1472 static const struct usb_ep_ops musb_ep_ops = {
1473 .enable = musb_gadget_enable,
1474 .disable = musb_gadget_disable,
1475 .alloc_request = musb_alloc_request,
1476 .free_request = musb_free_request,
1477 .queue = musb_gadget_queue,
1478 .dequeue = musb_gadget_dequeue,
1479 .set_halt = musb_gadget_set_halt,
1480 .set_wedge = musb_gadget_set_wedge,
1481 .fifo_status = musb_gadget_fifo_status,
1482 .fifo_flush = musb_gadget_fifo_flush
1485 /* ----------------------------------------------------------------------- */
1487 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1489 struct musb *musb = gadget_to_musb(gadget);
1491 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1494 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1496 struct musb *musb = gadget_to_musb(gadget);
1497 void __iomem *mregs = musb->mregs;
1498 unsigned long flags;
1499 int status = -EINVAL;
1503 spin_lock_irqsave(&musb->lock, flags);
1505 switch (musb->xceiv->state) {
1506 case OTG_STATE_B_PERIPHERAL:
1507 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1508 * that's part of the standard usb 1.1 state machine, and
1509 * doesn't affect OTG transitions.
1511 if (musb->may_wakeup && musb->is_suspended)
1514 case OTG_STATE_B_IDLE:
1515 /* Start SRP ... OTG not required. */
1516 devctl = musb_readb(mregs, MUSB_DEVCTL);
1517 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1518 devctl |= MUSB_DEVCTL_SESSION;
1519 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1520 devctl = musb_readb(mregs, MUSB_DEVCTL);
1522 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1523 devctl = musb_readb(mregs, MUSB_DEVCTL);
1528 while (devctl & MUSB_DEVCTL_SESSION) {
1529 devctl = musb_readb(mregs, MUSB_DEVCTL);
1534 /* Block idling for at least 1s */
1535 musb_platform_try_idle(musb,
1536 jiffies + msecs_to_jiffies(1 * HZ));
1541 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1547 power = musb_readb(mregs, MUSB_POWER);
1548 power |= MUSB_POWER_RESUME;
1549 musb_writeb(mregs, MUSB_POWER, power);
1550 DBG(2, "issue wakeup\n");
1552 /* FIXME do this next chunk in a timer callback, no udelay */
1555 power = musb_readb(mregs, MUSB_POWER);
1556 power &= ~MUSB_POWER_RESUME;
1557 musb_writeb(mregs, MUSB_POWER, power);
1559 spin_unlock_irqrestore(&musb->lock, flags);
1564 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1566 struct musb *musb = gadget_to_musb(gadget);
1568 musb->is_self_powered = !!is_selfpowered;
1572 static void musb_pullup(struct musb *musb, int is_on)
1576 power = musb_readb(musb->mregs, MUSB_POWER);
1578 power |= MUSB_POWER_SOFTCONN;
1580 power &= ~MUSB_POWER_SOFTCONN;
1582 /* FIXME if on, HdrcStart; if off, HdrcStop */
1584 DBG(3, "gadget %s D+ pullup %s\n",
1585 musb->gadget_driver->function, is_on ? "on" : "off");
1586 musb_writeb(musb->mregs, MUSB_POWER, power);
1590 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1592 DBG(2, "<= %s =>\n", __func__);
1595 * FIXME iff driver's softconnect flag is set (as it is during probe,
1596 * though that can clear it), just musb_pullup().
1603 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1605 struct musb *musb = gadget_to_musb(gadget);
1607 if (!musb->xceiv->set_power)
1609 return otg_set_power(musb->xceiv, mA);
1612 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1614 struct musb *musb = gadget_to_musb(gadget);
1615 unsigned long flags;
1619 /* NOTE: this assumes we are sensing vbus; we'd rather
1620 * not pullup unless the B-session is active.
1622 spin_lock_irqsave(&musb->lock, flags);
1623 if (is_on != musb->softconnect) {
1624 musb->softconnect = is_on;
1625 musb_pullup(musb, is_on);
1627 spin_unlock_irqrestore(&musb->lock, flags);
1631 static const struct usb_gadget_ops musb_gadget_operations = {
1632 .get_frame = musb_gadget_get_frame,
1633 .wakeup = musb_gadget_wakeup,
1634 .set_selfpowered = musb_gadget_set_self_powered,
1635 /* .vbus_session = musb_gadget_vbus_session, */
1636 .vbus_draw = musb_gadget_vbus_draw,
1637 .pullup = musb_gadget_pullup,
1640 /* ----------------------------------------------------------------------- */
1644 /* Only this registration code "knows" the rule (from USB standards)
1645 * about there being only one external upstream port. It assumes
1646 * all peripheral ports are external...
1648 static struct musb *the_gadget;
1650 static void musb_gadget_release(struct device *dev)
1652 /* kref_put(WHAT) */
1653 dev_dbg(dev, "%s\n", __func__);
1658 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1660 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1662 memset(ep, 0, sizeof *ep);
1664 ep->current_epnum = epnum;
1669 INIT_LIST_HEAD(&ep->req_list);
1671 sprintf(ep->name, "ep%d%s", epnum,
1672 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1673 is_in ? "in" : "out"));
1674 ep->end_point.name = ep->name;
1675 INIT_LIST_HEAD(&ep->end_point.ep_list);
1677 ep->end_point.maxpacket = 64;
1678 ep->end_point.ops = &musb_g_ep0_ops;
1679 musb->g.ep0 = &ep->end_point;
1682 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1684 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1685 ep->end_point.ops = &musb_ep_ops;
1686 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1691 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1692 * to the rest of the driver state.
1694 static inline void __init musb_g_init_endpoints(struct musb *musb)
1697 struct musb_hw_ep *hw_ep;
1700 /* initialize endpoint list just once */
1701 INIT_LIST_HEAD(&(musb->g.ep_list));
1703 for (epnum = 0, hw_ep = musb->endpoints;
1704 epnum < musb->nr_endpoints;
1706 if (hw_ep->is_shared_fifo /* || !epnum */) {
1707 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1710 if (hw_ep->max_packet_sz_tx) {
1711 init_peripheral_ep(musb, &hw_ep->ep_in,
1715 if (hw_ep->max_packet_sz_rx) {
1716 init_peripheral_ep(musb, &hw_ep->ep_out,
1724 /* called once during driver setup to initialize and link into
1725 * the driver model; memory is zeroed.
1727 int __init musb_gadget_setup(struct musb *musb)
1731 /* REVISIT minor race: if (erroneously) setting up two
1732 * musb peripherals at the same time, only the bus lock
1739 musb->g.ops = &musb_gadget_operations;
1740 musb->g.is_dualspeed = 1;
1741 musb->g.speed = USB_SPEED_UNKNOWN;
1743 /* this "gadget" abstracts/virtualizes the controller */
1744 dev_set_name(&musb->g.dev, "gadget");
1745 musb->g.dev.parent = musb->controller;
1746 musb->g.dev.dma_mask = musb->controller->dma_mask;
1747 musb->g.dev.release = musb_gadget_release;
1748 musb->g.name = musb_driver_name;
1750 if (is_otg_enabled(musb))
1753 musb_g_init_endpoints(musb);
1755 musb->is_active = 0;
1756 musb_platform_try_idle(musb, 0);
1758 status = device_register(&musb->g.dev);
1760 put_device(&musb->g.dev);
1766 void musb_gadget_cleanup(struct musb *musb)
1768 if (musb != the_gadget)
1771 device_unregister(&musb->g.dev);
1776 * Register the gadget driver. Used by gadget drivers when
1777 * registering themselves with the controller.
1779 * -EINVAL something went wrong (not driver)
1780 * -EBUSY another gadget is already using the controller
1781 * -ENOMEM no memory to perform the operation
1783 * @param driver the gadget driver
1784 * @param bind the driver's bind function
1785 * @return <0 if error, 0 if everything is fine
1787 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1788 int (*bind)(struct usb_gadget *))
1791 unsigned long flags;
1792 struct musb *musb = the_gadget;
1795 || driver->speed != USB_SPEED_HIGH
1796 || !bind || !driver->setup)
1799 /* driver must be initialized to support peripheral mode */
1801 DBG(1, "%s, no dev??\n", __func__);
1805 DBG(3, "registering driver %s\n", driver->function);
1806 spin_lock_irqsave(&musb->lock, flags);
1808 if (musb->gadget_driver) {
1809 DBG(1, "%s is already bound to %s\n",
1811 musb->gadget_driver->driver.name);
1814 musb->gadget_driver = driver;
1815 musb->g.dev.driver = &driver->driver;
1816 driver->driver.bus = NULL;
1817 musb->softconnect = 1;
1821 spin_unlock_irqrestore(&musb->lock, flags);
1824 retval = bind(&musb->g);
1826 DBG(3, "bind to driver %s failed --> %d\n",
1827 driver->driver.name, retval);
1828 musb->gadget_driver = NULL;
1829 musb->g.dev.driver = NULL;
1832 spin_lock_irqsave(&musb->lock, flags);
1834 otg_set_peripheral(musb->xceiv, &musb->g);
1835 musb->xceiv->state = OTG_STATE_B_IDLE;
1836 musb->is_active = 1;
1838 /* FIXME this ignores the softconnect flag. Drivers are
1839 * allowed hold the peripheral inactive until for example
1840 * userspace hooks up printer hardware or DSP codecs, so
1841 * hosts only see fully functional devices.
1844 if (!is_otg_enabled(musb))
1847 otg_set_peripheral(musb->xceiv, &musb->g);
1849 spin_unlock_irqrestore(&musb->lock, flags);
1851 if (is_otg_enabled(musb)) {
1852 struct usb_hcd *hcd = musb_to_hcd(musb);
1854 DBG(3, "OTG startup...\n");
1856 /* REVISIT: funcall to other code, which also
1857 * handles power budgeting ... this way also
1858 * ensures HdrcStart is indirectly called.
1860 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1862 DBG(1, "add_hcd failed, %d\n", retval);
1863 spin_lock_irqsave(&musb->lock, flags);
1864 otg_set_peripheral(musb->xceiv, NULL);
1865 musb->gadget_driver = NULL;
1866 musb->g.dev.driver = NULL;
1867 spin_unlock_irqrestore(&musb->lock, flags);
1869 hcd->self.uses_pio_for_control = 1;
1876 EXPORT_SYMBOL(usb_gadget_probe_driver);
1878 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1881 struct musb_hw_ep *hw_ep;
1883 /* don't disconnect if it's not connected */
1884 if (musb->g.speed == USB_SPEED_UNKNOWN)
1887 musb->g.speed = USB_SPEED_UNKNOWN;
1889 /* deactivate the hardware */
1890 if (musb->softconnect) {
1891 musb->softconnect = 0;
1892 musb_pullup(musb, 0);
1896 /* killing any outstanding requests will quiesce the driver;
1897 * then report disconnect
1900 for (i = 0, hw_ep = musb->endpoints;
1901 i < musb->nr_endpoints;
1903 musb_ep_select(musb->mregs, i);
1904 if (hw_ep->is_shared_fifo /* || !epnum */) {
1905 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1907 if (hw_ep->max_packet_sz_tx)
1908 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1909 if (hw_ep->max_packet_sz_rx)
1910 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1914 spin_unlock(&musb->lock);
1915 driver->disconnect(&musb->g);
1916 spin_lock(&musb->lock);
1921 * Unregister the gadget driver. Used by gadget drivers when
1922 * unregistering themselves from the controller.
1924 * @param driver the gadget driver to unregister
1926 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1928 unsigned long flags;
1930 struct musb *musb = the_gadget;
1932 if (!driver || !driver->unbind || !musb)
1935 /* REVISIT always use otg_set_peripheral() here too;
1936 * this needs to shut down the OTG engine.
1939 spin_lock_irqsave(&musb->lock, flags);
1941 #ifdef CONFIG_USB_MUSB_OTG
1942 musb_hnp_stop(musb);
1945 if (musb->gadget_driver == driver) {
1947 (void) musb_gadget_vbus_draw(&musb->g, 0);
1949 musb->xceiv->state = OTG_STATE_UNDEFINED;
1950 stop_activity(musb, driver);
1951 otg_set_peripheral(musb->xceiv, NULL);
1953 DBG(3, "unregistering driver %s\n", driver->function);
1954 spin_unlock_irqrestore(&musb->lock, flags);
1955 driver->unbind(&musb->g);
1956 spin_lock_irqsave(&musb->lock, flags);
1958 musb->gadget_driver = NULL;
1959 musb->g.dev.driver = NULL;
1961 musb->is_active = 0;
1962 musb_platform_try_idle(musb, 0);
1965 spin_unlock_irqrestore(&musb->lock, flags);
1967 if (is_otg_enabled(musb) && retval == 0) {
1968 usb_remove_hcd(musb_to_hcd(musb));
1969 /* FIXME we need to be able to register another
1970 * gadget driver here and have everything work;
1971 * that currently misbehaves.
1977 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1980 /* ----------------------------------------------------------------------- */
1982 /* lifecycle operations called through plat_uds.c */
1984 void musb_g_resume(struct musb *musb)
1986 musb->is_suspended = 0;
1987 switch (musb->xceiv->state) {
1988 case OTG_STATE_B_IDLE:
1990 case OTG_STATE_B_WAIT_ACON:
1991 case OTG_STATE_B_PERIPHERAL:
1992 musb->is_active = 1;
1993 if (musb->gadget_driver && musb->gadget_driver->resume) {
1994 spin_unlock(&musb->lock);
1995 musb->gadget_driver->resume(&musb->g);
1996 spin_lock(&musb->lock);
2000 WARNING("unhandled RESUME transition (%s)\n",
2001 otg_state_string(musb));
2005 /* called when SOF packets stop for 3+ msec */
2006 void musb_g_suspend(struct musb *musb)
2010 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2011 DBG(3, "devctl %02x\n", devctl);
2013 switch (musb->xceiv->state) {
2014 case OTG_STATE_B_IDLE:
2015 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2016 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2018 case OTG_STATE_B_PERIPHERAL:
2019 musb->is_suspended = 1;
2020 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2021 spin_unlock(&musb->lock);
2022 musb->gadget_driver->suspend(&musb->g);
2023 spin_lock(&musb->lock);
2027 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2028 * A_PERIPHERAL may need care too
2030 WARNING("unhandled SUSPEND transition (%s)\n",
2031 otg_state_string(musb));
2035 /* Called during SRP */
2036 void musb_g_wakeup(struct musb *musb)
2038 musb_gadget_wakeup(&musb->g);
2041 /* called when VBUS drops below session threshold, and in other cases */
2042 void musb_g_disconnect(struct musb *musb)
2044 void __iomem *mregs = musb->mregs;
2045 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2047 DBG(3, "devctl %02x\n", devctl);
2050 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2052 /* don't draw vbus until new b-default session */
2053 (void) musb_gadget_vbus_draw(&musb->g, 0);
2055 musb->g.speed = USB_SPEED_UNKNOWN;
2056 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2057 spin_unlock(&musb->lock);
2058 musb->gadget_driver->disconnect(&musb->g);
2059 spin_lock(&musb->lock);
2062 switch (musb->xceiv->state) {
2064 #ifdef CONFIG_USB_MUSB_OTG
2065 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
2066 otg_state_string(musb));
2067 musb->xceiv->state = OTG_STATE_A_IDLE;
2068 MUSB_HST_MODE(musb);
2070 case OTG_STATE_A_PERIPHERAL:
2071 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2072 MUSB_HST_MODE(musb);
2074 case OTG_STATE_B_WAIT_ACON:
2075 case OTG_STATE_B_HOST:
2077 case OTG_STATE_B_PERIPHERAL:
2078 case OTG_STATE_B_IDLE:
2079 musb->xceiv->state = OTG_STATE_B_IDLE;
2081 case OTG_STATE_B_SRP_INIT:
2085 musb->is_active = 0;
2088 void musb_g_reset(struct musb *musb)
2089 __releases(musb->lock)
2090 __acquires(musb->lock)
2092 void __iomem *mbase = musb->mregs;
2093 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2096 DBG(3, "<== %s addr=%x driver '%s'\n",
2097 (devctl & MUSB_DEVCTL_BDEVICE)
2098 ? "B-Device" : "A-Device",
2099 musb_readb(mbase, MUSB_FADDR),
2101 ? musb->gadget_driver->driver.name
2105 /* report disconnect, if we didn't already (flushing EP state) */
2106 if (musb->g.speed != USB_SPEED_UNKNOWN)
2107 musb_g_disconnect(musb);
2110 else if (devctl & MUSB_DEVCTL_HR)
2111 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2114 /* what speed did we negotiate? */
2115 power = musb_readb(mbase, MUSB_POWER);
2116 musb->g.speed = (power & MUSB_POWER_HSMODE)
2117 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2119 /* start in USB_STATE_DEFAULT */
2120 musb->is_active = 1;
2121 musb->is_suspended = 0;
2122 MUSB_DEV_MODE(musb);
2124 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2126 musb->may_wakeup = 0;
2127 musb->g.b_hnp_enable = 0;
2128 musb->g.a_alt_hnp_support = 0;
2129 musb->g.a_hnp_support = 0;
2131 /* Normal reset, as B-Device;
2132 * or else after HNP, as A-Device
2134 if (devctl & MUSB_DEVCTL_BDEVICE) {
2135 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2136 musb->g.is_a_peripheral = 0;
2137 } else if (is_otg_enabled(musb)) {
2138 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2139 musb->g.is_a_peripheral = 1;
2143 /* start with default limits on VBUS power draw */
2144 (void) musb_gadget_vbus_draw(&musb->g,
2145 is_otg_enabled(musb) ? 8 : 100);