2 * MUSB OTG driver host support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
45 #include "musb_core.h"
46 #include "musb_host.h"
49 /* MUSB HOST status 22-mar-2006
51 * - There's still lots of partial code duplication for fault paths, so
52 * they aren't handled as consistently as they need to be.
54 * - PIO mostly behaved when last tested.
55 * + including ep0, with all usbtest cases 9, 10
56 * + usbtest 14 (ep0out) doesn't seem to run at all
57 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
58 * configurations, but otherwise double buffering passes basic tests.
59 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
61 * - DMA (CPPI) ... partially behaves, not currently recommended
62 * + about 1/15 the speed of typical EHCI implementations (PCI)
63 * + RX, all too often reqpkt seems to misbehave after tx
64 * + TX, no known issues (other than evident silicon issue)
66 * - DMA (Mentor/OMAP) ...has at least toggle update problems
68 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
69 * starvation ... nothing yet for TX, interrupt, or bulk.
71 * - Not tested with HNP, but some SRP paths seem to behave.
73 * NOTE 24-August-2006:
75 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
76 * extra endpoint for periodic use enabling hub + keybd + mouse. That
77 * mostly works, except that with "usbnet" it's easy to trigger cases
78 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
79 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
80 * although ARP RX wins. (That test was done with a full speed link.)
85 * NOTE on endpoint usage:
87 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
88 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
89 * (Yes, bulk _could_ use more of the endpoints than that, and would even
92 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
93 * So far that scheduling is both dumb and optimistic: the endpoint will be
94 * "claimed" until its software queue is no longer refilled. No multiplexing
95 * of transfers between endpoints, or anything clever.
99 static void musb_ep_program(struct musb *musb, u8 epnum,
100 struct urb *urb, int is_out,
101 u8 *buf, u32 offset, u32 len);
104 * Clear TX fifo. Needed to avoid BABBLE errors.
106 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
108 void __iomem *epio = ep->regs;
113 csr = musb_readw(epio, MUSB_TXCSR);
114 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
116 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
118 csr |= MUSB_TXCSR_FLUSHFIFO;
119 musb_writew(epio, MUSB_TXCSR, csr);
120 csr = musb_readw(epio, MUSB_TXCSR);
121 if (WARN(retries-- < 1,
122 "Could not flush host TX%d fifo: csr: %04x\n",
129 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
131 void __iomem *epio = ep->regs;
135 /* scrub any data left in the fifo */
137 csr = musb_readw(epio, MUSB_TXCSR);
138 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
140 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
141 csr = musb_readw(epio, MUSB_TXCSR);
145 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
148 /* and reset for the next transfer */
149 musb_writew(epio, MUSB_TXCSR, 0);
153 * Start transmit. Caller is responsible for locking shared resources.
154 * musb must be locked.
156 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
160 /* NOTE: no locks here; caller should lock and select EP */
162 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
163 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
164 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
166 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
167 musb_writew(ep->regs, MUSB_CSR0, txcsr);
172 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
176 /* NOTE: no locks here; caller should lock and select EP */
177 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
178 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
179 if (is_cppi_enabled())
180 txcsr |= MUSB_TXCSR_DMAMODE;
181 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
184 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
186 if (is_in != 0 || ep->is_shared_fifo)
188 if (is_in == 0 || ep->is_shared_fifo)
192 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
194 return is_in ? ep->in_qh : ep->out_qh;
198 * Start the URB at the front of an endpoint's queue
199 * end must be claimed from the caller.
201 * Context: controller locked, irqs blocked
204 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
208 void __iomem *mbase = musb->mregs;
209 struct urb *urb = next_urb(qh);
210 void *buf = urb->transfer_buffer;
212 struct musb_hw_ep *hw_ep = qh->hw_ep;
213 unsigned pipe = urb->pipe;
214 u8 address = usb_pipedevice(pipe);
215 int epnum = hw_ep->epnum;
217 /* initialize software qh state */
221 /* gather right source of data */
223 case USB_ENDPOINT_XFER_CONTROL:
224 /* control transfers always start with SETUP */
226 musb->ep0_stage = MUSB_EP0_START;
227 buf = urb->setup_packet;
230 case USB_ENDPOINT_XFER_ISOC:
233 offset = urb->iso_frame_desc[0].offset;
234 len = urb->iso_frame_desc[0].length;
236 default: /* bulk, interrupt */
237 /* actual_length may be nonzero on retry paths */
238 buf = urb->transfer_buffer + urb->actual_length;
239 len = urb->transfer_buffer_length - urb->actual_length;
242 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
243 qh, urb, address, qh->epnum,
244 is_in ? "in" : "out",
245 ({char *s; switch (qh->type) {
246 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
247 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
248 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
249 default: s = "-intr"; break;
251 epnum, buf + offset, len);
253 /* Configure endpoint */
254 musb_ep_set_qh(hw_ep, is_in, qh);
255 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
257 /* transmit may have more work: start it when it is time */
261 /* determine if the time is right for a periodic transfer */
263 case USB_ENDPOINT_XFER_ISOC:
264 case USB_ENDPOINT_XFER_INT:
265 DBG(3, "check whether there's still time for periodic Tx\n");
266 frame = musb_readw(mbase, MUSB_FRAME);
267 /* FIXME this doesn't implement that scheduling policy ...
268 * or handle framecounter wrapping
270 if ((urb->transfer_flags & URB_ISO_ASAP)
271 || (frame >= urb->start_frame)) {
272 /* REVISIT the SOF irq handler shouldn't duplicate
273 * this code; and we don't init urb->start_frame...
278 qh->frame = urb->start_frame;
279 /* enable SOF interrupt so we can count down */
280 DBG(1, "SOF for %d\n", epnum);
281 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
282 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
288 DBG(4, "Start TX%d %s\n", epnum,
289 hw_ep->tx_channel ? "dma" : "pio");
291 if (!hw_ep->tx_channel)
292 musb_h_tx_start(hw_ep);
293 else if (is_cppi_enabled() || tusb_dma_omap())
294 musb_h_tx_dma_start(hw_ep);
298 /* Context: caller owns controller lock, IRQs are blocked */
299 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
300 __releases(musb->lock)
301 __acquires(musb->lock)
303 DBG(({ int level; switch (status) {
307 /* common/boring faults */
318 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
319 urb, urb->complete, status,
320 usb_pipedevice(urb->pipe),
321 usb_pipeendpoint(urb->pipe),
322 usb_pipein(urb->pipe) ? "in" : "out",
323 urb->actual_length, urb->transfer_buffer_length
326 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
327 spin_unlock(&musb->lock);
328 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
329 spin_lock(&musb->lock);
332 /* For bulk/interrupt endpoints only */
333 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
336 void __iomem *epio = qh->hw_ep->regs;
340 * FIXME: the current Mentor DMA code seems to have
341 * problems getting toggle correct.
345 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
347 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
349 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
353 * Advance this hardware endpoint's queue, completing the specified URB and
354 * advancing to either the next URB queued to that qh, or else invalidating
355 * that qh and advancing to the next qh scheduled after the current one.
357 * Context: caller owns controller lock, IRQs are blocked
359 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
360 struct musb_hw_ep *hw_ep, int is_in)
362 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
363 struct musb_hw_ep *ep = qh->hw_ep;
364 int ready = qh->is_ready;
367 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
369 /* save toggle eagerly, for paranoia */
371 case USB_ENDPOINT_XFER_BULK:
372 case USB_ENDPOINT_XFER_INT:
373 musb_save_toggle(qh, is_in, urb);
375 case USB_ENDPOINT_XFER_ISOC:
376 if (status == 0 && urb->error_count)
382 musb_giveback(musb, urb, status);
383 qh->is_ready = ready;
385 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
386 * invalidate qh as soon as list_empty(&hep->urb_list)
388 if (list_empty(&qh->hep->urb_list)) {
389 struct list_head *head;
396 /* Clobber old pointers to this qh */
397 musb_ep_set_qh(ep, is_in, NULL);
398 qh->hep->hcpriv = NULL;
402 case USB_ENDPOINT_XFER_CONTROL:
403 case USB_ENDPOINT_XFER_BULK:
404 /* fifo policy for these lists, except that NAKing
405 * should rotate a qh to the end (for fairness).
408 head = qh->ring.prev;
415 case USB_ENDPOINT_XFER_ISOC:
416 case USB_ENDPOINT_XFER_INT:
417 /* this is where periodic bandwidth should be
418 * de-allocated if it's tracked and allocated;
419 * and where we'd update the schedule tree...
427 if (qh != NULL && qh->is_ready) {
428 DBG(4, "... next ep%d %cX urb %p\n",
429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
430 musb_start_urb(musb, is_in, qh);
434 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
436 /* we don't want fifo to fill itself again;
437 * ignore dma (various models),
438 * leave toggle alone (may not have been saved yet)
440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
441 csr &= ~(MUSB_RXCSR_H_REQPKT
442 | MUSB_RXCSR_H_AUTOREQ
443 | MUSB_RXCSR_AUTOCLEAR);
445 /* write 2x to allow double buffering */
446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
449 /* flush writebuffer */
450 return musb_readw(hw_ep->regs, MUSB_RXCSR);
454 * PIO RX for a packet (or part of it).
457 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
466 void __iomem *epio = hw_ep->regs;
467 struct musb_qh *qh = hw_ep->in_qh;
468 int pipe = urb->pipe;
469 void *buffer = urb->transfer_buffer;
471 /* musb_ep_select(mbase, epnum); */
472 rx_count = musb_readw(epio, MUSB_RXCOUNT);
473 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
474 urb->transfer_buffer, qh->offset,
475 urb->transfer_buffer_length);
478 if (usb_pipeisoc(pipe)) {
480 struct usb_iso_packet_descriptor *d;
487 d = urb->iso_frame_desc + qh->iso_idx;
488 buf = buffer + d->offset;
490 if (rx_count > length) {
495 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
499 urb->actual_length += length;
500 d->actual_length = length;
504 /* see if we are done */
505 done = (++qh->iso_idx >= urb->number_of_packets);
508 buf = buffer + qh->offset;
509 length = urb->transfer_buffer_length - qh->offset;
510 if (rx_count > length) {
511 if (urb->status == -EINPROGRESS)
512 urb->status = -EOVERFLOW;
513 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
517 urb->actual_length += length;
518 qh->offset += length;
520 /* see if we are done */
521 done = (urb->actual_length == urb->transfer_buffer_length)
522 || (rx_count < qh->maxpacket)
523 || (urb->status != -EINPROGRESS);
525 && (urb->status == -EINPROGRESS)
526 && (urb->transfer_flags & URB_SHORT_NOT_OK)
527 && (urb->actual_length
528 < urb->transfer_buffer_length))
529 urb->status = -EREMOTEIO;
532 musb_read_fifo(hw_ep, length, buf);
534 csr = musb_readw(epio, MUSB_RXCSR);
535 csr |= MUSB_RXCSR_H_WZC_BITS;
536 if (unlikely(do_flush))
537 musb_h_flush_rxfifo(hw_ep, csr);
539 /* REVISIT this assumes AUTOCLEAR is never set */
540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
542 csr |= MUSB_RXCSR_H_REQPKT;
543 musb_writew(epio, MUSB_RXCSR, csr);
549 /* we don't always need to reinit a given side of an endpoint...
550 * when we do, use tx/rx reinit routine and then construct a new CSR
551 * to address data toggle, NYET, and DMA or PIO.
553 * it's possible that driver bugs (especially for DMA) or aborting a
554 * transfer might have left the endpoint busier than it should be.
555 * the busy/not-empty tests are basically paranoia.
558 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
562 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
563 * That always uses tx_reinit since ep0 repurposes TX register
564 * offsets; the initial SETUP packet is also a kind of OUT.
567 /* if programmed for Tx, put it in RX mode */
568 if (ep->is_shared_fifo) {
569 csr = musb_readw(ep->regs, MUSB_TXCSR);
570 if (csr & MUSB_TXCSR_MODE) {
571 musb_h_tx_flush_fifo(ep);
572 csr = musb_readw(ep->regs, MUSB_TXCSR);
573 musb_writew(ep->regs, MUSB_TXCSR,
574 csr | MUSB_TXCSR_FRCDATATOG);
578 * Clear the MODE bit (and everything else) to enable Rx.
579 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
581 if (csr & MUSB_TXCSR_DMAMODE)
582 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
583 musb_writew(ep->regs, MUSB_TXCSR, 0);
585 /* scrub all previous state, clearing toggle */
587 csr = musb_readw(ep->regs, MUSB_RXCSR);
588 if (csr & MUSB_RXCSR_RXPKTRDY)
589 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
590 musb_readw(ep->regs, MUSB_RXCOUNT));
592 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
595 /* target addr and (for multipoint) hub addr/port */
596 if (musb->is_multipoint) {
597 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
598 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
599 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 /* Set RXMAXP with the FIFO size of the endpoint
609 * to disable double buffer mode.
611 if (musb->hwvers < MUSB_HWVERS_2000)
612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
614 musb_writew(ep->regs, MUSB_RXMAXP,
615 qh->maxpacket | ((qh->hb_mult - 1) << 11));
620 static bool musb_tx_dma_program(struct dma_controller *dma,
621 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
622 struct urb *urb, u32 offset, u32 length)
624 struct dma_channel *channel = hw_ep->tx_channel;
625 void __iomem *epio = hw_ep->regs;
626 u16 pkt_size = qh->maxpacket;
630 #ifdef CONFIG_USB_INVENTRA_DMA
631 if (length > channel->max_len)
632 length = channel->max_len;
634 csr = musb_readw(epio, MUSB_TXCSR);
635 if (length > pkt_size) {
637 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
638 /* autoset shouldn't be set in high bandwidth */
639 if (qh->hb_mult == 1)
640 csr |= MUSB_TXCSR_AUTOSET;
643 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
644 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
646 channel->desired_mode = mode;
647 musb_writew(epio, MUSB_TXCSR, csr);
649 if (!is_cppi_enabled() && !tusb_dma_omap())
652 channel->actual_len = 0;
655 * TX uses "RNDIS" mode automatically but needs help
656 * to identify the zero-length-final-packet case.
658 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
661 qh->segsize = length;
664 * Ensure the data reaches to main memory before starting
669 if (!dma->channel_program(channel, pkt_size, mode,
670 urb->transfer_dma + offset, length)) {
671 dma->channel_release(channel);
672 hw_ep->tx_channel = NULL;
674 csr = musb_readw(epio, MUSB_TXCSR);
675 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
676 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
683 * Program an HDRC endpoint as per the given URB
684 * Context: irqs blocked, controller lock held
686 static void musb_ep_program(struct musb *musb, u8 epnum,
687 struct urb *urb, int is_out,
688 u8 *buf, u32 offset, u32 len)
690 struct dma_controller *dma_controller;
691 struct dma_channel *dma_channel;
693 void __iomem *mbase = musb->mregs;
694 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
695 void __iomem *epio = hw_ep->regs;
696 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
697 u16 packet_sz = qh->maxpacket;
699 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
700 "h_addr%02x h_port%02x bytes %d\n",
701 is_out ? "-->" : "<--",
702 epnum, urb, urb->dev->speed,
703 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
704 qh->h_addr_reg, qh->h_port_reg,
707 musb_ep_select(mbase, epnum);
709 /* candidate for DMA? */
710 dma_controller = musb->dma_controller;
711 if (is_dma_capable() && epnum && dma_controller) {
712 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
714 dma_channel = dma_controller->channel_alloc(
715 dma_controller, hw_ep, is_out);
717 hw_ep->tx_channel = dma_channel;
719 hw_ep->rx_channel = dma_channel;
724 /* make sure we clear DMAEnab, autoSet bits from previous run */
726 /* OUT/transmit/EP0 or IN/receive? */
732 csr = musb_readw(epio, MUSB_TXCSR);
734 /* disable interrupt in case we flush */
735 int_txe = musb_readw(mbase, MUSB_INTRTXE);
736 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
738 /* general endpoint setup */
740 /* flush all old state, set default */
741 musb_h_tx_flush_fifo(hw_ep);
744 * We must not clear the DMAMODE bit before or in
745 * the same cycle with the DMAENAB bit, so we clear
746 * the latter first...
748 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
751 | MUSB_TXCSR_FRCDATATOG
752 | MUSB_TXCSR_H_RXSTALL
754 | MUSB_TXCSR_TXPKTRDY
756 csr |= MUSB_TXCSR_MODE;
758 if (usb_gettoggle(urb->dev, qh->epnum, 1))
759 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
760 | MUSB_TXCSR_H_DATATOGGLE;
762 csr |= MUSB_TXCSR_CLRDATATOG;
764 musb_writew(epio, MUSB_TXCSR, csr);
765 /* REVISIT may need to clear FLUSHFIFO ... */
766 csr &= ~MUSB_TXCSR_DMAMODE;
767 musb_writew(epio, MUSB_TXCSR, csr);
768 csr = musb_readw(epio, MUSB_TXCSR);
770 /* endpoint 0: just flush */
771 musb_h_ep0_flush_fifo(hw_ep);
774 /* target addr and (for multipoint) hub addr/port */
775 if (musb->is_multipoint) {
776 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
777 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
778 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
779 /* FIXME if !epnum, do the same for RX ... */
781 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
783 /* protocol/endpoint/interval/NAKlimit */
785 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
786 if (can_bulk_split(musb, qh->type))
787 musb_writew(epio, MUSB_TXMAXP,
789 | ((hw_ep->max_packet_sz_tx /
790 packet_sz) - 1) << 11);
792 musb_writew(epio, MUSB_TXMAXP,
794 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
796 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
797 if (musb->is_multipoint)
798 musb_writeb(epio, MUSB_TYPE0,
802 if (can_bulk_split(musb, qh->type))
803 load_count = min((u32) hw_ep->max_packet_sz_tx,
806 load_count = min((u32) packet_sz, len);
808 if (dma_channel && musb_tx_dma_program(dma_controller,
809 hw_ep, qh, urb, offset, len))
813 /* PIO to load FIFO */
814 qh->segsize = load_count;
815 musb_write_fifo(hw_ep, load_count, buf);
818 /* re-enable interrupt */
819 musb_writew(mbase, MUSB_INTRTXE, int_txe);
825 if (hw_ep->rx_reinit) {
826 musb_rx_reinit(musb, qh, hw_ep);
828 /* init new state: toggle and NYET, maybe DMA later */
829 if (usb_gettoggle(urb->dev, qh->epnum, 0))
830 csr = MUSB_RXCSR_H_WR_DATATOGGLE
831 | MUSB_RXCSR_H_DATATOGGLE;
834 if (qh->type == USB_ENDPOINT_XFER_INT)
835 csr |= MUSB_RXCSR_DISNYET;
838 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
840 if (csr & (MUSB_RXCSR_RXPKTRDY
842 | MUSB_RXCSR_H_REQPKT))
843 ERR("broken !rx_reinit, ep%d csr %04x\n",
846 /* scrub any stale state, leaving toggle alone */
847 csr &= MUSB_RXCSR_DISNYET;
850 /* kick things off */
852 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
853 /* candidate for DMA */
855 dma_channel->actual_len = 0L;
858 /* AUTOREQ is in a DMA register */
859 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
860 csr = musb_readw(hw_ep->regs,
863 /* unless caller treats short rx transfers as
864 * errors, we dare not queue multiple transfers.
866 dma_ok = dma_controller->channel_program(
867 dma_channel, packet_sz,
868 !(urb->transfer_flags
870 urb->transfer_dma + offset,
873 dma_controller->channel_release(
875 hw_ep->rx_channel = NULL;
878 csr |= MUSB_RXCSR_DMAENAB;
882 csr |= MUSB_RXCSR_H_REQPKT;
883 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
884 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
885 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
891 * Service the default endpoint (ep0) as host.
892 * Return true until it's time to start the status stage.
894 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
897 u8 *fifo_dest = NULL;
899 struct musb_hw_ep *hw_ep = musb->control_ep;
900 struct musb_qh *qh = hw_ep->in_qh;
901 struct usb_ctrlrequest *request;
903 switch (musb->ep0_stage) {
905 fifo_dest = urb->transfer_buffer + urb->actual_length;
906 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
908 if (fifo_count < len)
909 urb->status = -EOVERFLOW;
911 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
913 urb->actual_length += fifo_count;
914 if (len < qh->maxpacket) {
915 /* always terminate on short read; it's
916 * rarely reported as an error.
918 } else if (urb->actual_length <
919 urb->transfer_buffer_length)
923 request = (struct usb_ctrlrequest *) urb->setup_packet;
925 if (!request->wLength) {
926 DBG(4, "start no-DATA\n");
928 } else if (request->bRequestType & USB_DIR_IN) {
929 DBG(4, "start IN-DATA\n");
930 musb->ep0_stage = MUSB_EP0_IN;
934 DBG(4, "start OUT-DATA\n");
935 musb->ep0_stage = MUSB_EP0_OUT;
940 fifo_count = min_t(size_t, qh->maxpacket,
941 urb->transfer_buffer_length -
944 fifo_dest = (u8 *) (urb->transfer_buffer
945 + urb->actual_length);
946 DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
948 (fifo_count == 1) ? "" : "s",
950 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
952 urb->actual_length += fifo_count;
957 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
965 * Handle default endpoint interrupt as host. Only called in IRQ time
966 * from musb_interrupt().
968 * called with controller irqlocked
970 irqreturn_t musb_h_ep0_irq(struct musb *musb)
975 void __iomem *mbase = musb->mregs;
976 struct musb_hw_ep *hw_ep = musb->control_ep;
977 void __iomem *epio = hw_ep->regs;
978 struct musb_qh *qh = hw_ep->in_qh;
979 bool complete = false;
980 irqreturn_t retval = IRQ_NONE;
982 /* ep0 only has one queue, "in" */
985 musb_ep_select(mbase, 0);
986 csr = musb_readw(epio, MUSB_CSR0);
987 len = (csr & MUSB_CSR0_RXPKTRDY)
988 ? musb_readb(epio, MUSB_COUNT0)
991 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
992 csr, qh, len, urb, musb->ep0_stage);
994 /* if we just did status stage, we are done */
995 if (MUSB_EP0_STATUS == musb->ep0_stage) {
996 retval = IRQ_HANDLED;
1000 /* prepare status */
1001 if (csr & MUSB_CSR0_H_RXSTALL) {
1002 DBG(6, "STALLING ENDPOINT\n");
1005 } else if (csr & MUSB_CSR0_H_ERROR) {
1006 DBG(2, "no response, csr0 %04x\n", csr);
1009 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1010 DBG(2, "control NAK timeout\n");
1012 /* NOTE: this code path would be a good place to PAUSE a
1013 * control transfer, if another one is queued, so that
1014 * ep0 is more likely to stay busy. That's already done
1015 * for bulk RX transfers.
1017 * if (qh->ring.next != &musb->control), then
1018 * we have a candidate... NAKing is *NOT* an error
1020 musb_writew(epio, MUSB_CSR0, 0);
1021 retval = IRQ_HANDLED;
1025 DBG(6, "aborting\n");
1026 retval = IRQ_HANDLED;
1028 urb->status = status;
1031 /* use the proper sequence to abort the transfer */
1032 if (csr & MUSB_CSR0_H_REQPKT) {
1033 csr &= ~MUSB_CSR0_H_REQPKT;
1034 musb_writew(epio, MUSB_CSR0, csr);
1035 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1036 musb_writew(epio, MUSB_CSR0, csr);
1038 musb_h_ep0_flush_fifo(hw_ep);
1041 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1044 musb_writew(epio, MUSB_CSR0, 0);
1047 if (unlikely(!urb)) {
1048 /* stop endpoint since we have no place for its data, this
1049 * SHOULD NEVER HAPPEN! */
1050 ERR("no URB for end 0\n");
1052 musb_h_ep0_flush_fifo(hw_ep);
1057 /* call common logic and prepare response */
1058 if (musb_h_ep0_continue(musb, len, urb)) {
1059 /* more packets required */
1060 csr = (MUSB_EP0_IN == musb->ep0_stage)
1061 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1063 /* data transfer complete; perform status phase */
1064 if (usb_pipeout(urb->pipe)
1065 || !urb->transfer_buffer_length)
1066 csr = MUSB_CSR0_H_STATUSPKT
1067 | MUSB_CSR0_H_REQPKT;
1069 csr = MUSB_CSR0_H_STATUSPKT
1070 | MUSB_CSR0_TXPKTRDY;
1072 /* flag status stage */
1073 musb->ep0_stage = MUSB_EP0_STATUS;
1075 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1078 musb_writew(epio, MUSB_CSR0, csr);
1079 retval = IRQ_HANDLED;
1081 musb->ep0_stage = MUSB_EP0_IDLE;
1083 /* call completion handler if done */
1085 musb_advance_schedule(musb, urb, hw_ep, 1);
1091 #ifdef CONFIG_USB_INVENTRA_DMA
1093 /* Host side TX (OUT) using Mentor DMA works as follows:
1095 - if queue was empty, Program Endpoint
1096 - ... which starts DMA to fifo in mode 1 or 0
1098 DMA Isr (transfer complete) -> TxAvail()
1099 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1100 only in musb_cleanup_urb)
1101 - TxPktRdy has to be set in mode 0 or for
1102 short packets in mode 1.
1107 /* Service a Tx-Available or dma completion irq for the endpoint */
1108 void musb_host_tx(struct musb *musb, u8 epnum)
1115 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1116 void __iomem *epio = hw_ep->regs;
1117 struct musb_qh *qh = hw_ep->out_qh;
1118 struct urb *urb = next_urb(qh);
1120 void __iomem *mbase = musb->mregs;
1121 struct dma_channel *dma;
1123 musb_ep_select(mbase, epnum);
1124 tx_csr = musb_readw(epio, MUSB_TXCSR);
1126 /* with CPPI, DMA sometimes triggers "extra" irqs */
1128 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1133 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1134 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1135 dma ? ", dma" : "");
1137 /* check for errors */
1138 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1139 /* dma was disabled, fifo flushed */
1140 DBG(3, "TX end %d stall\n", epnum);
1142 /* stall; record URB status */
1145 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1146 /* (NON-ISO) dma was disabled, fifo flushed */
1147 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1149 status = -ETIMEDOUT;
1151 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1152 DBG(6, "TX end=%d device not responding\n", epnum);
1154 /* NOTE: this code path would be a good place to PAUSE a
1155 * transfer, if there's some other (nonperiodic) tx urb
1156 * that could use this fifo. (dma complicates it...)
1157 * That's already done for bulk RX transfers.
1159 * if (bulk && qh->ring.next != &musb->out_bulk), then
1160 * we have a candidate... NAKing is *NOT* an error
1162 musb_ep_select(mbase, epnum);
1163 musb_writew(epio, MUSB_TXCSR,
1164 MUSB_TXCSR_H_WZC_BITS
1165 | MUSB_TXCSR_TXPKTRDY);
1170 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1171 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1172 (void) musb->dma_controller->channel_abort(dma);
1175 /* do the proper sequence to abort the transfer in the
1176 * usb core; the dma engine should already be stopped.
1178 musb_h_tx_flush_fifo(hw_ep);
1179 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1180 | MUSB_TXCSR_DMAENAB
1181 | MUSB_TXCSR_H_ERROR
1182 | MUSB_TXCSR_H_RXSTALL
1183 | MUSB_TXCSR_H_NAKTIMEOUT
1186 musb_ep_select(mbase, epnum);
1187 musb_writew(epio, MUSB_TXCSR, tx_csr);
1188 /* REVISIT may need to clear FLUSHFIFO ... */
1189 musb_writew(epio, MUSB_TXCSR, tx_csr);
1190 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1195 /* second cppi case */
1196 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1197 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1201 if (is_dma_capable() && dma && !status) {
1203 * DMA has completed. But if we're using DMA mode 1 (multi
1204 * packet DMA), we need a terminal TXPKTRDY interrupt before
1205 * we can consider this transfer completed, lest we trash
1206 * its last packet when writing the next URB's data. So we
1207 * switch back to mode 0 to get that interrupt; we'll come
1208 * back here once it happens.
1210 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1212 * We shouldn't clear DMAMODE with DMAENAB set; so
1213 * clear them in a safe order. That should be OK
1214 * once TXPKTRDY has been set (and I've never seen
1215 * it being 0 at this moment -- DMA interrupt latency
1216 * is significant) but if it hasn't been then we have
1217 * no choice but to stop being polite and ignore the
1218 * programmer's guide... :-)
1220 * Note that we must write TXCSR with TXPKTRDY cleared
1221 * in order not to re-trigger the packet send (this bit
1222 * can't be cleared by CPU), and there's another caveat:
1223 * TXPKTRDY may be set shortly and then cleared in the
1224 * double-buffered FIFO mode, so we do an extra TXCSR
1225 * read for debouncing...
1227 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1228 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1229 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1230 MUSB_TXCSR_TXPKTRDY);
1231 musb_writew(epio, MUSB_TXCSR,
1232 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1234 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1235 MUSB_TXCSR_TXPKTRDY);
1236 musb_writew(epio, MUSB_TXCSR,
1237 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1240 * There is no guarantee that we'll get an interrupt
1241 * after clearing DMAMODE as we might have done this
1242 * too late (after TXPKTRDY was cleared by controller).
1243 * Re-read TXCSR as we have spoiled its previous value.
1245 tx_csr = musb_readw(epio, MUSB_TXCSR);
1249 * We may get here from a DMA completion or TXPKTRDY interrupt.
1250 * In any case, we must check the FIFO status here and bail out
1251 * only if the FIFO still has data -- that should prevent the
1252 * "missed" TXPKTRDY interrupts and deal with double-buffered
1255 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1256 DBG(2, "DMA complete but packet still in FIFO, "
1257 "CSR %04x\n", tx_csr);
1262 if (!status || dma || usb_pipeisoc(pipe)) {
1264 length = dma->actual_len;
1266 length = qh->segsize;
1267 qh->offset += length;
1269 if (usb_pipeisoc(pipe)) {
1270 struct usb_iso_packet_descriptor *d;
1272 d = urb->iso_frame_desc + qh->iso_idx;
1273 d->actual_length = length;
1275 if (++qh->iso_idx >= urb->number_of_packets) {
1285 /* see if we need to send more data, or ZLP */
1286 if (qh->segsize < qh->maxpacket)
1288 else if (qh->offset == urb->transfer_buffer_length
1289 && !(urb->transfer_flags
1293 offset = qh->offset;
1294 length = urb->transfer_buffer_length - offset;
1299 /* urb->status != -EINPROGRESS means request has been faulted,
1300 * so we must abort this transfer after cleanup
1302 if (urb->status != -EINPROGRESS) {
1305 status = urb->status;
1310 urb->status = status;
1311 urb->actual_length = qh->offset;
1312 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1314 } else if (usb_pipeisoc(pipe) && dma) {
1315 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1317 if (is_cppi_enabled() || tusb_dma_omap())
1318 musb_h_tx_dma_start(hw_ep);
1321 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1322 DBG(1, "not complete, but DMA enabled?\n");
1327 * PIO: start next packet in this URB.
1329 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1330 * (and presumably, FIFO is not half-full) we should write *two*
1331 * packets before updating TXCSR; other docs disagree...
1333 if (length > qh->maxpacket)
1334 length = qh->maxpacket;
1335 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1336 qh->segsize = length;
1338 musb_ep_select(mbase, epnum);
1339 musb_writew(epio, MUSB_TXCSR,
1340 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1344 #ifdef CONFIG_USB_INVENTRA_DMA
1346 /* Host side RX (IN) using Mentor DMA works as follows:
1348 - if queue was empty, ProgramEndpoint
1349 - first IN token is sent out (by setting ReqPkt)
1350 LinuxIsr -> RxReady()
1351 /\ => first packet is received
1352 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1353 | -> DMA Isr (transfer complete) -> RxReady()
1354 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1355 | - if urb not complete, send next IN token (ReqPkt)
1356 | | else complete urb.
1358 ---------------------------
1360 * Nuances of mode 1:
1361 * For short packets, no ack (+RxPktRdy) is sent automatically
1362 * (even if AutoClear is ON)
1363 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1364 * automatically => major problem, as collecting the next packet becomes
1365 * difficult. Hence mode 1 is not used.
1368 * All we care about at this driver level is that
1369 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1370 * (b) termination conditions are: short RX, or buffer full;
1371 * (c) fault modes include
1372 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1373 * (and that endpoint's dma queue stops immediately)
1374 * - overflow (full, PLUS more bytes in the terminal packet)
1376 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1377 * thus be a great candidate for using mode 1 ... for all but the
1378 * last packet of one URB's transfer.
1383 /* Schedule next QH from musb->in_bulk and move the current qh to
1384 * the end; avoids starvation for other endpoints.
1386 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1388 struct dma_channel *dma;
1390 void __iomem *mbase = musb->mregs;
1391 void __iomem *epio = ep->regs;
1392 struct musb_qh *cur_qh, *next_qh;
1395 musb_ep_select(mbase, ep->epnum);
1396 dma = is_dma_capable() ? ep->rx_channel : NULL;
1398 /* clear nak timeout bit */
1399 rx_csr = musb_readw(epio, MUSB_RXCSR);
1400 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1401 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1402 musb_writew(epio, MUSB_RXCSR, rx_csr);
1404 cur_qh = first_qh(&musb->in_bulk);
1406 urb = next_urb(cur_qh);
1407 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1408 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1409 musb->dma_controller->channel_abort(dma);
1410 urb->actual_length += dma->actual_len;
1411 dma->actual_len = 0L;
1413 musb_save_toggle(cur_qh, 1, urb);
1415 /* move cur_qh to end of queue */
1416 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1418 /* get the next qh from musb->in_bulk */
1419 next_qh = first_qh(&musb->in_bulk);
1421 /* set rx_reinit and schedule the next qh */
1423 musb_start_urb(musb, 1, next_qh);
1428 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1429 * and high-bandwidth IN transfer cases.
1431 void musb_host_rx(struct musb *musb, u8 epnum)
1434 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1435 void __iomem *epio = hw_ep->regs;
1436 struct musb_qh *qh = hw_ep->in_qh;
1438 void __iomem *mbase = musb->mregs;
1441 bool iso_err = false;
1444 struct dma_channel *dma;
1446 musb_ep_select(mbase, epnum);
1449 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1453 rx_csr = musb_readw(epio, MUSB_RXCSR);
1456 if (unlikely(!urb)) {
1457 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1458 * usbtest #11 (unlinks) triggers it regularly, sometimes
1459 * with fifo full. (Only with DMA??)
1461 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1462 musb_readw(epio, MUSB_RXCOUNT));
1463 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1469 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1470 epnum, rx_csr, urb->actual_length,
1471 dma ? dma->actual_len : 0);
1473 /* check for errors, concurrent stall & unlink is not really
1475 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1476 DBG(3, "RX end %d STALL\n", epnum);
1478 /* stall; record URB status */
1481 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1482 DBG(3, "end %d RX proto error\n", epnum);
1485 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1487 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1489 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1490 DBG(6, "RX end %d NAK timeout\n", epnum);
1492 /* NOTE: NAKing is *NOT* an error, so we want to
1493 * continue. Except ... if there's a request for
1494 * another QH, use that instead of starving it.
1496 * Devices like Ethernet and serial adapters keep
1497 * reads posted at all times, which will starve
1498 * other devices without this logic.
1500 if (usb_pipebulk(urb->pipe)
1502 && !list_is_singular(&musb->in_bulk)) {
1503 musb_bulk_rx_nak_timeout(musb, hw_ep);
1506 musb_ep_select(mbase, epnum);
1507 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1508 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1509 musb_writew(epio, MUSB_RXCSR, rx_csr);
1513 DBG(4, "RX end %d ISO data error\n", epnum);
1514 /* packet error reported later */
1517 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1518 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
1523 /* faults abort the transfer */
1525 /* clean up dma and collect transfer count */
1526 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1527 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1528 (void) musb->dma_controller->channel_abort(dma);
1529 xfer_len = dma->actual_len;
1531 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1532 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1537 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1538 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1539 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1543 /* thorough shutdown for now ... given more precise fault handling
1544 * and better queueing support, we might keep a DMA pipeline going
1545 * while processing this irq for earlier completions.
1548 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1550 #ifndef CONFIG_USB_INVENTRA_DMA
1551 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1552 /* REVISIT this happened for a while on some short reads...
1553 * the cleanup still needs investigation... looks bad...
1554 * and also duplicates dma cleanup code above ... plus,
1555 * shouldn't this be the "half full" double buffer case?
1557 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1558 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1559 (void) musb->dma_controller->channel_abort(dma);
1560 xfer_len = dma->actual_len;
1564 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1565 xfer_len, dma ? ", dma" : "");
1566 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1568 musb_ep_select(mbase, epnum);
1569 musb_writew(epio, MUSB_RXCSR,
1570 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1573 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1574 xfer_len = dma->actual_len;
1576 val &= ~(MUSB_RXCSR_DMAENAB
1577 | MUSB_RXCSR_H_AUTOREQ
1578 | MUSB_RXCSR_AUTOCLEAR
1579 | MUSB_RXCSR_RXPKTRDY);
1580 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1582 #ifdef CONFIG_USB_INVENTRA_DMA
1583 if (usb_pipeisoc(pipe)) {
1584 struct usb_iso_packet_descriptor *d;
1586 d = urb->iso_frame_desc + qh->iso_idx;
1587 d->actual_length = xfer_len;
1589 /* even if there was an error, we did the dma
1590 * for iso_frame_desc->length
1592 if (d->status != EILSEQ && d->status != -EOVERFLOW)
1595 if (++qh->iso_idx >= urb->number_of_packets)
1601 /* done if urb buffer is full or short packet is recd */
1602 done = (urb->actual_length + xfer_len >=
1603 urb->transfer_buffer_length
1604 || dma->actual_len < qh->maxpacket);
1607 /* send IN token for next packet, without AUTOREQ */
1609 val |= MUSB_RXCSR_H_REQPKT;
1610 musb_writew(epio, MUSB_RXCSR,
1611 MUSB_RXCSR_H_WZC_BITS | val);
1614 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1615 done ? "off" : "reset",
1616 musb_readw(epio, MUSB_RXCSR),
1617 musb_readw(epio, MUSB_RXCOUNT));
1621 } else if (urb->status == -EINPROGRESS) {
1622 /* if no errors, be sure a packet is ready for unloading */
1623 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1625 ERR("Rx interrupt with no errors or packet!\n");
1627 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1630 /* do the proper sequence to abort the transfer */
1631 musb_ep_select(mbase, epnum);
1632 val &= ~MUSB_RXCSR_H_REQPKT;
1633 musb_writew(epio, MUSB_RXCSR, val);
1637 /* we are expecting IN packets */
1638 #ifdef CONFIG_USB_INVENTRA_DMA
1640 struct dma_controller *c;
1645 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1647 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1650 + urb->actual_length,
1652 urb->transfer_buffer_length);
1654 c = musb->dma_controller;
1656 if (usb_pipeisoc(pipe)) {
1658 struct usb_iso_packet_descriptor *d;
1660 d = urb->iso_frame_desc + qh->iso_idx;
1666 if (rx_count > d->length) {
1667 if (d_status == 0) {
1668 d_status = -EOVERFLOW;
1671 DBG(2, "** OVERFLOW %d into %d\n",\
1672 rx_count, d->length);
1677 d->status = d_status;
1678 buf = urb->transfer_dma + d->offset;
1681 buf = urb->transfer_dma +
1685 dma->desired_mode = 0;
1687 /* because of the issue below, mode 1 will
1688 * only rarely behave with correct semantics.
1690 if ((urb->transfer_flags &
1692 && (urb->transfer_buffer_length -
1695 dma->desired_mode = 1;
1696 if (rx_count < hw_ep->max_packet_sz_rx) {
1698 dma->desired_mode = 0;
1700 length = urb->transfer_buffer_length;
1704 /* Disadvantage of using mode 1:
1705 * It's basically usable only for mass storage class; essentially all
1706 * other protocols also terminate transfers on short packets.
1709 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1710 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1711 * to use the extra IN token to grab the last packet using mode 0, then
1712 * the problem is that you cannot be sure when the device will send the
1713 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1714 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1715 * transfer, while sometimes it is recd just a little late so that if you
1716 * try to configure for mode 0 soon after the mode 1 transfer is
1717 * completed, you will find rxcount 0. Okay, so you might think why not
1718 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1721 val = musb_readw(epio, MUSB_RXCSR);
1722 val &= ~MUSB_RXCSR_H_REQPKT;
1724 if (dma->desired_mode == 0)
1725 val &= ~MUSB_RXCSR_H_AUTOREQ;
1727 val |= MUSB_RXCSR_H_AUTOREQ;
1728 val |= MUSB_RXCSR_DMAENAB;
1730 /* autoclear shouldn't be set in high bandwidth */
1731 if (qh->hb_mult == 1)
1732 val |= MUSB_RXCSR_AUTOCLEAR;
1734 musb_writew(epio, MUSB_RXCSR,
1735 MUSB_RXCSR_H_WZC_BITS | val);
1737 /* REVISIT if when actual_length != 0,
1738 * transfer_buffer_length needs to be
1741 ret = c->channel_program(
1743 dma->desired_mode, buf, length);
1746 c->channel_release(dma);
1747 hw_ep->rx_channel = NULL;
1749 /* REVISIT reset CSR */
1752 #endif /* Mentor DMA */
1755 done = musb_host_packet_rx(musb, urb,
1757 DBG(6, "read %spacket\n", done ? "last " : "");
1762 urb->actual_length += xfer_len;
1763 qh->offset += xfer_len;
1765 if (urb->status == -EINPROGRESS)
1766 urb->status = status;
1767 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1771 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1772 * the software schedule associates multiple such nodes with a given
1773 * host side hardware endpoint + direction; scheduling may activate
1774 * that hardware endpoint.
1776 static int musb_schedule(
1783 int best_end, epnum;
1784 struct musb_hw_ep *hw_ep = NULL;
1785 struct list_head *head = NULL;
1788 struct urb *urb = next_urb(qh);
1790 /* use fixed hardware for control and bulk */
1791 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1792 head = &musb->control;
1793 hw_ep = musb->control_ep;
1797 /* else, periodic transfers get muxed to other endpoints */
1800 * We know this qh hasn't been scheduled, so all we need to do
1801 * is choose which hardware endpoint to put it on ...
1803 * REVISIT what we really want here is a regular schedule tree
1804 * like e.g. OHCI uses.
1809 for (epnum = 1, hw_ep = musb->endpoints + 1;
1810 epnum < musb->nr_endpoints;
1814 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1817 if (hw_ep == musb->bulk_ep)
1821 diff = hw_ep->max_packet_sz_rx;
1823 diff = hw_ep->max_packet_sz_tx;
1824 diff -= (qh->maxpacket * qh->hb_mult);
1826 if (diff >= 0 && best_diff > diff) {
1829 * Mentor controller has a bug in that if we schedule
1830 * a BULK Tx transfer on an endpoint that had earlier
1831 * handled ISOC then the BULK transfer has to start on
1832 * a zero toggle. If the BULK transfer starts on a 1
1833 * toggle then this transfer will fail as the mentor
1834 * controller starts the Bulk transfer on a 0 toggle
1835 * irrespective of the programming of the toggle bits
1836 * in the TXCSR register. Check for this condition
1837 * while allocating the EP for a Tx Bulk transfer. If
1840 hw_ep = musb->endpoints + epnum;
1841 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1842 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1844 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1845 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
1852 /* use bulk reserved ep1 if no other ep is free */
1853 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1854 hw_ep = musb->bulk_ep;
1856 head = &musb->in_bulk;
1858 head = &musb->out_bulk;
1860 /* Enable bulk RX NAK timeout scheme when bulk requests are
1861 * multiplexed. This scheme doen't work in high speed to full
1862 * speed scenario as NAK interrupts are not coming from a
1863 * full speed device connected to a high speed device.
1864 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1865 * 4 (8 frame or 8ms) for FS device.
1867 if (is_in && qh->dev)
1869 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
1871 } else if (best_end < 0) {
1877 hw_ep = musb->endpoints + best_end;
1878 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1881 idle = list_empty(head);
1882 list_add_tail(&qh->ring, head);
1886 qh->hep->hcpriv = qh;
1888 musb_start_urb(musb, is_in, qh);
1892 static int musb_urb_enqueue(
1893 struct usb_hcd *hcd,
1897 unsigned long flags;
1898 struct musb *musb = hcd_to_musb(hcd);
1899 struct usb_host_endpoint *hep = urb->ep;
1901 struct usb_endpoint_descriptor *epd = &hep->desc;
1906 /* host role must be active */
1907 if (!is_host_active(musb) || !musb->is_active)
1910 spin_lock_irqsave(&musb->lock, flags);
1911 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1912 qh = ret ? NULL : hep->hcpriv;
1915 spin_unlock_irqrestore(&musb->lock, flags);
1917 /* DMA mapping was already done, if needed, and this urb is on
1918 * hep->urb_list now ... so we're done, unless hep wasn't yet
1919 * scheduled onto a live qh.
1921 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1922 * disabled, testing for empty qh->ring and avoiding qh setup costs
1923 * except for the first urb queued after a config change.
1928 /* Allocate and initialize qh, minimizing the work done each time
1929 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1931 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1932 * for bugs in other kernel code to break this driver...
1934 qh = kzalloc(sizeof *qh, mem_flags);
1936 spin_lock_irqsave(&musb->lock, flags);
1937 usb_hcd_unlink_urb_from_ep(hcd, urb);
1938 spin_unlock_irqrestore(&musb->lock, flags);
1944 INIT_LIST_HEAD(&qh->ring);
1947 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1948 qh->type = usb_endpoint_type(epd);
1950 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
1951 * Some musb cores don't support high bandwidth ISO transfers; and
1952 * we don't (yet!) support high bandwidth interrupt transfers.
1954 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1955 if (qh->hb_mult > 1) {
1956 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1959 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1960 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1965 qh->maxpacket &= 0x7ff;
1968 qh->epnum = usb_endpoint_num(epd);
1970 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1971 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1973 /* precompute rxtype/txtype/type0 register */
1974 type_reg = (qh->type << 4) | qh->epnum;
1975 switch (urb->dev->speed) {
1979 case USB_SPEED_FULL:
1985 qh->type_reg = type_reg;
1987 /* Precompute RXINTERVAL/TXINTERVAL register */
1989 case USB_ENDPOINT_XFER_INT:
1991 * Full/low speeds use the linear encoding,
1992 * high speed uses the logarithmic encoding.
1994 if (urb->dev->speed <= USB_SPEED_FULL) {
1995 interval = max_t(u8, epd->bInterval, 1);
1999 case USB_ENDPOINT_XFER_ISOC:
2000 /* ISO always uses logarithmic encoding */
2001 interval = min_t(u8, epd->bInterval, 16);
2004 /* REVISIT we actually want to use NAK limits, hinting to the
2005 * transfer scheduling logic to try some other qh, e.g. try
2008 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2010 * The downside of disabling this is that transfer scheduling
2011 * gets VERY unfair for nonperiodic transfers; a misbehaving
2012 * peripheral could make that hurt. That's perfectly normal
2013 * for reads from network or serial adapters ... so we have
2014 * partial NAKlimit support for bulk RX.
2016 * The upside of disabling it is simpler transfer scheduling.
2020 qh->intv_reg = interval;
2022 /* precompute addressing for external hub/tt ports */
2023 if (musb->is_multipoint) {
2024 struct usb_device *parent = urb->dev->parent;
2026 if (parent != hcd->self.root_hub) {
2027 qh->h_addr_reg = (u8) parent->devnum;
2029 /* set up tt info if needed */
2031 qh->h_port_reg = (u8) urb->dev->ttport;
2032 if (urb->dev->tt->hub)
2034 (u8) urb->dev->tt->hub->devnum;
2035 if (urb->dev->tt->multi)
2036 qh->h_addr_reg |= 0x80;
2041 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2042 * until we get real dma queues (with an entry for each urb/buffer),
2043 * we only have work to do in the former case.
2045 spin_lock_irqsave(&musb->lock, flags);
2047 /* some concurrent activity submitted another urb to hep...
2048 * odd, rare, error prone, but legal.
2054 ret = musb_schedule(musb, qh,
2055 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2059 /* FIXME set urb->start_frame for iso/intr, it's tested in
2060 * musb_start_urb(), but otherwise only konicawc cares ...
2063 spin_unlock_irqrestore(&musb->lock, flags);
2067 spin_lock_irqsave(&musb->lock, flags);
2068 usb_hcd_unlink_urb_from_ep(hcd, urb);
2069 spin_unlock_irqrestore(&musb->lock, flags);
2077 * abort a transfer that's at the head of a hardware queue.
2078 * called with controller locked, irqs blocked
2079 * that hardware queue advances to the next transfer, unless prevented
2081 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2083 struct musb_hw_ep *ep = qh->hw_ep;
2084 void __iomem *epio = ep->regs;
2085 unsigned hw_end = ep->epnum;
2086 void __iomem *regs = ep->musb->mregs;
2087 int is_in = usb_pipein(urb->pipe);
2091 musb_ep_select(regs, hw_end);
2093 if (is_dma_capable()) {
2094 struct dma_channel *dma;
2096 dma = is_in ? ep->rx_channel : ep->tx_channel;
2098 status = ep->musb->dma_controller->channel_abort(dma);
2100 "abort %cX%d DMA for urb %p --> %d\n",
2101 is_in ? 'R' : 'T', ep->epnum,
2103 urb->actual_length += dma->actual_len;
2107 /* turn off DMA requests, discard state, stop polling ... */
2109 /* giveback saves bulk toggle */
2110 csr = musb_h_flush_rxfifo(ep, 0);
2112 /* REVISIT we still get an irq; should likely clear the
2113 * endpoint's irq status here to avoid bogus irqs.
2114 * clearing that status is platform-specific...
2116 } else if (ep->epnum) {
2117 musb_h_tx_flush_fifo(ep);
2118 csr = musb_readw(epio, MUSB_TXCSR);
2119 csr &= ~(MUSB_TXCSR_AUTOSET
2120 | MUSB_TXCSR_DMAENAB
2121 | MUSB_TXCSR_H_RXSTALL
2122 | MUSB_TXCSR_H_NAKTIMEOUT
2123 | MUSB_TXCSR_H_ERROR
2124 | MUSB_TXCSR_TXPKTRDY);
2125 musb_writew(epio, MUSB_TXCSR, csr);
2126 /* REVISIT may need to clear FLUSHFIFO ... */
2127 musb_writew(epio, MUSB_TXCSR, csr);
2128 /* flush cpu writebuffer */
2129 csr = musb_readw(epio, MUSB_TXCSR);
2131 musb_h_ep0_flush_fifo(ep);
2134 musb_advance_schedule(ep->musb, urb, ep, is_in);
2138 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2140 struct musb *musb = hcd_to_musb(hcd);
2142 unsigned long flags;
2143 int is_in = usb_pipein(urb->pipe);
2146 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2147 usb_pipedevice(urb->pipe),
2148 usb_pipeendpoint(urb->pipe),
2149 is_in ? "in" : "out");
2151 spin_lock_irqsave(&musb->lock, flags);
2152 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2161 * Any URB not actively programmed into endpoint hardware can be
2162 * immediately given back; that's any URB not at the head of an
2163 * endpoint queue, unless someday we get real DMA queues. And even
2164 * if it's at the head, it might not be known to the hardware...
2166 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2167 * has already been updated. This is a synchronous abort; it'd be
2168 * OK to hold off until after some IRQ, though.
2170 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2173 || urb->urb_list.prev != &qh->hep->urb_list
2174 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2175 int ready = qh->is_ready;
2178 musb_giveback(musb, urb, 0);
2179 qh->is_ready = ready;
2181 /* If nothing else (usually musb_giveback) is using it
2182 * and its URB list has emptied, recycle this qh.
2184 if (ready && list_empty(&qh->hep->urb_list)) {
2185 qh->hep->hcpriv = NULL;
2186 list_del(&qh->ring);
2190 ret = musb_cleanup_urb(urb, qh);
2192 spin_unlock_irqrestore(&musb->lock, flags);
2196 /* disable an endpoint */
2198 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2200 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2201 unsigned long flags;
2202 struct musb *musb = hcd_to_musb(hcd);
2206 spin_lock_irqsave(&musb->lock, flags);
2212 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2214 /* Kick the first URB off the hardware, if needed */
2216 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2219 /* make software (then hardware) stop ASAP */
2221 urb->status = -ESHUTDOWN;
2224 musb_cleanup_urb(urb, qh);
2226 /* Then nuke all the others ... and advance the
2227 * queue on hw_ep (e.g. bulk ring) when we're done.
2229 while (!list_empty(&hep->urb_list)) {
2231 urb->status = -ESHUTDOWN;
2232 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2235 /* Just empty the queue; the hardware is busy with
2236 * other transfers, and since !qh->is_ready nothing
2237 * will activate any of these as it advances.
2239 while (!list_empty(&hep->urb_list))
2240 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2243 list_del(&qh->ring);
2247 spin_unlock_irqrestore(&musb->lock, flags);
2250 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2252 struct musb *musb = hcd_to_musb(hcd);
2254 return musb_readw(musb->mregs, MUSB_FRAME);
2257 static int musb_h_start(struct usb_hcd *hcd)
2259 struct musb *musb = hcd_to_musb(hcd);
2261 /* NOTE: musb_start() is called when the hub driver turns
2262 * on port power, or when (OTG) peripheral starts.
2264 hcd->state = HC_STATE_RUNNING;
2265 musb->port1_status = 0;
2269 static void musb_h_stop(struct usb_hcd *hcd)
2271 musb_stop(hcd_to_musb(hcd));
2272 hcd->state = HC_STATE_HALT;
2275 static int musb_bus_suspend(struct usb_hcd *hcd)
2277 struct musb *musb = hcd_to_musb(hcd);
2280 if (!is_host_active(musb))
2283 switch (musb->xceiv->state) {
2284 case OTG_STATE_A_SUSPEND:
2286 case OTG_STATE_A_WAIT_VRISE:
2287 /* ID could be grounded even if there's no device
2288 * on the other end of the cable. NOTE that the
2289 * A_WAIT_VRISE timers are messy with MUSB...
2291 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2292 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2293 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2299 if (musb->is_active) {
2300 WARNING("trying to suspend as %s while active\n",
2301 otg_state_string(musb));
2307 static int musb_bus_resume(struct usb_hcd *hcd)
2309 /* resuming child port does the work */
2313 const struct hc_driver musb_hc_driver = {
2314 .description = "musb-hcd",
2315 .product_desc = "MUSB HDRC host driver",
2316 .hcd_priv_size = sizeof(struct musb),
2317 .flags = HCD_USB2 | HCD_MEMORY,
2319 /* not using irq handler or reset hooks from usbcore, since
2320 * those must be shared with peripheral code for OTG configs
2323 .start = musb_h_start,
2324 .stop = musb_h_stop,
2326 .get_frame_number = musb_h_get_frame_number,
2328 .urb_enqueue = musb_urb_enqueue,
2329 .urb_dequeue = musb_urb_dequeue,
2330 .endpoint_disable = musb_h_disable,
2332 .hub_status_data = musb_hub_status_data,
2333 .hub_control = musb_hub_control,
2334 .bus_suspend = musb_bus_suspend,
2335 .bus_resume = musb_bus_resume,
2336 /* .start_port_reset = NULL, */
2337 /* .hub_irq_enable = NULL, */