2 * MUSB OTG driver - support for Mentor's DMA controller
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <linux/device.h>
34 #include <linux/interrupt.h>
35 #include <linux/platform_device.h>
36 #include <linux/slab.h>
37 #include "musb_core.h"
38 #include "musbhsdma.h"
40 static int dma_controller_start(struct dma_controller *c)
46 static void dma_channel_release(struct dma_channel *channel);
48 static int dma_controller_stop(struct dma_controller *c)
50 struct musb_dma_controller *controller = container_of(c,
51 struct musb_dma_controller, controller);
52 struct musb *musb = controller->private_data;
53 struct dma_channel *channel;
56 if (controller->used_channels != 0) {
57 dev_err(musb->controller,
58 "Stopping DMA controller while channel active\n");
60 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
61 if (controller->used_channels & (1 << bit)) {
62 channel = &controller->channel[bit].channel;
63 dma_channel_release(channel);
65 if (!controller->used_channels)
74 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
75 struct musb_hw_ep *hw_ep, u8 transmit)
77 struct musb_dma_controller *controller = container_of(c,
78 struct musb_dma_controller, controller);
79 struct musb_dma_channel *musb_channel = NULL;
80 struct dma_channel *channel = NULL;
83 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
84 if (!(controller->used_channels & (1 << bit))) {
85 controller->used_channels |= (1 << bit);
86 musb_channel = &(controller->channel[bit]);
87 musb_channel->controller = controller;
88 musb_channel->idx = bit;
89 musb_channel->epnum = hw_ep->epnum;
90 musb_channel->transmit = transmit;
91 channel = &(musb_channel->channel);
92 channel->private_data = musb_channel;
93 channel->status = MUSB_DMA_STATUS_FREE;
94 channel->max_len = 0x10000;
95 /* Tx => mode 1; Rx => mode 0 */
96 channel->desired_mode = transmit;
97 channel->actual_len = 0;
105 static void dma_channel_release(struct dma_channel *channel)
107 struct musb_dma_channel *musb_channel = channel->private_data;
109 channel->actual_len = 0;
110 musb_channel->start_addr = 0;
111 musb_channel->len = 0;
113 musb_channel->controller->used_channels &=
114 ~(1 << musb_channel->idx);
116 channel->status = MUSB_DMA_STATUS_UNKNOWN;
119 static void configure_channel(struct dma_channel *channel,
120 u16 packet_sz, u8 mode,
121 dma_addr_t dma_addr, u32 len)
123 struct musb_dma_channel *musb_channel = channel->private_data;
124 struct musb_dma_controller *controller = musb_channel->controller;
125 void __iomem *mbase = controller->base;
126 u8 bchannel = musb_channel->idx;
129 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
130 channel, packet_sz, dma_addr, len, mode);
133 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
134 BUG_ON(len < packet_sz);
136 csr |= MUSB_HSDMA_BURSTMODE_INCR16
137 << MUSB_HSDMA_BURSTMODE_SHIFT;
139 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
140 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
141 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
142 | (musb_channel->transmit
143 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
147 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
148 musb_write_hsdma_count(mbase, bchannel, len);
150 /* control (this should start things) */
152 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
156 static int dma_channel_program(struct dma_channel *channel,
157 u16 packet_sz, u8 mode,
158 dma_addr_t dma_addr, u32 len)
160 struct musb_dma_channel *musb_channel = channel->private_data;
162 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
164 musb_channel->transmit ? "Tx" : "Rx",
165 packet_sz, dma_addr, len, mode);
167 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
168 channel->status == MUSB_DMA_STATUS_BUSY);
170 channel->actual_len = 0;
171 musb_channel->start_addr = dma_addr;
172 musb_channel->len = len;
173 musb_channel->max_packet_sz = packet_sz;
174 channel->status = MUSB_DMA_STATUS_BUSY;
176 if ((mode == 1) && (len >= packet_sz))
177 configure_channel(channel, packet_sz, 1, dma_addr, len);
179 configure_channel(channel, packet_sz, 0, dma_addr, len);
184 static int dma_channel_abort(struct dma_channel *channel)
186 struct musb_dma_channel *musb_channel = channel->private_data;
187 void __iomem *mbase = musb_channel->controller->base;
189 u8 bchannel = musb_channel->idx;
193 if (channel->status == MUSB_DMA_STATUS_BUSY) {
194 if (musb_channel->transmit) {
195 offset = MUSB_EP_OFFSET(musb_channel->epnum,
199 * The programming guide says that we must clear
200 * the DMAENAB bit before the DMAMODE bit...
202 csr = musb_readw(mbase, offset);
203 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
204 musb_writew(mbase, offset, csr);
205 csr &= ~MUSB_TXCSR_DMAMODE;
206 musb_writew(mbase, offset, csr);
208 offset = MUSB_EP_OFFSET(musb_channel->epnum,
211 csr = musb_readw(mbase, offset);
212 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
215 musb_writew(mbase, offset, csr);
219 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
221 musb_write_hsdma_addr(mbase, bchannel, 0);
222 musb_write_hsdma_count(mbase, bchannel, 0);
223 channel->status = MUSB_DMA_STATUS_FREE;
229 static irqreturn_t dma_controller_irq(int irq, void *private_data)
231 struct musb_dma_controller *controller = private_data;
232 struct musb *musb = controller->private_data;
233 struct musb_dma_channel *musb_channel;
234 struct dma_channel *channel;
236 void __iomem *mbase = controller->base;
238 irqreturn_t retval = IRQ_NONE;
248 spin_lock_irqsave(&musb->lock, flags);
250 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
252 #ifdef CONFIG_BLACKFIN
253 /* Clear DMA interrupt flags */
254 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
258 DBG(2, "spurious DMA irq\n");
260 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
261 musb_channel = (struct musb_dma_channel *)
262 &(controller->channel[bchannel]);
263 channel = &musb_channel->channel;
264 if (channel->status == MUSB_DMA_STATUS_BUSY) {
265 count = musb_read_hsdma_count(mbase, bchannel);
268 int_hsdma |= (1 << bchannel);
272 DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
278 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
279 if (int_hsdma & (1 << bchannel)) {
280 musb_channel = (struct musb_dma_channel *)
281 &(controller->channel[bchannel]);
282 channel = &musb_channel->channel;
284 csr = musb_readw(mbase,
285 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
286 MUSB_HSDMA_CONTROL));
288 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
289 musb_channel->channel.status =
290 MUSB_DMA_STATUS_BUS_ABORT;
294 addr = musb_read_hsdma_addr(mbase,
296 channel->actual_len = addr
297 - musb_channel->start_addr;
299 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
300 channel, musb_channel->start_addr,
301 addr, channel->actual_len,
304 < musb_channel->len) ?
305 "=> reconfig 0" : "=> complete");
307 devctl = musb_readb(mbase, MUSB_DEVCTL);
309 channel->status = MUSB_DMA_STATUS_FREE;
312 if ((devctl & MUSB_DEVCTL_HM)
313 && (musb_channel->transmit)
314 && ((channel->desired_mode == 0)
315 || (channel->actual_len &
316 (musb_channel->max_packet_sz - 1)))
318 u8 epnum = musb_channel->epnum;
319 int offset = MUSB_EP_OFFSET(epnum,
324 * The programming guide says that we
325 * must clear DMAENAB before DMAMODE.
327 musb_ep_select(mbase, epnum);
328 txcsr = musb_readw(mbase, offset);
329 txcsr &= ~(MUSB_TXCSR_DMAENAB
330 | MUSB_TXCSR_AUTOSET);
331 musb_writew(mbase, offset, txcsr);
332 /* Send out the packet */
333 txcsr &= ~MUSB_TXCSR_DMAMODE;
334 txcsr |= MUSB_TXCSR_TXPKTRDY;
335 musb_writew(mbase, offset, txcsr);
337 musb_dma_completion(musb, musb_channel->epnum,
338 musb_channel->transmit);
343 retval = IRQ_HANDLED;
345 spin_unlock_irqrestore(&musb->lock, flags);
349 void dma_controller_destroy(struct dma_controller *c)
351 struct musb_dma_controller *controller = container_of(c,
352 struct musb_dma_controller, controller);
358 free_irq(controller->irq, c);
363 struct dma_controller *__init
364 dma_controller_create(struct musb *musb, void __iomem *base)
366 struct musb_dma_controller *controller;
367 struct device *dev = musb->controller;
368 struct platform_device *pdev = to_platform_device(dev);
369 int irq = platform_get_irq(pdev, 1);
372 dev_err(dev, "No DMA interrupt line!\n");
376 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
380 controller->channel_count = MUSB_HSDMA_CHANNELS;
381 controller->private_data = musb;
382 controller->base = base;
384 controller->controller.start = dma_controller_start;
385 controller->controller.stop = dma_controller_stop;
386 controller->controller.channel_alloc = dma_channel_allocate;
387 controller->controller.channel_release = dma_channel_release;
388 controller->controller.channel_program = dma_channel_program;
389 controller->controller.channel_abort = dma_channel_abort;
391 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
392 dev_name(musb->controller), &controller->controller)) {
393 dev_err(dev, "request_irq %d failed!\n", irq);
394 dma_controller_destroy(&controller->controller);
399 controller->irq = irq;
401 return &controller->controller;