2 * MUSB OTG driver - support for Mentor's DMA controller
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
38 #ifndef CONFIG_BLACKFIN
40 #define MUSB_HSDMA_BASE 0x200
41 #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
42 #define MUSB_HSDMA_CONTROL 0x4
43 #define MUSB_HSDMA_ADDRESS 0x8
44 #define MUSB_HSDMA_COUNT 0xc
46 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
47 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
49 #define musb_read_hsdma_addr(mbase, bchannel) \
51 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
53 #define musb_write_hsdma_addr(mbase, bchannel, addr) \
55 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
58 #define musb_read_hsdma_count(mbase, bchannel) \
60 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
62 #define musb_write_hsdma_count(mbase, bchannel, len) \
64 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
68 #define MUSB_HSDMA_BASE 0x400
69 #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
70 #define MUSB_HSDMA_CONTROL 0x04
71 #define MUSB_HSDMA_ADDR_LOW 0x08
72 #define MUSB_HSDMA_ADDR_HIGH 0x0C
73 #define MUSB_HSDMA_COUNT_LOW 0x10
74 #define MUSB_HSDMA_COUNT_HIGH 0x14
76 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
77 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
79 static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
81 u32 addr = musb_readw(mbase,
82 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
86 addr |= musb_readw(mbase,
87 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
92 static inline void musb_write_hsdma_addr(void __iomem *mbase,
93 u8 bchannel, dma_addr_t dma_addr)
96 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
97 ((u16)((u32) dma_addr & 0xFFFF)));
99 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
100 ((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
103 static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
105 return musb_readl(mbase,
106 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
109 static inline void musb_write_hsdma_count(void __iomem *mbase,
110 u8 bchannel, u32 len)
113 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
117 #endif /* CONFIG_BLACKFIN */
119 /* control register (16-bit): */
120 #define MUSB_HSDMA_ENABLE_SHIFT 0
121 #define MUSB_HSDMA_TRANSMIT_SHIFT 1
122 #define MUSB_HSDMA_MODE1_SHIFT 2
123 #define MUSB_HSDMA_IRQENABLE_SHIFT 3
124 #define MUSB_HSDMA_ENDPOINT_SHIFT 4
125 #define MUSB_HSDMA_BUSERROR_SHIFT 8
126 #define MUSB_HSDMA_BURSTMODE_SHIFT 9
127 #define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
128 #define MUSB_HSDMA_BURSTMODE_UNSPEC 0
129 #define MUSB_HSDMA_BURSTMODE_INCR4 1
130 #define MUSB_HSDMA_BURSTMODE_INCR8 2
131 #define MUSB_HSDMA_BURSTMODE_INCR16 3
133 #define MUSB_HSDMA_CHANNELS 8
135 struct musb_dma_controller;
137 struct musb_dma_channel {
138 struct dma_channel channel;
139 struct musb_dma_controller *controller;
148 struct musb_dma_controller {
149 struct dma_controller controller;
150 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];