2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/init.h>
15 #include <linux/usb.h>
16 #include <linux/platform_device.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
22 #include "musb_core.h"
25 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
27 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
29 struct tusb_omap_dma_ch {
32 unsigned long phys_offset;
35 struct musb_hw_ep *hw_ep;
41 struct tusb_omap_dma *tusb_dma;
47 u16 transfer_packet_sz;
52 struct tusb_omap_dma {
53 struct dma_controller controller;
60 unsigned multichannel:1;
63 static int tusb_omap_dma_start(struct dma_controller *c)
65 struct tusb_omap_dma *tusb_dma;
67 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
69 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
74 static int tusb_omap_dma_stop(struct dma_controller *c)
76 struct tusb_omap_dma *tusb_dma;
78 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
80 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
86 * Allocate dmareq0 to the current channel unless it's already taken
88 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
90 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
93 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
94 chdat->epnum, reg & 0xf);
99 reg = (1 << 4) | chdat->epnum;
103 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
108 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
110 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
112 if ((reg & 0xf) != chdat->epnum) {
113 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
114 chdat->epnum, reg & 0xf);
117 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
121 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
124 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
126 struct dma_channel *channel = (struct dma_channel *)data;
127 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
128 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
129 struct musb *musb = chdat->musb;
130 struct device *dev = musb->controller;
131 struct musb_hw_ep *hw_ep = chdat->hw_ep;
132 void __iomem *ep_conf = hw_ep->conf;
133 void __iomem *mbase = musb->mregs;
134 unsigned long remaining, flags, pio;
137 spin_lock_irqsave(&musb->lock, flags);
139 if (tusb_dma->multichannel)
144 if (ch_status != OMAP_DMA_BLOCK_IRQ)
145 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
147 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
148 chdat->epnum, chdat->tx ? "tx" : "rx",
152 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
154 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
156 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
158 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
159 if (unlikely(remaining > chdat->transfer_len)) {
160 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
161 chdat->tx ? "tx" : "rx", chdat->ch,
166 channel->actual_len = chdat->transfer_len - remaining;
167 pio = chdat->len - channel->actual_len;
169 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
171 /* Transfer remaining 1 - 31 bytes */
172 if (pio > 0 && pio < 32) {
175 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
176 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
178 dma_unmap_single(dev, chdat->dma_addr,
181 musb_write_fifo(hw_ep, pio, buf);
183 dma_unmap_single(dev, chdat->dma_addr,
186 musb_read_fifo(hw_ep, pio, buf);
188 channel->actual_len += pio;
191 if (!tusb_dma->multichannel)
192 tusb_omap_free_shared_dmareq(chdat);
194 channel->status = MUSB_DMA_STATUS_FREE;
196 /* Handle only RX callbacks here. TX callbacks must be handled based
197 * on the TUSB DMA status interrupt.
198 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
199 * interrupt for RX and TX.
202 musb_dma_completion(musb, chdat->epnum, chdat->tx);
204 /* We must terminate short tx transfers manually by setting TXPKTRDY.
205 * REVISIT: This same problem may occur with other MUSB dma as well.
206 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
208 if ((chdat->transfer_len < chdat->packet_sz)
209 || (chdat->transfer_len % chdat->packet_sz != 0)) {
213 dev_dbg(musb->controller, "terminating short tx packet\n");
214 musb_ep_select(mbase, chdat->epnum);
215 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
216 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
217 | MUSB_TXCSR_P_WZC_BITS;
218 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
222 spin_unlock_irqrestore(&musb->lock, flags);
225 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
226 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
228 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
229 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
230 struct musb *musb = chdat->musb;
231 struct device *dev = musb->controller;
232 struct musb_hw_ep *hw_ep = chdat->hw_ep;
233 void __iomem *mbase = musb->mregs;
234 void __iomem *ep_conf = hw_ep->conf;
235 dma_addr_t fifo = hw_ep->fifo_sync;
236 struct omap_dma_channel_params dma_params;
238 int src_burst, dst_burst;
244 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
248 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
249 * register which will cause missed DMA interrupt. We could try to
250 * use a timer for the callback, but it is unsafe as the XFR_SIZE
251 * register is corrupt, and we won't know if the DMA worked.
257 * Because of HW issue #10, it seems like mixing sync DMA and async
258 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
259 * using the channel for DMA.
262 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
264 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
266 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
268 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
269 chdat->tx ? "tx" : "rx", chdat->ch,
274 chdat->transfer_len = len & ~0x1f;
277 chdat->transfer_packet_sz = chdat->transfer_len;
279 chdat->transfer_packet_sz = packet_sz;
281 if (tusb_dma->multichannel) {
283 dmareq = chdat->dmareq;
284 sync_dev = chdat->sync_dev;
286 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
287 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
290 if (tusb_dma->ch < 0) {
291 /* REVISIT: This should get blocked earlier, happens
292 * with MSC ErrorRecoveryTest
299 dmareq = tusb_dma->dmareq;
300 sync_dev = tusb_dma->sync_dev;
301 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
304 chdat->packet_sz = packet_sz;
306 channel->actual_len = 0;
307 chdat->dma_addr = dma_addr;
308 channel->status = MUSB_DMA_STATUS_BUSY;
310 /* Since we're recycling dma areas, we need to clean or invalidate */
312 dma_map_single(dev, phys_to_virt(dma_addr), len,
315 dma_map_single(dev, phys_to_virt(dma_addr), len,
318 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
319 if ((dma_addr & 0x3) == 0) {
320 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
321 dma_params.elem_count = 8; /* Elements in frame */
323 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
324 dma_params.elem_count = 16; /* Elements in frame */
325 fifo = hw_ep->fifo_async;
328 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
330 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
331 chdat->epnum, chdat->tx ? "tx" : "rx",
332 ch, dma_addr, chdat->transfer_len, len,
333 chdat->transfer_packet_sz, packet_sz);
336 * Prepare omap DMA for transfer
339 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
340 dma_params.src_start = (unsigned long)dma_addr;
341 dma_params.src_ei = 0;
342 dma_params.src_fi = 0;
344 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
345 dma_params.dst_start = (unsigned long)fifo;
346 dma_params.dst_ei = 1;
347 dma_params.dst_fi = -31; /* Loop 32 byte window */
349 dma_params.trigger = sync_dev;
350 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
351 dma_params.src_or_dst_synch = 0; /* Dest sync */
353 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
354 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
356 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
357 dma_params.src_start = (unsigned long)fifo;
358 dma_params.src_ei = 1;
359 dma_params.src_fi = -31; /* Loop 32 byte window */
361 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
362 dma_params.dst_start = (unsigned long)dma_addr;
363 dma_params.dst_ei = 0;
364 dma_params.dst_fi = 0;
366 dma_params.trigger = sync_dev;
367 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
368 dma_params.src_or_dst_synch = 1; /* Source sync */
370 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
371 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
374 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
375 chdat->epnum, chdat->tx ? "tx" : "rx",
376 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
377 ((dma_addr & 0x3) == 0) ? "sync" : "async",
378 dma_params.src_start, dma_params.dst_start);
380 omap_set_dma_params(ch, &dma_params);
381 omap_set_dma_src_burst_mode(ch, src_burst);
382 omap_set_dma_dest_burst_mode(ch, dst_burst);
383 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
386 * Prepare MUSB for DMA transfer
389 musb_ep_select(mbase, chdat->epnum);
390 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
391 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
392 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
393 csr &= ~MUSB_TXCSR_P_UNDERRUN;
394 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
396 musb_ep_select(mbase, chdat->epnum);
397 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
398 csr |= MUSB_RXCSR_DMAENAB;
399 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
400 musb_writew(hw_ep->regs, MUSB_RXCSR,
401 csr | MUSB_RXCSR_P_WZC_BITS);
410 /* Send transfer_packet_sz packets at a time */
411 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
412 chdat->transfer_packet_sz);
414 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
415 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
417 /* Receive transfer_packet_sz packets at a time */
418 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
419 chdat->transfer_packet_sz << 16);
421 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
422 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
428 static int tusb_omap_dma_abort(struct dma_channel *channel)
430 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
431 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
433 if (!tusb_dma->multichannel) {
434 if (tusb_dma->ch >= 0) {
435 omap_stop_dma(tusb_dma->ch);
436 omap_free_dma(tusb_dma->ch);
440 tusb_dma->dmareq = -1;
441 tusb_dma->sync_dev = -1;
444 channel->status = MUSB_DMA_STATUS_FREE;
449 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
451 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
452 int i, dmareq_nr = -1;
454 const int sync_dev[6] = {
455 OMAP24XX_DMA_EXT_DMAREQ0,
456 OMAP24XX_DMA_EXT_DMAREQ1,
457 OMAP242X_DMA_EXT_DMAREQ2,
458 OMAP242X_DMA_EXT_DMAREQ3,
459 OMAP242X_DMA_EXT_DMAREQ4,
460 OMAP242X_DMA_EXT_DMAREQ5,
463 for (i = 0; i < MAX_DMAREQ; i++) {
464 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
474 reg |= (chdat->epnum << (dmareq_nr * 5));
476 reg |= ((1 << 4) << (dmareq_nr * 5));
477 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
479 chdat->dmareq = dmareq_nr;
480 chdat->sync_dev = sync_dev[chdat->dmareq];
485 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
489 if (!chdat || chdat->dmareq < 0)
492 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
493 reg &= ~(0x1f << (chdat->dmareq * 5));
494 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
497 chdat->sync_dev = -1;
500 static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
502 static struct dma_channel *
503 tusb_omap_dma_allocate(struct dma_controller *c,
504 struct musb_hw_ep *hw_ep,
508 const char *dev_name;
509 struct tusb_omap_dma *tusb_dma;
512 struct dma_channel *channel = NULL;
513 struct tusb_omap_dma_ch *chdat = NULL;
516 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
517 musb = tusb_dma->musb;
518 tbase = musb->ctrl_base;
520 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
522 reg &= ~(1 << hw_ep->epnum);
524 reg &= ~(1 << (hw_ep->epnum + 15));
525 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
527 /* REVISIT: Why does dmareq5 not work? */
528 if (hw_ep->epnum == 0) {
529 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
533 for (i = 0; i < MAX_DMAREQ; i++) {
534 struct dma_channel *ch = dma_channel_pool[i];
535 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
536 ch->status = MUSB_DMA_STATUS_FREE;
538 chdat = ch->private_data;
548 dev_name = "TUSB transmit";
551 dev_name = "TUSB receive";
554 chdat->musb = tusb_dma->musb;
555 chdat->tbase = tusb_dma->tbase;
556 chdat->hw_ep = hw_ep;
557 chdat->epnum = hw_ep->epnum;
559 chdat->completed_len = 0;
560 chdat->tusb_dma = tusb_dma;
562 channel->max_len = 0x7fffffff;
563 channel->desired_mode = 0;
564 channel->actual_len = 0;
566 if (tusb_dma->multichannel) {
567 ret = tusb_omap_dma_allocate_dmareq(chdat);
571 ret = omap_request_dma(chdat->sync_dev, dev_name,
572 tusb_omap_dma_cb, channel, &chdat->ch);
575 } else if (tusb_dma->ch == -1) {
576 tusb_dma->dmareq = 0;
577 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
579 /* Callback data gets set later in the shared dmareq case */
580 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
581 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
589 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
591 chdat->tx ? "tx" : "rx",
592 chdat->ch >= 0 ? "dedicated" : "shared",
593 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
594 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
595 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
600 tusb_omap_dma_free_dmareq(chdat);
602 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
603 channel->status = MUSB_DMA_STATUS_UNKNOWN;
608 static void tusb_omap_dma_release(struct dma_channel *channel)
610 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
611 struct musb *musb = chdat->musb;
612 void __iomem *tbase = musb->ctrl_base;
615 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
617 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
619 reg |= (1 << chdat->epnum);
621 reg |= (1 << (chdat->epnum + 15));
622 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
624 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
626 reg |= (1 << chdat->epnum);
628 reg |= (1 << (chdat->epnum + 15));
629 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
631 channel->status = MUSB_DMA_STATUS_UNKNOWN;
633 if (chdat->ch >= 0) {
634 omap_stop_dma(chdat->ch);
635 omap_free_dma(chdat->ch);
639 if (chdat->dmareq >= 0)
640 tusb_omap_dma_free_dmareq(chdat);
645 void dma_controller_destroy(struct dma_controller *c)
647 struct tusb_omap_dma *tusb_dma;
650 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
651 for (i = 0; i < MAX_DMAREQ; i++) {
652 struct dma_channel *ch = dma_channel_pool[i];
654 kfree(ch->private_data);
659 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0)
660 omap_free_dma(tusb_dma->ch);
665 struct dma_controller *__init
666 dma_controller_create(struct musb *musb, void __iomem *base)
668 void __iomem *tbase = musb->ctrl_base;
669 struct tusb_omap_dma *tusb_dma;
672 /* REVISIT: Get dmareq lines used from board-*.c */
674 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
675 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
677 musb_writel(tbase, TUSB_DMA_REQ_CONF,
678 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
679 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
680 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
682 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
686 tusb_dma->musb = musb;
687 tusb_dma->tbase = musb->ctrl_base;
690 tusb_dma->dmareq = -1;
691 tusb_dma->sync_dev = -1;
693 tusb_dma->controller.start = tusb_omap_dma_start;
694 tusb_dma->controller.stop = tusb_omap_dma_stop;
695 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
696 tusb_dma->controller.channel_release = tusb_omap_dma_release;
697 tusb_dma->controller.channel_program = tusb_omap_dma_program;
698 tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
700 if (tusb_get_revision(musb) >= TUSB_REV_30)
701 tusb_dma->multichannel = 1;
703 for (i = 0; i < MAX_DMAREQ; i++) {
704 struct dma_channel *ch;
705 struct tusb_omap_dma_ch *chdat;
707 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
711 dma_channel_pool[i] = ch;
713 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
717 ch->status = MUSB_DMA_STATUS_UNKNOWN;
718 ch->private_data = chdat;
721 return &tusb_dma->controller;
724 dma_controller_destroy(&tusb_dma->controller);