drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/slab.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/err.h>
  27 #include <linux/delay.h>
  28 #include <linux/io.h>
  29 #include <linux/ioport.h>
  30 #include <linux/uaccess.h>
  31 #include <linux/debugfs.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/reboot.h>
  37 #include <linux/reset.h>
  38
  39 #include <linux/usb.h>
  40 #include <linux/usb/otg.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/ulpi.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/hcd.h>
  45 #include <linux/usb/msm_hsusb.h>
  46 #include <linux/usb/msm_hsusb_hw.h>
  47 #include <linux/regulator/consumer.h>
  48 #include <linux/msm-bus.h>
  49
  50 #define MSM_USB_BASE    (motg->regs)
  51 #define DRIVER_NAME     "msm_otg"
  52
  53 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  54 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
  55
  56 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
  57 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
  58 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
  59 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
  60
  61 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
  62 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
  63 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
  64 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
  65
  66 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
  67 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
  68 #define USB_PHY_SUSP_DIG_VOL    500000  /* uV */
  69
  70 enum vdd_levels {
  71         VDD_LEVEL_NONE = 0,
  72         VDD_LEVEL_MIN,
  73         VDD_LEVEL_MAX,
  74 };
  75
  76 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
  77 {
  78         int ret = 0;
  79
  80         if (IS_ERR(motg->vddcx))
  81                 return 0;
  82
  83         if (init) {
  84                 ret = regulator_set_voltage(motg->vddcx,
  85                                 motg->vdd_levels[VDD_LEVEL_MIN],
  86                                 motg->vdd_levels[VDD_LEVEL_MAX]);
  87                 if (ret) {
  88                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
  89                         return ret;
  90                 }
  91
  92                 ret = regulator_enable(motg->vddcx);
  93                 if (ret)
  94                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
  95         } else {
  96                 ret = regulator_set_voltage(motg->vddcx, 0,
  97                                 motg->vdd_levels[VDD_LEVEL_MAX]);
  98                 if (ret)
  99                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 100                 ret = regulator_disable(motg->vddcx);
 101                 if (ret)
 102                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
 103         }
 104
 105         return ret;
 106 }
 107
 108 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
 109 {
 110         int rc = 0;
 111
 112         if (init) {
 113                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
 114                                 USB_PHY_3P3_VOL_MAX);
 115                 if (rc) {
 116                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
 117                         goto exit;
 118                 }
 119                 rc = regulator_enable(motg->v3p3);
 120                 if (rc) {
 121                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 122                         goto exit;
 123                 }
 124                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 125                                 USB_PHY_1P8_VOL_MAX);
 126                 if (rc) {
 127                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
 128                         goto disable_3p3;
 129                 }
 130                 rc = regulator_enable(motg->v1p8);
 131                 if (rc) {
 132                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 133                         goto disable_3p3;
 134                 }
 135
 136                 return 0;
 137         }
 138
 139         regulator_disable(motg->v1p8);
 140 disable_3p3:
 141         regulator_disable(motg->v3p3);
 142 exit:
 143         return rc;
 144 }
 145
 146 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 147 {
 148         int ret = 0;
 149
 150         if (on) {
 151                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
 152                 if (ret < 0) {
 153                         pr_err("Could not set HPM for v1p8\n");
 154                         return ret;
 155                 }
 156                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
 157                 if (ret < 0) {
 158                         pr_err("Could not set HPM for v3p3\n");
 159                         regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 160                         return ret;
 161                 }
 162         } else {
 163                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 164                 if (ret < 0)
 165                         pr_err("Could not set LPM for v1p8\n");
 166                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
 167                 if (ret < 0)
 168                         pr_err("Could not set LPM for v3p3\n");
 169         }
 170
 171         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 172         return ret < 0 ? ret : 0;
 173 }
 174
 175 static int ulpi_read(struct usb_phy *phy, u32 reg)
 176 {
 177         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 178         int cnt = 0;
 179
 180         /* initiate read operation */
 181         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 182                USB_ULPI_VIEWPORT);
 183
 184         /* wait for completion */
 185         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 186                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 187                         break;
 188                 udelay(1);
 189                 cnt++;
 190         }
 191
 192         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 193                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 194                         readl(USB_ULPI_VIEWPORT));
 195                 return -ETIMEDOUT;
 196         }
 197         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 198 }
 199
 200 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 201 {
 202         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 203         int cnt = 0;
 204
 205         /* initiate write operation */
 206         writel(ULPI_RUN | ULPI_WRITE |
 207                ULPI_ADDR(reg) | ULPI_DATA(val),
 208                USB_ULPI_VIEWPORT);
 209
 210         /* wait for completion */
 211         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 212                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 213                         break;
 214                 udelay(1);
 215                 cnt++;
 216         }
 217
 218         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 219                 dev_err(phy->dev, "ulpi_write: timeout\n");
 220                 return -ETIMEDOUT;
 221         }
 222         return 0;
 223 }
 224
 225 static struct usb_phy_io_ops msm_otg_io_ops = {
 226         .read = ulpi_read,
 227         .write = ulpi_write,
 228 };
 229
 230 static void ulpi_init(struct msm_otg *motg)
 231 {
 232         struct msm_otg_platform_data *pdata = motg->pdata;
 233         int *seq = pdata->phy_init_seq, idx;
 234         u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
 235
 236         for (idx = 0; idx < pdata->phy_init_sz; idx++) {
 237                 if (seq[idx] == -1)
 238                         continue;
 239
 240                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 241                                 seq[idx], addr + idx);
 242                 ulpi_write(&motg->phy, seq[idx], addr + idx);
 243         }
 244 }
 245
 246 static int msm_phy_notify_disconnect(struct usb_phy *phy,
 247                                    enum usb_device_speed speed)
 248 {
 249         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 250         int val;
 251
 252         if (motg->manual_pullup) {
 253                 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
 254                 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
 255         }
 256
 257         /*
 258          * Put the transceiver in non-driving mode. Otherwise host
 259          * may not detect soft-disconnection.
 260          */
 261         val = ulpi_read(phy, ULPI_FUNC_CTRL);
 262         val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 263         val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 264         ulpi_write(phy, val, ULPI_FUNC_CTRL);
 265
 266         return 0;
 267 }
 268
 269 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 270 {
 271         int ret;
 272
 273         if (assert)
 274                 ret = reset_control_assert(motg->link_rst);
 275         else
 276                 ret = reset_control_deassert(motg->link_rst);
 277
 278         if (ret)
 279                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 280                         assert ? "assert" : "deassert");
 281
 282         return ret;
 283 }
 284
 285 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 286 {
 287         int ret = 0;
 288
 289         if (motg->phy_rst)
 290                 ret = reset_control_reset(motg->phy_rst);
 291
 292         if (ret)
 293                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 294
 295         return ret;
 296 }
 297
 298 static int msm_link_reset(struct msm_otg *motg)
 299 {
 300         u32 val;
 301         int ret;
 302
 303         ret = msm_otg_link_clk_reset(motg, 1);
 304         if (ret)
 305                 return ret;
 306
 307         /* wait for 1ms delay as suggested in HPG. */
 308         usleep_range(1000, 1200);
 309
 310         ret = msm_otg_link_clk_reset(motg, 0);
 311         if (ret)
 312                 return ret;
 313
 314         if (motg->phy_number)
 315                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 316
 317         /* put transceiver in serial mode as part of reset */
 318         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 319         writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
 320
 321         return 0;
 322 }
 323
 324 static int msm_otg_reset(struct usb_phy *phy)
 325 {
 326         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 327         int cnt = 0;
 328
 329         writel(USBCMD_RESET, USB_USBCMD);
 330         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 331                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 332                         break;
 333                 udelay(1);
 334                 cnt++;
 335         }
 336         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 337                 return -ETIMEDOUT;
 338
 339         /* select ULPI phy and clear other status/control bits in PORTSC */
 340         writel(PORTSC_PTS_ULPI, USB_PORTSC);
 341
 342         writel(0x0, USB_AHBBURST);
 343         writel(0x08, USB_AHBMODE);
 344
 345         if (motg->phy_number)
 346                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 347         return 0;
 348 }
 349
 350 static void msm_phy_reset(struct msm_otg *motg)
 351 {
 352         void __iomem *addr;
 353
 354         if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
 355                 msm_otg_phy_clk_reset(motg);
 356                 return;
 357         }
 358
 359         addr = USB_PHY_CTRL;
 360         if (motg->phy_number)
 361                 addr = USB_PHY_CTRL2;
 362
 363         /* Assert USB PHY_POR */
 364         writel(readl(addr) | PHY_POR_ASSERT, addr);
 365
 366         /*
 367          * wait for minimum 10 microseconds as suggested in HPG.
 368          * Use a slightly larger value since the exact value didn't
 369          * work 100% of the time.
 370          */
 371         udelay(12);
 372
 373         /* Deassert USB PHY_POR */
 374         writel(readl(addr) & ~PHY_POR_ASSERT, addr);
 375 }
 376
 377 static int msm_usb_reset(struct usb_phy *phy)
 378 {
 379         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 380         int ret;
 381
 382         if (!IS_ERR(motg->core_clk))
 383                 clk_prepare_enable(motg->core_clk);
 384
 385         ret = msm_link_reset(motg);
 386         if (ret) {
 387                 dev_err(phy->dev, "phy_reset failed\n");
 388                 return ret;
 389         }
 390
 391         ret = msm_otg_reset(&motg->phy);
 392         if (ret) {
 393                 dev_err(phy->dev, "link reset failed\n");
 394                 return ret;
 395         }
 396
 397         msleep(100);
 398
 399         /* Reset USB PHY after performing USB Link RESET */
 400         msm_phy_reset(motg);
 401
 402         if (!IS_ERR(motg->core_clk))
 403                 clk_disable_unprepare(motg->core_clk);
 404
 405         return 0;
 406 }
 407
 408 static int msm_phy_init(struct usb_phy *phy)
 409 {
 410         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 411         struct msm_otg_platform_data *pdata = motg->pdata;
 412         u32 val, ulpi_val = 0;
 413
 414         /* Program USB PHY Override registers. */
 415         ulpi_init(motg);
 416
 417         /*
 418          * It is recommended in HPG to reset USB PHY after programming
 419          * USB PHY Override registers.
 420          */
 421         msm_phy_reset(motg);
 422
 423         if (pdata->otg_control == OTG_PHY_CONTROL) {
 424                 val = readl(USB_OTGSC);
 425                 if (pdata->mode == USB_DR_MODE_OTG) {
 426                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 427                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 428                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
 429                         ulpi_val = ULPI_INT_SESS_VALID;
 430                         val |= OTGSC_BSVIE;
 431                 }
 432                 writel(val, USB_OTGSC);
 433                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 434                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 435         }
 436
 437         if (motg->manual_pullup) {
 438                 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
 439                 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
 440
 441                 val = readl(USB_GENCONFIG_2);
 442                 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
 443                 writel(val, USB_GENCONFIG_2);
 444
 445                 val = readl(USB_USBCMD);
 446                 val |= USBCMD_SESS_VLD_CTRL;
 447                 writel(val, USB_USBCMD);
 448
 449                 val = ulpi_read(phy, ULPI_FUNC_CTRL);
 450                 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 451                 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
 452                 ulpi_write(phy, val, ULPI_FUNC_CTRL);
 453         }
 454
 455         if (motg->phy_number)
 456                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 457
 458         return 0;
 459 }
 460
 461 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 462 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 463
 464 #ifdef CONFIG_PM
 465
 466 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 467 {
 468         int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
 469         int min_vol;
 470         int ret;
 471
 472         if (high)
 473                 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
 474         else
 475                 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
 476
 477         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 478         if (ret) {
 479                 pr_err("Cannot set vddcx voltage\n");
 480                 return ret;
 481         }
 482
 483         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 484
 485         return ret;
 486 }
 487
 488 static int msm_otg_suspend(struct msm_otg *motg)
 489 {
 490         struct usb_phy *phy = &motg->phy;
 491         struct usb_bus *bus = phy->otg->host;
 492         struct msm_otg_platform_data *pdata = motg->pdata;
 493         void __iomem *addr;
 494         int cnt = 0;
 495
 496         if (atomic_read(&motg->in_lpm))
 497                 return 0;
 498
 499         disable_irq(motg->irq);
 500         /*
 501          * Chipidea 45-nm PHY suspend sequence:
 502          *
 503          * Interrupt Latch Register auto-clear feature is not present
 504          * in all PHY versions. Latch register is clear on read type.
 505          * Clear latch register to avoid spurious wakeup from
 506          * low power mode (LPM).
 507          *
 508          * PHY comparators are disabled when PHY enters into low power
 509          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 510          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 511          * PHY comparators. This save significant amount of power.
 512          *
 513          * PLL is not turned off when PHY enters into low power mode (LPM).
 514          * Disable PLL for maximum power savings.
 515          */
 516
 517         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 518                 ulpi_read(phy, 0x14);
 519                 if (pdata->otg_control == OTG_PHY_CONTROL)
 520                         ulpi_write(phy, 0x01, 0x30);
 521                 ulpi_write(phy, 0x08, 0x09);
 522         }
 523
 524         /*
 525          * PHY may take some time or even fail to enter into low power
 526          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 527          * in failure case.
 528          */
 529         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 530         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 531                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 532                         break;
 533                 udelay(1);
 534                 cnt++;
 535         }
 536
 537         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 538                 dev_err(phy->dev, "Unable to suspend PHY\n");
 539                 msm_otg_reset(phy);
 540                 enable_irq(motg->irq);
 541                 return -ETIMEDOUT;
 542         }
 543
 544         /*
 545          * PHY has capability to generate interrupt asynchronously in low
 546          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 547          * line must be disabled till async interrupt enable bit is cleared
 548          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 549          * block data communication from PHY.
 550          */
 551         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 552
 553         addr = USB_PHY_CTRL;
 554         if (motg->phy_number)
 555                 addr = USB_PHY_CTRL2;
 556
 557         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 558                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 559                 writel(readl(addr) | PHY_RETEN, addr);
 560
 561         clk_disable_unprepare(motg->pclk);
 562         clk_disable_unprepare(motg->clk);
 563         if (!IS_ERR(motg->core_clk))
 564                 clk_disable_unprepare(motg->core_clk);
 565
 566         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 567                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 568                 msm_hsusb_ldo_set_mode(motg, 0);
 569                 msm_hsusb_config_vddcx(motg, 0);
 570         }
 571
 572         if (device_may_wakeup(phy->dev))
 573                 enable_irq_wake(motg->irq);
 574         if (bus)
 575                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 576
 577         atomic_set(&motg->in_lpm, 1);
 578         enable_irq(motg->irq);
 579
 580         dev_info(phy->dev, "USB in low power mode\n");
 581
 582         return 0;
 583 }
 584
 585 static int msm_otg_resume(struct msm_otg *motg)
 586 {
 587         struct usb_phy *phy = &motg->phy;
 588         struct usb_bus *bus = phy->otg->host;
 589         void __iomem *addr;
 590         int cnt = 0;
 591         unsigned temp;
 592
 593         if (!atomic_read(&motg->in_lpm))
 594                 return 0;
 595
 596         clk_prepare_enable(motg->pclk);
 597         clk_prepare_enable(motg->clk);
 598         if (!IS_ERR(motg->core_clk))
 599                 clk_prepare_enable(motg->core_clk);
 600
 601         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 602                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 603
 604                 addr = USB_PHY_CTRL;
 605                 if (motg->phy_number)
 606                         addr = USB_PHY_CTRL2;
 607
 608                 msm_hsusb_ldo_set_mode(motg, 1);
 609                 msm_hsusb_config_vddcx(motg, 1);
 610                 writel(readl(addr) & ~PHY_RETEN, addr);
 611         }
 612
 613         temp = readl(USB_USBCMD);
 614         temp &= ~ASYNC_INTR_CTRL;
 615         temp &= ~ULPI_STP_CTRL;
 616         writel(temp, USB_USBCMD);
 617
 618         /*
 619          * PHY comes out of low power mode (LPM) in case of wakeup
 620          * from asynchronous interrupt.
 621          */
 622         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 623                 goto skip_phy_resume;
 624
 625         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 626         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 627                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 628                         break;
 629                 udelay(1);
 630                 cnt++;
 631         }
 632
 633         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 634                 /*
 635                  * This is a fatal error. Reset the link and
 636                  * PHY. USB state can not be restored. Re-insertion
 637                  * of USB cable is the only way to get USB working.
 638                  */
 639                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
 640                 msm_otg_reset(phy);
 641         }
 642
 643 skip_phy_resume:
 644         if (device_may_wakeup(phy->dev))
 645                 disable_irq_wake(motg->irq);
 646         if (bus)
 647                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 648
 649         atomic_set(&motg->in_lpm, 0);
 650
 651         if (motg->async_int) {
 652                 motg->async_int = 0;
 653                 pm_runtime_put(phy->dev);
 654                 enable_irq(motg->irq);
 655         }
 656
 657         dev_info(phy->dev, "USB exited from low power mode\n");
 658
 659         return 0;
 660 }
 661 #endif
 662
 663 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 664 {
 665         if (motg->cur_power == mA)
 666                 return;
 667
 668         /* TODO: Notify PMIC about available current */
 669         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 670         motg->cur_power = mA;
 671 }
 672
 673 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
 674 {
 675         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 676
 677         /*
 678          * Gadget driver uses set_power method to notify about the
 679          * available current based on suspend/configured states.
 680          *
 681          * IDEV_CHG can be drawn irrespective of suspend/un-configured
 682          * states when CDP/ACA is connected.
 683          */
 684         if (motg->chg_type == USB_SDP_CHARGER)
 685                 msm_otg_notify_charger(motg, mA);
 686
 687         return 0;
 688 }
 689
 690 static void msm_otg_start_host(struct usb_phy *phy, int on)
 691 {
 692         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 693         struct msm_otg_platform_data *pdata = motg->pdata;
 694         struct usb_hcd *hcd;
 695
 696         if (!phy->otg->host)
 697                 return;
 698
 699         hcd = bus_to_hcd(phy->otg->host);
 700
 701         if (on) {
 702                 dev_dbg(phy->dev, "host on\n");
 703
 704                 if (pdata->vbus_power)
 705                         pdata->vbus_power(1);
 706                 /*
 707                  * Some boards have a switch cotrolled by gpio
 708                  * to enable/disable internal HUB. Enable internal
 709                  * HUB before kicking the host.
 710                  */
 711                 if (pdata->setup_gpio)
 712                         pdata->setup_gpio(OTG_STATE_A_HOST);
 713 #ifdef CONFIG_USB
 714                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 715                 device_wakeup_enable(hcd->self.controller);
 716 #endif
 717         } else {
 718                 dev_dbg(phy->dev, "host off\n");
 719
 720 #ifdef CONFIG_USB
 721                 usb_remove_hcd(hcd);
 722 #endif
 723                 if (pdata->setup_gpio)
 724                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 725                 if (pdata->vbus_power)
 726                         pdata->vbus_power(0);
 727         }
 728 }
 729
 730 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 731 {
 732         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 733         struct usb_hcd *hcd;
 734
 735         /*
 736          * Fail host registration if this board can support
 737          * only peripheral configuration.
 738          */
 739         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
 740                 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
 741                 return -ENODEV;
 742         }
 743
 744         if (!host) {
 745                 if (otg->state == OTG_STATE_A_HOST) {
 746                         pm_runtime_get_sync(otg->usb_phy->dev);
 747                         msm_otg_start_host(otg->usb_phy, 0);
 748                         otg->host = NULL;
 749                         otg->state = OTG_STATE_UNDEFINED;
 750                         schedule_work(&motg->sm_work);
 751                 } else {
 752                         otg->host = NULL;
 753                 }
 754
 755                 return 0;
 756         }
 757
 758         hcd = bus_to_hcd(host);
 759         hcd->power_budget = motg->pdata->power_budget;
 760
 761         otg->host = host;
 762         dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
 763
 764         /*
 765          * Kick the state machine work, if peripheral is not supported
 766          * or peripheral is already registered with us.
 767          */
 768         if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
 769                 pm_runtime_get_sync(otg->usb_phy->dev);
 770                 schedule_work(&motg->sm_work);
 771         }
 772
 773         return 0;
 774 }
 775
 776 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 777 {
 778         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 779         struct msm_otg_platform_data *pdata = motg->pdata;
 780
 781         if (!phy->otg->gadget)
 782                 return;
 783
 784         if (on) {
 785                 dev_dbg(phy->dev, "gadget on\n");
 786                 /*
 787                  * Some boards have a switch cotrolled by gpio
 788                  * to enable/disable internal HUB. Disable internal
 789                  * HUB before kicking the gadget.
 790                  */
 791                 if (pdata->setup_gpio)
 792                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 793                 usb_gadget_vbus_connect(phy->otg->gadget);
 794         } else {
 795                 dev_dbg(phy->dev, "gadget off\n");
 796                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 797                 if (pdata->setup_gpio)
 798                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 799         }
 800
 801 }
 802
 803 static int msm_otg_set_peripheral(struct usb_otg *otg,
 804                                         struct usb_gadget *gadget)
 805 {
 806         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 807
 808         /*
 809          * Fail peripheral registration if this board can support
 810          * only host configuration.
 811          */
 812         if (motg->pdata->mode == USB_DR_MODE_HOST) {
 813                 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
 814                 return -ENODEV;
 815         }
 816
 817         if (!gadget) {
 818                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
 819                         pm_runtime_get_sync(otg->usb_phy->dev);
 820                         msm_otg_start_peripheral(otg->usb_phy, 0);
 821                         otg->gadget = NULL;
 822                         otg->state = OTG_STATE_UNDEFINED;
 823                         schedule_work(&motg->sm_work);
 824                 } else {
 825                         otg->gadget = NULL;
 826                 }
 827
 828                 return 0;
 829         }
 830         otg->gadget = gadget;
 831         dev_dbg(otg->usb_phy->dev,
 832                 "peripheral driver registered w/ tranceiver\n");
 833
 834         /*
 835          * Kick the state machine work, if host is not supported
 836          * or host is already registered with us.
 837          */
 838         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
 839                 pm_runtime_get_sync(otg->usb_phy->dev);
 840                 schedule_work(&motg->sm_work);
 841         }
 842
 843         return 0;
 844 }
 845
 846 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 847 {
 848         struct usb_phy *phy = &motg->phy;
 849         u32 chg_det;
 850         bool ret = false;
 851
 852         switch (motg->pdata->phy_type) {
 853         case CI_45NM_INTEGRATED_PHY:
 854                 chg_det = ulpi_read(phy, 0x34);
 855                 ret = chg_det & (1 << 4);
 856                 break;
 857         case SNPS_28NM_INTEGRATED_PHY:
 858                 chg_det = ulpi_read(phy, 0x87);
 859                 ret = chg_det & 1;
 860                 break;
 861         default:
 862                 break;
 863         }
 864         return ret;
 865 }
 866
 867 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 868 {
 869         struct usb_phy *phy = &motg->phy;
 870         u32 chg_det;
 871
 872         switch (motg->pdata->phy_type) {
 873         case CI_45NM_INTEGRATED_PHY:
 874                 chg_det = ulpi_read(phy, 0x34);
 875                 /* Turn off charger block */
 876                 chg_det |= ~(1 << 1);
 877                 ulpi_write(phy, chg_det, 0x34);
 878                 udelay(20);
 879                 /* control chg block via ULPI */
 880                 chg_det &= ~(1 << 3);
 881                 ulpi_write(phy, chg_det, 0x34);
 882                 /* put it in host mode for enabling D- source */
 883                 chg_det &= ~(1 << 2);
 884                 ulpi_write(phy, chg_det, 0x34);
 885                 /* Turn on chg detect block */
 886                 chg_det &= ~(1 << 1);
 887                 ulpi_write(phy, chg_det, 0x34);
 888                 udelay(20);
 889                 /* enable chg detection */
 890                 chg_det &= ~(1 << 0);
 891                 ulpi_write(phy, chg_det, 0x34);
 892                 break;
 893         case SNPS_28NM_INTEGRATED_PHY:
 894                 /*
 895                  * Configure DM as current source, DP as current sink
 896                  * and enable battery charging comparators.
 897                  */
 898                 ulpi_write(phy, 0x8, 0x85);
 899                 ulpi_write(phy, 0x2, 0x85);
 900                 ulpi_write(phy, 0x1, 0x85);
 901                 break;
 902         default:
 903                 break;
 904         }
 905 }
 906
 907 static bool msm_chg_check_primary_det(struct msm_otg *motg)
 908 {
 909         struct usb_phy *phy = &motg->phy;
 910         u32 chg_det;
 911         bool ret = false;
 912
 913         switch (motg->pdata->phy_type) {
 914         case CI_45NM_INTEGRATED_PHY:
 915                 chg_det = ulpi_read(phy, 0x34);
 916                 ret = chg_det & (1 << 4);
 917                 break;
 918         case SNPS_28NM_INTEGRATED_PHY:
 919                 chg_det = ulpi_read(phy, 0x87);
 920                 ret = chg_det & 1;
 921                 break;
 922         default:
 923                 break;
 924         }
 925         return ret;
 926 }
 927
 928 static void msm_chg_enable_primary_det(struct msm_otg *motg)
 929 {
 930         struct usb_phy *phy = &motg->phy;
 931         u32 chg_det;
 932
 933         switch (motg->pdata->phy_type) {
 934         case CI_45NM_INTEGRATED_PHY:
 935                 chg_det = ulpi_read(phy, 0x34);
 936                 /* enable chg detection */
 937                 chg_det &= ~(1 << 0);
 938                 ulpi_write(phy, chg_det, 0x34);
 939                 break;
 940         case SNPS_28NM_INTEGRATED_PHY:
 941                 /*
 942                  * Configure DP as current source, DM as current sink
 943                  * and enable battery charging comparators.
 944                  */
 945                 ulpi_write(phy, 0x2, 0x85);
 946                 ulpi_write(phy, 0x1, 0x85);
 947                 break;
 948         default:
 949                 break;
 950         }
 951 }
 952
 953 static bool msm_chg_check_dcd(struct msm_otg *motg)
 954 {
 955         struct usb_phy *phy = &motg->phy;
 956         u32 line_state;
 957         bool ret = false;
 958
 959         switch (motg->pdata->phy_type) {
 960         case CI_45NM_INTEGRATED_PHY:
 961                 line_state = ulpi_read(phy, 0x15);
 962                 ret = !(line_state & 1);
 963                 break;
 964         case SNPS_28NM_INTEGRATED_PHY:
 965                 line_state = ulpi_read(phy, 0x87);
 966                 ret = line_state & 2;
 967                 break;
 968         default:
 969                 break;
 970         }
 971         return ret;
 972 }
 973
 974 static void msm_chg_disable_dcd(struct msm_otg *motg)
 975 {
 976         struct usb_phy *phy = &motg->phy;
 977         u32 chg_det;
 978
 979         switch (motg->pdata->phy_type) {
 980         case CI_45NM_INTEGRATED_PHY:
 981                 chg_det = ulpi_read(phy, 0x34);
 982                 chg_det &= ~(1 << 5);
 983                 ulpi_write(phy, chg_det, 0x34);
 984                 break;
 985         case SNPS_28NM_INTEGRATED_PHY:
 986                 ulpi_write(phy, 0x10, 0x86);
 987                 break;
 988         default:
 989                 break;
 990         }
 991 }
 992
 993 static void msm_chg_enable_dcd(struct msm_otg *motg)
 994 {
 995         struct usb_phy *phy = &motg->phy;
 996         u32 chg_det;
 997
 998         switch (motg->pdata->phy_type) {
 999         case CI_45NM_INTEGRATED_PHY:
1000                 chg_det = ulpi_read(phy, 0x34);
1001                 /* Turn on D+ current source */
1002                 chg_det |= (1 << 5);
1003                 ulpi_write(phy, chg_det, 0x34);
1004                 break;
1005         case SNPS_28NM_INTEGRATED_PHY:
1006                 /* Data contact detection enable */
1007                 ulpi_write(phy, 0x10, 0x85);
1008                 break;
1009         default:
1010                 break;
1011         }
1012 }
1013
1014 static void msm_chg_block_on(struct msm_otg *motg)
1015 {
1016         struct usb_phy *phy = &motg->phy;
1017         u32 func_ctrl, chg_det;
1018
1019         /* put the controller in non-driving mode */
1020         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1021         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1022         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1023         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1024
1025         switch (motg->pdata->phy_type) {
1026         case CI_45NM_INTEGRATED_PHY:
1027                 chg_det = ulpi_read(phy, 0x34);
1028                 /* control chg block via ULPI */
1029                 chg_det &= ~(1 << 3);
1030                 ulpi_write(phy, chg_det, 0x34);
1031                 /* Turn on chg detect block */
1032                 chg_det &= ~(1 << 1);
1033                 ulpi_write(phy, chg_det, 0x34);
1034                 udelay(20);
1035                 break;
1036         case SNPS_28NM_INTEGRATED_PHY:
1037                 /* Clear charger detecting control bits */
1038                 ulpi_write(phy, 0x3F, 0x86);
1039                 /* Clear alt interrupt latch and enable bits */
1040                 ulpi_write(phy, 0x1F, 0x92);
1041                 ulpi_write(phy, 0x1F, 0x95);
1042                 udelay(100);
1043                 break;
1044         default:
1045                 break;
1046         }
1047 }
1048
1049 static void msm_chg_block_off(struct msm_otg *motg)
1050 {
1051         struct usb_phy *phy = &motg->phy;
1052         u32 func_ctrl, chg_det;
1053
1054         switch (motg->pdata->phy_type) {
1055         case CI_45NM_INTEGRATED_PHY:
1056                 chg_det = ulpi_read(phy, 0x34);
1057                 /* Turn off charger block */
1058                 chg_det |= ~(1 << 1);
1059                 ulpi_write(phy, chg_det, 0x34);
1060                 break;
1061         case SNPS_28NM_INTEGRATED_PHY:
1062                 /* Clear charger detecting control bits */
1063                 ulpi_write(phy, 0x3F, 0x86);
1064                 /* Clear alt interrupt latch and enable bits */
1065                 ulpi_write(phy, 0x1F, 0x92);
1066                 ulpi_write(phy, 0x1F, 0x95);
1067                 break;
1068         default:
1069                 break;
1070         }
1071
1072         /* put the controller in normal mode */
1073         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1074         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1075         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1076         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1077 }
1078
1079 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1080 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1081 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1082 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1083 static void msm_chg_detect_work(struct work_struct *w)
1084 {
1085         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1086         struct usb_phy *phy = &motg->phy;
1087         bool is_dcd, tmout, vout;
1088         unsigned long delay;
1089
1090         dev_dbg(phy->dev, "chg detection work\n");
1091         switch (motg->chg_state) {
1092         case USB_CHG_STATE_UNDEFINED:
1093                 pm_runtime_get_sync(phy->dev);
1094                 msm_chg_block_on(motg);
1095                 msm_chg_enable_dcd(motg);
1096                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1097                 motg->dcd_retries = 0;
1098                 delay = MSM_CHG_DCD_POLL_TIME;
1099                 break;
1100         case USB_CHG_STATE_WAIT_FOR_DCD:
1101                 is_dcd = msm_chg_check_dcd(motg);
1102                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1103                 if (is_dcd || tmout) {
1104                         msm_chg_disable_dcd(motg);
1105                         msm_chg_enable_primary_det(motg);
1106                         delay = MSM_CHG_PRIMARY_DET_TIME;
1107                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1108                 } else {
1109                         delay = MSM_CHG_DCD_POLL_TIME;
1110                 }
1111                 break;
1112         case USB_CHG_STATE_DCD_DONE:
1113                 vout = msm_chg_check_primary_det(motg);
1114                 if (vout) {
1115                         msm_chg_enable_secondary_det(motg);
1116                         delay = MSM_CHG_SECONDARY_DET_TIME;
1117                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1118                 } else {
1119                         motg->chg_type = USB_SDP_CHARGER;
1120                         motg->chg_state = USB_CHG_STATE_DETECTED;
1121                         delay = 0;
1122                 }
1123                 break;
1124         case USB_CHG_STATE_PRIMARY_DONE:
1125                 vout = msm_chg_check_secondary_det(motg);
1126                 if (vout)
1127                         motg->chg_type = USB_DCP_CHARGER;
1128                 else
1129                         motg->chg_type = USB_CDP_CHARGER;
1130                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1131                 /* fall through */
1132         case USB_CHG_STATE_SECONDARY_DONE:
1133                 motg->chg_state = USB_CHG_STATE_DETECTED;
1134         case USB_CHG_STATE_DETECTED:
1135                 msm_chg_block_off(motg);
1136                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1137                 schedule_work(&motg->sm_work);
1138                 return;
1139         default:
1140                 return;
1141         }
1142
1143         schedule_delayed_work(&motg->chg_work, delay);
1144 }
1145
1146 /*
1147  * We support OTG, Peripheral only and Host only configurations. In case
1148  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1149  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1150  * enabled when switch is controlled by user and default mode is supplied
1151  * by board file, which can be changed by userspace later.
1152  */
1153 static void msm_otg_init_sm(struct msm_otg *motg)
1154 {
1155         struct msm_otg_platform_data *pdata = motg->pdata;
1156         u32 otgsc = readl(USB_OTGSC);
1157
1158         switch (pdata->mode) {
1159         case USB_DR_MODE_OTG:
1160                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1161                         if (otgsc & OTGSC_ID)
1162                                 set_bit(ID, &motg->inputs);
1163                         else
1164                                 clear_bit(ID, &motg->inputs);
1165
1166                         if (otgsc & OTGSC_BSV)
1167                                 set_bit(B_SESS_VLD, &motg->inputs);
1168                         else
1169                                 clear_bit(B_SESS_VLD, &motg->inputs);
1170                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1171                                 set_bit(ID, &motg->inputs);
1172                                 clear_bit(B_SESS_VLD, &motg->inputs);
1173                 }
1174                 break;
1175         case USB_DR_MODE_HOST:
1176                 clear_bit(ID, &motg->inputs);
1177                 break;
1178         case USB_DR_MODE_PERIPHERAL:
1179                 set_bit(ID, &motg->inputs);
1180                 if (otgsc & OTGSC_BSV)
1181                         set_bit(B_SESS_VLD, &motg->inputs);
1182                 else
1183                         clear_bit(B_SESS_VLD, &motg->inputs);
1184                 break;
1185         default:
1186                 break;
1187         }
1188 }
1189
1190 static void msm_otg_sm_work(struct work_struct *w)
1191 {
1192         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1193         struct usb_otg *otg = motg->phy.otg;
1194
1195         switch (otg->state) {
1196         case OTG_STATE_UNDEFINED:
1197                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1198                 msm_otg_reset(otg->usb_phy);
1199                 msm_otg_init_sm(motg);
1200                 otg->state = OTG_STATE_B_IDLE;
1201                 /* FALL THROUGH */
1202         case OTG_STATE_B_IDLE:
1203                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1204                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1205                         /* disable BSV bit */
1206                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1207                         msm_otg_start_host(otg->usb_phy, 1);
1208                         otg->state = OTG_STATE_A_HOST;
1209                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1210                         switch (motg->chg_state) {
1211                         case USB_CHG_STATE_UNDEFINED:
1212                                 msm_chg_detect_work(&motg->chg_work.work);
1213                                 break;
1214                         case USB_CHG_STATE_DETECTED:
1215                                 switch (motg->chg_type) {
1216                                 case USB_DCP_CHARGER:
1217                                         msm_otg_notify_charger(motg,
1218                                                         IDEV_CHG_MAX);
1219                                         break;
1220                                 case USB_CDP_CHARGER:
1221                                         msm_otg_notify_charger(motg,
1222                                                         IDEV_CHG_MAX);
1223                                         msm_otg_start_peripheral(otg->usb_phy,
1224                                                                  1);
1225                                         otg->state
1226                                                 = OTG_STATE_B_PERIPHERAL;
1227                                         break;
1228                                 case USB_SDP_CHARGER:
1229                                         msm_otg_notify_charger(motg, IUNIT);
1230                                         msm_otg_start_peripheral(otg->usb_phy,
1231                                                                  1);
1232                                         otg->state
1233                                                 = OTG_STATE_B_PERIPHERAL;
1234                                         break;
1235                                 default:
1236                                         break;
1237                                 }
1238                                 break;
1239                         default:
1240                                 break;
1241                         }
1242                 } else {
1243                         /*
1244                          * If charger detection work is pending, decrement
1245                          * the pm usage counter to balance with the one that
1246                          * is incremented in charger detection work.
1247                          */
1248                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1249                                 pm_runtime_put_sync(otg->usb_phy->dev);
1250                                 msm_otg_reset(otg->usb_phy);
1251                         }
1252                         msm_otg_notify_charger(motg, 0);
1253                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1254                         motg->chg_type = USB_INVALID_CHARGER;
1255                 }
1256
1257                 if (otg->state == OTG_STATE_B_IDLE)
1258                         pm_runtime_put_sync(otg->usb_phy->dev);
1259                 break;
1260         case OTG_STATE_B_PERIPHERAL:
1261                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1262                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1263                                 !test_bit(ID, &motg->inputs)) {
1264                         msm_otg_notify_charger(motg, 0);
1265                         msm_otg_start_peripheral(otg->usb_phy, 0);
1266                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1267                         motg->chg_type = USB_INVALID_CHARGER;
1268                         otg->state = OTG_STATE_B_IDLE;
1269                         msm_otg_reset(otg->usb_phy);
1270                         schedule_work(w);
1271                 }
1272                 break;
1273         case OTG_STATE_A_HOST:
1274                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1275                 if (test_bit(ID, &motg->inputs)) {
1276                         msm_otg_start_host(otg->usb_phy, 0);
1277                         otg->state = OTG_STATE_B_IDLE;
1278                         msm_otg_reset(otg->usb_phy);
1279                         schedule_work(w);
1280                 }
1281                 break;
1282         default:
1283                 break;
1284         }
1285 }
1286
1287 static irqreturn_t msm_otg_irq(int irq, void *data)
1288 {
1289         struct msm_otg *motg = data;
1290         struct usb_phy *phy = &motg->phy;
1291         u32 otgsc = 0;
1292
1293         if (atomic_read(&motg->in_lpm)) {
1294                 disable_irq_nosync(irq);
1295                 motg->async_int = 1;
1296                 pm_runtime_get(phy->dev);
1297                 return IRQ_HANDLED;
1298         }
1299
1300         otgsc = readl(USB_OTGSC);
1301         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1302                 return IRQ_NONE;
1303
1304         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1305                 if (otgsc & OTGSC_ID)
1306                         set_bit(ID, &motg->inputs);
1307                 else
1308                         clear_bit(ID, &motg->inputs);
1309                 dev_dbg(phy->dev, "ID set/clear\n");
1310                 pm_runtime_get_noresume(phy->dev);
1311         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1312                 if (otgsc & OTGSC_BSV)
1313                         set_bit(B_SESS_VLD, &motg->inputs);
1314                 else
1315                         clear_bit(B_SESS_VLD, &motg->inputs);
1316                 dev_dbg(phy->dev, "BSV set/clear\n");
1317                 pm_runtime_get_noresume(phy->dev);
1318         }
1319
1320         writel(otgsc, USB_OTGSC);
1321         schedule_work(&motg->sm_work);
1322         return IRQ_HANDLED;
1323 }
1324
1325 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1326 {
1327         struct msm_otg *motg = s->private;
1328         struct usb_otg *otg = motg->phy.otg;
1329
1330         switch (otg->state) {
1331         case OTG_STATE_A_HOST:
1332                 seq_puts(s, "host\n");
1333                 break;
1334         case OTG_STATE_B_PERIPHERAL:
1335                 seq_puts(s, "peripheral\n");
1336                 break;
1337         default:
1338                 seq_puts(s, "none\n");
1339                 break;
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1346 {
1347         return single_open(file, msm_otg_mode_show, inode->i_private);
1348 }
1349
1350 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1351                                 size_t count, loff_t *ppos)
1352 {
1353         struct seq_file *s = file->private_data;
1354         struct msm_otg *motg = s->private;
1355         char buf[16];
1356         struct usb_otg *otg = motg->phy.otg;
1357         int status = count;
1358         enum usb_dr_mode req_mode;
1359
1360         memset(buf, 0x00, sizeof(buf));
1361
1362         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1363                 status = -EFAULT;
1364                 goto out;
1365         }
1366
1367         if (!strncmp(buf, "host", 4)) {
1368                 req_mode = USB_DR_MODE_HOST;
1369         } else if (!strncmp(buf, "peripheral", 10)) {
1370                 req_mode = USB_DR_MODE_PERIPHERAL;
1371         } else if (!strncmp(buf, "none", 4)) {
1372                 req_mode = USB_DR_MODE_UNKNOWN;
1373         } else {
1374                 status = -EINVAL;
1375                 goto out;
1376         }
1377
1378         switch (req_mode) {
1379         case USB_DR_MODE_UNKNOWN:
1380                 switch (otg->state) {
1381                 case OTG_STATE_A_HOST:
1382                 case OTG_STATE_B_PERIPHERAL:
1383                         set_bit(ID, &motg->inputs);
1384                         clear_bit(B_SESS_VLD, &motg->inputs);
1385                         break;
1386                 default:
1387                         goto out;
1388                 }
1389                 break;
1390         case USB_DR_MODE_PERIPHERAL:
1391                 switch (otg->state) {
1392                 case OTG_STATE_B_IDLE:
1393                 case OTG_STATE_A_HOST:
1394                         set_bit(ID, &motg->inputs);
1395                         set_bit(B_SESS_VLD, &motg->inputs);
1396                         break;
1397                 default:
1398                         goto out;
1399                 }
1400                 break;
1401         case USB_DR_MODE_HOST:
1402                 switch (otg->state) {
1403                 case OTG_STATE_B_IDLE:
1404                 case OTG_STATE_B_PERIPHERAL:
1405                         clear_bit(ID, &motg->inputs);
1406                         break;
1407                 default:
1408                         goto out;
1409                 }
1410                 break;
1411         default:
1412                 goto out;
1413         }
1414
1415         pm_runtime_get_sync(otg->usb_phy->dev);
1416         schedule_work(&motg->sm_work);
1417 out:
1418         return status;
1419 }
1420
1421 static const struct file_operations msm_otg_mode_fops = {
1422         .open = msm_otg_mode_open,
1423         .read = seq_read,
1424         .write = msm_otg_mode_write,
1425         .llseek = seq_lseek,
1426         .release = single_release,
1427 };
1428
1429 static struct dentry *msm_otg_dbg_root;
1430 static struct dentry *msm_otg_dbg_mode;
1431
1432 static int msm_otg_debugfs_init(struct msm_otg *motg)
1433 {
1434         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1435
1436         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1437                 return -ENODEV;
1438
1439         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1440                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1441         if (!msm_otg_dbg_mode) {
1442                 debugfs_remove(msm_otg_dbg_root);
1443                 msm_otg_dbg_root = NULL;
1444                 return -ENODEV;
1445         }
1446
1447         return 0;
1448 }
1449
1450 static void msm_otg_debugfs_cleanup(void)
1451 {
1452         debugfs_remove(msm_otg_dbg_mode);
1453         debugfs_remove(msm_otg_dbg_root);
1454 }
1455
1456 static const struct of_device_id msm_otg_dt_match[] = {
1457         {
1458                 .compatible = "qcom,usb-otg-ci",
1459                 .data = (void *) CI_45NM_INTEGRATED_PHY
1460         },
1461         {
1462                 .compatible = "qcom,usb-otg-snps",
1463                 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1464         },
1465         { }
1466 };
1467 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1468
1469 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1470                                 void *ptr)
1471 {
1472         struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb);
1473         struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus);
1474
1475         if (event)
1476                 set_bit(B_SESS_VLD, &motg->inputs);
1477         else
1478                 clear_bit(B_SESS_VLD, &motg->inputs);
1479
1480         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1481                 /* Switch D+/D- lines to Device connector */
1482                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1483         } else {
1484                 /* Switch D+/D- lines to Hub */
1485                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1486         }
1487
1488         schedule_work(&motg->sm_work);
1489
1490         return NOTIFY_DONE;
1491 }
1492
1493 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1494                                 void *ptr)
1495 {
1496         struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb);
1497         struct msm_otg *motg = container_of(id, struct msm_otg, id);
1498
1499         if (event)
1500                 clear_bit(ID, &motg->inputs);
1501         else
1502                 set_bit(ID, &motg->inputs);
1503
1504         schedule_work(&motg->sm_work);
1505
1506         return NOTIFY_DONE;
1507 }
1508
1509 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1510 {
1511         struct msm_otg_platform_data *pdata;
1512         struct extcon_dev *ext_id, *ext_vbus;
1513         struct device_node *node = pdev->dev.of_node;
1514         struct property *prop;
1515         int len, ret, words;
1516         u32 val, tmp[3];
1517
1518         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1519         if (!pdata)
1520                 return -ENOMEM;
1521
1522         motg->pdata = pdata;
1523
1524         pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1525         if (!pdata->phy_type)
1526                 return 1;
1527
1528         motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1529         if (IS_ERR(motg->link_rst))
1530                 return PTR_ERR(motg->link_rst);
1531
1532         motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1533         if (IS_ERR(motg->phy_rst))
1534                 motg->phy_rst = NULL;
1535
1536         pdata->mode = usb_get_dr_mode(&pdev->dev);
1537         if (pdata->mode == USB_DR_MODE_UNKNOWN)
1538                 pdata->mode = USB_DR_MODE_OTG;
1539
1540         pdata->otg_control = OTG_PHY_CONTROL;
1541         if (!of_property_read_u32(node, "qcom,otg-control", &val))
1542                 if (val == OTG_PMIC_CONTROL)
1543                         pdata->otg_control = val;
1544
1545         if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1546                 motg->phy_number = val;
1547
1548         motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1549         motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1550         motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1551
1552         if (of_get_property(node, "qcom,vdd-levels", &len) &&
1553             len == sizeof(tmp)) {
1554                 of_property_read_u32_array(node, "qcom,vdd-levels",
1555                                            tmp, len / sizeof(*tmp));
1556                 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1557                 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1558                 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1559         }
1560
1561         motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1562
1563         motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1564                                                     GPIOD_OUT_LOW);
1565         if (IS_ERR(motg->switch_gpio))
1566                 return PTR_ERR(motg->switch_gpio);
1567
1568         ext_id = ERR_PTR(-ENODEV);
1569         ext_vbus = ERR_PTR(-ENODEV);
1570         if (of_property_read_bool(node, "extcon")) {
1571
1572                 /* Each one of them is not mandatory */
1573                 ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0);
1574                 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
1575                         return PTR_ERR(ext_vbus);
1576
1577                 ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1);
1578                 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
1579                         return PTR_ERR(ext_id);
1580         }
1581
1582         if (!IS_ERR(ext_vbus)) {
1583                 motg->vbus.extcon = ext_vbus;
1584                 motg->vbus.nb.notifier_call = msm_otg_vbus_notifier;
1585                 ret = extcon_register_notifier(ext_vbus, EXTCON_USB,
1586                                                 &motg->vbus.nb);
1587                 if (ret < 0) {
1588                         dev_err(&pdev->dev, "register VBUS notifier failed\n");
1589                         return ret;
1590                 }
1591
1592                 ret = extcon_get_cable_state_(ext_vbus, EXTCON_USB);
1593                 if (ret)
1594                         set_bit(B_SESS_VLD, &motg->inputs);
1595                 else
1596                         clear_bit(B_SESS_VLD, &motg->inputs);
1597         }
1598
1599         if (!IS_ERR(ext_id)) {
1600                 motg->id.extcon = ext_id;
1601                 motg->id.nb.notifier_call = msm_otg_id_notifier;
1602                 ret = extcon_register_notifier(ext_id, EXTCON_USB_HOST,
1603                                                 &motg->id.nb);
1604                 if (ret < 0) {
1605                         dev_err(&pdev->dev, "register ID notifier failed\n");
1606                         extcon_unregister_notifier(motg->vbus.extcon,
1607                                                    EXTCON_USB, &motg->vbus.nb);
1608                         return ret;
1609                 }
1610
1611                 ret = extcon_get_cable_state_(ext_id, EXTCON_USB_HOST);
1612                 if (ret)
1613                         clear_bit(ID, &motg->inputs);
1614                 else
1615                         set_bit(ID, &motg->inputs);
1616         }
1617
1618         prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1619         if (!prop || !len)
1620                 return 0;
1621
1622         words = len / sizeof(u32);
1623
1624         if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1625                 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1626                 return 0;
1627         }
1628
1629         pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1630         if (!pdata->phy_init_seq)
1631                 return 0;
1632
1633         ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1634                                          pdata->phy_init_seq, words);
1635         if (!ret)
1636                 pdata->phy_init_sz = words;
1637
1638         return 0;
1639 }
1640
1641 static int msm_otg_reboot_notify(struct notifier_block *this,
1642                                  unsigned long code, void *unused)
1643 {
1644         struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1645
1646         /*
1647          * Ensure that D+/D- lines are routed to uB connector, so
1648          * we could load bootloader/kernel at next reboot
1649          */
1650         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1651         return NOTIFY_DONE;
1652 }
1653
1654 static void msm_otg_bus_vote(struct msm_otg *motg, enum usb_bus_vote vote)
1655 {
1656         int ret;
1657
1658         if (motg->bus_perf_client) {
1659                 ret = msm_bus_scale_client_update_request(
1660                                 motg->bus_perf_client, vote);
1661                 if (ret)
1662                         dev_err(motg->phy.dev, "%s: Failed to vote (%d)\n"
1663                                         "for bus bw %d\n", __func__, vote, ret);
1664         }
1665 }
1666
1667 static int msm_otg_probe(struct platform_device *pdev)
1668 {
1669         struct regulator_bulk_data regs[2];
1670         int ret = 0;
1671         struct device_node *np = pdev->dev.of_node;
1672         struct msm_otg_platform_data *pdata;
1673         struct resource *res;
1674         struct msm_otg *motg;
1675         struct usb_phy *phy;
1676         void __iomem *phy_select;
1677
1678         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1679         if (!motg)
1680                 return -ENOMEM;
1681
1682         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1683                                      GFP_KERNEL);
1684         if (!motg->phy.otg)
1685                 return -ENOMEM;
1686
1687         phy = &motg->phy;
1688         phy->dev = &pdev->dev;
1689         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1690         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1691
1692         motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1693         if (IS_ERR(motg->clk)) {
1694                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1695                 return PTR_ERR(motg->clk);
1696         }
1697
1698         /*
1699          * If USB Core is running its protocol engine based on CORE CLK,
1700          * CORE CLK  must be running at >55Mhz for correct HSUSB
1701          * operation and USB core cannot tolerate frequency changes on
1702          * CORE CLK.
1703          */
1704         motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1705         if (IS_ERR(motg->pclk)) {
1706                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1707                 return PTR_ERR(motg->pclk);
1708         }
1709
1710         /*
1711          * USB core clock is not present on all MSM chips. This
1712          * clock is introduced to remove the dependency on AXI
1713          * bus frequency.
1714          */
1715         motg->core_clk = devm_clk_get(&pdev->dev,
1716                                       np ? "alt_core" : "usb_hs_core_clk");
1717
1718         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1719         if (!res)
1720                 return -EINVAL;
1721         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1722         if (!motg->regs)
1723                 return -ENOMEM;
1724
1725         pdata = dev_get_platdata(&pdev->dev);
1726         if (!pdata) {
1727                 if (!np)
1728                         return -ENXIO;
1729                 ret = msm_otg_read_dt(pdev, motg);
1730                 if (ret)
1731                         return ret;
1732         }
1733
1734         /*
1735          * NOTE: The PHYs can be multiplexed between the chipidea controller
1736          * and the dwc3 controller, using a single bit. It is important that
1737          * the dwc3 driver does not set this bit in an incompatible way.
1738          */
1739         if (motg->phy_number) {
1740                 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1741                 if (!phy_select) {
1742                         ret = -ENOMEM;
1743                         goto unregister_extcon;
1744                 }
1745                 /* Enable second PHY with the OTG port */
1746                 writel(0x1, phy_select);
1747         }
1748
1749         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1750
1751         motg->irq = platform_get_irq(pdev, 0);
1752         if (motg->irq < 0) {
1753                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1754                 ret = motg->irq;
1755                 goto unregister_extcon;
1756         }
1757
1758         regs[0].supply = "v3p3";
1759         regs[1].supply = "v1p8";
1760
1761         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1762         if (ret) {
1763                 dev_err(&pdev->dev, "no v3p3 or v1p8\n");
1764                 goto unregister_extcon;
1765         }
1766
1767         motg->v3p3  = regs[0].consumer;
1768         motg->v1p8  = regs[1].consumer;
1769
1770         motg->vddcx = devm_regulator_get_optional(motg->phy.dev, "vddcx");
1771         if (IS_ERR(motg->vddcx))
1772                 dev_info(&pdev->dev, "no vddcx\n");
1773
1774         clk_set_rate(motg->clk, 60000000);
1775
1776         clk_prepare_enable(motg->clk);
1777         clk_prepare_enable(motg->pclk);
1778
1779         if (!IS_ERR(motg->core_clk))
1780                 clk_prepare_enable(motg->core_clk);
1781
1782         ret = msm_hsusb_init_vddcx(motg, 1);
1783         if (ret) {
1784                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1785                 goto disable_clks;
1786         }
1787
1788         ret = msm_hsusb_ldo_init(motg, 1);
1789         if (ret) {
1790                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1791                 goto disable_vddcx;
1792         }
1793         ret = msm_hsusb_ldo_set_mode(motg, 1);
1794         if (ret) {
1795                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1796                 goto disable_ldo;
1797         }
1798
1799         writel(0, USB_USBINTR);
1800         writel(0, USB_OTGSC);
1801
1802         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1803                                         "msm_otg", motg);
1804         if (ret) {
1805                 dev_err(&pdev->dev, "request irq failed\n");
1806                 goto disable_ldo;
1807         }
1808
1809         phy->init = msm_phy_init;
1810         phy->set_power = msm_otg_set_power;
1811         phy->notify_disconnect = msm_phy_notify_disconnect;
1812         phy->type = USB_PHY_TYPE_USB2;
1813
1814         phy->io_ops = &msm_otg_io_ops;
1815
1816         phy->otg->usb_phy = &motg->phy;
1817         phy->otg->set_host = msm_otg_set_host;
1818         phy->otg->set_peripheral = msm_otg_set_peripheral;
1819
1820         msm_usb_reset(phy);
1821
1822         ret = usb_add_phy_dev(&motg->phy);
1823         if (ret) {
1824                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1825                 goto disable_ldo;
1826         }
1827
1828         motg->pdata->bus_scale_table = msm_bus_cl_get_pdata(pdev);
1829         if (!motg->pdata->bus_scale_table)
1830                 dev_dbg(&pdev->dev, "bus scaling is disabled\n");
1831         else {
1832                 motg->bus_perf_client =
1833                         msm_bus_scale_register_client(motg->pdata->bus_scale_table);
1834                 if (!motg->bus_perf_client)
1835                         dev_err(motg->phy.dev, "%s: Failed to register BUS\n"
1836                                         "scaling client!!\n", __func__);
1837         }
1838         /* Hack to max out usb performace */
1839         msm_otg_bus_vote(motg, USB_MAX_PERF_VOTE);
1840
1841         platform_set_drvdata(pdev, motg);
1842         device_init_wakeup(&pdev->dev, 1);
1843
1844         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1845                 motg->pdata->otg_control == OTG_USER_CONTROL) {
1846                 ret = msm_otg_debugfs_init(motg);
1847                 if (ret)
1848                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1849         }
1850
1851         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1852                 /* Switch D+/D- lines to Device connector */
1853                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1854         } else {
1855                 /* Switch D+/D- lines to Hub */
1856                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1857         }
1858
1859         motg->reboot.notifier_call = msm_otg_reboot_notify;
1860         register_reboot_notifier(&motg->reboot);
1861
1862         pm_runtime_set_active(&pdev->dev);
1863
1864         return 0;
1865
1866 disable_ldo:
1867         msm_hsusb_ldo_init(motg, 0);
1868 disable_vddcx:
1869         msm_hsusb_init_vddcx(motg, 0);
1870 disable_clks:
1871         clk_disable_unprepare(motg->pclk);
1872         clk_disable_unprepare(motg->clk);
1873         if (!IS_ERR(motg->core_clk))
1874                 clk_disable_unprepare(motg->core_clk);
1875 unregister_extcon:
1876         extcon_unregister_notifier(motg->id.extcon,
1877                                    EXTCON_USB_HOST, &motg->id.nb);
1878         extcon_unregister_notifier(motg->vbus.extcon,
1879                                    EXTCON_USB, &motg->vbus.nb);
1880
1881         return ret;
1882 }
1883
1884 static int msm_otg_remove(struct platform_device *pdev)
1885 {
1886         struct msm_otg *motg = platform_get_drvdata(pdev);
1887         struct usb_phy *phy = &motg->phy;
1888         int cnt = 0;
1889
1890         if (phy->otg->host || phy->otg->gadget)
1891                 return -EBUSY;
1892
1893         unregister_reboot_notifier(&motg->reboot);
1894
1895         /*
1896          * Ensure that D+/D- lines are routed to uB connector, so
1897          * we could load bootloader/kernel at next reboot
1898          */
1899         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1900
1901         extcon_unregister_notifier(motg->id.extcon, EXTCON_USB_HOST, &motg->id.nb);
1902         extcon_unregister_notifier(motg->vbus.extcon, EXTCON_USB, &motg->vbus.nb);
1903
1904         msm_otg_debugfs_cleanup();
1905         cancel_delayed_work_sync(&motg->chg_work);
1906         cancel_work_sync(&motg->sm_work);
1907
1908         pm_runtime_resume(&pdev->dev);
1909
1910         device_init_wakeup(&pdev->dev, 0);
1911         pm_runtime_disable(&pdev->dev);
1912
1913         usb_remove_phy(phy);
1914         disable_irq(motg->irq);
1915         msm_bus_scale_unregister_client(motg->bus_perf_client);
1916
1917         /*
1918          * Put PHY in low power mode.
1919          */
1920         ulpi_read(phy, 0x14);
1921         ulpi_write(phy, 0x08, 0x09);
1922
1923         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1924         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1925                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1926                         break;
1927                 udelay(1);
1928                 cnt++;
1929         }
1930         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1931                 dev_err(phy->dev, "Unable to suspend PHY\n");
1932
1933         clk_disable_unprepare(motg->pclk);
1934         clk_disable_unprepare(motg->clk);
1935         if (!IS_ERR(motg->core_clk))
1936                 clk_disable_unprepare(motg->core_clk);
1937         msm_hsusb_ldo_init(motg, 0);
1938
1939         pm_runtime_set_suspended(&pdev->dev);
1940
1941         return 0;
1942 }
1943
1944 #ifdef CONFIG_PM
1945 static int msm_otg_runtime_idle(struct device *dev)
1946 {
1947         struct msm_otg *motg = dev_get_drvdata(dev);
1948         struct usb_otg *otg = motg->phy.otg;
1949
1950         dev_dbg(dev, "OTG runtime idle\n");
1951
1952         /*
1953          * It is observed some times that a spurious interrupt
1954          * comes when PHY is put into LPM immediately after PHY reset.
1955          * This 1 sec delay also prevents entering into LPM immediately
1956          * after asynchronous interrupt.
1957          */
1958         if (otg->state != OTG_STATE_UNDEFINED)
1959                 pm_schedule_suspend(dev, 1000);
1960
1961         return -EAGAIN;
1962 }
1963
1964 static int msm_otg_runtime_suspend(struct device *dev)
1965 {
1966         struct msm_otg *motg = dev_get_drvdata(dev);
1967
1968         dev_dbg(dev, "OTG runtime suspend\n");
1969         return msm_otg_suspend(motg);
1970 }
1971
1972 static int msm_otg_runtime_resume(struct device *dev)
1973 {
1974         struct msm_otg *motg = dev_get_drvdata(dev);
1975
1976         dev_dbg(dev, "OTG runtime resume\n");
1977         return msm_otg_resume(motg);
1978 }
1979 #endif
1980
1981 #ifdef CONFIG_PM_SLEEP
1982 static int msm_otg_pm_suspend(struct device *dev)
1983 {
1984         struct msm_otg *motg = dev_get_drvdata(dev);
1985
1986         dev_dbg(dev, "OTG PM suspend\n");
1987         return msm_otg_suspend(motg);
1988 }
1989
1990 static int msm_otg_pm_resume(struct device *dev)
1991 {
1992         struct msm_otg *motg = dev_get_drvdata(dev);
1993         int ret;
1994
1995         dev_dbg(dev, "OTG PM resume\n");
1996
1997         ret = msm_otg_resume(motg);
1998         if (ret)
1999                 return ret;
2000
2001         /*
2002          * Runtime PM Documentation recommends bringing the
2003          * device to full powered state upon resume.
2004          */
2005         pm_runtime_disable(dev);
2006         pm_runtime_set_active(dev);
2007         pm_runtime_enable(dev);
2008
2009         return 0;
2010 }
2011 #endif
2012
2013 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
2014         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
2015         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
2016                                 msm_otg_runtime_idle)
2017 };
2018
2019 static struct platform_driver msm_otg_driver = {
2020         .probe = msm_otg_probe,
2021         .remove = msm_otg_remove,
2022         .driver = {
2023                 .name = DRIVER_NAME,
2024                 .pm = &msm_otg_dev_pm_ops,
2025                 .of_match_table = msm_otg_dt_match,
2026         },
2027 };
2028
2029 module_platform_driver(msm_otg_driver);
2030
2031 MODULE_LICENSE("GPL v2");
2032 MODULE_DESCRIPTION("MSM USB transceiver driver");