2 * Copyright (C) 2010 Google, Inc.
3 * Copyright (C) 2013 NVIDIA Corporation
6 * Erik Gilling <konkers@google.com>
7 * Benoit Goby <benoit@android.com>
8 * Venu Byravarasu <vbyravarasu@nvidia.com>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/resource.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/export.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/gpio.h>
31 #include <linux/of_gpio.h>
32 #include <linux/usb/otg.h>
33 #include <linux/usb/ulpi.h>
34 #include <linux/usb/of.h>
35 #include <asm/mach-types.h>
36 #include <linux/usb/ehci_def.h>
37 #include <linux/usb/tegra_usb_phy.h>
38 #include <linux/regulator/consumer.h>
40 #define ULPI_VIEWPORT 0x170
42 /* PORTSC registers */
43 #define TEGRA_USB_PORTSC1 0x184
44 #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
45 #define TEGRA_USB_PORTSC1_PHCD (1 << 23)
47 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
48 #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
50 #define USB_SUSP_CTRL 0x400
51 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
52 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
53 #define USB_SUSP_CLR (1 << 5)
54 #define USB_PHY_CLK_VALID (1 << 7)
55 #define UTMIP_RESET (1 << 11)
56 #define UHSIC_RESET (1 << 11)
57 #define UTMIP_PHY_ENABLE (1 << 12)
58 #define ULPI_PHY_ENABLE (1 << 13)
59 #define USB_SUSP_SET (1 << 14)
60 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
62 #define USB1_LEGACY_CTRL 0x410
63 #define USB1_NO_LEGACY_MODE (1 << 0)
64 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
65 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
66 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
68 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
69 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
71 #define ULPI_TIMING_CTRL_0 0x424
72 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
73 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
75 #define ULPI_TIMING_CTRL_1 0x428
76 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
77 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
78 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
79 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
80 #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
81 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
83 #define UTMIP_PLL_CFG1 0x804
84 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
85 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
87 #define UTMIP_XCVR_CFG0 0x808
88 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
89 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
90 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
91 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
92 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
93 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
94 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
96 #define UTMIP_BIAS_CFG0 0x80c
97 #define UTMIP_OTGPD (1 << 11)
98 #define UTMIP_BIASPD (1 << 10)
100 #define UTMIP_HSRX_CFG0 0x810
101 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
102 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
104 #define UTMIP_HSRX_CFG1 0x814
105 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
107 #define UTMIP_TX_CFG0 0x820
108 #define UTMIP_FS_PREABMLE_J (1 << 19)
109 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
111 #define UTMIP_MISC_CFG0 0x824
112 #define UTMIP_DPDM_OBSERVE (1 << 26)
113 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
114 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
115 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
116 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
117 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
118 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
120 #define UTMIP_MISC_CFG1 0x828
121 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
122 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
124 #define UTMIP_DEBOUNCE_CFG0 0x82c
125 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
127 #define UTMIP_BAT_CHRG_CFG0 0x830
128 #define UTMIP_PD_CHRG (1 << 0)
130 #define UTMIP_SPARE_CFG0 0x834
131 #define FUSE_SETUP_SEL (1 << 3)
133 #define UTMIP_XCVR_CFG1 0x838
134 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
135 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
136 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
137 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
139 #define UTMIP_BIAS_CFG1 0x83c
140 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
142 static DEFINE_SPINLOCK(utmip_pad_lock);
143 static int utmip_pad_count;
145 struct tegra_xtal_freq {
154 static const struct tegra_xtal_freq tegra_freq_table[] = {
157 .enable_delay = 0x02,
158 .stable_count = 0x2F,
159 .active_delay = 0x04,
160 .xtal_freq_count = 0x76,
165 .enable_delay = 0x02,
166 .stable_count = 0x33,
167 .active_delay = 0x05,
168 .xtal_freq_count = 0x7F,
173 .enable_delay = 0x03,
174 .stable_count = 0x4B,
175 .active_delay = 0x06,
176 .xtal_freq_count = 0xBB,
181 .enable_delay = 0x04,
182 .stable_count = 0x66,
183 .active_delay = 0x09,
184 .xtal_freq_count = 0xFE,
189 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
191 void __iomem *base = phy->regs;
194 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
195 val &= ~TEGRA_USB_PORTSC1_PTS(3);
196 val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
197 writel(val, base + TEGRA_USB_PORTSC1);
200 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
202 void __iomem *base = phy->regs;
205 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
207 val |= TEGRA_USB_PORTSC1_PHCD;
209 val &= ~TEGRA_USB_PORTSC1_PHCD;
210 writel(val, base + TEGRA_USB_PORTSC1);
213 static int utmip_pad_open(struct tegra_usb_phy *phy)
215 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
216 if (IS_ERR(phy->pad_clk)) {
217 pr_err("%s: can't get utmip pad clock\n", __func__);
218 return PTR_ERR(phy->pad_clk);
224 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
226 unsigned long val, flags;
227 void __iomem *base = phy->pad_regs;
229 clk_prepare_enable(phy->pad_clk);
231 spin_lock_irqsave(&utmip_pad_lock, flags);
233 if (utmip_pad_count++ == 0) {
234 val = readl(base + UTMIP_BIAS_CFG0);
235 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
236 writel(val, base + UTMIP_BIAS_CFG0);
239 spin_unlock_irqrestore(&utmip_pad_lock, flags);
241 clk_disable_unprepare(phy->pad_clk);
244 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
246 unsigned long val, flags;
247 void __iomem *base = phy->pad_regs;
249 if (!utmip_pad_count) {
250 pr_err("%s: utmip pad already powered off\n", __func__);
254 clk_prepare_enable(phy->pad_clk);
256 spin_lock_irqsave(&utmip_pad_lock, flags);
258 if (--utmip_pad_count == 0) {
259 val = readl(base + UTMIP_BIAS_CFG0);
260 val |= UTMIP_OTGPD | UTMIP_BIASPD;
261 writel(val, base + UTMIP_BIAS_CFG0);
264 spin_unlock_irqrestore(&utmip_pad_lock, flags);
266 clk_disable_unprepare(phy->pad_clk);
271 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
273 unsigned long timeout = 2000;
275 if ((readl(reg) & mask) == result)
283 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
286 void __iomem *base = phy->regs;
288 if (phy->is_legacy_phy) {
289 val = readl(base + USB_SUSP_CTRL);
291 writel(val, base + USB_SUSP_CTRL);
295 val = readl(base + USB_SUSP_CTRL);
296 val &= ~USB_SUSP_SET;
297 writel(val, base + USB_SUSP_CTRL);
301 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
302 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
305 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
308 void __iomem *base = phy->regs;
310 if (phy->is_legacy_phy) {
311 val = readl(base + USB_SUSP_CTRL);
313 writel(val, base + USB_SUSP_CTRL);
317 val = readl(base + USB_SUSP_CTRL);
318 val &= ~USB_SUSP_CLR;
319 writel(val, base + USB_SUSP_CTRL);
321 set_phcd(phy, false);
323 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
325 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
328 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
331 void __iomem *base = phy->regs;
332 struct tegra_utmip_config *config = phy->config;
334 val = readl(base + USB_SUSP_CTRL);
336 writel(val, base + USB_SUSP_CTRL);
338 if (phy->is_legacy_phy) {
339 val = readl(base + USB1_LEGACY_CTRL);
340 val |= USB1_NO_LEGACY_MODE;
341 writel(val, base + USB1_LEGACY_CTRL);
344 val = readl(base + UTMIP_TX_CFG0);
345 val &= ~UTMIP_FS_PREABMLE_J;
346 writel(val, base + UTMIP_TX_CFG0);
348 val = readl(base + UTMIP_HSRX_CFG0);
349 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
350 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
351 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
352 writel(val, base + UTMIP_HSRX_CFG0);
354 val = readl(base + UTMIP_HSRX_CFG1);
355 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
356 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
357 writel(val, base + UTMIP_HSRX_CFG1);
359 val = readl(base + UTMIP_DEBOUNCE_CFG0);
360 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
361 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
362 writel(val, base + UTMIP_DEBOUNCE_CFG0);
364 val = readl(base + UTMIP_MISC_CFG0);
365 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
366 writel(val, base + UTMIP_MISC_CFG0);
368 val = readl(base + UTMIP_MISC_CFG1);
369 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
370 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
371 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
372 writel(val, base + UTMIP_MISC_CFG1);
374 val = readl(base + UTMIP_PLL_CFG1);
375 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
376 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
377 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
378 writel(val, base + UTMIP_PLL_CFG1);
380 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
381 val = readl(base + USB_SUSP_CTRL);
382 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
383 writel(val, base + USB_SUSP_CTRL);
386 utmip_pad_power_on(phy);
388 val = readl(base + UTMIP_XCVR_CFG0);
389 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
390 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
391 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
392 UTMIP_XCVR_HSSLEW_MSB(~0));
393 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
394 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
395 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
396 writel(val, base + UTMIP_XCVR_CFG0);
398 val = readl(base + UTMIP_XCVR_CFG1);
399 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
400 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
401 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
402 writel(val, base + UTMIP_XCVR_CFG1);
404 val = readl(base + UTMIP_BAT_CHRG_CFG0);
405 val &= ~UTMIP_PD_CHRG;
406 writel(val, base + UTMIP_BAT_CHRG_CFG0);
408 val = readl(base + UTMIP_BIAS_CFG1);
409 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
410 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
411 writel(val, base + UTMIP_BIAS_CFG1);
413 if (phy->is_legacy_phy) {
414 val = readl(base + UTMIP_SPARE_CFG0);
415 if (phy->mode == USB_DR_MODE_PERIPHERAL)
416 val &= ~FUSE_SETUP_SEL;
418 val |= FUSE_SETUP_SEL;
419 writel(val, base + UTMIP_SPARE_CFG0);
421 val = readl(base + USB_SUSP_CTRL);
422 val |= UTMIP_PHY_ENABLE;
423 writel(val, base + USB_SUSP_CTRL);
426 val = readl(base + USB_SUSP_CTRL);
428 writel(val, base + USB_SUSP_CTRL);
430 if (phy->is_legacy_phy) {
431 val = readl(base + USB1_LEGACY_CTRL);
432 val &= ~USB1_VBUS_SENSE_CTL_MASK;
433 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
434 writel(val, base + USB1_LEGACY_CTRL);
436 val = readl(base + USB_SUSP_CTRL);
437 val &= ~USB_SUSP_SET;
438 writel(val, base + USB_SUSP_CTRL);
441 utmi_phy_clk_enable(phy);
443 if (!phy->is_legacy_phy)
449 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
452 void __iomem *base = phy->regs;
454 utmi_phy_clk_disable(phy);
456 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
457 val = readl(base + USB_SUSP_CTRL);
458 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
459 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
460 writel(val, base + USB_SUSP_CTRL);
463 val = readl(base + USB_SUSP_CTRL);
465 writel(val, base + USB_SUSP_CTRL);
467 val = readl(base + UTMIP_BAT_CHRG_CFG0);
468 val |= UTMIP_PD_CHRG;
469 writel(val, base + UTMIP_BAT_CHRG_CFG0);
471 val = readl(base + UTMIP_XCVR_CFG0);
472 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
473 UTMIP_FORCE_PDZI_POWERDOWN;
474 writel(val, base + UTMIP_XCVR_CFG0);
476 val = readl(base + UTMIP_XCVR_CFG1);
477 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
478 UTMIP_FORCE_PDDR_POWERDOWN;
479 writel(val, base + UTMIP_XCVR_CFG1);
481 return utmip_pad_power_off(phy);
484 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
487 void __iomem *base = phy->regs;
489 val = readl(base + UTMIP_TX_CFG0);
490 val |= UTMIP_HS_DISCON_DISABLE;
491 writel(val, base + UTMIP_TX_CFG0);
494 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
497 void __iomem *base = phy->regs;
499 val = readl(base + UTMIP_TX_CFG0);
500 val &= ~UTMIP_HS_DISCON_DISABLE;
501 writel(val, base + UTMIP_TX_CFG0);
504 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
505 enum tegra_usb_phy_port_speed port_speed)
508 void __iomem *base = phy->regs;
510 val = readl(base + UTMIP_MISC_CFG0);
511 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
512 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
513 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
515 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
516 writel(val, base + UTMIP_MISC_CFG0);
519 val = readl(base + UTMIP_MISC_CFG0);
520 val |= UTMIP_DPDM_OBSERVE;
521 writel(val, base + UTMIP_MISC_CFG0);
525 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
528 void __iomem *base = phy->regs;
530 val = readl(base + UTMIP_MISC_CFG0);
531 val &= ~UTMIP_DPDM_OBSERVE;
532 writel(val, base + UTMIP_MISC_CFG0);
536 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
540 void __iomem *base = phy->regs;
542 ret = gpio_direction_output(phy->reset_gpio, 0);
544 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
549 ret = gpio_direction_output(phy->reset_gpio, 1);
551 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
556 clk_prepare_enable(phy->clk);
559 val = readl(base + USB_SUSP_CTRL);
561 writel(val, base + USB_SUSP_CTRL);
563 val = readl(base + ULPI_TIMING_CTRL_0);
564 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
565 writel(val, base + ULPI_TIMING_CTRL_0);
567 val = readl(base + USB_SUSP_CTRL);
568 val |= ULPI_PHY_ENABLE;
569 writel(val, base + USB_SUSP_CTRL);
572 writel(val, base + ULPI_TIMING_CTRL_1);
574 val |= ULPI_DATA_TRIMMER_SEL(4);
575 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
576 val |= ULPI_DIR_TRIMMER_SEL(4);
577 writel(val, base + ULPI_TIMING_CTRL_1);
580 val |= ULPI_DATA_TRIMMER_LOAD;
581 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
582 val |= ULPI_DIR_TRIMMER_LOAD;
583 writel(val, base + ULPI_TIMING_CTRL_1);
585 /* Fix VbusInvalid due to floating VBUS */
586 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
588 pr_err("%s: ulpi write failed\n", __func__);
592 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
594 pr_err("%s: ulpi write failed\n", __func__);
598 val = readl(base + USB_SUSP_CTRL);
600 writel(val, base + USB_SUSP_CTRL);
603 val = readl(base + USB_SUSP_CTRL);
604 val &= ~USB_SUSP_CLR;
605 writel(val, base + USB_SUSP_CTRL);
610 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
612 clk_disable(phy->clk);
613 return gpio_direction_output(phy->reset_gpio, 0);
616 static void tegra_usb_phy_close(struct usb_phy *x)
618 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
620 if (!IS_ERR(phy->vbus))
621 regulator_disable(phy->vbus);
623 clk_disable_unprepare(phy->pll_u);
626 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
628 if (phy->is_ulpi_phy)
629 return ulpi_phy_power_on(phy);
631 return utmi_phy_power_on(phy);
634 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
636 if (phy->is_ulpi_phy)
637 return ulpi_phy_power_off(phy);
639 return utmi_phy_power_off(phy);
642 static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
644 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
646 return tegra_usb_phy_power_off(phy);
648 return tegra_usb_phy_power_on(phy);
651 static int ulpi_open(struct tegra_usb_phy *phy)
655 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
656 if (IS_ERR(phy->clk)) {
657 pr_err("%s: can't get ulpi clock\n", __func__);
658 return PTR_ERR(phy->clk);
661 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
664 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
669 err = gpio_direction_output(phy->reset_gpio, 0);
671 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
676 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
678 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
683 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
687 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
689 unsigned long parent_rate;
693 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
694 if (IS_ERR(phy->pll_u)) {
695 pr_err("Can't get pll_u clock\n");
696 return PTR_ERR(phy->pll_u);
699 err = clk_prepare_enable(phy->pll_u);
703 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
704 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
705 if (tegra_freq_table[i].freq == parent_rate) {
706 phy->freq = &tegra_freq_table[i];
711 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
716 if (!IS_ERR(phy->vbus)) {
717 err = regulator_enable(phy->vbus);
719 dev_err(phy->u_phy.dev,
720 "failed to enable usb vbus regulator: %d\n",
726 if (phy->is_ulpi_phy)
727 err = ulpi_open(phy);
729 err = utmip_pad_open(phy);
736 clk_disable_unprepare(phy->pll_u);
740 void tegra_usb_phy_preresume(struct usb_phy *x)
742 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
744 if (!phy->is_ulpi_phy)
745 utmi_phy_preresume(phy);
747 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
749 void tegra_usb_phy_postresume(struct usb_phy *x)
751 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
753 if (!phy->is_ulpi_phy)
754 utmi_phy_postresume(phy);
756 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
758 void tegra_ehci_phy_restore_start(struct usb_phy *x,
759 enum tegra_usb_phy_port_speed port_speed)
761 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
763 if (!phy->is_ulpi_phy)
764 utmi_phy_restore_start(phy, port_speed);
766 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
768 void tegra_ehci_phy_restore_end(struct usb_phy *x)
770 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
772 if (!phy->is_ulpi_phy)
773 utmi_phy_restore_end(phy);
775 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
777 static int read_utmi_param(struct platform_device *pdev, const char *param,
781 int err = of_property_read_u32(pdev->dev.of_node, param, &value);
784 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
789 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
790 struct platform_device *pdev)
792 struct resource *res;
794 struct tegra_utmip_config *config;
796 tegra_phy->is_ulpi_phy = false;
798 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
800 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
804 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
806 if (!tegra_phy->regs) {
807 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
811 tegra_phy->config = devm_kzalloc(&pdev->dev,
812 sizeof(*tegra_phy->config), GFP_KERNEL);
813 if (!tegra_phy->config) {
815 "unable to allocate memory for USB UTMIP config\n");
819 config = tegra_phy->config;
821 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
822 &config->hssync_start_delay);
826 err = read_utmi_param(pdev, "nvidia,elastic-limit",
827 &config->elastic_limit);
831 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
832 &config->idle_wait_delay);
836 err = read_utmi_param(pdev, "nvidia,term-range-adj",
837 &config->term_range_adj);
841 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
842 &config->xcvr_setup);
846 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
847 &config->xcvr_lsfslew);
851 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
852 &config->xcvr_lsrslew);
859 static int tegra_usb_phy_probe(struct platform_device *pdev)
861 struct resource *res;
862 struct tegra_usb_phy *tegra_phy = NULL;
863 struct device_node *np = pdev->dev.of_node;
864 enum usb_phy_interface phy_type;
867 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
869 dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
873 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
875 dev_err(&pdev->dev, "Failed to get I/O memory\n");
879 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
881 if (!tegra_phy->regs) {
882 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
886 tegra_phy->is_legacy_phy =
887 of_property_read_bool(np, "nvidia,has-legacy-mode");
889 phy_type = of_usb_get_phy_mode(np);
890 if (phy_type == USBPHY_INTERFACE_MODE_UTMI) {
891 err = utmi_phy_probe(tegra_phy, pdev);
894 } else if (phy_type == USBPHY_INTERFACE_MODE_ULPI) {
895 tegra_phy->is_ulpi_phy = true;
897 tegra_phy->reset_gpio =
898 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
899 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
900 dev_err(&pdev->dev, "invalid gpio: %d\n",
901 tegra_phy->reset_gpio);
902 return tegra_phy->reset_gpio;
904 tegra_phy->config = NULL;
906 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
910 if (of_find_property(np, "dr_mode", NULL))
911 tegra_phy->mode = of_usb_get_dr_mode(np);
913 tegra_phy->mode = USB_DR_MODE_HOST;
915 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
916 dev_err(&pdev->dev, "dr_mode is invalid\n");
920 /* On some boards, the VBUS regulator doesn't need to be controlled */
921 if (of_find_property(np, "vbus-supply", NULL)) {
922 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
923 if (IS_ERR(tegra_phy->vbus))
924 return PTR_ERR(tegra_phy->vbus);
926 dev_notice(&pdev->dev, "no vbus regulator");
927 tegra_phy->vbus = ERR_PTR(-ENODEV);
930 tegra_phy->u_phy.dev = &pdev->dev;
931 err = tegra_usb_phy_init(tegra_phy);
935 tegra_phy->u_phy.shutdown = tegra_usb_phy_close;
936 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
938 dev_set_drvdata(&pdev->dev, tegra_phy);
940 err = usb_add_phy_dev(&tegra_phy->u_phy);
942 tegra_usb_phy_close(&tegra_phy->u_phy);
949 static int tegra_usb_phy_remove(struct platform_device *pdev)
951 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
953 usb_remove_phy(&tegra_phy->u_phy);
958 static struct of_device_id tegra_usb_phy_id_table[] = {
959 { .compatible = "nvidia,tegra20-usb-phy", },
962 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
964 static struct platform_driver tegra_usb_phy_driver = {
965 .probe = tegra_usb_phy_probe,
966 .remove = tegra_usb_phy_remove,
969 .owner = THIS_MODULE,
970 .of_match_table = of_match_ptr(tegra_usb_phy_id_table),
973 module_platform_driver(tegra_usb_phy_driver);
975 MODULE_DESCRIPTION("Tegra USB PHY driver");
976 MODULE_LICENSE("GPL v2");