drivers/usb/phy/phy-tegra-usb.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  *
   5  * Author:
   6  *      Erik Gilling <konkers@google.com>
   7  *      Benoit Goby <benoit@android.com>
   8  *      Venu Byravarasu <vbyravarasu@nvidia.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/resource.h>
  22 #include <linux/delay.h>
  23 #include <linux/slab.h>
  24 #include <linux/err.h>
  25 #include <linux/export.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/usb/otg.h>
  33 #include <linux/usb/ulpi.h>
  34 #include <linux/usb/of.h>
  35 #include <asm/mach-types.h>
  36 #include <linux/usb/ehci_def.h>
  37 #include <linux/usb/tegra_usb_phy.h>
  38 #include <linux/regulator/consumer.h>
  39
  40 #define ULPI_VIEWPORT           0x170
  41
  42 /* PORTSC registers */
  43 #define TEGRA_USB_PORTSC1                               0x184
  44 #define TEGRA_USB_PORTSC1_PTS(x)                        (((x) & 0x3) << 30)
  45 #define TEGRA_USB_PORTSC1_PHCD                          (1 << 23)
  46
  47 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  48 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  49
  50 #define USB_SUSP_CTRL           0x400
  51 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  52 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  53 #define   USB_SUSP_CLR          (1 << 5)
  54 #define   USB_PHY_CLK_VALID     (1 << 7)
  55 #define   UTMIP_RESET                   (1 << 11)
  56 #define   UHSIC_RESET                   (1 << 11)
  57 #define   UTMIP_PHY_ENABLE              (1 << 12)
  58 #define   ULPI_PHY_ENABLE       (1 << 13)
  59 #define   USB_SUSP_SET          (1 << 14)
  60 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  61
  62 #define USB1_LEGACY_CTRL        0x410
  63 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  64 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  65 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  66 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  67                                                 (1 << 1)
  68 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  69 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  70
  71 #define ULPI_TIMING_CTRL_0      0x424
  72 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  73 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  74
  75 #define ULPI_TIMING_CTRL_1      0x428
  76 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  77 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  78 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  79 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  80 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  81 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  82
  83 #define UTMIP_PLL_CFG1          0x804
  84 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  85 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  86
  87 #define UTMIP_XCVR_CFG0         0x808
  88 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  89 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  90 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  91 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  92 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
  93 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
  94 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
  95 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
  96 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
  97
  98 #define UTMIP_BIAS_CFG0         0x80c
  99 #define   UTMIP_OTGPD                   (1 << 11)
 100 #define   UTMIP_BIASPD                  (1 << 10)
 101
 102 #define UTMIP_HSRX_CFG0         0x810
 103 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 104 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 105
 106 #define UTMIP_HSRX_CFG1         0x814
 107 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 108
 109 #define UTMIP_TX_CFG0           0x820
 110 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 111 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 112
 113 #define UTMIP_MISC_CFG0         0x824
 114 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
 115 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
 116 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
 117 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
 118 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 119 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 120 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 121
 122 #define UTMIP_MISC_CFG1         0x828
 123 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 124 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 125
 126 #define UTMIP_DEBOUNCE_CFG0     0x82c
 127 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 128
 129 #define UTMIP_BAT_CHRG_CFG0     0x830
 130 #define   UTMIP_PD_CHRG                 (1 << 0)
 131
 132 #define UTMIP_SPARE_CFG0        0x834
 133 #define   FUSE_SETUP_SEL                (1 << 3)
 134
 135 #define UTMIP_XCVR_CFG1         0x838
 136 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 137 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 138 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 139 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 140
 141 #define UTMIP_BIAS_CFG1         0x83c
 142 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 143
 144 static DEFINE_SPINLOCK(utmip_pad_lock);
 145 static int utmip_pad_count;
 146
 147 struct tegra_xtal_freq {
 148         int freq;
 149         u8 enable_delay;
 150         u8 stable_count;
 151         u8 active_delay;
 152         u8 xtal_freq_count;
 153         u16 debounce;
 154 };
 155
 156 static const struct tegra_xtal_freq tegra_freq_table[] = {
 157         {
 158                 .freq = 12000000,
 159                 .enable_delay = 0x02,
 160                 .stable_count = 0x2F,
 161                 .active_delay = 0x04,
 162                 .xtal_freq_count = 0x76,
 163                 .debounce = 0x7530,
 164         },
 165         {
 166                 .freq = 13000000,
 167                 .enable_delay = 0x02,
 168                 .stable_count = 0x33,
 169                 .active_delay = 0x05,
 170                 .xtal_freq_count = 0x7F,
 171                 .debounce = 0x7EF4,
 172         },
 173         {
 174                 .freq = 19200000,
 175                 .enable_delay = 0x03,
 176                 .stable_count = 0x4B,
 177                 .active_delay = 0x06,
 178                 .xtal_freq_count = 0xBB,
 179                 .debounce = 0xBB80,
 180         },
 181         {
 182                 .freq = 26000000,
 183                 .enable_delay = 0x04,
 184                 .stable_count = 0x66,
 185                 .active_delay = 0x09,
 186                 .xtal_freq_count = 0xFE,
 187                 .debounce = 0xFDE8,
 188         },
 189 };
 190
 191 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 192 {
 193         void __iomem *base = phy->regs;
 194         unsigned long val;
 195
 196         val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 197         val &= ~TEGRA_USB_PORTSC1_PTS(3);
 198         val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
 199         writel(val, base + TEGRA_USB_PORTSC1);
 200 }
 201
 202 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 203 {
 204         void __iomem *base = phy->regs;
 205         unsigned long val;
 206
 207         val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 208         if (enable)
 209                 val |= TEGRA_USB_PORTSC1_PHCD;
 210         else
 211                 val &= ~TEGRA_USB_PORTSC1_PHCD;
 212         writel(val, base + TEGRA_USB_PORTSC1);
 213 }
 214
 215 static int utmip_pad_open(struct tegra_usb_phy *phy)
 216 {
 217         phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
 218         if (IS_ERR(phy->pad_clk)) {
 219                 pr_err("%s: can't get utmip pad clock\n", __func__);
 220                 return PTR_ERR(phy->pad_clk);
 221         }
 222
 223         return 0;
 224 }
 225
 226 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 227 {
 228         unsigned long val, flags;
 229         void __iomem *base = phy->pad_regs;
 230
 231         clk_prepare_enable(phy->pad_clk);
 232
 233         spin_lock_irqsave(&utmip_pad_lock, flags);
 234
 235         if (utmip_pad_count++ == 0) {
 236                 val = readl(base + UTMIP_BIAS_CFG0);
 237                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 238                 writel(val, base + UTMIP_BIAS_CFG0);
 239         }
 240
 241         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 242
 243         clk_disable_unprepare(phy->pad_clk);
 244 }
 245
 246 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 247 {
 248         unsigned long val, flags;
 249         void __iomem *base = phy->pad_regs;
 250
 251         if (!utmip_pad_count) {
 252                 pr_err("%s: utmip pad already powered off\n", __func__);
 253                 return -EINVAL;
 254         }
 255
 256         clk_prepare_enable(phy->pad_clk);
 257
 258         spin_lock_irqsave(&utmip_pad_lock, flags);
 259
 260         if (--utmip_pad_count == 0) {
 261                 val = readl(base + UTMIP_BIAS_CFG0);
 262                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 263                 writel(val, base + UTMIP_BIAS_CFG0);
 264         }
 265
 266         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 267
 268         clk_disable_unprepare(phy->pad_clk);
 269
 270         return 0;
 271 }
 272
 273 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 274 {
 275         unsigned long timeout = 2000;
 276         do {
 277                 if ((readl(reg) & mask) == result)
 278                         return 0;
 279                 udelay(1);
 280                 timeout--;
 281         } while (timeout);
 282         return -1;
 283 }
 284
 285 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 286 {
 287         unsigned long val;
 288         void __iomem *base = phy->regs;
 289
 290         if (phy->is_legacy_phy) {
 291                 val = readl(base + USB_SUSP_CTRL);
 292                 val |= USB_SUSP_SET;
 293                 writel(val, base + USB_SUSP_CTRL);
 294
 295                 udelay(10);
 296
 297                 val = readl(base + USB_SUSP_CTRL);
 298                 val &= ~USB_SUSP_SET;
 299                 writel(val, base + USB_SUSP_CTRL);
 300         } else
 301                 set_phcd(phy, true);
 302
 303         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 304                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 305 }
 306
 307 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 308 {
 309         unsigned long val;
 310         void __iomem *base = phy->regs;
 311
 312         if (phy->is_legacy_phy) {
 313                 val = readl(base + USB_SUSP_CTRL);
 314                 val |= USB_SUSP_CLR;
 315                 writel(val, base + USB_SUSP_CTRL);
 316
 317                 udelay(10);
 318
 319                 val = readl(base + USB_SUSP_CTRL);
 320                 val &= ~USB_SUSP_CLR;
 321                 writel(val, base + USB_SUSP_CTRL);
 322         } else
 323                 set_phcd(phy, false);
 324
 325         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 326                                                      USB_PHY_CLK_VALID))
 327                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 328 }
 329
 330 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 331 {
 332         unsigned long val;
 333         void __iomem *base = phy->regs;
 334         struct tegra_utmip_config *config = phy->config;
 335
 336         val = readl(base + USB_SUSP_CTRL);
 337         val |= UTMIP_RESET;
 338         writel(val, base + USB_SUSP_CTRL);
 339
 340         if (phy->is_legacy_phy) {
 341                 val = readl(base + USB1_LEGACY_CTRL);
 342                 val |= USB1_NO_LEGACY_MODE;
 343                 writel(val, base + USB1_LEGACY_CTRL);
 344         }
 345
 346         val = readl(base + UTMIP_TX_CFG0);
 347         val |= UTMIP_FS_PREABMLE_J;
 348         writel(val, base + UTMIP_TX_CFG0);
 349
 350         val = readl(base + UTMIP_HSRX_CFG0);
 351         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 352         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 353         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 354         writel(val, base + UTMIP_HSRX_CFG0);
 355
 356         val = readl(base + UTMIP_HSRX_CFG1);
 357         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 358         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 359         writel(val, base + UTMIP_HSRX_CFG1);
 360
 361         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 362         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 363         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 364         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 365
 366         val = readl(base + UTMIP_MISC_CFG0);
 367         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 368         writel(val, base + UTMIP_MISC_CFG0);
 369
 370         val = readl(base + UTMIP_MISC_CFG1);
 371         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
 372         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 373                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 374         writel(val, base + UTMIP_MISC_CFG1);
 375
 376         val = readl(base + UTMIP_PLL_CFG1);
 377         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 378         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 379                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 380         writel(val, base + UTMIP_PLL_CFG1);
 381
 382         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 383                 val = readl(base + USB_SUSP_CTRL);
 384                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 385                 writel(val, base + USB_SUSP_CTRL);
 386
 387                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 388                 val &= ~UTMIP_PD_CHRG;
 389                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 390         } else {
 391                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 392                 val |= UTMIP_PD_CHRG;
 393                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 394         }
 395
 396         utmip_pad_power_on(phy);
 397
 398         val = readl(base + UTMIP_XCVR_CFG0);
 399         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 400                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 401                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 402                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
 403                  UTMIP_XCVR_HSSLEW_MSB(~0));
 404         val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 405         val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 406         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 407         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 408         writel(val, base + UTMIP_XCVR_CFG0);
 409
 410         val = readl(base + UTMIP_XCVR_CFG1);
 411         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 412                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 413         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 414         writel(val, base + UTMIP_XCVR_CFG1);
 415
 416         val = readl(base + UTMIP_BIAS_CFG1);
 417         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 418         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 419         writel(val, base + UTMIP_BIAS_CFG1);
 420
 421         if (phy->is_legacy_phy) {
 422                 val = readl(base + UTMIP_SPARE_CFG0);
 423                 if (phy->mode == USB_DR_MODE_PERIPHERAL)
 424                         val &= ~FUSE_SETUP_SEL;
 425                 else
 426                         val |= FUSE_SETUP_SEL;
 427                 writel(val, base + UTMIP_SPARE_CFG0);
 428         } else {
 429                 val = readl(base + USB_SUSP_CTRL);
 430                 val |= UTMIP_PHY_ENABLE;
 431                 writel(val, base + USB_SUSP_CTRL);
 432         }
 433
 434         val = readl(base + USB_SUSP_CTRL);
 435         val &= ~UTMIP_RESET;
 436         writel(val, base + USB_SUSP_CTRL);
 437
 438         if (phy->is_legacy_phy) {
 439                 val = readl(base + USB1_LEGACY_CTRL);
 440                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 441                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 442                 writel(val, base + USB1_LEGACY_CTRL);
 443
 444                 val = readl(base + USB_SUSP_CTRL);
 445                 val &= ~USB_SUSP_SET;
 446                 writel(val, base + USB_SUSP_CTRL);
 447         }
 448
 449         utmi_phy_clk_enable(phy);
 450
 451         if (!phy->is_legacy_phy)
 452                 set_pts(phy, 0);
 453
 454         return 0;
 455 }
 456
 457 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 458 {
 459         unsigned long val;
 460         void __iomem *base = phy->regs;
 461
 462         utmi_phy_clk_disable(phy);
 463
 464         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 465                 val = readl(base + USB_SUSP_CTRL);
 466                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 467                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 468                 writel(val, base + USB_SUSP_CTRL);
 469         }
 470
 471         val = readl(base + USB_SUSP_CTRL);
 472         val |= UTMIP_RESET;
 473         writel(val, base + USB_SUSP_CTRL);
 474
 475         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 476         val |= UTMIP_PD_CHRG;
 477         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 478
 479         val = readl(base + UTMIP_XCVR_CFG0);
 480         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 481                UTMIP_FORCE_PDZI_POWERDOWN;
 482         writel(val, base + UTMIP_XCVR_CFG0);
 483
 484         val = readl(base + UTMIP_XCVR_CFG1);
 485         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 486                UTMIP_FORCE_PDDR_POWERDOWN;
 487         writel(val, base + UTMIP_XCVR_CFG1);
 488
 489         return utmip_pad_power_off(phy);
 490 }
 491
 492 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 493 {
 494         unsigned long val;
 495         void __iomem *base = phy->regs;
 496
 497         val = readl(base + UTMIP_TX_CFG0);
 498         val |= UTMIP_HS_DISCON_DISABLE;
 499         writel(val, base + UTMIP_TX_CFG0);
 500 }
 501
 502 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 503 {
 504         unsigned long val;
 505         void __iomem *base = phy->regs;
 506
 507         val = readl(base + UTMIP_TX_CFG0);
 508         val &= ~UTMIP_HS_DISCON_DISABLE;
 509         writel(val, base + UTMIP_TX_CFG0);
 510 }
 511
 512 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 513                                    enum tegra_usb_phy_port_speed port_speed)
 514 {
 515         unsigned long val;
 516         void __iomem *base = phy->regs;
 517
 518         val = readl(base + UTMIP_MISC_CFG0);
 519         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 520         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 521                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 522         else
 523                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 524         writel(val, base + UTMIP_MISC_CFG0);
 525         udelay(1);
 526
 527         val = readl(base + UTMIP_MISC_CFG0);
 528         val |= UTMIP_DPDM_OBSERVE;
 529         writel(val, base + UTMIP_MISC_CFG0);
 530         udelay(10);
 531 }
 532
 533 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 534 {
 535         unsigned long val;
 536         void __iomem *base = phy->regs;
 537
 538         val = readl(base + UTMIP_MISC_CFG0);
 539         val &= ~UTMIP_DPDM_OBSERVE;
 540         writel(val, base + UTMIP_MISC_CFG0);
 541         udelay(10);
 542 }
 543
 544 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 545 {
 546         int ret;
 547         unsigned long val;
 548         void __iomem *base = phy->regs;
 549
 550         ret = gpio_direction_output(phy->reset_gpio, 0);
 551         if (ret < 0) {
 552                 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
 553                         phy->reset_gpio);
 554                 return ret;
 555         }
 556         msleep(5);
 557         ret = gpio_direction_output(phy->reset_gpio, 1);
 558         if (ret < 0) {
 559                 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
 560                         phy->reset_gpio);
 561                 return ret;
 562         }
 563
 564         clk_prepare_enable(phy->clk);
 565         msleep(1);
 566
 567         val = readl(base + USB_SUSP_CTRL);
 568         val |= UHSIC_RESET;
 569         writel(val, base + USB_SUSP_CTRL);
 570
 571         val = readl(base + ULPI_TIMING_CTRL_0);
 572         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 573         writel(val, base + ULPI_TIMING_CTRL_0);
 574
 575         val = readl(base + USB_SUSP_CTRL);
 576         val |= ULPI_PHY_ENABLE;
 577         writel(val, base + USB_SUSP_CTRL);
 578
 579         val = 0;
 580         writel(val, base + ULPI_TIMING_CTRL_1);
 581
 582         val |= ULPI_DATA_TRIMMER_SEL(4);
 583         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 584         val |= ULPI_DIR_TRIMMER_SEL(4);
 585         writel(val, base + ULPI_TIMING_CTRL_1);
 586         udelay(10);
 587
 588         val |= ULPI_DATA_TRIMMER_LOAD;
 589         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 590         val |= ULPI_DIR_TRIMMER_LOAD;
 591         writel(val, base + ULPI_TIMING_CTRL_1);
 592
 593         /* Fix VbusInvalid due to floating VBUS */
 594         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 595         if (ret) {
 596                 pr_err("%s: ulpi write failed\n", __func__);
 597                 return ret;
 598         }
 599
 600         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 601         if (ret) {
 602                 pr_err("%s: ulpi write failed\n", __func__);
 603                 return ret;
 604         }
 605
 606         val = readl(base + USB_SUSP_CTRL);
 607         val |= USB_SUSP_CLR;
 608         writel(val, base + USB_SUSP_CTRL);
 609         udelay(100);
 610
 611         val = readl(base + USB_SUSP_CTRL);
 612         val &= ~USB_SUSP_CLR;
 613         writel(val, base + USB_SUSP_CTRL);
 614
 615         return 0;
 616 }
 617
 618 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 619 {
 620         clk_disable(phy->clk);
 621         return gpio_direction_output(phy->reset_gpio, 0);
 622 }
 623
 624 static void tegra_usb_phy_close(struct usb_phy *x)
 625 {
 626         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 627
 628         if (!IS_ERR(phy->vbus))
 629                 regulator_disable(phy->vbus);
 630
 631         clk_disable_unprepare(phy->pll_u);
 632 }
 633
 634 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 635 {
 636         if (phy->is_ulpi_phy)
 637                 return ulpi_phy_power_on(phy);
 638         else
 639                 return utmi_phy_power_on(phy);
 640 }
 641
 642 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 643 {
 644         if (phy->is_ulpi_phy)
 645                 return ulpi_phy_power_off(phy);
 646         else
 647                 return utmi_phy_power_off(phy);
 648 }
 649
 650 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 651 {
 652         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 653         if (suspend)
 654                 return tegra_usb_phy_power_off(phy);
 655         else
 656                 return tegra_usb_phy_power_on(phy);
 657 }
 658
 659 static int ulpi_open(struct tegra_usb_phy *phy)
 660 {
 661         int err;
 662
 663         phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
 664         if (IS_ERR(phy->clk)) {
 665                 pr_err("%s: can't get ulpi clock\n", __func__);
 666                 return PTR_ERR(phy->clk);
 667         }
 668
 669         err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
 670                 "ulpi_phy_reset_b");
 671         if (err < 0) {
 672                 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
 673                        phy->reset_gpio);
 674                 return err;
 675         }
 676
 677         err = gpio_direction_output(phy->reset_gpio, 0);
 678         if (err < 0) {
 679                 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
 680                        phy->reset_gpio);
 681                 return err;
 682         }
 683
 684         phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 685         if (!phy->ulpi) {
 686                 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
 687                 err = -ENOMEM;
 688                 return err;
 689         }
 690
 691         phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 692         return 0;
 693 }
 694
 695 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
 696 {
 697         unsigned long parent_rate;
 698         int i;
 699         int err;
 700
 701         phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
 702         if (IS_ERR(phy->pll_u)) {
 703                 pr_err("Can't get pll_u clock\n");
 704                 return PTR_ERR(phy->pll_u);
 705         }
 706
 707         err = clk_prepare_enable(phy->pll_u);
 708         if (err)
 709                 return err;
 710
 711         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 712         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 713                 if (tegra_freq_table[i].freq == parent_rate) {
 714                         phy->freq = &tegra_freq_table[i];
 715                         break;
 716                 }
 717         }
 718         if (!phy->freq) {
 719                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 720                 err = -EINVAL;
 721                 goto fail;
 722         }
 723
 724         if (!IS_ERR(phy->vbus)) {
 725                 err = regulator_enable(phy->vbus);
 726                 if (err) {
 727                         dev_err(phy->u_phy.dev,
 728                                 "failed to enable usb vbus regulator: %d\n",
 729                                 err);
 730                         goto fail;
 731                 }
 732         }
 733
 734         if (phy->is_ulpi_phy)
 735                 err = ulpi_open(phy);
 736         else
 737                 err = utmip_pad_open(phy);
 738         if (err < 0)
 739                 goto fail;
 740
 741         return 0;
 742
 743 fail:
 744         clk_disable_unprepare(phy->pll_u);
 745         return err;
 746 }
 747
 748 void tegra_usb_phy_preresume(struct usb_phy *x)
 749 {
 750         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 751
 752         if (!phy->is_ulpi_phy)
 753                 utmi_phy_preresume(phy);
 754 }
 755 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 756
 757 void tegra_usb_phy_postresume(struct usb_phy *x)
 758 {
 759         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 760
 761         if (!phy->is_ulpi_phy)
 762                 utmi_phy_postresume(phy);
 763 }
 764 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 765
 766 void tegra_ehci_phy_restore_start(struct usb_phy *x,
 767                                  enum tegra_usb_phy_port_speed port_speed)
 768 {
 769         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 770
 771         if (!phy->is_ulpi_phy)
 772                 utmi_phy_restore_start(phy, port_speed);
 773 }
 774 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 775
 776 void tegra_ehci_phy_restore_end(struct usb_phy *x)
 777 {
 778         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 779
 780         if (!phy->is_ulpi_phy)
 781                 utmi_phy_restore_end(phy);
 782 }
 783 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 784
 785 static int read_utmi_param(struct platform_device *pdev, const char *param,
 786                            u8 *dest)
 787 {
 788         u32 value;
 789         int err = of_property_read_u32(pdev->dev.of_node, param, &value);
 790         *dest = (u8)value;
 791         if (err < 0)
 792                 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
 793                         param, err);
 794         return err;
 795 }
 796
 797 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 798                           struct platform_device *pdev)
 799 {
 800         struct resource *res;
 801         int err;
 802         struct tegra_utmip_config *config;
 803
 804         tegra_phy->is_ulpi_phy = false;
 805
 806         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 807         if (!res) {
 808                 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
 809                 return  -ENXIO;
 810         }
 811
 812         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 813                 resource_size(res));
 814         if (!tegra_phy->regs) {
 815                 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
 816                 return -ENOMEM;
 817         }
 818
 819         tegra_phy->config = devm_kzalloc(&pdev->dev,
 820                 sizeof(*tegra_phy->config), GFP_KERNEL);
 821         if (!tegra_phy->config) {
 822                 dev_err(&pdev->dev,
 823                         "unable to allocate memory for USB UTMIP config\n");
 824                 return -ENOMEM;
 825         }
 826
 827         config = tegra_phy->config;
 828
 829         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 830                 &config->hssync_start_delay);
 831         if (err < 0)
 832                 return err;
 833
 834         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 835                 &config->elastic_limit);
 836         if (err < 0)
 837                 return err;
 838
 839         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
 840                 &config->idle_wait_delay);
 841         if (err < 0)
 842                 return err;
 843
 844         err = read_utmi_param(pdev, "nvidia,term-range-adj",
 845                 &config->term_range_adj);
 846         if (err < 0)
 847                 return err;
 848
 849         err = read_utmi_param(pdev, "nvidia,xcvr-setup",
 850                 &config->xcvr_setup);
 851         if (err < 0)
 852                 return err;
 853
 854         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
 855                 &config->xcvr_lsfslew);
 856         if (err < 0)
 857                 return err;
 858
 859         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
 860                 &config->xcvr_lsrslew);
 861         if (err < 0)
 862                 return err;
 863
 864         return 0;
 865 }
 866
 867 static int tegra_usb_phy_probe(struct platform_device *pdev)
 868 {
 869         struct resource *res;
 870         struct tegra_usb_phy *tegra_phy = NULL;
 871         struct device_node *np = pdev->dev.of_node;
 872         enum usb_phy_interface phy_type;
 873         int err;
 874
 875         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
 876         if (!tegra_phy) {
 877                 dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
 878                 return -ENOMEM;
 879         }
 880
 881         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 882         if (!res) {
 883                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
 884                 return  -ENXIO;
 885         }
 886
 887         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
 888                 resource_size(res));
 889         if (!tegra_phy->regs) {
 890                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 891                 return -ENOMEM;
 892         }
 893
 894         tegra_phy->is_legacy_phy =
 895                 of_property_read_bool(np, "nvidia,has-legacy-mode");
 896
 897         phy_type = of_usb_get_phy_mode(np);
 898         switch (phy_type) {
 899         case USBPHY_INTERFACE_MODE_UTMI:
 900                 err = utmi_phy_probe(tegra_phy, pdev);
 901                 if (err < 0)
 902                         return err;
 903                 break;
 904
 905         case USBPHY_INTERFACE_MODE_ULPI:
 906                 tegra_phy->is_ulpi_phy = true;
 907
 908                 tegra_phy->reset_gpio =
 909                         of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
 910                 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
 911                         dev_err(&pdev->dev, "invalid gpio: %d\n",
 912                                 tegra_phy->reset_gpio);
 913                         return tegra_phy->reset_gpio;
 914                 }
 915                 tegra_phy->config = NULL;
 916                 break;
 917
 918         default:
 919                 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
 920                 return -EINVAL;
 921         }
 922
 923         if (of_find_property(np, "dr_mode", NULL))
 924                 tegra_phy->mode = of_usb_get_dr_mode(np);
 925         else
 926                 tegra_phy->mode = USB_DR_MODE_HOST;
 927
 928         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
 929                 dev_err(&pdev->dev, "dr_mode is invalid\n");
 930                 return -EINVAL;
 931         }
 932
 933         /* On some boards, the VBUS regulator doesn't need to be controlled */
 934         if (of_find_property(np, "vbus-supply", NULL)) {
 935                 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
 936                 if (IS_ERR(tegra_phy->vbus))
 937                         return PTR_ERR(tegra_phy->vbus);
 938         } else {
 939                 dev_notice(&pdev->dev, "no vbus regulator");
 940                 tegra_phy->vbus = ERR_PTR(-ENODEV);
 941         }
 942
 943         tegra_phy->u_phy.dev = &pdev->dev;
 944         err = tegra_usb_phy_init(tegra_phy);
 945         if (err < 0)
 946                 return err;
 947
 948         tegra_phy->u_phy.shutdown = tegra_usb_phy_close;
 949         tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
 950
 951         dev_set_drvdata(&pdev->dev, tegra_phy);
 952
 953         err = usb_add_phy_dev(&tegra_phy->u_phy);
 954         if (err < 0) {
 955                 tegra_usb_phy_close(&tegra_phy->u_phy);
 956                 return err;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static int tegra_usb_phy_remove(struct platform_device *pdev)
 963 {
 964         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
 965
 966         usb_remove_phy(&tegra_phy->u_phy);
 967
 968         return 0;
 969 }
 970
 971 static struct of_device_id tegra_usb_phy_id_table[] = {
 972         { .compatible = "nvidia,tegra20-usb-phy", },
 973         { },
 974 };
 975 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
 976
 977 static struct platform_driver tegra_usb_phy_driver = {
 978         .probe          = tegra_usb_phy_probe,
 979         .remove         = tegra_usb_phy_remove,
 980         .driver         = {
 981                 .name   = "tegra-phy",
 982                 .owner  = THIS_MODULE,
 983                 .of_match_table = of_match_ptr(tegra_usb_phy_id_table),
 984         },
 985 };
 986 module_platform_driver(tegra_usb_phy_driver);
 987
 988 MODULE_DESCRIPTION("Tegra USB PHY driver");
 989 MODULE_LICENSE("GPL v2");