drivers/usb/phy/phy-tegra-usb.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  *
   5  * Author:
   6  *      Erik Gilling <konkers@google.com>
   7  *      Benoit Goby <benoit@android.com>
   8  *      Venu Byravarasu <vbyravarasu@nvidia.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/resource.h>
  22 #include <linux/delay.h>
  23 #include <linux/slab.h>
  24 #include <linux/err.h>
  25 #include <linux/export.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/usb/otg.h>
  33 #include <linux/usb/ulpi.h>
  34 #include <linux/usb/of.h>
  35 #include <asm/mach-types.h>
  36 #include <linux/usb/ehci_def.h>
  37 #include <linux/usb/tegra_usb_phy.h>
  38 #include <linux/regulator/consumer.h>
  39
  40 #define ULPI_VIEWPORT           0x170
  41
  42 /* PORTSC registers */
  43 #define TEGRA_USB_PORTSC1                               0x184
  44 #define TEGRA_USB_PORTSC1_PTS(x)                        (((x) & 0x3) << 30)
  45 #define TEGRA_USB_PORTSC1_PHCD                          (1 << 23)
  46
  47 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  48 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  49
  50 #define USB_SUSP_CTRL           0x400
  51 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  52 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  53 #define   USB_SUSP_CLR          (1 << 5)
  54 #define   USB_PHY_CLK_VALID     (1 << 7)
  55 #define   UTMIP_RESET                   (1 << 11)
  56 #define   UHSIC_RESET                   (1 << 11)
  57 #define   UTMIP_PHY_ENABLE              (1 << 12)
  58 #define   ULPI_PHY_ENABLE       (1 << 13)
  59 #define   USB_SUSP_SET          (1 << 14)
  60 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  61
  62 #define USB1_LEGACY_CTRL        0x410
  63 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  64 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  65 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  66 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  67                                                 (1 << 1)
  68 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  69 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  70
  71 #define ULPI_TIMING_CTRL_0      0x424
  72 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  73 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  74
  75 #define ULPI_TIMING_CTRL_1      0x428
  76 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  77 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  78 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  79 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  80 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  81 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  82
  83 #define UTMIP_PLL_CFG1          0x804
  84 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  85 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  86
  87 #define UTMIP_XCVR_CFG0         0x808
  88 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  89 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  90 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  91 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
  92 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
  93 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
  94 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
  95
  96 #define UTMIP_BIAS_CFG0         0x80c
  97 #define   UTMIP_OTGPD                   (1 << 11)
  98 #define   UTMIP_BIASPD                  (1 << 10)
  99
 100 #define UTMIP_HSRX_CFG0         0x810
 101 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 102 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 103
 104 #define UTMIP_HSRX_CFG1         0x814
 105 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 106
 107 #define UTMIP_TX_CFG0           0x820
 108 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 109 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 110
 111 #define UTMIP_MISC_CFG0         0x824
 112 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
 113 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
 114 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
 115 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
 116 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 117 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 118 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 119
 120 #define UTMIP_MISC_CFG1         0x828
 121 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 122 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 123
 124 #define UTMIP_DEBOUNCE_CFG0     0x82c
 125 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 126
 127 #define UTMIP_BAT_CHRG_CFG0     0x830
 128 #define   UTMIP_PD_CHRG                 (1 << 0)
 129
 130 #define UTMIP_SPARE_CFG0        0x834
 131 #define   FUSE_SETUP_SEL                (1 << 3)
 132
 133 #define UTMIP_XCVR_CFG1         0x838
 134 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 135 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 136 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 137 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 138
 139 #define UTMIP_BIAS_CFG1         0x83c
 140 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 141
 142 static DEFINE_SPINLOCK(utmip_pad_lock);
 143 static int utmip_pad_count;
 144
 145 struct tegra_xtal_freq {
 146         int freq;
 147         u8 enable_delay;
 148         u8 stable_count;
 149         u8 active_delay;
 150         u8 xtal_freq_count;
 151         u16 debounce;
 152 };
 153
 154 static const struct tegra_xtal_freq tegra_freq_table[] = {
 155         {
 156                 .freq = 12000000,
 157                 .enable_delay = 0x02,
 158                 .stable_count = 0x2F,
 159                 .active_delay = 0x04,
 160                 .xtal_freq_count = 0x76,
 161                 .debounce = 0x7530,
 162         },
 163         {
 164                 .freq = 13000000,
 165                 .enable_delay = 0x02,
 166                 .stable_count = 0x33,
 167                 .active_delay = 0x05,
 168                 .xtal_freq_count = 0x7F,
 169                 .debounce = 0x7EF4,
 170         },
 171         {
 172                 .freq = 19200000,
 173                 .enable_delay = 0x03,
 174                 .stable_count = 0x4B,
 175                 .active_delay = 0x06,
 176                 .xtal_freq_count = 0xBB,
 177                 .debounce = 0xBB80,
 178         },
 179         {
 180                 .freq = 26000000,
 181                 .enable_delay = 0x04,
 182                 .stable_count = 0x66,
 183                 .active_delay = 0x09,
 184                 .xtal_freq_count = 0xFE,
 185                 .debounce = 0xFDE8,
 186         },
 187 };
 188
 189 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 190 {
 191         void __iomem *base = phy->regs;
 192         unsigned long val;
 193
 194         val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 195         val &= ~TEGRA_USB_PORTSC1_PTS(3);
 196         val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
 197         writel(val, base + TEGRA_USB_PORTSC1);
 198 }
 199
 200 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 201 {
 202         void __iomem *base = phy->regs;
 203         unsigned long val;
 204
 205         val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 206         if (enable)
 207                 val |= TEGRA_USB_PORTSC1_PHCD;
 208         else
 209                 val &= ~TEGRA_USB_PORTSC1_PHCD;
 210         writel(val, base + TEGRA_USB_PORTSC1);
 211 }
 212
 213 static int utmip_pad_open(struct tegra_usb_phy *phy)
 214 {
 215         phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
 216         if (IS_ERR(phy->pad_clk)) {
 217                 pr_err("%s: can't get utmip pad clock\n", __func__);
 218                 return PTR_ERR(phy->pad_clk);
 219         }
 220
 221         return 0;
 222 }
 223
 224 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 225 {
 226         unsigned long val, flags;
 227         void __iomem *base = phy->pad_regs;
 228
 229         clk_prepare_enable(phy->pad_clk);
 230
 231         spin_lock_irqsave(&utmip_pad_lock, flags);
 232
 233         if (utmip_pad_count++ == 0) {
 234                 val = readl(base + UTMIP_BIAS_CFG0);
 235                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 236                 writel(val, base + UTMIP_BIAS_CFG0);
 237         }
 238
 239         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 240
 241         clk_disable_unprepare(phy->pad_clk);
 242 }
 243
 244 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 245 {
 246         unsigned long val, flags;
 247         void __iomem *base = phy->pad_regs;
 248
 249         if (!utmip_pad_count) {
 250                 pr_err("%s: utmip pad already powered off\n", __func__);
 251                 return -EINVAL;
 252         }
 253
 254         clk_prepare_enable(phy->pad_clk);
 255
 256         spin_lock_irqsave(&utmip_pad_lock, flags);
 257
 258         if (--utmip_pad_count == 0) {
 259                 val = readl(base + UTMIP_BIAS_CFG0);
 260                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 261                 writel(val, base + UTMIP_BIAS_CFG0);
 262         }
 263
 264         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 265
 266         clk_disable_unprepare(phy->pad_clk);
 267
 268         return 0;
 269 }
 270
 271 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 272 {
 273         unsigned long timeout = 2000;
 274         do {
 275                 if ((readl(reg) & mask) == result)
 276                         return 0;
 277                 udelay(1);
 278                 timeout--;
 279         } while (timeout);
 280         return -1;
 281 }
 282
 283 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 284 {
 285         unsigned long val;
 286         void __iomem *base = phy->regs;
 287
 288         if (phy->is_legacy_phy) {
 289                 val = readl(base + USB_SUSP_CTRL);
 290                 val |= USB_SUSP_SET;
 291                 writel(val, base + USB_SUSP_CTRL);
 292
 293                 udelay(10);
 294
 295                 val = readl(base + USB_SUSP_CTRL);
 296                 val &= ~USB_SUSP_SET;
 297                 writel(val, base + USB_SUSP_CTRL);
 298         } else
 299                 set_phcd(phy, true);
 300
 301         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 302                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 303 }
 304
 305 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 306 {
 307         unsigned long val;
 308         void __iomem *base = phy->regs;
 309
 310         if (phy->is_legacy_phy) {
 311                 val = readl(base + USB_SUSP_CTRL);
 312                 val |= USB_SUSP_CLR;
 313                 writel(val, base + USB_SUSP_CTRL);
 314
 315                 udelay(10);
 316
 317                 val = readl(base + USB_SUSP_CTRL);
 318                 val &= ~USB_SUSP_CLR;
 319                 writel(val, base + USB_SUSP_CTRL);
 320         } else
 321                 set_phcd(phy, false);
 322
 323         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 324                                                      USB_PHY_CLK_VALID))
 325                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 326 }
 327
 328 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 329 {
 330         unsigned long val;
 331         void __iomem *base = phy->regs;
 332         struct tegra_utmip_config *config = phy->config;
 333
 334         val = readl(base + USB_SUSP_CTRL);
 335         val |= UTMIP_RESET;
 336         writel(val, base + USB_SUSP_CTRL);
 337
 338         if (phy->is_legacy_phy) {
 339                 val = readl(base + USB1_LEGACY_CTRL);
 340                 val |= USB1_NO_LEGACY_MODE;
 341                 writel(val, base + USB1_LEGACY_CTRL);
 342         }
 343
 344         val = readl(base + UTMIP_TX_CFG0);
 345         val &= ~UTMIP_FS_PREABMLE_J;
 346         writel(val, base + UTMIP_TX_CFG0);
 347
 348         val = readl(base + UTMIP_HSRX_CFG0);
 349         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 350         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 351         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 352         writel(val, base + UTMIP_HSRX_CFG0);
 353
 354         val = readl(base + UTMIP_HSRX_CFG1);
 355         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 356         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 357         writel(val, base + UTMIP_HSRX_CFG1);
 358
 359         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 360         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 361         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 362         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 363
 364         val = readl(base + UTMIP_MISC_CFG0);
 365         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 366         writel(val, base + UTMIP_MISC_CFG0);
 367
 368         val = readl(base + UTMIP_MISC_CFG1);
 369         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
 370         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 371                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 372         writel(val, base + UTMIP_MISC_CFG1);
 373
 374         val = readl(base + UTMIP_PLL_CFG1);
 375         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 376         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 377                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 378         writel(val, base + UTMIP_PLL_CFG1);
 379
 380         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 381                 val = readl(base + USB_SUSP_CTRL);
 382                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 383                 writel(val, base + USB_SUSP_CTRL);
 384         }
 385
 386         utmip_pad_power_on(phy);
 387
 388         val = readl(base + UTMIP_XCVR_CFG0);
 389         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 390                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
 391                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
 392                  UTMIP_XCVR_HSSLEW_MSB(~0));
 393         val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 394         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 395         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 396         writel(val, base + UTMIP_XCVR_CFG0);
 397
 398         val = readl(base + UTMIP_XCVR_CFG1);
 399         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 400                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 401         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 402         writel(val, base + UTMIP_XCVR_CFG1);
 403
 404         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 405         val &= ~UTMIP_PD_CHRG;
 406         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 407
 408         val = readl(base + UTMIP_BIAS_CFG1);
 409         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 410         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 411         writel(val, base + UTMIP_BIAS_CFG1);
 412
 413         if (phy->is_legacy_phy) {
 414                 val = readl(base + UTMIP_SPARE_CFG0);
 415                 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
 416                         val &= ~FUSE_SETUP_SEL;
 417                 else
 418                         val |= FUSE_SETUP_SEL;
 419                 writel(val, base + UTMIP_SPARE_CFG0);
 420         } else {
 421                 val = readl(base + USB_SUSP_CTRL);
 422                 val |= UTMIP_PHY_ENABLE;
 423                 writel(val, base + USB_SUSP_CTRL);
 424         }
 425
 426         val = readl(base + USB_SUSP_CTRL);
 427         val &= ~UTMIP_RESET;
 428         writel(val, base + USB_SUSP_CTRL);
 429
 430         if (phy->is_legacy_phy) {
 431                 val = readl(base + USB1_LEGACY_CTRL);
 432                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 433                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 434                 writel(val, base + USB1_LEGACY_CTRL);
 435
 436                 val = readl(base + USB_SUSP_CTRL);
 437                 val &= ~USB_SUSP_SET;
 438                 writel(val, base + USB_SUSP_CTRL);
 439         }
 440
 441         utmi_phy_clk_enable(phy);
 442
 443         if (!phy->is_legacy_phy)
 444                 set_pts(phy, 0);
 445
 446         return 0;
 447 }
 448
 449 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 450 {
 451         unsigned long val;
 452         void __iomem *base = phy->regs;
 453
 454         utmi_phy_clk_disable(phy);
 455
 456         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 457                 val = readl(base + USB_SUSP_CTRL);
 458                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 459                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 460                 writel(val, base + USB_SUSP_CTRL);
 461         }
 462
 463         val = readl(base + USB_SUSP_CTRL);
 464         val |= UTMIP_RESET;
 465         writel(val, base + USB_SUSP_CTRL);
 466
 467         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 468         val |= UTMIP_PD_CHRG;
 469         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 470
 471         val = readl(base + UTMIP_XCVR_CFG0);
 472         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 473                UTMIP_FORCE_PDZI_POWERDOWN;
 474         writel(val, base + UTMIP_XCVR_CFG0);
 475
 476         val = readl(base + UTMIP_XCVR_CFG1);
 477         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 478                UTMIP_FORCE_PDDR_POWERDOWN;
 479         writel(val, base + UTMIP_XCVR_CFG1);
 480
 481         return utmip_pad_power_off(phy);
 482 }
 483
 484 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 485 {
 486         unsigned long val;
 487         void __iomem *base = phy->regs;
 488
 489         val = readl(base + UTMIP_TX_CFG0);
 490         val |= UTMIP_HS_DISCON_DISABLE;
 491         writel(val, base + UTMIP_TX_CFG0);
 492 }
 493
 494 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 495 {
 496         unsigned long val;
 497         void __iomem *base = phy->regs;
 498
 499         val = readl(base + UTMIP_TX_CFG0);
 500         val &= ~UTMIP_HS_DISCON_DISABLE;
 501         writel(val, base + UTMIP_TX_CFG0);
 502 }
 503
 504 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 505                                    enum tegra_usb_phy_port_speed port_speed)
 506 {
 507         unsigned long val;
 508         void __iomem *base = phy->regs;
 509
 510         val = readl(base + UTMIP_MISC_CFG0);
 511         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 512         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 513                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 514         else
 515                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 516         writel(val, base + UTMIP_MISC_CFG0);
 517         udelay(1);
 518
 519         val = readl(base + UTMIP_MISC_CFG0);
 520         val |= UTMIP_DPDM_OBSERVE;
 521         writel(val, base + UTMIP_MISC_CFG0);
 522         udelay(10);
 523 }
 524
 525 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 526 {
 527         unsigned long val;
 528         void __iomem *base = phy->regs;
 529
 530         val = readl(base + UTMIP_MISC_CFG0);
 531         val &= ~UTMIP_DPDM_OBSERVE;
 532         writel(val, base + UTMIP_MISC_CFG0);
 533         udelay(10);
 534 }
 535
 536 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 537 {
 538         int ret;
 539         unsigned long val;
 540         void __iomem *base = phy->regs;
 541
 542         ret = gpio_direction_output(phy->reset_gpio, 0);
 543         if (ret < 0) {
 544                 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
 545                         phy->reset_gpio);
 546                 return ret;
 547         }
 548         msleep(5);
 549         ret = gpio_direction_output(phy->reset_gpio, 1);
 550         if (ret < 0) {
 551                 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
 552                         phy->reset_gpio);
 553                 return ret;
 554         }
 555
 556         clk_prepare_enable(phy->clk);
 557         msleep(1);
 558
 559         val = readl(base + USB_SUSP_CTRL);
 560         val |= UHSIC_RESET;
 561         writel(val, base + USB_SUSP_CTRL);
 562
 563         val = readl(base + ULPI_TIMING_CTRL_0);
 564         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 565         writel(val, base + ULPI_TIMING_CTRL_0);
 566
 567         val = readl(base + USB_SUSP_CTRL);
 568         val |= ULPI_PHY_ENABLE;
 569         writel(val, base + USB_SUSP_CTRL);
 570
 571         val = 0;
 572         writel(val, base + ULPI_TIMING_CTRL_1);
 573
 574         val |= ULPI_DATA_TRIMMER_SEL(4);
 575         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 576         val |= ULPI_DIR_TRIMMER_SEL(4);
 577         writel(val, base + ULPI_TIMING_CTRL_1);
 578         udelay(10);
 579
 580         val |= ULPI_DATA_TRIMMER_LOAD;
 581         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 582         val |= ULPI_DIR_TRIMMER_LOAD;
 583         writel(val, base + ULPI_TIMING_CTRL_1);
 584
 585         /* Fix VbusInvalid due to floating VBUS */
 586         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 587         if (ret) {
 588                 pr_err("%s: ulpi write failed\n", __func__);
 589                 return ret;
 590         }
 591
 592         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 593         if (ret) {
 594                 pr_err("%s: ulpi write failed\n", __func__);
 595                 return ret;
 596         }
 597
 598         val = readl(base + USB_SUSP_CTRL);
 599         val |= USB_SUSP_CLR;
 600         writel(val, base + USB_SUSP_CTRL);
 601         udelay(100);
 602
 603         val = readl(base + USB_SUSP_CTRL);
 604         val &= ~USB_SUSP_CLR;
 605         writel(val, base + USB_SUSP_CTRL);
 606
 607         return 0;
 608 }
 609
 610 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 611 {
 612         clk_disable(phy->clk);
 613         return gpio_direction_output(phy->reset_gpio, 0);
 614 }
 615
 616 static void tegra_usb_phy_close(struct usb_phy *x)
 617 {
 618         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 619
 620         if (!IS_ERR(phy->vbus))
 621                 regulator_disable(phy->vbus);
 622
 623         clk_disable_unprepare(phy->pll_u);
 624 }
 625
 626 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 627 {
 628         if (phy->is_ulpi_phy)
 629                 return ulpi_phy_power_on(phy);
 630         else
 631                 return utmi_phy_power_on(phy);
 632 }
 633
 634 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 635 {
 636         if (phy->is_ulpi_phy)
 637                 return ulpi_phy_power_off(phy);
 638         else
 639                 return utmi_phy_power_off(phy);
 640 }
 641
 642 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 643 {
 644         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 645         if (suspend)
 646                 return tegra_usb_phy_power_off(phy);
 647         else
 648                 return tegra_usb_phy_power_on(phy);
 649 }
 650
 651 static int ulpi_open(struct tegra_usb_phy *phy)
 652 {
 653         int err;
 654
 655         phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
 656         if (IS_ERR(phy->clk)) {
 657                 pr_err("%s: can't get ulpi clock\n", __func__);
 658                 return PTR_ERR(phy->clk);
 659         }
 660
 661         err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
 662                 "ulpi_phy_reset_b");
 663         if (err < 0) {
 664                 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
 665                        phy->reset_gpio);
 666                 return err;
 667         }
 668
 669         err = gpio_direction_output(phy->reset_gpio, 0);
 670         if (err < 0) {
 671                 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
 672                        phy->reset_gpio);
 673                 return err;
 674         }
 675
 676         phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 677         if (!phy->ulpi) {
 678                 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
 679                 err = -ENOMEM;
 680                 return err;
 681         }
 682
 683         phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 684         return 0;
 685 }
 686
 687 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
 688 {
 689         unsigned long parent_rate;
 690         int i;
 691         int err;
 692
 693         phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
 694         if (IS_ERR(phy->pll_u)) {
 695                 pr_err("Can't get pll_u clock\n");
 696                 return PTR_ERR(phy->pll_u);
 697         }
 698
 699         err = clk_prepare_enable(phy->pll_u);
 700         if (err)
 701                 return err;
 702
 703         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 704         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 705                 if (tegra_freq_table[i].freq == parent_rate) {
 706                         phy->freq = &tegra_freq_table[i];
 707                         break;
 708                 }
 709         }
 710         if (!phy->freq) {
 711                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 712                 err = -EINVAL;
 713                 goto fail;
 714         }
 715
 716         if (!IS_ERR(phy->vbus)) {
 717                 err = regulator_enable(phy->vbus);
 718                 if (err) {
 719                         dev_err(phy->u_phy.dev,
 720                                 "failed to enable usb vbus regulator: %d\n",
 721                                 err);
 722                         goto fail;
 723                 }
 724         }
 725
 726         if (phy->is_ulpi_phy)
 727                 err = ulpi_open(phy);
 728         else
 729                 err = utmip_pad_open(phy);
 730         if (err < 0)
 731                 goto fail;
 732
 733         return 0;
 734
 735 fail:
 736         clk_disable_unprepare(phy->pll_u);
 737         return err;
 738 }
 739
 740 void tegra_usb_phy_preresume(struct usb_phy *x)
 741 {
 742         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 743
 744         if (!phy->is_ulpi_phy)
 745                 utmi_phy_preresume(phy);
 746 }
 747 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 748
 749 void tegra_usb_phy_postresume(struct usb_phy *x)
 750 {
 751         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 752
 753         if (!phy->is_ulpi_phy)
 754                 utmi_phy_postresume(phy);
 755 }
 756 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 757
 758 void tegra_ehci_phy_restore_start(struct usb_phy *x,
 759                                  enum tegra_usb_phy_port_speed port_speed)
 760 {
 761         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 762
 763         if (!phy->is_ulpi_phy)
 764                 utmi_phy_restore_start(phy, port_speed);
 765 }
 766 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 767
 768 void tegra_ehci_phy_restore_end(struct usb_phy *x)
 769 {
 770         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 771
 772         if (!phy->is_ulpi_phy)
 773                 utmi_phy_restore_end(phy);
 774 }
 775 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 776
 777 static int read_utmi_param(struct platform_device *pdev, const char *param,
 778                            u8 *dest)
 779 {
 780         u32 value;
 781         int err = of_property_read_u32(pdev->dev.of_node, param, &value);
 782         *dest = (u8)value;
 783         if (err < 0)
 784                 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
 785                         param, err);
 786         return err;
 787 }
 788
 789 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 790                           struct platform_device *pdev)
 791 {
 792         struct resource *res;
 793         int err;
 794         struct tegra_utmip_config *config;
 795
 796         tegra_phy->is_ulpi_phy = false;
 797
 798         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 799         if (!res) {
 800                 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
 801                 return  -ENXIO;
 802         }
 803
 804         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 805                 resource_size(res));
 806         if (!tegra_phy->regs) {
 807                 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
 808                 return -ENOMEM;
 809         }
 810
 811         tegra_phy->config = devm_kzalloc(&pdev->dev,
 812                 sizeof(*tegra_phy->config), GFP_KERNEL);
 813         if (!tegra_phy->config) {
 814                 dev_err(&pdev->dev,
 815                         "unable to allocate memory for USB UTMIP config\n");
 816                 return -ENOMEM;
 817         }
 818
 819         config = tegra_phy->config;
 820
 821         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 822                 &config->hssync_start_delay);
 823         if (err < 0)
 824                 return err;
 825
 826         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 827                 &config->elastic_limit);
 828         if (err < 0)
 829                 return err;
 830
 831         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
 832                 &config->idle_wait_delay);
 833         if (err < 0)
 834                 return err;
 835
 836         err = read_utmi_param(pdev, "nvidia,term-range-adj",
 837                 &config->term_range_adj);
 838         if (err < 0)
 839                 return err;
 840
 841         err = read_utmi_param(pdev, "nvidia,xcvr-setup",
 842                 &config->xcvr_setup);
 843         if (err < 0)
 844                 return err;
 845
 846         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
 847                 &config->xcvr_lsfslew);
 848         if (err < 0)
 849                 return err;
 850
 851         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
 852                 &config->xcvr_lsrslew);
 853         if (err < 0)
 854                 return err;
 855
 856         return 0;
 857 }
 858
 859 static int tegra_usb_phy_probe(struct platform_device *pdev)
 860 {
 861         struct resource *res;
 862         struct tegra_usb_phy *tegra_phy = NULL;
 863         struct device_node *np = pdev->dev.of_node;
 864         enum usb_phy_interface phy_type;
 865         int err;
 866
 867         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
 868         if (!tegra_phy) {
 869                 dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
 870                 return -ENOMEM;
 871         }
 872
 873         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 874         if (!res) {
 875                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
 876                 return  -ENXIO;
 877         }
 878
 879         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
 880                 resource_size(res));
 881         if (!tegra_phy->regs) {
 882                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 883                 return -ENOMEM;
 884         }
 885
 886         tegra_phy->is_legacy_phy =
 887                 of_property_read_bool(np, "nvidia,has-legacy-mode");
 888
 889         phy_type = of_usb_get_phy_mode(np);
 890         if (phy_type == USBPHY_INTERFACE_MODE_UTMI) {
 891                 err = utmi_phy_probe(tegra_phy, pdev);
 892                 if (err < 0)
 893                         return err;
 894         } else if (phy_type == USBPHY_INTERFACE_MODE_ULPI) {
 895                 tegra_phy->is_ulpi_phy = true;
 896
 897                 tegra_phy->reset_gpio =
 898                         of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
 899                 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
 900                         dev_err(&pdev->dev, "invalid gpio: %d\n",
 901                                 tegra_phy->reset_gpio);
 902                         return tegra_phy->reset_gpio;
 903                 }
 904                 tegra_phy->config = NULL;
 905         } else {
 906                 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
 907                 return -EINVAL;
 908         }
 909
 910         err = of_property_match_string(np, "dr_mode", "otg");
 911         if (err < 0) {
 912                 err = of_property_match_string(np, "dr_mode", "peripheral");
 913                 if (err < 0)
 914                         tegra_phy->mode = TEGRA_USB_PHY_MODE_HOST;
 915                 else
 916                         tegra_phy->mode = TEGRA_USB_PHY_MODE_DEVICE;
 917         } else
 918                 tegra_phy->mode = TEGRA_USB_PHY_MODE_OTG;
 919
 920         /* On some boards, the VBUS regulator doesn't need to be controlled */
 921         if (of_find_property(np, "vbus-supply", NULL)) {
 922                 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
 923                 if (IS_ERR(tegra_phy->vbus))
 924                         return PTR_ERR(tegra_phy->vbus);
 925         } else {
 926                 dev_notice(&pdev->dev, "no vbus regulator");
 927                 tegra_phy->vbus = ERR_PTR(-ENODEV);
 928         }
 929
 930         tegra_phy->u_phy.dev = &pdev->dev;
 931         err = tegra_usb_phy_init(tegra_phy);
 932         if (err < 0)
 933                 return err;
 934
 935         tegra_phy->u_phy.shutdown = tegra_usb_phy_close;
 936         tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
 937
 938         dev_set_drvdata(&pdev->dev, tegra_phy);
 939
 940         err = usb_add_phy_dev(&tegra_phy->u_phy);
 941         if (err < 0) {
 942                 tegra_usb_phy_close(&tegra_phy->u_phy);
 943                 return err;
 944         }
 945
 946         return 0;
 947 }
 948
 949 static int tegra_usb_phy_remove(struct platform_device *pdev)
 950 {
 951         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
 952
 953         usb_remove_phy(&tegra_phy->u_phy);
 954
 955         return 0;
 956 }
 957
 958 static struct of_device_id tegra_usb_phy_id_table[] = {
 959         { .compatible = "nvidia,tegra20-usb-phy", },
 960         { },
 961 };
 962 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
 963
 964 static struct platform_driver tegra_usb_phy_driver = {
 965         .probe          = tegra_usb_phy_probe,
 966         .remove         = tegra_usb_phy_remove,
 967         .driver         = {
 968                 .name   = "tegra-phy",
 969                 .owner  = THIS_MODULE,
 970                 .of_match_table = of_match_ptr(tegra_usb_phy_id_table),
 971         },
 972 };
 973 module_platform_driver(tegra_usb_phy_driver);
 974
 975 MODULE_DESCRIPTION("Tegra USB PHY driver");
 976 MODULE_LICENSE("GPL v2");