drivers/usb/phy/phy-twl4030-usb.c

   1 /*
   2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
   3  *
   4  * Copyright (C) 2004-2007 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Current status:
  23  *      - HS USB ULPI mode works.
  24  *      - 3-pin mode support may be added in future.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/io.h>
  34 #include <linux/delay.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/musb-omap.h>
  37 #include <linux/usb/ulpi.h>
  38 #include <linux/i2c/twl.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/err.h>
  41 #include <linux/slab.h>
  42
  43 /* Register defines */
  44
  45 #define MCPC_CTRL                       0x30
  46 #define MCPC_CTRL_RTSOL                 (1 << 7)
  47 #define MCPC_CTRL_EXTSWR                (1 << 6)
  48 #define MCPC_CTRL_EXTSWC                (1 << 5)
  49 #define MCPC_CTRL_VOICESW               (1 << 4)
  50 #define MCPC_CTRL_OUT64K                (1 << 3)
  51 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
  52 #define MCPC_CTRL_HS_UART               (1 << 0)
  53
  54 #define MCPC_IO_CTRL                    0x33
  55 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
  56 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
  57 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
  58 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
  59 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
  60 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
  61
  62 #define MCPC_CTRL2                      0x36
  63 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
  64
  65 #define OTHER_FUNC_CTRL                 0x80
  66 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
  67 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
  68
  69 #define OTHER_IFC_CTRL                  0x83
  70 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
  71 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
  72 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
  73 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
  74 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
  75 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
  76
  77 #define OTHER_INT_EN_RISE               0x86
  78 #define OTHER_INT_EN_FALL               0x89
  79 #define OTHER_INT_STS                   0x8C
  80 #define OTHER_INT_LATCH                 0x8D
  81 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
  82 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
  83 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
  84 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
  85 #define OTHER_INT_MANU                  (1 << 1)
  86 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
  87
  88 #define ID_STATUS                       0x96
  89 #define ID_RES_FLOAT                    (1 << 4)
  90 #define ID_RES_440K                     (1 << 3)
  91 #define ID_RES_200K                     (1 << 2)
  92 #define ID_RES_102K                     (1 << 1)
  93 #define ID_RES_GND                      (1 << 0)
  94
  95 #define POWER_CTRL                      0xAC
  96 #define POWER_CTRL_OTG_ENAB             (1 << 5)
  97
  98 #define OTHER_IFC_CTRL2                 0xAF
  99 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
 100 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
 101 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
 102 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
 103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
 104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
 105
 106 #define REG_CTRL_EN                     0xB2
 107 #define REG_CTRL_ERROR                  0xB5
 108 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
 109
 110 #define OTHER_FUNC_CTRL2                0xB8
 111 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
 112
 113 /* following registers do not have separate _clr and _set registers */
 114 #define VBUS_DEBOUNCE                   0xC0
 115 #define ID_DEBOUNCE                     0xC1
 116 #define VBAT_TIMER                      0xD3
 117 #define PHY_PWR_CTRL                    0xFD
 118 #define PHY_PWR_PHYPWD                  (1 << 0)
 119 #define PHY_CLK_CTRL                    0xFE
 120 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
 121 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
 122 #define REQ_PHY_DPLL_CLK                (1 << 0)
 123 #define PHY_CLK_CTRL_STS                0xFF
 124 #define PHY_DPLL_CLK                    (1 << 0)
 125
 126 /* In module TWL_MODULE_PM_MASTER */
 127 #define STS_HW_CONDITIONS               0x0F
 128
 129 /* In module TWL_MODULE_PM_RECEIVER */
 130 #define VUSB_DEDICATED1                 0x7D
 131 #define VUSB_DEDICATED2                 0x7E
 132 #define VUSB1V5_DEV_GRP                 0x71
 133 #define VUSB1V5_TYPE                    0x72
 134 #define VUSB1V5_REMAP                   0x73
 135 #define VUSB1V8_DEV_GRP                 0x74
 136 #define VUSB1V8_TYPE                    0x75
 137 #define VUSB1V8_REMAP                   0x76
 138 #define VUSB3V1_DEV_GRP                 0x77
 139 #define VUSB3V1_TYPE                    0x78
 140 #define VUSB3V1_REMAP                   0x79
 141
 142 /* In module TWL4030_MODULE_INTBR */
 143 #define PMBR1                           0x0D
 144 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
 145
 146 struct twl4030_usb {
 147         struct usb_phy          phy;
 148         struct device           *dev;
 149
 150         /* TWL4030 internal USB regulator supplies */
 151         struct regulator        *usb1v5;
 152         struct regulator        *usb1v8;
 153         struct regulator        *usb3v1;
 154
 155         /* for vbus reporting with irqs disabled */
 156         spinlock_t              lock;
 157
 158         /* pin configuration */
 159         enum twl4030_usb_mode   usb_mode;
 160
 161         int                     irq;
 162         enum omap_musb_vbus_id_status linkstat;
 163         bool                    vbus_supplied;
 164         u8                      asleep;
 165         bool                    irq_enabled;
 166
 167         struct delayed_work     id_workaround_work;
 168 };
 169
 170 /* internal define on top of container_of */
 171 #define phy_to_twl(x)           container_of((x), struct twl4030_usb, phy)
 172
 173 /*-------------------------------------------------------------------------*/
 174
 175 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
 176                 u8 module, u8 data, u8 address)
 177 {
 178         u8 check;
 179
 180         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 181             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 182                                                 (check == data))
 183                 return 0;
 184         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 185                         1, module, address, check, data);
 186
 187         /* Failed once: Try again */
 188         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 189             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 190                                                 (check == data))
 191                 return 0;
 192         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 193                         2, module, address, check, data);
 194
 195         /* Failed again: Return error */
 196         return -EBUSY;
 197 }
 198
 199 #define twl4030_usb_write_verify(twl, address, data)    \
 200         twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
 201
 202 static inline int twl4030_usb_write(struct twl4030_usb *twl,
 203                 u8 address, u8 data)
 204 {
 205         int ret = 0;
 206
 207         ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
 208         if (ret < 0)
 209                 dev_dbg(twl->dev,
 210                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 211         return ret;
 212 }
 213
 214 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
 215 {
 216         u8 data;
 217         int ret = 0;
 218
 219         ret = twl_i2c_read_u8(module, &data, address);
 220         if (ret >= 0)
 221                 ret = data;
 222         else
 223                 dev_dbg(twl->dev,
 224                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
 225                                         module, address, ret);
 226
 227         return ret;
 228 }
 229
 230 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
 231 {
 232         return twl4030_readb(twl, TWL_MODULE_USB, address);
 233 }
 234
 235 /*-------------------------------------------------------------------------*/
 236
 237 static inline int
 238 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 239 {
 240         return twl4030_usb_write(twl, ULPI_SET(reg), bits);
 241 }
 242
 243 static inline int
 244 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 245 {
 246         return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
 247 }
 248
 249 /*-------------------------------------------------------------------------*/
 250
 251 static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
 252 {
 253         int ret;
 254
 255         ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
 256         if (ret < 0 || !(ret & PHY_DPLL_CLK))
 257                 /*
 258                  * if clocks are off, registers are not updated,
 259                  * but we can assume we don't drive VBUS in this case
 260                  */
 261                 return false;
 262
 263         ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
 264         if (ret < 0)
 265                 return false;
 266
 267         return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
 268 }
 269
 270 static enum omap_musb_vbus_id_status
 271         twl4030_usb_linkstat(struct twl4030_usb *twl)
 272 {
 273         int     status;
 274         enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
 275
 276         twl->vbus_supplied = false;
 277
 278         /*
 279          * For ID/VBUS sensing, see manual section 15.4.8 ...
 280          * except when using only battery backup power, two
 281          * comparators produce VBUS_PRES and ID_PRES signals,
 282          * which don't match docs elsewhere.  But ... BIT(7)
 283          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
 284          * seem to match up.  If either is true the USB_PRES
 285          * signal is active, the OTG module is activated, and
 286          * its interrupt may be raised (may wake the system).
 287          */
 288         status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
 289         if (status < 0)
 290                 dev_err(twl->dev, "USB link status err %d\n", status);
 291         else if (status & (BIT(7) | BIT(2))) {
 292                 if (status & BIT(7)) {
 293                         if (twl4030_is_driving_vbus(twl))
 294                                 status &= ~BIT(7);
 295                         else
 296                                 twl->vbus_supplied = true;
 297                 }
 298
 299                 if (status & BIT(2))
 300                         linkstat = OMAP_MUSB_ID_GROUND;
 301                 else if (status & BIT(7))
 302                         linkstat = OMAP_MUSB_VBUS_VALID;
 303                 else
 304                         linkstat = OMAP_MUSB_VBUS_OFF;
 305         } else {
 306                 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
 307                         linkstat = OMAP_MUSB_VBUS_OFF;
 308         }
 309
 310         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
 311                         status, status, linkstat);
 312
 313         /* REVISIT this assumes host and peripheral controllers
 314          * are registered, and that both are active...
 315          */
 316
 317         return linkstat;
 318 }
 319
 320 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
 321 {
 322         twl->usb_mode = mode;
 323
 324         switch (mode) {
 325         case T2_USB_MODE_ULPI:
 326                 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
 327                                         ULPI_IFC_CTRL_CARKITMODE);
 328                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 329                 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
 330                                         ULPI_FUNC_CTRL_XCVRSEL_MASK |
 331                                         ULPI_FUNC_CTRL_OPMODE_MASK);
 332                 break;
 333         case -1:
 334                 /* FIXME: power on defaults */
 335                 break;
 336         default:
 337                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
 338                                 mode);
 339                 break;
 340         };
 341 }
 342
 343 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
 344 {
 345         unsigned long timeout;
 346         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 347
 348         if (val >= 0) {
 349                 if (on) {
 350                         /* enable DPLL to access PHY registers over I2C */
 351                         val |= REQ_PHY_DPLL_CLK;
 352                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 353                                                 (u8)val) < 0);
 354
 355                         timeout = jiffies + HZ;
 356                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 357                                                         PHY_DPLL_CLK)
 358                                 && time_before(jiffies, timeout))
 359                                         udelay(10);
 360                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 361                                                         PHY_DPLL_CLK))
 362                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
 363                                                 "PHY DPLL clock\n");
 364                 } else {
 365                         /* let ULPI control the DPLL clock */
 366                         val &= ~REQ_PHY_DPLL_CLK;
 367                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 368                                                 (u8)val) < 0);
 369                 }
 370         }
 371 }
 372
 373 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
 374 {
 375         u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
 376
 377         if (on)
 378                 pwr &= ~PHY_PWR_PHYPWD;
 379         else
 380                 pwr |= PHY_PWR_PHYPWD;
 381
 382         WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 383 }
 384
 385 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
 386 {
 387         int ret;
 388
 389         if (on) {
 390                 ret = regulator_enable(twl->usb3v1);
 391                 if (ret)
 392                         dev_err(twl->dev, "Failed to enable usb3v1\n");
 393
 394                 ret = regulator_enable(twl->usb1v8);
 395                 if (ret)
 396                         dev_err(twl->dev, "Failed to enable usb1v8\n");
 397
 398                 /*
 399                  * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
 400                  * in twl4030) resets the VUSB_DEDICATED2 register. This reset
 401                  * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
 402                  * SLEEP. We work around this by clearing the bit after usv3v1
 403                  * is re-activated. This ensures that VUSB3V1 is really active.
 404                  */
 405                 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
 406
 407                 ret = regulator_enable(twl->usb1v5);
 408                 if (ret)
 409                         dev_err(twl->dev, "Failed to enable usb1v5\n");
 410
 411                 __twl4030_phy_power(twl, 1);
 412                 twl4030_usb_write(twl, PHY_CLK_CTRL,
 413                                   twl4030_usb_read(twl, PHY_CLK_CTRL) |
 414                                         (PHY_CLK_CTRL_CLOCKGATING_EN |
 415                                                 PHY_CLK_CTRL_CLK32K_EN));
 416         } else {
 417                 __twl4030_phy_power(twl, 0);
 418                 regulator_disable(twl->usb1v5);
 419                 regulator_disable(twl->usb1v8);
 420                 regulator_disable(twl->usb3v1);
 421         }
 422 }
 423
 424 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
 425 {
 426         if (twl->asleep)
 427                 return;
 428
 429         twl4030_phy_power(twl, 0);
 430         twl->asleep = 1;
 431         dev_dbg(twl->dev, "%s\n", __func__);
 432 }
 433
 434 static void __twl4030_phy_resume(struct twl4030_usb *twl)
 435 {
 436         twl4030_phy_power(twl, 1);
 437         twl4030_i2c_access(twl, 1);
 438         twl4030_usb_set_mode(twl, twl->usb_mode);
 439         if (twl->usb_mode == T2_USB_MODE_ULPI)
 440                 twl4030_i2c_access(twl, 0);
 441 }
 442
 443 static void twl4030_phy_resume(struct twl4030_usb *twl)
 444 {
 445         if (!twl->asleep)
 446                 return;
 447         __twl4030_phy_resume(twl);
 448         twl->asleep = 0;
 449         dev_dbg(twl->dev, "%s\n", __func__);
 450
 451         /*
 452          * XXX When VBUS gets driven after musb goes to A mode,
 453          * ID_PRES related interrupts no longer arrive, why?
 454          * Register itself is updated fine though, so we must poll.
 455          */
 456         if (twl->linkstat == OMAP_MUSB_ID_GROUND) {
 457                 cancel_delayed_work(&twl->id_workaround_work);
 458                 schedule_delayed_work(&twl->id_workaround_work, HZ);
 459         }
 460 }
 461
 462 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
 463 {
 464         /* Enable writing to power configuration registers */
 465         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
 466                          TWL4030_PM_MASTER_PROTECT_KEY);
 467
 468         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
 469                          TWL4030_PM_MASTER_PROTECT_KEY);
 470
 471         /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
 472         /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
 473
 474         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
 475         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
 476
 477         /* Initialize 3.1V regulator */
 478         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
 479
 480         twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
 481         if (IS_ERR(twl->usb3v1))
 482                 return -ENODEV;
 483
 484         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
 485
 486         /* Initialize 1.5V regulator */
 487         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
 488
 489         twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
 490         if (IS_ERR(twl->usb1v5))
 491                 return -ENODEV;
 492
 493         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
 494
 495         /* Initialize 1.8V regulator */
 496         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
 497
 498         twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
 499         if (IS_ERR(twl->usb1v8))
 500                 return -ENODEV;
 501
 502         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
 503
 504         /* disable access to power configuration registers */
 505         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
 506                          TWL4030_PM_MASTER_PROTECT_KEY);
 507
 508         return 0;
 509 }
 510
 511 static ssize_t twl4030_usb_vbus_show(struct device *dev,
 512                 struct device_attribute *attr, char *buf)
 513 {
 514         struct twl4030_usb *twl = dev_get_drvdata(dev);
 515         unsigned long flags;
 516         int ret = -EINVAL;
 517
 518         spin_lock_irqsave(&twl->lock, flags);
 519         ret = sprintf(buf, "%s\n",
 520                         twl->vbus_supplied ? "on" : "off");
 521         spin_unlock_irqrestore(&twl->lock, flags);
 522
 523         return ret;
 524 }
 525 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
 526
 527 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
 528 {
 529         struct twl4030_usb *twl = _twl;
 530         enum omap_musb_vbus_id_status status;
 531         bool status_changed = false;
 532
 533         status = twl4030_usb_linkstat(twl);
 534
 535         spin_lock_irq(&twl->lock);
 536         if (status >= 0 && status != twl->linkstat) {
 537                 twl->linkstat = status;
 538                 status_changed = true;
 539         }
 540         spin_unlock_irq(&twl->lock);
 541
 542         if (status_changed) {
 543                 /* FIXME add a set_power() method so that B-devices can
 544                  * configure the charger appropriately.  It's not always
 545                  * correct to consume VBUS power, and how much current to
 546                  * consume is a function of the USB configuration chosen
 547                  * by the host.
 548                  *
 549                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
 550                  * its disconnect() sibling, when changing to/from the
 551                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
 552                  * starts to handle softconnect right.
 553                  */
 554                 omap_musb_mailbox(status);
 555         }
 556         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 557
 558         return IRQ_HANDLED;
 559 }
 560
 561 static void twl4030_id_workaround_work(struct work_struct *work)
 562 {
 563         struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
 564                 id_workaround_work.work);
 565         enum omap_musb_vbus_id_status status;
 566         bool status_changed = false;
 567
 568         status = twl4030_usb_linkstat(twl);
 569
 570         spin_lock_irq(&twl->lock);
 571         if (status >= 0 && status != twl->linkstat) {
 572                 twl->linkstat = status;
 573                 status_changed = true;
 574         }
 575         spin_unlock_irq(&twl->lock);
 576
 577         if (status_changed) {
 578                 dev_dbg(twl->dev, "handle missing status change to %d\n",
 579                                 status);
 580                 omap_musb_mailbox(status);
 581         }
 582
 583         /* don't schedule during sleep - irq works right then */
 584         if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) {
 585                 cancel_delayed_work(&twl->id_workaround_work);
 586                 schedule_delayed_work(&twl->id_workaround_work, HZ);
 587         }
 588 }
 589
 590 static int twl4030_usb_phy_init(struct usb_phy *phy)
 591 {
 592         struct twl4030_usb *twl = phy_to_twl(phy);
 593         enum omap_musb_vbus_id_status status;
 594
 595         /*
 596          * Start in sleep state, we'll get called through set_suspend()
 597          * callback when musb is runtime resumed and it's time to start.
 598          */
 599         __twl4030_phy_power(twl, 0);
 600         twl->asleep = 1;
 601
 602         status = twl4030_usb_linkstat(twl);
 603         twl->linkstat = status;
 604
 605         if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID)
 606                 omap_musb_mailbox(twl->linkstat);
 607
 608         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 609         return 0;
 610 }
 611
 612 static int twl4030_set_suspend(struct usb_phy *x, int suspend)
 613 {
 614         struct twl4030_usb *twl = phy_to_twl(x);
 615
 616         if (suspend)
 617                 twl4030_phy_suspend(twl, 1);
 618         else
 619                 twl4030_phy_resume(twl);
 620
 621         return 0;
 622 }
 623
 624 static int twl4030_set_peripheral(struct usb_otg *otg,
 625                                         struct usb_gadget *gadget)
 626 {
 627         if (!otg)
 628                 return -ENODEV;
 629
 630         otg->gadget = gadget;
 631         if (!gadget)
 632                 otg->phy->state = OTG_STATE_UNDEFINED;
 633
 634         return 0;
 635 }
 636
 637 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
 638 {
 639         if (!otg)
 640                 return -ENODEV;
 641
 642         otg->host = host;
 643         if (!host)
 644                 otg->phy->state = OTG_STATE_UNDEFINED;
 645
 646         return 0;
 647 }
 648
 649 static int twl4030_usb_probe(struct platform_device *pdev)
 650 {
 651         struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
 652         struct twl4030_usb      *twl;
 653         int                     status, err;
 654         struct usb_otg          *otg;
 655         struct device_node      *np = pdev->dev.of_node;
 656
 657         twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
 658         if (!twl)
 659                 return -ENOMEM;
 660
 661         if (np)
 662                 of_property_read_u32(np, "usb_mode",
 663                                 (enum twl4030_usb_mode *)&twl->usb_mode);
 664         else if (pdata)
 665                 twl->usb_mode = pdata->usb_mode;
 666         else {
 667                 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
 668                 return -EINVAL;
 669         }
 670
 671         otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
 672         if (!otg)
 673                 return -ENOMEM;
 674
 675         twl->dev                = &pdev->dev;
 676         twl->irq                = platform_get_irq(pdev, 0);
 677         twl->vbus_supplied      = false;
 678         twl->asleep             = 1;
 679         twl->linkstat           = OMAP_MUSB_UNKNOWN;
 680
 681         twl->phy.dev            = twl->dev;
 682         twl->phy.label          = "twl4030";
 683         twl->phy.otg            = otg;
 684         twl->phy.type           = USB_PHY_TYPE_USB2;
 685         twl->phy.set_suspend    = twl4030_set_suspend;
 686         twl->phy.init           = twl4030_usb_phy_init;
 687
 688         otg->phy                = &twl->phy;
 689         otg->set_host           = twl4030_set_host;
 690         otg->set_peripheral     = twl4030_set_peripheral;
 691
 692         /* init spinlock for workqueue */
 693         spin_lock_init(&twl->lock);
 694
 695         INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
 696
 697         err = twl4030_usb_ldo_init(twl);
 698         if (err) {
 699                 dev_err(&pdev->dev, "ldo init failed\n");
 700                 return err;
 701         }
 702         usb_add_phy_dev(&twl->phy);
 703
 704         platform_set_drvdata(pdev, twl);
 705         if (device_create_file(&pdev->dev, &dev_attr_vbus))
 706                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 707
 708         ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
 709
 710         /* Our job is to use irqs and status from the power module
 711          * to keep the transceiver disabled when nothing's connected.
 712          *
 713          * FIXME we actually shouldn't start enabling it until the
 714          * USB controller drivers have said they're ready, by calling
 715          * set_host() and/or set_peripheral() ... OTG_capable boards
 716          * need both handles, otherwise just one suffices.
 717          */
 718         twl->irq_enabled = true;
 719         status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
 720                         twl4030_usb_irq, IRQF_TRIGGER_FALLING |
 721                         IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
 722         if (status < 0) {
 723                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
 724                         twl->irq, status);
 725                 return status;
 726         }
 727
 728         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
 729         return 0;
 730 }
 731
 732 static int twl4030_usb_remove(struct platform_device *pdev)
 733 {
 734         struct twl4030_usb *twl = platform_get_drvdata(pdev);
 735         int val;
 736
 737         cancel_delayed_work(&twl->id_workaround_work);
 738         device_remove_file(twl->dev, &dev_attr_vbus);
 739
 740         /* set transceiver mode to power on defaults */
 741         twl4030_usb_set_mode(twl, -1);
 742
 743         /* autogate 60MHz ULPI clock,
 744          * clear dpll clock request for i2c access,
 745          * disable 32KHz
 746          */
 747         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 748         if (val >= 0) {
 749                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
 750                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
 751                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
 752         }
 753
 754         /* disable complete OTG block */
 755         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 756
 757         if (!twl->asleep)
 758                 twl4030_phy_power(twl, 0);
 759
 760         return 0;
 761 }
 762
 763 #ifdef CONFIG_OF
 764 static const struct of_device_id twl4030_usb_id_table[] = {
 765         { .compatible = "ti,twl4030-usb" },
 766         {}
 767 };
 768 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
 769 #endif
 770
 771 static struct platform_driver twl4030_usb_driver = {
 772         .probe          = twl4030_usb_probe,
 773         .remove         = twl4030_usb_remove,
 774         .driver         = {
 775                 .name   = "twl4030_usb",
 776                 .owner  = THIS_MODULE,
 777                 .of_match_table = of_match_ptr(twl4030_usb_id_table),
 778         },
 779 };
 780
 781 static int __init twl4030_usb_init(void)
 782 {
 783         return platform_driver_register(&twl4030_usb_driver);
 784 }
 785 subsys_initcall(twl4030_usb_init);
 786
 787 static void __exit twl4030_usb_exit(void)
 788 {
 789         platform_driver_unregister(&twl4030_usb_driver);
 790 }
 791 module_exit(twl4030_usb_exit);
 792
 793 MODULE_ALIAS("platform:twl4030_usb");
 794 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
 795 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
 796 MODULE_LICENSE("GPL");