1 /* linux/drivers/usb/phy/samsung-usbphy.c
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Author: Praveen Paneri <p.paneri@samsung.com>
8 * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
27 #include <linux/usb/otg.h>
28 #include <linux/platform_data/samsung-usbphy.h>
30 /* Register definitions */
32 #define SAMSUNG_PHYPWR (0x00)
34 #define PHYPWR_NORMAL_MASK (0x19 << 0)
35 #define PHYPWR_OTG_DISABLE (0x1 << 4)
36 #define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
37 #define PHYPWR_FORCE_SUSPEND (0x1 << 1)
39 #define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
40 #define PHYPWR_SLEEP_PHY0 (0x1 << 5)
42 #define SAMSUNG_PHYCLK (0x04)
44 #define PHYCLK_MODE_USB11 (0x1 << 6)
45 #define PHYCLK_EXT_OSC (0x1 << 5)
46 #define PHYCLK_COMMON_ON_N (0x1 << 4)
47 #define PHYCLK_ID_PULL (0x1 << 2)
48 #define PHYCLK_CLKSEL_MASK (0x3 << 0)
49 #define PHYCLK_CLKSEL_48M (0x0 << 0)
50 #define PHYCLK_CLKSEL_12M (0x2 << 0)
51 #define PHYCLK_CLKSEL_24M (0x3 << 0)
53 #define SAMSUNG_RSTCON (0x08)
55 #define RSTCON_PHYLINK_SWRST (0x1 << 2)
56 #define RSTCON_HLINK_SWRST (0x1 << 1)
57 #define RSTCON_SWRST (0x1 << 0)
60 #define MHZ (1000*1000)
63 enum samsung_cpu_type {
69 * struct samsung_usbphy - transceiver driver state
70 * @phy: transceiver structure
71 * @plat: platform data
72 * @dev: The parent device supplied to the probe function
74 * @regs: usb phy register memory base
75 * @ref_clk_freq: reference clock frequency selection
76 * @cpu_type: machine identifier
78 struct samsung_usbphy {
80 struct samsung_usbphy_data *plat;
88 #define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
91 * Returns reference clock frequency selection value
93 static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
98 ref_clk = clk_get(sphy->dev, "xusbxti");
99 if (IS_ERR(ref_clk)) {
100 dev_err(sphy->dev, "Failed to get reference clock\n");
101 return PTR_ERR(ref_clk);
104 switch (clk_get_rate(ref_clk)) {
106 refclk_freq = PHYCLK_CLKSEL_12M;
109 refclk_freq = PHYCLK_CLKSEL_24M;
112 refclk_freq = PHYCLK_CLKSEL_48M;
115 if (sphy->cpu_type == TYPE_S3C64XX)
116 refclk_freq = PHYCLK_CLKSEL_48M;
118 refclk_freq = PHYCLK_CLKSEL_24M;
126 static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
128 void __iomem *regs = sphy->regs;
133 /* set clock frequency for PLL */
134 phyclk = sphy->ref_clk_freq;
135 phypwr = readl(regs + SAMSUNG_PHYPWR);
136 rstcon = readl(regs + SAMSUNG_RSTCON);
138 switch (sphy->cpu_type) {
140 phyclk &= ~PHYCLK_COMMON_ON_N;
141 phypwr &= ~PHYPWR_NORMAL_MASK;
142 rstcon |= RSTCON_SWRST;
144 case TYPE_EXYNOS4210:
145 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
146 rstcon |= RSTCON_SWRST;
151 writel(phyclk, regs + SAMSUNG_PHYCLK);
152 /* Configure PHY0 for normal operation*/
153 writel(phypwr, regs + SAMSUNG_PHYPWR);
154 /* reset all ports of PHY and Link */
155 writel(rstcon, regs + SAMSUNG_RSTCON);
157 rstcon &= ~RSTCON_SWRST;
158 writel(rstcon, regs + SAMSUNG_RSTCON);
161 static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
163 void __iomem *regs = sphy->regs;
166 phypwr = readl(regs + SAMSUNG_PHYPWR);
168 switch (sphy->cpu_type) {
170 phypwr |= PHYPWR_NORMAL_MASK;
172 case TYPE_EXYNOS4210:
173 phypwr |= PHYPWR_NORMAL_MASK_PHY0;
178 /* Disable analog and otg block power */
179 writel(phypwr, regs + SAMSUNG_PHYPWR);
183 * The function passed to the usb driver for phy initialization
185 static int samsung_usbphy_init(struct usb_phy *phy)
187 struct samsung_usbphy *sphy;
190 sphy = phy_to_sphy(phy);
192 /* Enable the phy clock */
193 ret = clk_prepare_enable(sphy->clk);
195 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
199 /* Disable phy isolation */
200 if (sphy->plat && sphy->plat->pmu_isolation)
201 sphy->plat->pmu_isolation(false);
203 /* Initialize usb phy registers */
204 samsung_usbphy_enable(sphy);
206 /* Disable the phy clock */
207 clk_disable_unprepare(sphy->clk);
212 * The function passed to the usb driver for phy shutdown
214 static void samsung_usbphy_shutdown(struct usb_phy *phy)
216 struct samsung_usbphy *sphy;
218 sphy = phy_to_sphy(phy);
220 if (clk_prepare_enable(sphy->clk)) {
221 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
225 /* De-initialize usb phy registers */
226 samsung_usbphy_disable(sphy);
228 /* Enable phy isolation */
229 if (sphy->plat && sphy->plat->pmu_isolation)
230 sphy->plat->pmu_isolation(true);
232 clk_disable_unprepare(sphy->clk);
235 static const struct of_device_id samsung_usbphy_dt_match[];
237 static inline int samsung_usbphy_get_driver_data(struct platform_device *pdev)
239 if (pdev->dev.of_node) {
240 const struct of_device_id *match;
241 match = of_match_node(samsung_usbphy_dt_match,
243 return (int) match->data;
246 return platform_get_device_id(pdev)->driver_data;
249 static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
251 struct samsung_usbphy *sphy;
252 struct samsung_usbphy_data *pdata;
253 struct device *dev = &pdev->dev;
254 struct resource *phy_mem;
255 void __iomem *phy_base;
258 pdata = pdev->dev.platform_data;
260 dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
264 phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
266 dev_err(dev, "%s: missing mem resource\n", __func__);
270 phy_base = devm_request_and_ioremap(dev, phy_mem);
272 dev_err(dev, "%s: register mapping failed\n", __func__);
276 sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
280 clk = devm_clk_get(dev, "otg");
282 dev_err(dev, "Failed to get otg clock\n");
286 sphy->dev = &pdev->dev;
288 sphy->regs = phy_base;
290 sphy->phy.dev = sphy->dev;
291 sphy->phy.label = "samsung-usbphy";
292 sphy->phy.init = samsung_usbphy_init;
293 sphy->phy.shutdown = samsung_usbphy_shutdown;
294 sphy->cpu_type = samsung_usbphy_get_driver_data(pdev);
295 sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
297 platform_set_drvdata(pdev, sphy);
299 return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
302 static int __exit samsung_usbphy_remove(struct platform_device *pdev)
304 struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
306 usb_remove_phy(&sphy->phy);
312 static const struct of_device_id samsung_usbphy_dt_match[] = {
314 .compatible = "samsung,s3c64xx-usbphy",
315 .data = (void *)TYPE_S3C64XX,
317 .compatible = "samsung,exynos4210-usbphy",
318 .data = (void *)TYPE_EXYNOS4210,
322 MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
325 static struct platform_device_id samsung_usbphy_driver_ids[] = {
327 .name = "s3c64xx-usbphy",
328 .driver_data = TYPE_S3C64XX,
330 .name = "exynos4210-usbphy",
331 .driver_data = TYPE_EXYNOS4210,
336 MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
338 static struct platform_driver samsung_usbphy_driver = {
339 .probe = samsung_usbphy_probe,
340 .remove = __devexit_p(samsung_usbphy_remove),
341 .id_table = samsung_usbphy_driver_ids,
343 .name = "samsung-usbphy",
344 .owner = THIS_MODULE,
345 .of_match_table = of_match_ptr(samsung_usbphy_dt_match),
349 module_platform_driver(samsung_usbphy_driver);
351 MODULE_DESCRIPTION("Samsung USB phy controller");
352 MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
353 MODULE_LICENSE("GPL");
354 MODULE_ALIAS("platform:samsung-usbphy");