2 * Driver for AT91/AT32 MULTI LAYER LCD Controller
4 * Copyright (C) 2012 Atmel Corporation
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/clk.h>
14 #include <atmel_hlcdc.h>
16 #if defined(CONFIG_LCD_LOGO)
20 /* configurable parameters */
21 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
22 #define ATMEL_LCDC_DMA_BURST_LEN 8
23 #ifndef ATMEL_LCDC_GUARD_TIME
24 #define ATMEL_LCDC_GUARD_TIME 1
27 #define ATMEL_LCDC_FIFO_SIZE 512
29 #define lcdc_readl(reg) __raw_readl((reg))
30 #define lcdc_writel(reg, val) __raw_writel((val), (reg))
33 * the CLUT register map as following
34 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
36 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
38 lcdc_writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
39 ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) |
40 ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) |
41 ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
44 ushort *configuration_get_cmap(void)
46 #if defined(CONFIG_LCD_LOGO)
47 return bmp_logo_palette;
53 ushort *configuration_get_cmap(void)
55 #if defined(CONFIG_LCD_LOGO)
56 return bmp_logo_palette;
62 void lcd_ctrl_init(void *lcdbase)
65 struct lcd_dma_desc *desc;
66 struct atmel_hlcd_regs *regs;
72 regs = panel_info.mmio;
73 clk_pol = panel_info.vl_clk_pol ? LCDC_LCDCFG0_CLKPOL : 0;
75 /* Disable DISP signal */
76 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
77 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
79 /* Disable synchronization */
80 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
81 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
83 /* Disable pixel clock */
84 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
85 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
88 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
89 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
93 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
94 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
98 /* Using system clock as pixel clock */
99 lcdc_writel(®s->lcdc_lcdcfg0,
100 LCDC_LCDCFG0_CLKDIV(0)
101 | LCDC_LCDCFG0_CGDISHCR
102 | LCDC_LCDCFG0_CGDISHEO
103 | LCDC_LCDCFG0_CGDISOVR1
104 | LCDC_LCDCFG0_CGDISBASE
105 | LCDC_LCDCFG0_CLKSEL
109 lcdc_writel(®s->lcdc_lcdcfg0,
110 LCDC_LCDCFG0_CLKDIV(value - 2)
111 | LCDC_LCDCFG0_CGDISHCR
112 | LCDC_LCDCFG0_CGDISHEO
113 | LCDC_LCDCFG0_CGDISOVR1
114 | LCDC_LCDCFG0_CGDISBASE
118 /* Initialize control register 5 */
121 value |= panel_info.vl_sync;
123 #ifndef LCD_OUTPUT_BPP
124 /* Output is 24bpp */
125 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
127 switch (LCD_OUTPUT_BPP) {
129 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
132 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
135 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
138 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
146 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
147 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
148 lcdc_writel(®s->lcdc_lcdcfg5, value);
150 /* Vertical & Horizontal Timing */
151 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
152 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
153 lcdc_writel(®s->lcdc_lcdcfg1, value);
155 value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
156 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
157 lcdc_writel(®s->lcdc_lcdcfg2, value);
159 value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
160 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
161 lcdc_writel(®s->lcdc_lcdcfg3, value);
164 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
165 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
166 lcdc_writel(®s->lcdc_lcdcfg4, value);
168 lcdc_writel(®s->lcdc_basecfg0,
169 LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
171 switch (NBITS(panel_info.vl_bpix)) {
173 lcdc_writel(®s->lcdc_basecfg1,
174 LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
181 lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
182 lcdc_writel(®s->lcdc_basecfg3, 0);
183 lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA);
185 /* Disable all interrupts */
186 lcdc_writel(®s->lcdc_lcdidr, ~0UL);
187 lcdc_writel(®s->lcdc_baseidr, ~0UL);
189 /* Setup the DMA descriptor, this descriptor will loop to itself */
190 desc = (struct lcd_dma_desc *)(lcdbase - 16);
192 desc->address = (u32)lcdbase;
193 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
194 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
195 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
196 desc->next = (u32)desc;
198 /* Flush the DMA descriptor if we enabled dcache */
199 flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
201 lcdc_writel(®s->lcdc_baseaddr, desc->address);
202 lcdc_writel(®s->lcdc_basectrl, desc->control);
203 lcdc_writel(®s->lcdc_basenext, desc->next);
204 lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN |
205 LCDC_BASECHER_UPDATEEN);
208 value = lcdc_readl(®s->lcdc_lcden);
209 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
210 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
212 value = lcdc_readl(®s->lcdc_lcden);
213 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
214 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
216 value = lcdc_readl(®s->lcdc_lcden);
217 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
218 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
220 value = lcdc_readl(®s->lcdc_lcden);
221 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
222 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
225 /* Enable flushing if we enabled dcache */
226 lcd_set_flush_dcache(1);