2 * Driver for AT91/AT32 LCD Controller
4 * Copyright (C) 2007 Atmel Corporation
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/interrupt.h>
15 #include <linux/clk.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
20 #include <asm/arch/board.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/gpio.h>
24 #include <video/atmel_lcdc.h>
26 #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
27 #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
29 /* configurable parameters */
30 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
31 #define ATMEL_LCDC_DMA_BURST_LEN 8
33 #if defined(CONFIG_ARCH_AT91SAM9263)
34 #define ATMEL_LCDC_FIFO_SIZE 2048
36 #define ATMEL_LCDC_FIFO_SIZE 512
39 #if defined(CONFIG_ARCH_AT91)
40 #define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
42 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
43 struct fb_var_screeninfo *var)
47 #elif defined(CONFIG_AVR32)
48 #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
49 | FBINFO_PARTIAL_PAN_OK \
50 | FBINFO_HWACCEL_XPAN \
51 | FBINFO_HWACCEL_YPAN)
53 static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
54 struct fb_var_screeninfo *var)
59 pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
61 dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
62 dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
63 lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
65 /* Update configuration */
66 lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
67 lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
68 | ATMEL_LCDC_DMAUPDT);
73 static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
74 .type = FB_TYPE_PACKED_PIXELS,
75 .visual = FB_VISUAL_TRUECOLOR,
79 .accel = FB_ACCEL_NONE,
82 static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
86 if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000()))
90 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
92 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
95 if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
96 || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
97 && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
98 value = DIV_ROUND_UP(value, 4);
100 value = DIV_ROUND_UP(value, 8);
106 static void atmel_lcdfb_update_dma(struct fb_info *info,
107 struct fb_var_screeninfo *var)
109 struct atmel_lcdfb_info *sinfo = info->par;
110 struct fb_fix_screeninfo *fix = &info->fix;
111 unsigned long dma_addr;
113 dma_addr = (fix->smem_start + var->yoffset * fix->line_length
114 + var->xoffset * var->bits_per_pixel / 8);
118 /* Set framebuffer DMA base address and pixel offset */
119 lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
121 atmel_lcdfb_update_dma2d(sinfo, var);
124 static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
126 struct fb_info *info = sinfo->info;
128 dma_free_writecombine(info->device, info->fix.smem_len,
129 info->screen_base, info->fix.smem_start);
133 * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
134 * @sinfo: the frame buffer to allocate memory for
136 static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
138 struct fb_info *info = sinfo->info;
139 struct fb_var_screeninfo *var = &info->var;
141 info->fix.smem_len = (var->xres_virtual * var->yres_virtual
142 * ((var->bits_per_pixel + 7) / 8));
144 info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
145 (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
147 if (!info->screen_base) {
155 * atmel_lcdfb_check_var - Validates a var passed in.
156 * @var: frame buffer variable screen structure
157 * @info: frame buffer structure that represents a single frame buffer
159 * Checks to see if the hardware supports the state requested by
160 * var passed in. This function does not alter the hardware
161 * state!!! This means the data stored in struct fb_info and
162 * struct atmel_lcdfb_info do not change. This includes the var
163 * inside of struct fb_info. Do NOT change these. This function
164 * can be called on its own if we intent to only test a mode and
165 * not actually set it. The stuff in modedb.c is a example of
166 * this. If the var passed in is slightly off by what the
167 * hardware can support then we alter the var PASSED in to what
168 * we can do. If the hardware doesn't support mode change a
169 * -EINVAL will be returned by the upper layers. You don't need
170 * to implement this function then. If you hardware doesn't
171 * support changing the resolution then this function is not
172 * needed. In this case the driver would just provide a var that
173 * represents the static state the screen is in.
175 * Returns negative errno on error, or zero on success.
177 static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
178 struct fb_info *info)
180 struct device *dev = info->device;
181 struct atmel_lcdfb_info *sinfo = info->par;
182 unsigned long clk_value_khz;
184 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
186 dev_dbg(dev, "%s:\n", __func__);
187 dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
188 dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
189 dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
190 dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
192 if ((PICOS2KHZ(var->pixclock) * var->bits_per_pixel / 8) > clk_value_khz) {
193 dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
197 /* Force same alignment for each line */
198 var->xres = (var->xres + 3) & ~3UL;
199 var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
201 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
202 var->transp.msb_right = 0;
203 var->transp.offset = var->transp.length = 0;
204 var->xoffset = var->yoffset = 0;
206 switch (var->bits_per_pixel) {
211 var->red.offset = var->green.offset = var->blue.offset = 0;
212 var->red.length = var->green.length = var->blue.length
213 = var->bits_per_pixel;
218 var->green.offset = 5;
219 var->blue.offset = 10;
220 var->red.length = var->green.length = var->blue.length = 5;
225 var->green.offset = 8;
226 var->blue.offset = 16;
227 var->red.length = var->green.length = var->blue.length = 8;
230 dev_err(dev, "color depth %d not supported\n",
231 var->bits_per_pixel);
239 * atmel_lcdfb_set_par - Alters the hardware state.
240 * @info: frame buffer structure that represents a single frame buffer
242 * Using the fb_var_screeninfo in fb_info we set the resolution
243 * of the this particular framebuffer. This function alters the
244 * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
245 * not alter var in fb_info since we are using that data. This
246 * means we depend on the data in var inside fb_info to be
247 * supported by the hardware. atmel_lcdfb_check_var is always called
248 * before atmel_lcdfb_set_par to ensure this. Again if you can't
249 * change the resolution you don't need this function.
252 static int atmel_lcdfb_set_par(struct fb_info *info)
254 struct atmel_lcdfb_info *sinfo = info->par;
255 unsigned long hozval_linesz;
257 unsigned long clk_value_khz;
258 unsigned long bits_per_line;
260 dev_dbg(info->device, "%s:\n", __func__);
261 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
262 info->var.xres, info->var.yres,
263 info->var.xres_virtual, info->var.yres_virtual);
265 /* Turn off the LCD controller and the DMA controller */
266 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
268 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
270 if (info->var.bits_per_pixel == 1)
271 info->fix.visual = FB_VISUAL_MONO01;
272 else if (info->var.bits_per_pixel <= 8)
273 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
275 info->fix.visual = FB_VISUAL_TRUECOLOR;
277 bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
278 info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
280 /* Re-initialize the DMA engine... */
281 dev_dbg(info->device, " * update DMA engine\n");
282 atmel_lcdfb_update_dma(info, &info->var);
284 /* ...set frame size and burst length = 8 words (?) */
285 value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
286 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
287 lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
289 /* Now, the LCDC core... */
291 /* Set pixel clock */
292 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
294 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
296 value = (value / 2) - 1;
297 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value);
300 dev_notice(info->device, "Bypassing pixel clock divider\n");
301 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
303 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);
304 info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));
305 dev_dbg(info->device, " updated pixclk: %lu KHz\n",
306 PICOS2KHZ(info->var.pixclock));
310 /* Initialize control register 2 */
311 value = sinfo->default_lcdcon2;
313 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
314 value |= ATMEL_LCDC_INVLINE_INVERTED;
315 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
316 value |= ATMEL_LCDC_INVFRAME_INVERTED;
318 switch (info->var.bits_per_pixel) {
319 case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
320 case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
321 case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
322 case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
323 case 15: /* fall through */
324 case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
325 case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
326 case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
327 default: BUG(); break;
329 dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
330 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
332 /* Vertical timing */
333 value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
334 value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
335 value |= info->var.lower_margin;
336 dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
337 lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
339 /* Horizontal timing */
340 value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
341 value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
342 value |= (info->var.left_margin - 1);
343 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
344 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
346 /* Horizontal value (aka line size) */
347 hozval_linesz = compute_hozval(info->var.xres,
348 lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
351 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
352 value |= info->var.yres - 1;
353 dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
354 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
356 /* FIFO Threshold: Use formula from data sheet */
357 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
358 lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
360 /* Toggle LCD_MODE every frame */
361 lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
363 /* Disable all interrupts */
364 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
367 value = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE;
368 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
369 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
370 /* ...wait for DMA engine to become idle... */
371 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
374 dev_dbg(info->device, " * re-enable DMA engine\n");
375 /* ...and enable it with updated configuration */
376 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
378 dev_dbg(info->device, " * re-enable LCDC core\n");
379 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
380 (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
382 dev_dbg(info->device, " * DONE\n");
387 static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
390 chan >>= 16 - bf->length;
391 return chan << bf->offset;
395 * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
396 * @regno: Which register in the CLUT we are programming
397 * @red: The red value which can be up to 16 bits wide
398 * @green: The green value which can be up to 16 bits wide
399 * @blue: The blue value which can be up to 16 bits wide.
400 * @transp: If supported the alpha value which can be up to 16 bits wide.
401 * @info: frame buffer info structure
403 * Set a single color register. The values supplied have a 16 bit
404 * magnitude which needs to be scaled in this function for the hardware.
405 * Things to take into consideration are how many color registers, if
406 * any, are supported with the current color visual. With truecolor mode
407 * no color palettes are supported. Here a psuedo palette is created
408 * which we store the value in pseudo_palette in struct fb_info. For
409 * pseudocolor mode we have a limited color palette. To deal with this
410 * we can program what color is displayed for a particular pixel value.
411 * DirectColor is similar in that we can program each color field. If
412 * we have a static colormap we don't need to implement this function.
414 * Returns negative errno on error, or zero on success. In an
415 * ideal world, this would have been the case, but as it turns
416 * out, the other drivers return 1 on failure, so that's what
419 static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
420 unsigned int green, unsigned int blue,
421 unsigned int transp, struct fb_info *info)
423 struct atmel_lcdfb_info *sinfo = info->par;
428 if (info->var.grayscale)
429 red = green = blue = (19595 * red + 38470 * green
430 + 7471 * blue) >> 16;
432 switch (info->fix.visual) {
433 case FB_VISUAL_TRUECOLOR:
435 pal = info->pseudo_palette;
437 val = chan_to_field(red, &info->var.red);
438 val |= chan_to_field(green, &info->var.green);
439 val |= chan_to_field(blue, &info->var.blue);
446 case FB_VISUAL_PSEUDOCOLOR:
448 val = ((red >> 11) & 0x001f);
449 val |= ((green >> 6) & 0x03e0);
450 val |= ((blue >> 1) & 0x7c00);
453 * TODO: intensity bit. Maybe something like
454 * ~(red[10] ^ green[10] ^ blue[10]) & 1
457 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
462 case FB_VISUAL_MONO01:
464 val = (regno == 0) ? 0x00 : 0x1F;
465 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
475 static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
476 struct fb_info *info)
478 dev_dbg(info->device, "%s\n", __func__);
480 atmel_lcdfb_update_dma(info, var);
485 static struct fb_ops atmel_lcdfb_ops = {
486 .owner = THIS_MODULE,
487 .fb_check_var = atmel_lcdfb_check_var,
488 .fb_set_par = atmel_lcdfb_set_par,
489 .fb_setcolreg = atmel_lcdfb_setcolreg,
490 .fb_pan_display = atmel_lcdfb_pan_display,
491 .fb_fillrect = cfb_fillrect,
492 .fb_copyarea = cfb_copyarea,
493 .fb_imageblit = cfb_imageblit,
496 static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
498 struct fb_info *info = dev_id;
499 struct atmel_lcdfb_info *sinfo = info->par;
502 status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
503 lcdc_writel(sinfo, ATMEL_LCDC_IDR, status);
507 static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
509 struct fb_info *info = sinfo->info;
512 memset_io(info->screen_base, 0, info->fix.smem_len);
513 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
515 dev_info(info->device,
516 "%luKiB frame buffer at %08lx (mapped at %p)\n",
517 (unsigned long)info->fix.smem_len / 1024,
518 (unsigned long)info->fix.smem_start,
521 /* Allocate colormap */
522 ret = fb_alloc_cmap(&info->cmap, 256, 0);
524 dev_err(info->device, "Alloc color map failed\n");
529 static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
532 clk_enable(sinfo->bus_clk);
533 clk_enable(sinfo->lcdc_clk);
536 static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
539 clk_disable(sinfo->bus_clk);
540 clk_disable(sinfo->lcdc_clk);
544 static int __init atmel_lcdfb_probe(struct platform_device *pdev)
546 struct device *dev = &pdev->dev;
547 struct fb_info *info;
548 struct atmel_lcdfb_info *sinfo;
549 struct atmel_lcdfb_info *pdata_sinfo;
550 struct resource *regs = NULL;
551 struct resource *map = NULL;
554 dev_dbg(dev, "%s BEGIN\n", __func__);
557 info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
559 dev_err(dev, "cannot allocate memory\n");
565 if (dev->platform_data) {
566 pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
567 sinfo->default_bpp = pdata_sinfo->default_bpp;
568 sinfo->default_dmacon = pdata_sinfo->default_dmacon;
569 sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
570 sinfo->default_monspecs = pdata_sinfo->default_monspecs;
571 sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
572 sinfo->guard_time = pdata_sinfo->guard_time;
574 dev_err(dev, "cannot get default configuration\n");
580 strcpy(info->fix.id, sinfo->pdev->name);
581 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
582 info->pseudo_palette = sinfo->pseudo_palette;
583 info->fbops = &atmel_lcdfb_ops;
585 memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
586 info->fix = atmel_lcdfb_fix;
588 /* Enable LCDC Clocks */
589 if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
590 sinfo->bus_clk = clk_get(dev, "hck1");
591 if (IS_ERR(sinfo->bus_clk)) {
592 ret = PTR_ERR(sinfo->bus_clk);
596 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
597 if (IS_ERR(sinfo->lcdc_clk)) {
598 ret = PTR_ERR(sinfo->lcdc_clk);
601 atmel_lcdfb_start_clock(sinfo);
603 ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
604 info->monspecs.modedb_len, info->monspecs.modedb,
607 dev_err(dev, "no suitable video mode found\n");
612 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614 dev_err(dev, "resources unusable\n");
619 sinfo->irq_base = platform_get_irq(pdev, 0);
620 if (sinfo->irq_base < 0) {
621 dev_err(dev, "unable to get irq\n");
622 ret = sinfo->irq_base;
626 /* Initialize video memory */
627 map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
629 /* use a pre-allocated memory buffer */
630 info->fix.smem_start = map->start;
631 info->fix.smem_len = map->end - map->start + 1;
632 if (!request_mem_region(info->fix.smem_start,
633 info->fix.smem_len, pdev->name)) {
638 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
639 if (!info->screen_base)
642 /* alocate memory buffer */
643 ret = atmel_lcdfb_alloc_video_memory(sinfo);
645 dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
651 info->fix.mmio_start = regs->start;
652 info->fix.mmio_len = regs->end - regs->start + 1;
654 if (!request_mem_region(info->fix.mmio_start,
655 info->fix.mmio_len, pdev->name)) {
660 sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
662 dev_err(dev, "cannot map LCDC registers\n");
667 ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
669 dev_err(dev, "request_irq failed: %d\n", ret);
673 ret = atmel_lcdfb_init_fbinfo(sinfo);
675 dev_err(dev, "init fbinfo failed: %d\n", ret);
676 goto unregister_irqs;
680 * This makes sure that our colour bitfield
681 * descriptors are correctly initialised.
683 atmel_lcdfb_check_var(&info->var, info);
685 ret = fb_set_var(info, &info->var);
687 dev_warn(dev, "unable to set display parameters\n");
691 dev_set_drvdata(dev, info);
694 * Tell the world that we're ready to go
696 ret = register_framebuffer(info);
698 dev_err(dev, "failed to register framebuffer device: %d\n", ret);
702 /* Power up the LCDC screen */
703 if (sinfo->atmel_lcdfb_power_control)
704 sinfo->atmel_lcdfb_power_control(1);
706 dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n",
707 info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
713 fb_dealloc_cmap(&info->cmap);
715 free_irq(sinfo->irq_base, info);
717 iounmap(sinfo->mmio);
719 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
722 iounmap(info->screen_base);
724 atmel_lcdfb_free_video_memory(sinfo);
728 release_mem_region(info->fix.smem_start, info->fix.smem_len);
730 atmel_lcdfb_stop_clock(sinfo);
731 clk_put(sinfo->lcdc_clk);
734 clk_put(sinfo->bus_clk);
736 framebuffer_release(info);
738 dev_dbg(dev, "%s FAILED\n", __func__);
742 static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
744 struct device *dev = &pdev->dev;
745 struct fb_info *info = dev_get_drvdata(dev);
746 struct atmel_lcdfb_info *sinfo = info->par;
751 if (sinfo->atmel_lcdfb_power_control)
752 sinfo->atmel_lcdfb_power_control(0);
753 unregister_framebuffer(info);
754 atmel_lcdfb_stop_clock(sinfo);
755 clk_put(sinfo->lcdc_clk);
757 clk_put(sinfo->bus_clk);
758 fb_dealloc_cmap(&info->cmap);
759 free_irq(sinfo->irq_base, info);
760 iounmap(sinfo->mmio);
761 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
762 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
763 iounmap(info->screen_base);
764 release_mem_region(info->fix.smem_start, info->fix.smem_len);
766 atmel_lcdfb_free_video_memory(sinfo);
769 dev_set_drvdata(dev, NULL);
770 framebuffer_release(info);
775 static struct platform_driver atmel_lcdfb_driver = {
776 .remove = __exit_p(atmel_lcdfb_remove),
778 .name = "atmel_lcdfb",
779 .owner = THIS_MODULE,
783 static int __init atmel_lcdfb_init(void)
785 return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
788 static void __exit atmel_lcdfb_exit(void)
790 platform_driver_unregister(&atmel_lcdfb_driver);
793 module_init(atmel_lcdfb_init);
794 module_exit(atmel_lcdfb_exit);
796 MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
797 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@rfo.atmel.com>");
798 MODULE_LICENSE("GPL");