2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #define CIRRUSFB_VERSION "2.0-pre2"
39 #include <linux/config.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/errno.h>
43 #include <linux/string.h>
45 #include <linux/tty.h>
46 #include <linux/slab.h>
47 #include <linux/delay.h>
49 #include <linux/init.h>
50 #include <linux/selection.h>
51 #include <asm/pgtable.h>
54 #include <linux/zorro.h>
57 #include <linux/pci.h>
60 #include <asm/amigahw.h>
62 #ifdef CONFIG_PPC_PREP
63 #include <asm/processor.h>
64 #define isPReP (_machine == _MACH_prep)
69 #include "video/vga.h"
70 #include "video/cirrus.h"
73 /*****************************************************************
75 * debugging and utility macros
79 /* enable debug output? */
80 /* #define CIRRUSFB_DEBUG 1 */
82 /* disable runtime assertions? */
83 /* #define CIRRUSFB_NDEBUG */
87 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
89 #define DPRINTK(fmt, args...)
92 /* debugging assertions */
93 #ifndef CIRRUSFB_NDEBUG
94 #define assert(expr) \
96 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
97 #expr,__FILE__,__FUNCTION__,__LINE__); \
112 #define MB_ (1024*1024)
115 #define MAX_NUM_BOARDS 7
118 /*****************************************************************
120 * chipset information
131 BT_PICASSO4, /* GD5446 */
132 BT_ALPINE, /* GD543x/4x */
134 BT_LAGUNA, /* GD546x */
139 * per-board-type information, used for enumerating and abstracting
140 * chip-specific information
141 * NOTE: MUST be in the same order as cirrusfb_board_t in order to
142 * use direct indexing on this array
143 * NOTE: '__initdata' cannot be used as some of this info
144 * is required at runtime. Maybe separate into an init-only and
147 static const struct cirrusfb_board_info_rec {
148 char *name; /* ASCII name of chipset */
149 long maxclock[5]; /* maximum video clock */
150 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
151 unsigned init_sr07 : 1; /* init SR07 during init_vgachip() */
152 unsigned init_sr1f : 1; /* write SR1F during init_vgachip() */
153 unsigned scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
155 /* initial SR07 value, then for each mode */
157 unsigned char sr07_1bpp;
158 unsigned char sr07_1bpp_mux;
159 unsigned char sr07_8bpp;
160 unsigned char sr07_8bpp_mux;
162 unsigned char sr1f; /* SR1F VGA initial register value */
163 } cirrusfb_board_info[] = {
168 /* the SD64/P4 have a higher max. videoclock */
169 140000, 140000, 140000, 140000, 140000,
173 .scrn_start_bit19 = TRUE,
180 .name = "CL Piccolo",
183 90000, 90000, 90000, 90000, 90000
187 .scrn_start_bit19 = FALSE,
194 .name = "CL Picasso",
197 90000, 90000, 90000, 90000, 90000
201 .scrn_start_bit19 = FALSE,
208 .name = "CL Spectrum",
211 90000, 90000, 90000, 90000, 90000
215 .scrn_start_bit19 = FALSE,
222 .name = "CL Picasso4",
224 135100, 135100, 85500, 85500, 0
228 .scrn_start_bit19 = TRUE,
237 /* for the GD5430. GD5446 can do more... */
238 85500, 85500, 50000, 28500, 0
242 .scrn_start_bit19 = TRUE,
245 .sr07_1bpp_mux = 0xA7,
247 .sr07_8bpp_mux = 0xA7,
253 135100, 200000, 200000, 135100, 135100
257 .scrn_start_bit19 = TRUE,
267 135100, 135100, 135100, 135100, 135100,
271 .scrn_start_bit19 = TRUE,
277 #define CHIP(id, btype) \
278 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
280 static struct pci_device_id cirrusfb_pci_table[] = {
281 CHIP( PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE ),
282 CHIP( PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE ),
283 CHIP( PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE ),
284 CHIP( PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE ), /* GD-5440 is same id */
285 CHIP( PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE ),
286 CHIP( PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE ),
287 CHIP( PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480 ), /* MacPicasso likely */
288 CHIP( PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is 5446 */
289 CHIP( PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */
290 CHIP( PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */
291 CHIP( PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/
294 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
296 #endif /* CONFIG_PCI */
300 static const struct zorro_device_id cirrusfb_zorro_table[] = {
302 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
303 .driver_data = BT_SD64,
305 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
306 .driver_data = BT_PICCOLO,
308 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
309 .driver_data = BT_PICASSO,
311 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
312 .driver_data = BT_SPECTRUM,
314 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
315 .driver_data = BT_PICASSO4,
320 static const struct {
323 } cirrusfb_zorro_table2[] = {
325 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
329 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
333 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
337 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
345 #endif /* CONFIG_ZORRO */
348 struct cirrusfb_regs {
349 __u32 line_length; /* in BYTES! */
361 long HorizRes; /* The x resolution in pixel */
364 long HorizBlankStart;
369 long VertRes; /* the physical y resolution in scanlines */
380 #ifdef CIRRUSFB_DEBUG
384 } cirrusfb_dbg_reg_class_t;
385 #endif /* CIRRUSFB_DEBUG */
390 /* info about board */
391 struct cirrusfb_info {
392 struct fb_info *info;
398 cirrusfb_board_t btype;
399 unsigned char SFR; /* Shadow of special function register */
401 unsigned long fbmem_phys;
402 unsigned long fbregs_phys;
404 struct cirrusfb_regs currentmode;
407 u32 pseudo_palette[17];
408 struct { u8 red, green, blue, pad; } palette[256];
411 struct zorro_dev *zdev;
414 struct pci_dev *pdev;
416 void (*unmap)(struct cirrusfb_info *cinfo);
420 static unsigned cirrusfb_def_mode = 1;
421 static int noaccel = 0;
424 * Predefined Video Modes
427 static const struct {
429 struct fb_var_screeninfo var;
430 } cirrusfb_predefined[] = {
432 /* autodetect mode */
433 .name = "Autodetect",
435 /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
443 .red = { .length = 8 },
444 .green = { .length = 8 },
445 .blue = { .length = 8 },
455 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
456 .vmode = FB_VMODE_NONINTERLACED
459 /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
467 .red = { .length = 8 },
468 .green = { .length = 8 },
469 .blue = { .length = 8 },
479 .vmode = FB_VMODE_NONINTERLACED
483 * Modeline from XF86Config:
484 * Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
486 /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
491 .xres_virtual = 1024,
494 .red = { .length = 8 },
495 .green = { .length = 8 },
496 .blue = { .length = 8 },
506 .vmode = FB_VMODE_NONINTERLACED
511 #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
513 /****************************************************************************/
514 /**** BEGIN PROTOTYPES ******************************************************/
517 /*--- Interface used by the world ------------------------------------------*/
518 static int cirrusfb_init (void);
520 static int cirrusfb_setup (char *options);
523 static int cirrusfb_open (struct fb_info *info, int user);
524 static int cirrusfb_release (struct fb_info *info, int user);
525 static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
526 unsigned blue, unsigned transp,
527 struct fb_info *info);
528 static int cirrusfb_check_var (struct fb_var_screeninfo *var,
529 struct fb_info *info);
530 static int cirrusfb_set_par (struct fb_info *info);
531 static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
532 struct fb_info *info);
533 static int cirrusfb_blank (int blank_mode, struct fb_info *info);
534 static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region);
535 static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
536 static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image);
538 /* function table of the above functions */
539 static struct fb_ops cirrusfb_ops = {
540 .owner = THIS_MODULE,
541 .fb_open = cirrusfb_open,
542 .fb_release = cirrusfb_release,
543 .fb_setcolreg = cirrusfb_setcolreg,
544 .fb_check_var = cirrusfb_check_var,
545 .fb_set_par = cirrusfb_set_par,
546 .fb_pan_display = cirrusfb_pan_display,
547 .fb_blank = cirrusfb_blank,
548 .fb_fillrect = cirrusfb_fillrect,
549 .fb_copyarea = cirrusfb_copyarea,
550 .fb_imageblit = cirrusfb_imageblit,
553 /*--- Hardware Specific Routines -------------------------------------------*/
554 static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
555 struct cirrusfb_regs *regs,
556 const struct fb_info *info);
557 /*--- Internal routines ----------------------------------------------------*/
558 static void init_vgachip (struct cirrusfb_info *cinfo);
559 static void switch_monitor (struct cirrusfb_info *cinfo, int on);
560 static void WGen (const struct cirrusfb_info *cinfo,
561 int regnum, unsigned char val);
562 static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum);
563 static void AttrOn (const struct cirrusfb_info *cinfo);
564 static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val);
565 static void WSFR (struct cirrusfb_info *cinfo, unsigned char val);
566 static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val);
567 static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
571 static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
572 unsigned char *green,
573 unsigned char *blue);
575 static void cirrusfb_WaitBLT (u8 __iomem *regbase);
576 static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
577 u_short curx, u_short cury,
578 u_short destx, u_short desty,
579 u_short width, u_short height,
580 u_short line_length);
581 static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
582 u_short x, u_short y,
583 u_short width, u_short height,
584 u_char color, u_short line_length);
586 static void bestclock (long freq, long *best,
587 long *nom, long *den,
588 long *div, long maxfreq);
590 #ifdef CIRRUSFB_DEBUG
591 static void cirrusfb_dump (void);
592 static void cirrusfb_dbg_reg_dump (caddr_t regbase);
593 static void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...);
594 static void cirrusfb_dbg_print_byte (const char *name, unsigned char val);
595 #endif /* CIRRUSFB_DEBUG */
597 /*** END PROTOTYPES ********************************************************/
598 /*****************************************************************************/
599 /*** BEGIN Interface Used by the World ***************************************/
601 static int opencount = 0;
603 /*--- Open /dev/fbx ---------------------------------------------------------*/
604 static int cirrusfb_open (struct fb_info *info, int user)
606 if (opencount++ == 0)
607 switch_monitor (info->par, 1);
611 /*--- Close /dev/fbx --------------------------------------------------------*/
612 static int cirrusfb_release (struct fb_info *info, int user)
614 if (--opencount == 0)
615 switch_monitor (info->par, 0);
619 /**** END Interface used by the World *************************************/
620 /****************************************************************************/
621 /**** BEGIN Hardware specific Routines **************************************/
623 /* Get a good MCLK value */
624 static long cirrusfb_get_mclk (long freq, int bpp, long *div)
628 assert (div != NULL);
630 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
631 * Assume a 64-bit data path for now. The formula is:
632 * ((B * PCLK * 2)/W) * 1.2
633 * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
634 mclk = ((bpp / 8) * freq * 2) / 4;
635 mclk = (mclk * 12) / 10;
638 DPRINTK ("Use MCLK of %ld kHz\n", mclk);
640 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
641 mclk = ((mclk * 16) / 14318);
642 mclk = (mclk + 1) / 2;
643 DPRINTK ("Set SR1F[5:0] to 0x%lx\n", mclk);
645 /* Determine if we should use MCLK instead of VCLK, and if so, what we
646 * should divide it by to get VCLK */
648 case 24751 ... 25249:
650 DPRINTK ("Using VCLK = MCLK/2\n");
652 case 49501 ... 50499:
654 DPRINTK ("Using VCLK = MCLK\n");
664 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
665 struct fb_info *info)
667 struct cirrusfb_info *cinfo = info->par;
668 int nom, den; /* translyting from pixels->bytes */
670 static struct { int xres, yres; } modes[] =
678 switch (var->bits_per_pixel) {
680 var->bits_per_pixel = 1;
683 break; /* 8 pixel per byte, only 1/4th of mem usable */
685 var->bits_per_pixel = 8;
688 break; /* 1 pixel == 1 byte */
690 var->bits_per_pixel = 16;
693 break; /* 2 bytes per pixel */
695 var->bits_per_pixel = 24;
698 break; /* 3 bytes per pixel */
700 var->bits_per_pixel = 32;
703 break; /* 4 bytes per pixel */
705 printk ("cirrusfb: mode %dx%dx%d rejected...color depth not supported.\n",
706 var->xres, var->yres, var->bits_per_pixel);
707 DPRINTK ("EXIT - EINVAL error\n");
711 if (var->xres * nom / den * var->yres > cinfo->size) {
712 printk ("cirrusfb: mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
713 var->xres, var->yres, var->bits_per_pixel);
714 DPRINTK ("EXIT - EINVAL error\n");
718 /* use highest possible virtual resolution */
719 if (var->xres_virtual == -1 &&
720 var->yres_virtual == -1) {
721 printk ("cirrusfb: using maximum available virtual resolution\n");
722 for (i = 0; modes[i].xres != -1; i++) {
723 if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
726 if (modes[i].xres == -1) {
727 printk ("cirrusfb: could not find a virtual resolution that fits into video memory!!\n");
728 DPRINTK ("EXIT - EINVAL error\n");
731 var->xres_virtual = modes[i].xres;
732 var->yres_virtual = modes[i].yres;
734 printk ("cirrusfb: virtual resolution set to maximum of %dx%d\n",
735 var->xres_virtual, var->yres_virtual);
738 if (var->xres_virtual < var->xres)
739 var->xres_virtual = var->xres;
740 if (var->yres_virtual < var->yres)
741 var->yres_virtual = var->yres;
743 if (var->xoffset < 0)
745 if (var->yoffset < 0)
748 /* truncate xoffset and yoffset to maximum if too high */
749 if (var->xoffset > var->xres_virtual - var->xres)
750 var->xoffset = var->xres_virtual - var->xres - 1;
751 if (var->yoffset > var->yres_virtual - var->yres)
752 var->yoffset = var->yres_virtual - var->yres - 1;
754 switch (var->bits_per_pixel) {
758 var->green.offset = 0;
759 var->green.length = 1;
760 var->blue.offset = 0;
761 var->blue.length = 1;
767 var->green.offset = 0;
768 var->green.length = 6;
769 var->blue.offset = 0;
770 var->blue.length = 6;
776 var->green.offset = -3;
777 var->blue.offset = 8;
779 var->red.offset = 10;
780 var->green.offset = 5;
781 var->blue.offset = 0;
784 var->green.length = 5;
785 var->blue.length = 5;
791 var->green.offset = 16;
792 var->blue.offset = 24;
794 var->red.offset = 16;
795 var->green.offset = 8;
796 var->blue.offset = 0;
799 var->green.length = 8;
800 var->blue.length = 8;
806 var->green.offset = 16;
807 var->blue.offset = 24;
809 var->red.offset = 16;
810 var->green.offset = 8;
811 var->blue.offset = 0;
814 var->green.length = 8;
815 var->blue.length = 8;
819 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
821 /* should never occur */
826 var->green.msb_right =
827 var->blue.msb_right =
830 var->transp.msb_right = 0;
833 if (var->vmode & FB_VMODE_DOUBLE)
835 else if (var->vmode & FB_VMODE_INTERLACED)
836 yres = (yres + 1) / 2;
839 printk (KERN_WARNING "cirrusfb: ERROR: VerticalTotal >= 1280; special treatment required! (TODO)\n");
840 DPRINTK ("EXIT - EINVAL error\n");
847 static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
848 struct cirrusfb_regs *regs,
849 const struct fb_info *info)
854 struct cirrusfb_info *cinfo = info->par;
855 int xres, hfront, hsync, hback;
856 int yres, vfront, vsync, vback;
858 switch(var->bits_per_pixel) {
860 regs->line_length = var->xres_virtual / 8;
861 regs->visual = FB_VISUAL_MONO10;
866 regs->line_length = var->xres_virtual;
867 regs->visual = FB_VISUAL_PSEUDOCOLOR;
872 regs->line_length = var->xres_virtual * 2;
873 regs->visual = FB_VISUAL_DIRECTCOLOR;
878 regs->line_length = var->xres_virtual * 3;
879 regs->visual = FB_VISUAL_DIRECTCOLOR;
884 regs->line_length = var->xres_virtual * 4;
885 regs->visual = FB_VISUAL_DIRECTCOLOR;
890 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
892 /* should never occur */
896 regs->type = FB_TYPE_PACKED_PIXELS;
898 /* convert from ps to kHz */
899 freq = 1000000000 / var->pixclock;
901 DPRINTK ("desired pixclock: %ld kHz\n", freq);
903 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
904 regs->multiplexing = 0;
906 /* If the frequency is greater than we can support, we might be able
907 * to use multiplexing for the video mode */
908 if (freq > maxclock) {
909 switch (cinfo->btype) {
912 regs->multiplexing = 1;
916 printk (KERN_WARNING "cirrusfb: ERROR: Frequency greater than maxclock (%ld kHz)\n", maxclock);
917 DPRINTK ("EXIT - return -EINVAL\n");
922 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
923 * the VCLK is double the pixel clock. */
924 switch (var->bits_per_pixel) {
927 if (regs->HorizRes <= 800)
928 freq /= 2; /* Xbh has this type of clock for 32-bit */
933 bestclock (freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
935 regs->mclk = cirrusfb_get_mclk (freq, var->bits_per_pixel, ®s->divMCLK);
938 hfront = var->right_margin;
939 hsync = var->hsync_len;
940 hback = var->left_margin;
943 vfront = var->lower_margin;
944 vsync = var->vsync_len;
945 vback = var->upper_margin;
947 if (var->vmode & FB_VMODE_DOUBLE) {
952 } else if (var->vmode & FB_VMODE_INTERLACED) {
953 yres = (yres + 1) / 2;
954 vfront = (vfront + 1) / 2;
955 vsync = (vsync + 1) / 2;
956 vback = (vback + 1) / 2;
958 regs->HorizRes = xres;
959 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
960 regs->HorizDispEnd = xres / 8 - 1;
961 regs->HorizBlankStart = xres / 8;
962 regs->HorizBlankEnd = regs->HorizTotal + 5; /* does not count with "-5" */
963 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
964 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
966 regs->VertRes = yres;
967 regs->VertTotal = yres + vfront + vsync + vback - 2;
968 regs->VertDispEnd = yres - 1;
969 regs->VertBlankStart = yres;
970 regs->VertBlankEnd = regs->VertTotal;
971 regs->VertSyncStart = yres + vfront - 1;
972 regs->VertSyncEnd = yres + vfront + vsync - 1;
974 if (regs->VertRes >= 1024) {
975 regs->VertTotal /= 2;
976 regs->VertSyncStart /= 2;
977 regs->VertSyncEnd /= 2;
978 regs->VertDispEnd /= 2;
980 if (regs->multiplexing) {
981 regs->HorizTotal /= 2;
982 regs->HorizSyncStart /= 2;
983 regs->HorizSyncEnd /= 2;
984 regs->HorizDispEnd /= 2;
991 static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int div)
993 assert (cinfo != NULL);
997 unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
998 vga_wseq (cinfo->regbase, CL_SEQR1E, old | 0x1);
999 vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
1000 } else if (div == 1) {
1002 unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
1003 vga_wseq (cinfo->regbase, CL_SEQR1E, old & ~0x1);
1004 vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
1006 vga_wseq (cinfo->regbase, CL_SEQR1F, val & 0x3f);
1010 /*************************************************************************
1011 cirrusfb_set_par_foo()
1013 actually writes the values for a new video mode into the hardware,
1014 **************************************************************************/
1015 static int cirrusfb_set_par_foo (struct fb_info *info)
1017 struct cirrusfb_info *cinfo = info->par;
1018 struct fb_var_screeninfo *var = &info->var;
1019 struct cirrusfb_regs regs;
1020 u8 __iomem *regbase = cinfo->regbase;
1022 int offset = 0, err;
1023 const struct cirrusfb_board_info_rec *bi;
1025 DPRINTK ("ENTER\n");
1026 DPRINTK ("Requested mode: %dx%dx%d\n",
1027 var->xres, var->yres, var->bits_per_pixel);
1028 DPRINTK ("pixclock: %d\n", var->pixclock);
1030 init_vgachip (cinfo);
1032 err = cirrusfb_decode_var(var, ®s, info);
1034 /* should never happen */
1035 DPRINTK("mode change aborted. invalid var.\n");
1039 bi = &cirrusfb_board_info[cinfo->btype];
1042 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
1043 vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
1045 /* if debugging is enabled, all parameters get output before writing */
1046 DPRINTK ("CRT0: %ld\n", regs.HorizTotal);
1047 vga_wcrt (regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
1049 DPRINTK ("CRT1: %ld\n", regs.HorizDispEnd);
1050 vga_wcrt (regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
1052 DPRINTK ("CRT2: %ld\n", regs.HorizBlankStart);
1053 vga_wcrt (regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
1055 DPRINTK ("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32); /* + 128: Compatible read */
1056 vga_wcrt (regbase, VGA_CRTC_H_BLANK_END, 128 + (regs.HorizBlankEnd % 32));
1058 DPRINTK ("CRT4: %ld\n", regs.HorizSyncStart);
1059 vga_wcrt (regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
1061 tmp = regs.HorizSyncEnd % 32;
1062 if (regs.HorizBlankEnd & 32)
1064 DPRINTK ("CRT5: %d\n", tmp);
1065 vga_wcrt (regbase, VGA_CRTC_H_SYNC_END, tmp);
1067 DPRINTK ("CRT6: %ld\n", regs.VertTotal & 0xff);
1068 vga_wcrt (regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
1070 tmp = 16; /* LineCompare bit #9 */
1071 if (regs.VertTotal & 256)
1073 if (regs.VertDispEnd & 256)
1075 if (regs.VertSyncStart & 256)
1077 if (regs.VertBlankStart & 256)
1079 if (regs.VertTotal & 512)
1081 if (regs.VertDispEnd & 512)
1083 if (regs.VertSyncStart & 512)
1085 DPRINTK ("CRT7: %d\n", tmp);
1086 vga_wcrt (regbase, VGA_CRTC_OVERFLOW, tmp);
1088 tmp = 0x40; /* LineCompare bit #8 */
1089 if (regs.VertBlankStart & 512)
1091 if (var->vmode & FB_VMODE_DOUBLE)
1093 DPRINTK ("CRT9: %d\n", tmp);
1094 vga_wcrt (regbase, VGA_CRTC_MAX_SCAN, tmp);
1096 DPRINTK ("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1097 vga_wcrt (regbase, VGA_CRTC_V_SYNC_START, (regs.VertSyncStart & 0xff));
1099 DPRINTK ("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1100 vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, (regs.VertSyncEnd % 16 + 64 + 32));
1102 DPRINTK ("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1103 vga_wcrt (regbase, VGA_CRTC_V_DISP_END, (regs.VertDispEnd & 0xff));
1105 DPRINTK ("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1106 vga_wcrt (regbase, VGA_CRTC_V_BLANK_START, (regs.VertBlankStart & 0xff));
1108 DPRINTK ("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1109 vga_wcrt (regbase, VGA_CRTC_V_BLANK_END, (regs.VertBlankEnd & 0xff));
1111 DPRINTK ("CRT18: 0xff\n");
1112 vga_wcrt (regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1115 if (var->vmode & FB_VMODE_INTERLACED)
1117 if (regs.HorizBlankEnd & 64)
1119 if (regs.HorizBlankEnd & 128)
1121 if (regs.VertBlankEnd & 256)
1123 if (regs.VertBlankEnd & 512)
1126 DPRINTK ("CRT1a: %d\n", tmp);
1127 vga_wcrt (regbase, CL_CRT1A, tmp);
1130 /* hardware RefClock: 14.31818 MHz */
1131 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1132 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1134 vga_wseq (regbase, CL_SEQRB, regs.nom);
1135 tmp = regs.den << 1;
1139 if ((cinfo->btype == BT_SD64) ||
1140 (cinfo->btype == BT_ALPINE) ||
1141 (cinfo->btype == BT_GD5480))
1142 tmp |= 0x80; /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1144 DPRINTK ("CL_SEQR1B: %ld\n", (long) tmp);
1145 vga_wseq (regbase, CL_SEQR1B, tmp);
1147 if (regs.VertRes >= 1024)
1149 vga_wcrt (regbase, VGA_CRTC_MODE, 0xc7);
1151 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1152 * address wrap, no compat. */
1153 vga_wcrt (regbase, VGA_CRTC_MODE, 0xc3);
1155 /* HAEH? vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1157 /* don't know if it would hurt to also program this if no interlaced */
1158 /* mode is used, but I feel better this way.. :-) */
1159 if (var->vmode & FB_VMODE_INTERLACED)
1160 vga_wcrt (regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1162 vga_wcrt (regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1164 vga_wseq (regbase, VGA_SEQ_CHARACTER_MAP, 0);
1166 /* adjust horizontal/vertical sync type (low/high) */
1167 tmp = 0x03; /* enable display memory & CRTC I/O address for color mode */
1168 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1170 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1172 WGen (cinfo, VGA_MIS_W, tmp);
1174 vga_wcrt (regbase, VGA_CRTC_PRESET_ROW, 0); /* Screen A Preset Row-Scan register */
1175 vga_wcrt (regbase, VGA_CRTC_CURSOR_START, 0); /* text cursor on and start line */
1176 vga_wcrt (regbase, VGA_CRTC_CURSOR_END, 31); /* text cursor end line */
1178 /******************************************************
1184 /* programming for different color depths */
1185 if (var->bits_per_pixel == 1) {
1186 DPRINTK ("cirrusfb: preparing for 1 bit deep display\n");
1187 vga_wgfx (regbase, VGA_GFX_MODE, 0); /* mode register */
1190 switch (cinfo->btype) {
1198 DPRINTK (" (for GD54xx)\n");
1199 vga_wseq (regbase, CL_SEQR7,
1201 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1205 DPRINTK (" (for GD546x)\n");
1206 vga_wseq (regbase, CL_SEQR7,
1207 vga_rseq (regbase, CL_SEQR7) & ~0x01);
1211 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1215 /* Extended Sequencer Mode */
1216 switch (cinfo->btype) {
1218 /* setting the SEQRF on SD64 is not necessary (only during init) */
1219 DPRINTK ("(for SD64)\n");
1220 vga_wseq (regbase, CL_SEQR1F, 0x1a); /* MCLK select */
1224 DPRINTK ("(for Piccolo)\n");
1225 /* ### ueberall 0x22? */
1226 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */
1227 vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1231 DPRINTK ("(for Picasso)\n");
1232 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 22 MCLK select */
1233 vga_wseq (regbase, CL_SEQRF, 0xd0); /* ## vorher d0 avoid FIFO underruns..? */
1237 DPRINTK ("(for Spectrum)\n");
1238 /* ### ueberall 0x22? */
1239 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */
1240 vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0? avoid FIFO underruns..? */
1247 DPRINTK (" (for GD54xx)\n");
1252 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1256 WGen (cinfo, VGA_PEL_MSK, 0x01); /* pixel mask: pass-through for first plane */
1257 if (regs.multiplexing)
1258 WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */
1260 WHDR (cinfo, 0); /* hidden dac: nothing */
1261 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x06); /* memory mode: odd/even, ext. memory */
1262 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0x01); /* plane mask: only write to first plane */
1263 offset = var->xres_virtual / 16;
1266 /******************************************************
1272 else if (var->bits_per_pixel == 8) {
1273 DPRINTK ("cirrusfb: preparing for 8 bit deep display\n");
1274 switch (cinfo->btype) {
1282 DPRINTK (" (for GD54xx)\n");
1283 vga_wseq (regbase, CL_SEQR7,
1285 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1289 DPRINTK (" (for GD546x)\n");
1290 vga_wseq (regbase, CL_SEQR7,
1291 vga_rseq (regbase, CL_SEQR7) | 0x01);
1295 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1299 switch (cinfo->btype) {
1301 vga_wseq (regbase, CL_SEQR1F, 0x1d); /* MCLK select */
1305 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
1306 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1310 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
1311 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1315 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
1316 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1321 vga_wseq (regbase, CL_SEQRF, 0xb8); /* ### INCOMPLETE!! */
1323 /* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
1327 DPRINTK (" (for GD543x)\n");
1328 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
1329 /* We already set SRF and SR1F */
1334 DPRINTK (" (for GD54xx)\n");
1339 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1343 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
1344 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
1345 if (regs.multiplexing)
1346 WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */
1348 WHDR (cinfo, 0); /* hidden dac: nothing */
1349 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
1350 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
1351 offset = var->xres_virtual / 8;
1354 /******************************************************
1360 else if (var->bits_per_pixel == 16) {
1361 DPRINTK ("cirrusfb: preparing for 16 bit deep display\n");
1362 switch (cinfo->btype) {
1364 vga_wseq (regbase, CL_SEQR7, 0xf7); /* Extended Sequencer Mode: 256c col. mode */
1365 vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */
1369 vga_wseq (regbase, CL_SEQR7, 0x87);
1370 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1371 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1375 vga_wseq (regbase, CL_SEQR7, 0x27);
1376 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1377 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1381 vga_wseq (regbase, CL_SEQR7, 0x87);
1382 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1383 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1387 vga_wseq (regbase, CL_SEQR7, 0x27);
1388 /* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
1392 DPRINTK (" (for GD543x)\n");
1393 if (regs.HorizRes >= 1024)
1394 vga_wseq (regbase, CL_SEQR7, 0xa7);
1396 vga_wseq (regbase, CL_SEQR7, 0xa3);
1397 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
1401 DPRINTK (" (for GD5480)\n");
1402 vga_wseq (regbase, CL_SEQR7, 0x17);
1403 /* We already set SRF and SR1F */
1407 DPRINTK (" (for GD546x)\n");
1408 vga_wseq (regbase, CL_SEQR7,
1409 vga_rseq (regbase, CL_SEQR7) & ~0x01);
1413 printk (KERN_WARNING "CIRRUSFB: unknown Board\n");
1417 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
1418 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
1420 WHDR (cinfo, 0xc0); /* Copy Xbh */
1421 #elif defined(CONFIG_ZORRO)
1422 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1423 WHDR (cinfo, 0xa0); /* hidden dac reg: nothing special */
1425 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
1426 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
1427 offset = var->xres_virtual / 4;
1430 /******************************************************
1436 else if (var->bits_per_pixel == 32) {
1437 DPRINTK ("cirrusfb: preparing for 24/32 bit deep display\n");
1438 switch (cinfo->btype) {
1440 vga_wseq (regbase, CL_SEQR7, 0xf9); /* Extended Sequencer Mode: 256c col. mode */
1441 vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */
1445 vga_wseq (regbase, CL_SEQR7, 0x85);
1446 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1447 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1451 vga_wseq (regbase, CL_SEQR7, 0x25);
1452 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1453 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1457 vga_wseq (regbase, CL_SEQR7, 0x85);
1458 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1459 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1463 vga_wseq (regbase, CL_SEQR7, 0x25);
1464 /* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
1468 DPRINTK (" (for GD543x)\n");
1469 vga_wseq (regbase, CL_SEQR7, 0xa9);
1470 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
1474 DPRINTK (" (for GD5480)\n");
1475 vga_wseq (regbase, CL_SEQR7, 0x19);
1476 /* We already set SRF and SR1F */
1480 DPRINTK (" (for GD546x)\n");
1481 vga_wseq (regbase, CL_SEQR7,
1482 vga_rseq (regbase, CL_SEQR7) & ~0x01);
1486 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1490 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
1491 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
1492 WHDR (cinfo, 0xc5); /* hidden dac reg: 8-8-8 mode (24 or 32) */
1493 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
1494 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
1495 offset = var->xres_virtual / 4;
1498 /******************************************************
1500 * unknown/unsupported bpp
1505 printk (KERN_ERR "cirrusfb: What's this?? requested color depth == %d.\n",
1506 var->bits_per_pixel);
1509 vga_wcrt (regbase, VGA_CRTC_OFFSET, offset & 0xff);
1512 tmp |= 0x10; /* offset overflow bit */
1514 vga_wcrt (regbase, CL_CRT1B, tmp); /* screen start addr #16-18, fastpagemode cycles */
1516 if (cinfo->btype == BT_SD64 ||
1517 cinfo->btype == BT_PICASSO4 ||
1518 cinfo->btype == BT_ALPINE ||
1519 cinfo->btype == BT_GD5480)
1520 vga_wcrt (regbase, CL_CRT1D, 0x00); /* screen start address bit 19 */
1522 vga_wcrt (regbase, VGA_CRTC_CURSOR_HI, 0); /* text cursor location high */
1523 vga_wcrt (regbase, VGA_CRTC_CURSOR_LO, 0); /* text cursor location low */
1524 vga_wcrt (regbase, VGA_CRTC_UNDERLINE, 0); /* underline row scanline = at very bottom */
1526 vga_wattr (regbase, VGA_ATC_MODE, 1); /* controller mode */
1527 vga_wattr (regbase, VGA_ATC_OVERSCAN, 0); /* overscan (border) color */
1528 vga_wattr (regbase, VGA_ATC_PLANE_ENABLE, 15); /* color plane enable */
1529 vga_wattr (regbase, CL_AR33, 0); /* pixel panning */
1530 vga_wattr (regbase, VGA_ATC_COLOR_PAGE, 0); /* color select */
1532 /* [ EGS: SetOffset(); ] */
1533 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1536 vga_wgfx (regbase, VGA_GFX_SR_VALUE, 0); /* set/reset register */
1537 vga_wgfx (regbase, VGA_GFX_SR_ENABLE, 0); /* set/reset enable */
1538 vga_wgfx (regbase, VGA_GFX_COMPARE_VALUE, 0); /* color compare */
1539 vga_wgfx (regbase, VGA_GFX_DATA_ROTATE, 0); /* data rotate */
1540 vga_wgfx (regbase, VGA_GFX_PLANE_READ, 0); /* read map select */
1541 vga_wgfx (regbase, VGA_GFX_MISC, 1); /* miscellaneous register */
1542 vga_wgfx (regbase, VGA_GFX_COMPARE_MASK, 15); /* color don't care */
1543 vga_wgfx (regbase, VGA_GFX_BIT_MASK, 255); /* bit mask */
1545 vga_wseq (regbase, CL_SEQR12, 0x0); /* graphics cursor attributes: nothing special */
1547 /* finally, turn on everything - turn off "FullBandwidth" bit */
1548 /* also, set "DotClock%2" bit where requested */
1551 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1552 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1556 vga_wseq (regbase, VGA_SEQ_CLOCK_MODE, tmp);
1557 DPRINTK ("CL_SEQR1: %d\n", tmp);
1559 cinfo->currentmode = regs;
1560 info->fix.type = regs.type;
1561 info->fix.visual = regs.visual;
1562 info->fix.line_length = regs.line_length;
1564 /* pan to requested offset */
1565 cirrusfb_pan_display (var, info);
1567 #ifdef CIRRUSFB_DEBUG
1575 /* for some reason incomprehensible to me, cirrusfb requires that you write
1576 * the registers twice for the settings to take..grr. -dte */
1577 static int cirrusfb_set_par (struct fb_info *info)
1579 cirrusfb_set_par_foo (info);
1580 return cirrusfb_set_par_foo (info);
1583 static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1584 unsigned blue, unsigned transp,
1585 struct fb_info *info)
1587 struct cirrusfb_info *cinfo = info->par;
1592 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1594 red >>= (16 - info->var.red.length);
1595 green >>= (16 - info->var.green.length);
1596 blue >>= (16 - info->var.blue.length);
1600 v = (red << info->var.red.offset) |
1601 (green << info->var.green.offset) |
1602 (blue << info->var.blue.offset);
1604 switch (info->var.bits_per_pixel) {
1606 ((u8*)(info->pseudo_palette))[regno] = v;
1609 ((u16*)(info->pseudo_palette))[regno] = v;
1613 ((u32*)(info->pseudo_palette))[regno] = v;
1619 cinfo->palette[regno].red = red;
1620 cinfo->palette[regno].green = green;
1621 cinfo->palette[regno].blue = blue;
1623 if (info->var.bits_per_pixel == 8) {
1624 WClut (cinfo, regno, red >> 10, green >> 10, blue >> 10);
1631 /*************************************************************************
1632 cirrusfb_pan_display()
1634 performs display panning - provided hardware permits this
1635 **************************************************************************/
1636 static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
1637 struct fb_info *info)
1642 unsigned char tmp = 0, tmp2 = 0, xpix;
1643 struct cirrusfb_info *cinfo = info->par;
1645 DPRINTK ("ENTER\n");
1646 DPRINTK ("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1648 /* no range checks for xoffset and yoffset, */
1649 /* as fb_pan_display has already done this */
1650 if (var->vmode & FB_VMODE_YWRAP)
1653 info->var.xoffset = var->xoffset;
1654 info->var.yoffset = var->yoffset;
1656 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1657 yoffset = var->yoffset;
1659 base = yoffset * cinfo->currentmode.line_length + xoffset;
1661 if (info->var.bits_per_pixel == 1) {
1662 /* base is already correct */
1663 xpix = (unsigned char) (var->xoffset % 8);
1666 xpix = (unsigned char) ((xoffset % 4) * 2);
1669 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1671 /* lower 8 + 8 bits of screen start address */
1672 vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, (unsigned char) (base & 0xff));
1673 vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, (unsigned char) (base >> 8));
1675 /* construct bits 16, 17 and 18 of screen start address */
1683 tmp2 = (vga_rcrt (cinfo->regbase, CL_CRT1B) & 0xf2) | tmp; /* 0xf2 is %11110010, exclude tmp bits */
1684 vga_wcrt (cinfo->regbase, CL_CRT1B, tmp2);
1686 /* construct bit 19 of screen start address */
1687 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1691 vga_wcrt (cinfo->regbase, CL_CRT1D, tmp2);
1694 /* write pixel panning value to AR33; this does not quite work in 8bpp */
1695 /* ### Piccolo..? Will this work? */
1696 if (info->var.bits_per_pixel == 1)
1697 vga_wattr (cinfo->regbase, CL_AR33, xpix);
1699 cirrusfb_WaitBLT (cinfo->regbase);
1706 static int cirrusfb_blank (int blank_mode, struct fb_info *info)
1709 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1710 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
1711 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
1712 * to e.g. a video mode which doesn't support it. Implements VESA suspend
1713 * and powerdown modes on hardware that supports disabling hsync/vsync:
1714 * blank_mode == 2: suspend vsync
1715 * blank_mode == 3: suspend hsync
1716 * blank_mode == 4: powerdown
1719 struct cirrusfb_info *cinfo = info->par;
1720 int current_mode = cinfo->blank_mode;
1722 DPRINTK ("ENTER, blank mode = %d\n", blank_mode);
1724 if (info->state != FBINFO_STATE_RUNNING ||
1725 current_mode == blank_mode) {
1726 DPRINTK ("EXIT, returning 0\n");
1731 if (current_mode == FB_BLANK_NORMAL ||
1732 current_mode == FB_BLANK_UNBLANK) {
1733 /* unblank the screen */
1734 val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1735 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf); /* clear "FullBandwidth" bit */
1736 /* and undo VESA suspend trickery */
1737 vga_wgfx (cinfo->regbase, CL_GRE, 0x00);
1741 if(blank_mode > FB_BLANK_NORMAL) {
1742 /* blank the screen */
1743 val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1744 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20); /* set "FullBandwidth" bit */
1747 switch (blank_mode) {
1748 case FB_BLANK_UNBLANK:
1749 case FB_BLANK_NORMAL:
1751 case FB_BLANK_VSYNC_SUSPEND:
1752 vga_wgfx (cinfo->regbase, CL_GRE, 0x04);
1754 case FB_BLANK_HSYNC_SUSPEND:
1755 vga_wgfx (cinfo->regbase, CL_GRE, 0x02);
1757 case FB_BLANK_POWERDOWN:
1758 vga_wgfx (cinfo->regbase, CL_GRE, 0x06);
1761 DPRINTK ("EXIT, returning 1\n");
1765 cinfo->blank_mode = blank_mode;
1766 DPRINTK ("EXIT, returning 0\n");
1768 /* Let fbcon do a soft blank for us */
1769 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1771 /**** END Hardware specific Routines **************************************/
1772 /****************************************************************************/
1773 /**** BEGIN Internal Routines ***********************************************/
1775 static void init_vgachip (struct cirrusfb_info *cinfo)
1777 const struct cirrusfb_board_info_rec *bi;
1779 DPRINTK ("ENTER\n");
1781 assert (cinfo != NULL);
1783 bi = &cirrusfb_board_info[cinfo->btype];
1785 /* reset board globally */
1786 switch (cinfo->btype) {
1794 WSFR2 (cinfo, 0xff);
1805 vga_wcrt (cinfo->regbase, CL_CRT51, 0x00); /* disable flickerfixer */
1807 vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */
1808 vga_wgfx (cinfo->regbase, CL_GR33, 0x00); /* put blitter into 542x compat */
1809 vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* mode */
1813 vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */
1817 /* Nothing to do to reset the board. */
1821 printk (KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1825 assert (cinfo->size > 0); /* make sure RAM size set by this point */
1827 /* the P4 is not fully initialized here; I rely on it having been */
1828 /* inited under AmigaOS already, which seems to work just fine */
1829 /* (Klaus advised to do it this way) */
1831 if (cinfo->btype != BT_PICASSO4) {
1832 WGen (cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1833 WGen (cinfo, CL_POS102, 0x01);
1834 WGen (cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1836 if (cinfo->btype != BT_SD64)
1837 WGen (cinfo, CL_VSSM2, 0x01);
1839 vga_wseq (cinfo->regbase, CL_SEQR0, 0x03); /* reset sequencer logic */
1841 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); /* FullBandwidth (video off) and 8/9 dot clock */
1842 WGen (cinfo, VGA_MIS_W, 0xc1); /* polarity (-/-), disable access to display memory, VGA_CRTC_START_HI base address: color */
1844 /* vga_wgfx (cinfo->regbase, CL_GRA, 0xce); "magic cookie" - doesn't make any sense to me.. */
1845 vga_wseq (cinfo->regbase, CL_SEQR6, 0x12); /* unlock all extension registers */
1847 vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* reset blitter */
1849 switch (cinfo->btype) {
1851 vga_wseq (cinfo->regbase, CL_SEQRF, 0x98);
1856 vga_wseq (cinfo->regbase, CL_SEQRF, 0xb8);
1859 vga_wseq (cinfo->regbase, CL_SEQR16, 0x0f);
1860 vga_wseq (cinfo->regbase, CL_SEQRF, 0xb0);
1864 vga_wseq (cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: nothing */
1865 vga_wseq (cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); /* character map select: doesn't even matter in gx mode */
1866 vga_wseq (cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e); /* memory mode: chain-4, no odd/even, ext. memory */
1868 /* controller-internal base address of video memory */
1870 vga_wseq (cinfo->regbase, CL_SEQR7, bi->sr07);
1872 /* vga_wseq (cinfo->regbase, CL_SEQR8, 0x00); *//* EEPROM control: shouldn't be necessary to write to this at all.. */
1874 vga_wseq (cinfo->regbase, CL_SEQR10, 0x00); /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1875 vga_wseq (cinfo->regbase, CL_SEQR11, 0x00); /* graphics cursor Y position (..."... ) */
1876 vga_wseq (cinfo->regbase, CL_SEQR12, 0x00); /* graphics cursor attributes */
1877 vga_wseq (cinfo->regbase, CL_SEQR13, 0x00); /* graphics cursor pattern address */
1879 /* writing these on a P4 might give problems.. */
1880 if (cinfo->btype != BT_PICASSO4) {
1881 vga_wseq (cinfo->regbase, CL_SEQR17, 0x00); /* configuration readback and ext. color */
1882 vga_wseq (cinfo->regbase, CL_SEQR18, 0x02); /* signature generator */
1885 /* MCLK select etc. */
1887 vga_wseq (cinfo->regbase, CL_SEQR1F, bi->sr1f);
1889 vga_wcrt (cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); /* Screen A preset row scan: none */
1890 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); /* Text cursor start: disable text cursor */
1891 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); /* Text cursor end: - */
1892 vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, 0x00); /* Screen start address high: 0 */
1893 vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, 0x00); /* Screen start address low: 0 */
1894 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); /* text cursor location high: 0 */
1895 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); /* text cursor location low: 0 */
1897 vga_wcrt (cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); /* Underline Row scanline: - */
1898 vga_wcrt (cinfo->regbase, VGA_CRTC_MODE, 0xc3); /* mode control: timing enable, byte mode, no compat modes */
1899 vga_wcrt (cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00); /* Line Compare: not needed */
1900 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1901 vga_wcrt (cinfo->regbase, CL_CRT1B, 0x02); /* ext. display controls: ext.adr. wrap */
1903 vga_wgfx (cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); /* Set/Reset registes: - */
1904 vga_wgfx (cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); /* Set/Reset enable: - */
1905 vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); /* Color Compare: - */
1906 vga_wgfx (cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); /* Data Rotate: - */
1907 vga_wgfx (cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); /* Read Map Select: - */
1908 vga_wgfx (cinfo->regbase, VGA_GFX_MODE, 0x00); /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1909 vga_wgfx (cinfo->regbase, VGA_GFX_MISC, 0x01); /* Miscellaneous: memory map base address, graphics mode */
1910 vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); /* Color Don't care: involve all planes */
1911 vga_wgfx (cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); /* Bit Mask: no mask at all */
1912 if (cinfo->btype == BT_ALPINE)
1913 vga_wgfx (cinfo->regbase, CL_GRB, 0x20); /* (5434 can't have bit 3 set for bitblt) */
1915 vga_wgfx (cinfo->regbase, CL_GRB, 0x28); /* Graphics controller mode extensions: finer granularity, 8byte data latches */
1917 vga_wgfx (cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1918 vga_wgfx (cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1919 vga_wgfx (cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1920 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); *//* Background color byte 1: - */
1921 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1923 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE0, 0x00); /* Attribute Controller palette registers: "identity mapping" */
1924 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1925 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1926 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1927 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1928 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1929 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1930 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1931 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1932 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1933 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1934 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1935 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1936 vga_wattr (cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1937 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1938 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1940 vga_wattr (cinfo->regbase, VGA_ATC_MODE, 0x01); /* Attribute Controller mode: graphics mode */
1941 vga_wattr (cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); /* Overscan color reg.: reg. 0 */
1942 vga_wattr (cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); /* Color Plane enable: Enable all 4 planes */
1943 /* ### vga_wattr (cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
1944 vga_wattr (cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); /* Color Select: - */
1946 WGen (cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1948 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1949 WGen (cinfo, VGA_MIS_W, 0xc3); /* polarity (-/-), enable display mem, VGA_CRTC_START_HI i/o base = color */
1951 vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* BLT Start/status: Blitter reset */
1952 vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* - " - : "end-of-reset" */
1955 WHDR (cinfo, 0); /* Hidden DAC register: - */
1957 printk (KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n", cinfo->size);
1962 static void switch_monitor (struct cirrusfb_info *cinfo, int on)
1964 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1965 static int IsOn = 0; /* XXX not ok for multiple boards */
1967 DPRINTK ("ENTER\n");
1969 if (cinfo->btype == BT_PICASSO4)
1970 return; /* nothing to switch */
1971 if (cinfo->btype == BT_ALPINE)
1972 return; /* nothing to switch */
1973 if (cinfo->btype == BT_GD5480)
1974 return; /* nothing to switch */
1975 if (cinfo->btype == BT_PICASSO) {
1976 if ((on && !IsOn) || (!on && IsOn))
1983 switch (cinfo->btype) {
1985 WSFR (cinfo, cinfo->SFR | 0x21);
1988 WSFR (cinfo, cinfo->SFR | 0x28);
1993 default: /* do nothing */ break;
1996 switch (cinfo->btype) {
1998 WSFR (cinfo, cinfo->SFR & 0xde);
2001 WSFR (cinfo, cinfo->SFR & 0xd7);
2006 default: /* do nothing */ break;
2011 #endif /* CONFIG_ZORRO */
2015 /******************************************/
2016 /* Linux 2.6-style accelerated functions */
2017 /******************************************/
2019 static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
2020 const struct fb_fillrect *region)
2022 int m; /* bytes per pixel */
2023 if(cinfo->info->var.bits_per_pixel == 1) {
2024 cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2025 region->dx / 8, region->dy,
2026 region->width / 8, region->height,
2028 cinfo->currentmode.line_length);
2030 m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
2031 cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2032 region->dx * m, region->dy,
2033 region->width * m, region->height,
2035 cinfo->currentmode.line_length);
2040 static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region)
2042 struct cirrusfb_info *cinfo = info->par;
2043 struct fb_fillrect modded;
2046 if (info->state != FBINFO_STATE_RUNNING)
2048 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2049 cfb_fillrect(info, region);
2053 vxres = info->var.xres_virtual;
2054 vyres = info->var.yres_virtual;
2056 memcpy(&modded, region, sizeof(struct fb_fillrect));
2058 if(!modded.width || !modded.height ||
2059 modded.dx >= vxres || modded.dy >= vyres)
2062 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
2063 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
2065 cirrusfb_prim_fillrect(cinfo, &modded);
2068 static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
2069 const struct fb_copyarea *area)
2071 int m; /* bytes per pixel */
2072 if(cinfo->info->var.bits_per_pixel == 1) {
2073 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2074 area->sx / 8, area->sy,
2075 area->dx / 8, area->dy,
2076 area->width / 8, area->height,
2077 cinfo->currentmode.line_length);
2079 m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
2080 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2081 area->sx * m, area->sy,
2082 area->dx * m, area->dy,
2083 area->width * m, area->height,
2084 cinfo->currentmode.line_length);
2090 static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
2092 struct cirrusfb_info *cinfo = info->par;
2093 struct fb_copyarea modded;
2095 modded.sx = area->sx;
2096 modded.sy = area->sy;
2097 modded.dx = area->dx;
2098 modded.dy = area->dy;
2099 modded.width = area->width;
2100 modded.height = area->height;
2102 if (info->state != FBINFO_STATE_RUNNING)
2104 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2105 cfb_copyarea(info, area);
2109 vxres = info->var.xres_virtual;
2110 vyres = info->var.yres_virtual;
2112 if(!modded.width || !modded.height ||
2113 modded.sx >= vxres || modded.sy >= vyres ||
2114 modded.dx >= vxres || modded.dy >= vyres)
2117 if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
2118 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
2119 if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
2120 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
2122 cirrusfb_prim_copyarea(cinfo, &modded);
2125 static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image)
2127 struct cirrusfb_info *cinfo = info->par;
2129 cirrusfb_WaitBLT(cinfo->regbase);
2130 cfb_imageblit(info, image);
2134 #ifdef CONFIG_PPC_PREP
2135 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2136 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2137 static void get_prep_addrs (unsigned long *display, unsigned long *registers)
2139 DPRINTK ("ENTER\n");
2141 *display = PREP_VIDEO_BASE;
2142 *registers = (unsigned long) PREP_IO_BASE;
2147 #endif /* CONFIG_PPC_PREP */
2151 static int release_io_ports = 0;
2153 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2154 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2155 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2157 static unsigned int cirrusfb_get_memsize (u8 __iomem *regbase)
2162 DPRINTK ("ENTER\n");
2164 SRF = vga_rseq (regbase, CL_SEQRF);
2165 switch ((SRF & 0x18)) {
2166 case 0x08: mem = 512 * 1024; break;
2167 case 0x10: mem = 1024 * 1024; break;
2168 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2170 case 0x18: mem = 2048 * 1024; break;
2171 default: printk ("CLgenfb: Unknown memory size!\n");
2175 /* If DRAM bank switching is enabled, there must be twice as much
2176 * memory installed. (4MB on the 5434) */
2179 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2187 static void get_pci_addrs (const struct pci_dev *pdev,
2188 unsigned long *display, unsigned long *registers)
2190 assert (pdev != NULL);
2191 assert (display != NULL);
2192 assert (registers != NULL);
2194 DPRINTK ("ENTER\n");
2199 /* This is a best-guess for now */
2201 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
2202 *display = pci_resource_start(pdev, 1);
2203 *registers = pci_resource_start(pdev, 0);
2205 *display = pci_resource_start(pdev, 0);
2206 *registers = pci_resource_start(pdev, 1);
2209 assert (*display != 0);
2215 static void cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
2217 struct pci_dev *pdev = cinfo->pdev;
2219 iounmap(cinfo->fbmem);
2220 #if 0 /* if system didn't claim this region, we would... */
2221 release_mem_region(0xA0000, 65535);
2223 if (release_io_ports)
2224 release_region(0x3C0, 32);
2225 pci_release_regions(pdev);
2226 framebuffer_release(cinfo->info);
2227 pci_disable_device(pdev);
2229 #endif /* CONFIG_PCI */
2233 static void __devexit cirrusfb_zorro_unmap (struct cirrusfb_info *cinfo)
2235 zorro_release_device(cinfo->zdev);
2237 if (cinfo->btype == BT_PICASSO4) {
2238 cinfo->regbase -= 0x600000;
2239 iounmap ((void *)cinfo->regbase);
2240 iounmap ((void *)cinfo->fbmem);
2242 if (zorro_resource_start(cinfo->zdev) > 0x01000000)
2243 iounmap ((void *)cinfo->fbmem);
2245 framebuffer_release(cinfo->info);
2247 #endif /* CONFIG_ZORRO */
2249 static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
2251 struct fb_info *info = cinfo->info;
2252 struct fb_var_screeninfo *var = &info->var;
2255 info->pseudo_palette = cinfo->pseudo_palette;
2256 info->flags = FBINFO_DEFAULT
2257 | FBINFO_HWACCEL_XPAN
2258 | FBINFO_HWACCEL_YPAN
2259 | FBINFO_HWACCEL_FILLRECT
2260 | FBINFO_HWACCEL_COPYAREA;
2262 info->flags |= FBINFO_HWACCEL_DISABLED;
2263 info->fbops = &cirrusfb_ops;
2264 info->screen_base = cinfo->fbmem;
2265 if (cinfo->btype == BT_GD5480) {
2266 if (var->bits_per_pixel == 16)
2267 info->screen_base += 1 * MB_;
2268 if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
2269 info->screen_base += 2 * MB_;
2272 /* Fill fix common fields */
2273 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2274 sizeof(info->fix.id));
2276 /* monochrome: only 1 memory plane */
2277 /* 8 bit and above: Use whole memory area */
2278 info->fix.smem_start = cinfo->fbmem_phys;
2279 info->fix.smem_len = (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
2280 info->fix.type = cinfo->currentmode.type;
2281 info->fix.type_aux = 0;
2282 info->fix.visual = cinfo->currentmode.visual;
2283 info->fix.xpanstep = 1;
2284 info->fix.ypanstep = 1;
2285 info->fix.ywrapstep = 0;
2286 info->fix.line_length = cinfo->currentmode.line_length;
2288 /* FIXME: map region at 0xB8000 if available, fill in here */
2289 info->fix.mmio_start = cinfo->fbregs_phys;
2290 info->fix.mmio_len = 0;
2291 info->fix.accel = FB_ACCEL_NONE;
2293 fb_alloc_cmap(&info->cmap, 256, 0);
2298 static int cirrusfb_register(struct cirrusfb_info *cinfo)
2300 struct fb_info *info;
2302 cirrusfb_board_t btype;
2304 DPRINTK ("ENTER\n");
2306 printk (KERN_INFO "cirrusfb: Driver for Cirrus Logic based graphic boards, v" CIRRUSFB_VERSION "\n");
2309 btype = cinfo->btype;
2312 assert (btype != BT_NONE);
2314 DPRINTK ("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
2316 /* Make pretend we've set the var so our structures are in a "good" */
2317 /* state, even though we haven't written the mode to the hw yet... */
2318 info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
2319 info->var.activate = FB_ACTIVATE_NOW;
2321 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2323 /* should never happen */
2324 DPRINTK("choking on default var... umm, no good.\n");
2325 goto err_unmap_cirrusfb;
2328 /* set all the vital stuff */
2329 cirrusfb_set_fbinfo(cinfo);
2331 err = register_framebuffer(info);
2333 printk (KERN_ERR "cirrusfb: could not register fb device; err = %d!\n", err);
2334 goto err_dealloc_cmap;
2337 DPRINTK ("EXIT, returning 0\n");
2341 fb_dealloc_cmap(&info->cmap);
2343 cinfo->unmap(cinfo);
2347 static void __devexit cirrusfb_cleanup (struct fb_info *info)
2349 struct cirrusfb_info *cinfo = info->par;
2350 DPRINTK ("ENTER\n");
2352 switch_monitor (cinfo, 0);
2354 unregister_framebuffer (info);
2355 fb_dealloc_cmap (&info->cmap);
2356 printk ("Framebuffer unregistered\n");
2357 cinfo->unmap(cinfo);
2364 static int cirrusfb_pci_register (struct pci_dev *pdev,
2365 const struct pci_device_id *ent)
2367 struct cirrusfb_info *cinfo;
2368 struct fb_info *info;
2369 cirrusfb_board_t btype;
2370 unsigned long board_addr, board_size;
2373 ret = pci_enable_device(pdev);
2375 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2379 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2381 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2389 cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data;
2391 DPRINTK (" Found PCI device, base address 0 is 0x%lx, btype set to %d\n",
2392 pdev->resource[0].start, btype);
2393 DPRINTK (" base address 1 is 0x%lx\n", pdev->resource[1].start);
2396 pci_write_config_dword (pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2397 #ifdef CONFIG_PPC_PREP
2398 get_prep_addrs (&board_addr, &cinfo->fbregs_phys);
2400 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2401 cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
2403 DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n");
2404 get_pci_addrs (pdev, &board_addr, &cinfo->fbregs_phys);
2405 cinfo->regbase = NULL; /* FIXME: this forces VGA. alternatives? */
2408 DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n", board_addr, cinfo->fbregs_phys);
2410 board_size = (btype == BT_GD5480) ?
2411 32 * MB_ : cirrusfb_get_memsize (cinfo->regbase);
2413 ret = pci_request_regions(pdev, "cirrusfb");
2415 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
2417 goto err_release_fb;
2419 #if 0 /* if the system didn't claim this region, we would... */
2420 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2421 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
2425 goto err_release_regions;
2428 if (request_region(0x3C0, 32, "cirrusfb"))
2429 release_io_ports = 1;
2431 cinfo->fbmem = ioremap(board_addr, board_size);
2432 if (!cinfo->fbmem) {
2434 goto err_release_legacy;
2437 cinfo->fbmem_phys = board_addr;
2438 cinfo->size = board_size;
2439 cinfo->unmap = cirrusfb_pci_unmap;
2441 printk (" RAM (%lu kB) at 0xx%lx, ", cinfo->size / KB_, board_addr);
2442 printk ("Cirrus Logic chipset on PCI bus\n");
2443 pci_set_drvdata(pdev, info);
2445 return cirrusfb_register(cinfo);
2448 if (release_io_ports)
2449 release_region(0x3C0, 32);
2451 release_mem_region(0xA0000, 65535);
2452 err_release_regions:
2454 pci_release_regions(pdev);
2456 framebuffer_release(info);
2458 pci_disable_device(pdev);
2463 static void __devexit cirrusfb_pci_unregister (struct pci_dev *pdev)
2465 struct fb_info *info = pci_get_drvdata(pdev);
2466 DPRINTK ("ENTER\n");
2468 cirrusfb_cleanup (info);
2473 static struct pci_driver cirrusfb_pci_driver = {
2475 .id_table = cirrusfb_pci_table,
2476 .probe = cirrusfb_pci_register,
2477 .remove = __devexit_p(cirrusfb_pci_unregister),
2480 .suspend = cirrusfb_pci_suspend,
2481 .resume = cirrusfb_pci_resume,
2485 #endif /* CONFIG_PCI */
2489 static int cirrusfb_zorro_register(struct zorro_dev *z,
2490 const struct zorro_device_id *ent)
2492 struct cirrusfb_info *cinfo;
2493 struct fb_info *info;
2494 cirrusfb_board_t btype;
2495 struct zorro_dev *z2 = NULL;
2496 unsigned long board_addr, board_size, size;
2499 btype = ent->driver_data;
2500 if (cirrusfb_zorro_table2[btype].id2)
2501 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2502 size = cirrusfb_zorro_table2[btype].size;
2503 printk(KERN_INFO "cirrusfb: %s board detected; ",
2504 cirrusfb_board_info[btype].name);
2506 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2508 printk (KERN_ERR "cirrusfb: could not allocate memory\n");
2515 cinfo->btype = btype;
2519 assert (btype != BT_NONE);
2522 board_addr = zorro_resource_start(z);
2523 board_size = zorro_resource_len(z);
2526 if (!zorro_request_device(z, "cirrusfb")) {
2527 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
2530 goto err_release_fb;
2533 printk (" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2537 if (btype == BT_PICASSO4) {
2538 printk (" REG at $%lx\n", board_addr + 0x600000);
2540 /* To be precise, for the P4 this is not the */
2541 /* begin of the board, but the begin of RAM. */
2542 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2543 /* (note the ugly hardcoded 16M number) */
2544 cinfo->regbase = ioremap (board_addr, 16777216);
2545 if (!cinfo->regbase)
2546 goto err_release_region;
2548 DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
2549 cinfo->regbase += 0x600000;
2550 cinfo->fbregs_phys = board_addr + 0x600000;
2552 cinfo->fbmem_phys = board_addr + 16777216;
2553 cinfo->fbmem = ioremap (cinfo->fbmem_phys, 16777216);
2555 goto err_unmap_regbase;
2557 printk (" REG at $%lx\n", (unsigned long) z2->resource.start);
2559 cinfo->fbmem_phys = board_addr;
2560 if (board_addr > 0x01000000)
2561 cinfo->fbmem = ioremap (board_addr, board_size);
2563 cinfo->fbmem = (caddr_t) ZTWO_VADDR (board_addr);
2565 goto err_release_region;
2567 /* set address for REG area of board */
2568 cinfo->regbase = (caddr_t) ZTWO_VADDR (z2->resource.start);
2569 cinfo->fbregs_phys = z2->resource.start;
2571 DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
2573 cinfo->unmap = cirrusfb_zorro_unmap;
2575 printk (KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2576 zorro_set_drvdata(z, info);
2578 return cirrusfb_register(cinfo);
2581 /* Parental advisory: explicit hack */
2582 iounmap(cinfo->regbase - 0x600000);
2584 release_region(board_addr, board_size);
2586 framebuffer_release(info);
2591 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2593 struct fb_info *info = zorro_get_drvdata(z);
2594 DPRINTK ("ENTER\n");
2596 cirrusfb_cleanup (info);
2601 static struct zorro_driver cirrusfb_zorro_driver = {
2603 .id_table = cirrusfb_zorro_table,
2604 .probe = cirrusfb_zorro_register,
2605 .remove = __devexit_p(cirrusfb_zorro_unregister),
2607 #endif /* CONFIG_ZORRO */
2609 static int __init cirrusfb_init(void)
2614 char *option = NULL;
2616 if (fb_get_options("cirrusfb", &option))
2618 cirrusfb_setup(option);
2622 error |= zorro_module_init(&cirrusfb_zorro_driver);
2625 error |= pci_register_driver(&cirrusfb_pci_driver);
2633 static int __init cirrusfb_setup(char *options) {
2634 char *this_opt, s[32];
2637 DPRINTK ("ENTER\n");
2639 if (!options || !*options)
2642 while ((this_opt = strsep (&options, ",")) != NULL) {
2643 if (!*this_opt) continue;
2645 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2647 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2648 sprintf (s, "mode:%s", cirrusfb_predefined[i].name);
2649 if (strcmp (this_opt, s) == 0)
2650 cirrusfb_def_mode = i;
2652 if (!strcmp(this_opt, "noaccel"))
2664 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2665 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2666 MODULE_LICENSE("GPL");
2668 static void __exit cirrusfb_exit (void)
2671 pci_unregister_driver(&cirrusfb_pci_driver);
2674 zorro_unregister_driver(&cirrusfb_zorro_driver);
2678 module_init(cirrusfb_init);
2681 module_exit(cirrusfb_exit);
2685 /**********************************************************************/
2686 /* about the following functions - I have used the same names for the */
2687 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2688 /* they just made sense for this purpose. Apart from that, I wrote */
2689 /* these functions myself. */
2690 /**********************************************************************/
2692 /*** WGen() - write into one of the external/general registers ***/
2693 static void WGen (const struct cirrusfb_info *cinfo,
2694 int regnum, unsigned char val)
2696 unsigned long regofs = 0;
2698 if (cinfo->btype == BT_PICASSO) {
2699 /* Picasso II specific hack */
2700 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
2701 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2705 vga_w (cinfo->regbase, regofs + regnum, val);
2708 /*** RGen() - read out one of the external/general registers ***/
2709 static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum)
2711 unsigned long regofs = 0;
2713 if (cinfo->btype == BT_PICASSO) {
2714 /* Picasso II specific hack */
2715 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
2716 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2720 return vga_r (cinfo->regbase, regofs + regnum);
2723 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2724 static void AttrOn (const struct cirrusfb_info *cinfo)
2726 assert (cinfo != NULL);
2728 DPRINTK ("ENTER\n");
2730 if (vga_rcrt (cinfo->regbase, CL_CRT24) & 0x80) {
2731 /* if we're just in "write value" mode, write back the */
2732 /* same value as before to not modify anything */
2733 vga_w (cinfo->regbase, VGA_ATT_IW,
2734 vga_r (cinfo->regbase, VGA_ATT_R));
2736 /* turn on video bit */
2737 /* vga_w (cinfo->regbase, VGA_ATT_IW, 0x20); */
2738 vga_w (cinfo->regbase, VGA_ATT_IW, 0x33);
2740 /* dummy write on Reg0 to be on "write index" mode next time */
2741 vga_w (cinfo->regbase, VGA_ATT_IW, 0x00);
2746 /*** WHDR() - write into the Hidden DAC register ***/
2747 /* as the HDR is the only extension register that requires special treatment
2748 * (the other extension registers are accessible just like the "ordinary"
2749 * registers of their functional group) here is a specialized routine for
2752 static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val)
2754 unsigned char dummy;
2756 if (cinfo->btype == BT_PICASSO) {
2757 /* Klaus' hint for correct access to HDR on some boards */
2758 /* first write 0 to pixel mask (3c6) */
2759 WGen (cinfo, VGA_PEL_MSK, 0x00);
2761 /* next read dummy from pixel address (3c8) */
2762 dummy = RGen (cinfo, VGA_PEL_IW);
2765 /* now do the usual stuff to access the HDR */
2767 dummy = RGen (cinfo, VGA_PEL_MSK);
2769 dummy = RGen (cinfo, VGA_PEL_MSK);
2771 dummy = RGen (cinfo, VGA_PEL_MSK);
2773 dummy = RGen (cinfo, VGA_PEL_MSK);
2776 WGen (cinfo, VGA_PEL_MSK, val);
2779 if (cinfo->btype == BT_PICASSO) {
2780 /* now first reset HDR access counter */
2781 dummy = RGen (cinfo, VGA_PEL_IW);
2784 /* and at the end, restore the mask value */
2785 /* ## is this mask always 0xff? */
2786 WGen (cinfo, VGA_PEL_MSK, 0xff);
2792 /*** WSFR() - write to the "special function register" (SFR) ***/
2793 static void WSFR (struct cirrusfb_info *cinfo, unsigned char val)
2796 assert (cinfo->regbase != NULL);
2798 z_writeb (val, cinfo->regbase + 0x8000);
2802 /* The Picasso has a second register for switching the monitor bit */
2803 static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val)
2806 /* writing an arbitrary value to this one causes the monitor switcher */
2807 /* to flip to Amiga display */
2808 assert (cinfo->regbase != NULL);
2810 z_writeb (val, cinfo->regbase + 0x9000);
2815 /*** WClut - set CLUT entry (range: 0..63) ***/
2816 static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2817 unsigned char green, unsigned char blue)
2819 unsigned int data = VGA_PEL_D;
2821 /* address write mode register is not translated.. */
2822 vga_w (cinfo->regbase, VGA_PEL_IW, regnum);
2824 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2825 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2826 /* but DAC data register IS, at least for Picasso II */
2827 if (cinfo->btype == BT_PICASSO)
2829 vga_w (cinfo->regbase, data, red);
2830 vga_w (cinfo->regbase, data, green);
2831 vga_w (cinfo->regbase, data, blue);
2833 vga_w (cinfo->regbase, data, blue);
2834 vga_w (cinfo->regbase, data, green);
2835 vga_w (cinfo->regbase, data, red);
2841 /*** RClut - read CLUT entry (range 0..63) ***/
2842 static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2843 unsigned char *green, unsigned char *blue)
2845 unsigned int data = VGA_PEL_D;
2847 vga_w (cinfo->regbase, VGA_PEL_IR, regnum);
2849 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2850 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2851 if (cinfo->btype == BT_PICASSO)
2853 *red = vga_r (cinfo->regbase, data);
2854 *green = vga_r (cinfo->regbase, data);
2855 *blue = vga_r (cinfo->regbase, data);
2857 *blue = vga_r (cinfo->regbase, data);
2858 *green = vga_r (cinfo->regbase, data);
2859 *red = vga_r (cinfo->regbase, data);
2865 /*******************************************************************
2868 Wait for the BitBLT engine to complete a possible earlier job
2869 *********************************************************************/
2871 /* FIXME: use interrupts instead */
2872 static void cirrusfb_WaitBLT (u8 __iomem *regbase)
2874 /* now busy-wait until we're done */
2875 while (vga_rgfx (regbase, CL_GR31) & 0x08)
2879 /*******************************************************************
2882 perform accelerated "scrolling"
2883 ********************************************************************/
2885 static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
2886 u_short curx, u_short cury, u_short destx, u_short desty,
2887 u_short width, u_short height, u_short line_length)
2889 u_short nwidth, nheight;
2893 DPRINTK ("ENTER\n");
2896 nheight = height - 1;
2899 /* if source adr < dest addr, do the Blt backwards */
2900 if (cury <= desty) {
2901 if (cury == desty) {
2902 /* if src and dest are on the same line, check x */
2909 /* standard case: forward blitting */
2910 nsrc = (cury * line_length) + curx;
2911 ndest = (desty * line_length) + destx;
2913 /* this means start addresses are at the end, counting backwards */
2914 nsrc = cury * line_length + curx + nheight * line_length + nwidth;
2915 ndest = desty * line_length + destx + nheight * line_length + nwidth;
2919 run-down of registers to be programmed:
2927 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2931 cirrusfb_WaitBLT(regbase);
2933 /* pitch: set to line_length */
2934 vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2935 vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */
2936 vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2937 vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */
2939 /* BLT width: actual number of pixels - 1 */
2940 vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2941 vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */
2943 /* BLT height: actual number of lines -1 */
2944 vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2945 vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */
2947 /* BLT destination */
2948 vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */
2949 vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */
2950 vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */
2953 vga_wgfx (regbase, CL_GR2C, (u_char) (nsrc & 0xff)); /* BLT src low */
2954 vga_wgfx (regbase, CL_GR2D, (u_char) (nsrc >> 8)); /* BLT src mid */
2955 vga_wgfx (regbase, CL_GR2E, (u_char) (nsrc >> 16)); /* BLT src hi */
2958 vga_wgfx (regbase, CL_GR30, bltmode); /* BLT mode */
2960 /* BLT ROP: SrcCopy */
2961 vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
2963 /* and finally: GO! */
2964 vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */
2970 /*******************************************************************
2973 perform accelerated rectangle fill
2974 ********************************************************************/
2976 static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
2977 u_short x, u_short y, u_short width, u_short height,
2978 u_char color, u_short line_length)
2980 u_short nwidth, nheight;
2984 DPRINTK ("ENTER\n");
2987 nheight = height - 1;
2989 ndest = (y * line_length) + x;
2991 cirrusfb_WaitBLT(regbase);
2993 /* pitch: set to line_length */
2994 vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2995 vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */
2996 vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2997 vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */
2999 /* BLT width: actual number of pixels - 1 */
3000 vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
3001 vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */
3003 /* BLT height: actual number of lines -1 */
3004 vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */
3005 vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */
3007 /* BLT destination */
3008 vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */
3009 vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */
3010 vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */
3012 /* BLT source: set to 0 (is a dummy here anyway) */
3013 vga_wgfx (regbase, CL_GR2C, 0x00); /* BLT src low */
3014 vga_wgfx (regbase, CL_GR2D, 0x00); /* BLT src mid */
3015 vga_wgfx (regbase, CL_GR2E, 0x00); /* BLT src hi */
3017 /* This is a ColorExpand Blt, using the */
3018 /* same color for foreground and background */
3019 vga_wgfx (regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
3020 vga_wgfx (regbase, VGA_GFX_SR_ENABLE, color); /* background color */
3023 if (bits_per_pixel == 16) {
3024 vga_wgfx (regbase, CL_GR10, color); /* foreground color */
3025 vga_wgfx (regbase, CL_GR11, color); /* background color */
3028 } else if (bits_per_pixel == 32) {
3029 vga_wgfx (regbase, CL_GR10, color); /* foreground color */
3030 vga_wgfx (regbase, CL_GR11, color); /* background color */
3031 vga_wgfx (regbase, CL_GR12, color); /* foreground color */
3032 vga_wgfx (regbase, CL_GR13, color); /* background color */
3033 vga_wgfx (regbase, CL_GR14, 0); /* foreground color */
3034 vga_wgfx (regbase, CL_GR15, 0); /* background color */
3038 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
3039 vga_wgfx (regbase, CL_GR30, op); /* BLT mode */
3041 /* BLT ROP: SrcCopy */
3042 vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
3044 /* and finally: GO! */
3045 vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */
3051 /**************************************************************************
3052 * bestclock() - determine closest possible clock lower(?) than the
3053 * desired pixel clock
3054 **************************************************************************/
3055 static void bestclock (long freq, long *best, long *nom,
3056 long *den, long *div, long maxfreq)
3060 assert (best != NULL);
3061 assert (nom != NULL);
3062 assert (den != NULL);
3063 assert (div != NULL);
3064 assert (maxfreq > 0);
3070 DPRINTK ("ENTER\n");
3081 for (n = 32; n < 128; n++) {
3082 d = (143181 * n) / f;
3083 if ((d >= 7) && (d <= 63)) {
3086 h = (14318 * n) / d;
3087 if (abs (h - freq) < abs (*best - freq)) {
3099 d = ((143181 * n) + f - 1) / f;
3100 if ((d >= 7) && (d <= 63)) {
3103 h = (14318 * n) / d;
3104 if (abs (h - freq) < abs (*best - freq)) {
3118 DPRINTK ("Best possible values for given frequency:\n");
3119 DPRINTK (" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3120 freq, *nom, *den, *div);
3126 /* -------------------------------------------------------------------------
3128 * debugging functions
3130 * -------------------------------------------------------------------------
3133 #ifdef CIRRUSFB_DEBUG
3136 * cirrusfb_dbg_print_byte
3137 * @name: name associated with byte value to be displayed
3138 * @val: byte value to be displayed
3141 * Display an indented string, along with a hexidecimal byte value, and
3142 * its decoded bits. Bits 7 through 0 are listed in left-to-right
3147 void cirrusfb_dbg_print_byte (const char *name, unsigned char val)
3149 DPRINTK ("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3151 val & 0x80 ? '1' : '0',
3152 val & 0x40 ? '1' : '0',
3153 val & 0x20 ? '1' : '0',
3154 val & 0x10 ? '1' : '0',
3155 val & 0x08 ? '1' : '0',
3156 val & 0x04 ? '1' : '0',
3157 val & 0x02 ? '1' : '0',
3158 val & 0x01 ? '1' : '0');
3163 * cirrusfb_dbg_print_regs
3164 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3165 * @reg_class: type of registers to read: %CRT, or %SEQ
3168 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
3169 * old-style I/O ports are queried for information, otherwise MMIO is
3170 * used at the given @base address to query the information.
3174 void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...)
3177 unsigned char val = 0;
3181 va_start (list, reg_class);
3183 name = va_arg (list, char *);
3184 while (name != NULL) {
3185 reg = va_arg (list, int);
3187 switch (reg_class) {
3189 val = vga_rcrt (regbase, (unsigned char) reg);
3192 val = vga_rseq (regbase, (unsigned char) reg);
3195 /* should never occur */
3200 cirrusfb_dbg_print_byte (name, val);
3202 name = va_arg (list, char *);
3217 void cirrusfb_dump (void)
3219 cirrusfb_dbg_reg_dump (NULL);
3224 * cirrusfb_dbg_reg_dump
3225 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3228 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
3229 * old-style I/O ports are queried for information, otherwise MMIO is
3230 * used at the given @base address to query the information.
3234 void cirrusfb_dbg_reg_dump (caddr_t regbase)
3236 DPRINTK ("CIRRUSFB VGA CRTC register dump:\n");
3238 cirrusfb_dbg_print_regs (regbase, CRT,
3290 DPRINTK ("CIRRUSFB VGA SEQ register dump:\n");
3292 cirrusfb_dbg_print_regs (regbase, SEQ,
3324 #endif /* CIRRUSFB_DEBUG */