drivers/video/exynos/exynos_dp_core.h

   1 /*
   2  * Header file for Samsung DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #ifndef _EXYNOS_DP_CORE_H
  14 #define _EXYNOS_DP_CORE_H
  15
  16 enum dp_irq_type {
  17         DP_IRQ_TYPE_HP_CABLE_IN,
  18         DP_IRQ_TYPE_HP_CABLE_OUT,
  19         DP_IRQ_TYPE_HP_CHANGE,
  20         DP_IRQ_TYPE_UNKNOWN,
  21 };
  22
  23 struct link_train {
  24         int eq_loop;
  25         int cr_loop[4];
  26
  27         u8 link_rate;
  28         u8 lane_count;
  29         u8 training_lane[4];
  30
  31         enum link_training_state lt_state;
  32 };
  33
  34 struct exynos_dp_device {
  35         struct device           *dev;
  36         struct clk              *clock;
  37         unsigned int            irq;
  38         void __iomem            *reg_base;
  39         void __iomem            *phy_addr;
  40         unsigned int            enable_mask;
  41
  42         struct video_info       *video_info;
  43         struct link_train       link_train;
  44         struct work_struct      hotplug_work;
  45 };
  46
  47 /* exynos_dp_reg.c */
  48 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
  49 void exynos_dp_stop_video(struct exynos_dp_device *dp);
  50 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
  51 void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
  52 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
  53 void exynos_dp_reset(struct exynos_dp_device *dp);
  54 void exynos_dp_swreset(struct exynos_dp_device *dp);
  55 void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
  56 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
  57 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
  58 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
  59                                 enum analog_power_block block,
  60                                 bool enable);
  61 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
  62 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
  63 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
  64 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
  65 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
  66 void exynos_dp_init_aux(struct exynos_dp_device *dp);
  67 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
  68 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
  69 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
  70 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
  71                                 unsigned int reg_addr,
  72                                 unsigned char data);
  73 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
  74                                 unsigned int reg_addr,
  75                                 unsigned char *data);
  76 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
  77                                 unsigned int reg_addr,
  78                                 unsigned int count,
  79                                 unsigned char data[]);
  80 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
  81                                 unsigned int reg_addr,
  82                                 unsigned int count,
  83                                 unsigned char data[]);
  84 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
  85                                 unsigned int device_addr,
  86                                 unsigned int reg_addr);
  87 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
  88                                 unsigned int device_addr,
  89                                 unsigned int reg_addr,
  90                                 unsigned int *data);
  91 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
  92                                 unsigned int device_addr,
  93                                 unsigned int reg_addr,
  94                                 unsigned int count,
  95                                 unsigned char edid[]);
  96 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
  97 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
  98 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
  99 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
 100 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
 101 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 102                                  enum pattern_set pattern);
 103 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 104 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 105 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 106 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 107 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 108                                 u32 training_lane);
 109 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 110                                 u32 training_lane);
 111 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 112                                 u32 training_lane);
 113 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 114                                 u32 training_lane);
 115 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
 116 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
 117 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
 118 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
 119 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
 120 void exynos_dp_init_video(struct exynos_dp_device *dp);
 121
 122 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
 123                                 u32 color_depth,
 124                                 u32 color_space,
 125                                 u32 dynamic_range,
 126                                 u32 ycbcr_coeff);
 127 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
 128 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
 129                         enum clock_recovery_m_value_type type,
 130                         u32 m_value,
 131                         u32 n_value);
 132 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
 133 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
 134 void exynos_dp_start_video(struct exynos_dp_device *dp);
 135 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
 136 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
 137                         struct video_info *video_info);
 138 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
 139 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
 140
 141 /* I2C EDID Chip ID, Slave Address */
 142 #define I2C_EDID_DEVICE_ADDR                    0x50
 143 #define I2C_E_EDID_DEVICE_ADDR                  0x30
 144
 145 #define EDID_BLOCK_LENGTH                       0x80
 146 #define EDID_HEADER_PATTERN                     0x00
 147 #define EDID_EXTENSION_FLAG                     0x7e
 148 #define EDID_CHECKSUM                           0x7f
 149
 150 /* Definition for DPCD Register */
 151 #define DPCD_ADDR_DPCD_REV                      0x0000
 152 #define DPCD_ADDR_MAX_LINK_RATE                 0x0001
 153 #define DPCD_ADDR_MAX_LANE_COUNT                0x0002
 154 #define DPCD_ADDR_LINK_BW_SET                   0x0100
 155 #define DPCD_ADDR_LANE_COUNT_SET                0x0101
 156 #define DPCD_ADDR_TRAINING_PATTERN_SET          0x0102
 157 #define DPCD_ADDR_TRAINING_LANE0_SET            0x0103
 158 #define DPCD_ADDR_LANE0_1_STATUS                0x0202
 159 #define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED     0x0204
 160 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1        0x0206
 161 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3        0x0207
 162 #define DPCD_ADDR_TEST_REQUEST                  0x0218
 163 #define DPCD_ADDR_TEST_RESPONSE                 0x0260
 164 #define DPCD_ADDR_TEST_EDID_CHECKSUM            0x0261
 165 #define DPCD_ADDR_SINK_POWER_STATE              0x0600
 166
 167 /* DPCD_ADDR_MAX_LANE_COUNT */
 168 #define DPCD_ENHANCED_FRAME_CAP(x)              (((x) >> 7) & 0x1)
 169 #define DPCD_MAX_LANE_COUNT(x)                  ((x) & 0x1f)
 170
 171 /* DPCD_ADDR_LANE_COUNT_SET */
 172 #define DPCD_ENHANCED_FRAME_EN                  (0x1 << 7)
 173 #define DPCD_LANE_COUNT_SET(x)                  ((x) & 0x1f)
 174
 175 /* DPCD_ADDR_TRAINING_PATTERN_SET */
 176 #define DPCD_SCRAMBLING_DISABLED                (0x1 << 5)
 177 #define DPCD_SCRAMBLING_ENABLED                 (0x0 << 5)
 178 #define DPCD_TRAINING_PATTERN_2                 (0x2 << 0)
 179 #define DPCD_TRAINING_PATTERN_1                 (0x1 << 0)
 180 #define DPCD_TRAINING_PATTERN_DISABLED          (0x0 << 0)
 181
 182 /* DPCD_ADDR_TRAINING_LANE0_SET */
 183 #define DPCD_MAX_PRE_EMPHASIS_REACHED           (0x1 << 5)
 184 #define DPCD_PRE_EMPHASIS_SET(x)                (((x) & 0x3) << 3)
 185 #define DPCD_PRE_EMPHASIS_GET(x)                (((x) >> 3) & 0x3)
 186 #define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0       (0x0 << 3)
 187 #define DPCD_MAX_SWING_REACHED                  (0x1 << 2)
 188 #define DPCD_VOLTAGE_SWING_SET(x)               (((x) & 0x3) << 0)
 189 #define DPCD_VOLTAGE_SWING_GET(x)               (((x) >> 0) & 0x3)
 190 #define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0      (0x0 << 0)
 191
 192 /* DPCD_ADDR_LANE0_1_STATUS */
 193 #define DPCD_LANE_SYMBOL_LOCKED                 (0x1 << 2)
 194 #define DPCD_LANE_CHANNEL_EQ_DONE               (0x1 << 1)
 195 #define DPCD_LANE_CR_DONE                       (0x1 << 0)
 196 #define DPCD_CHANNEL_EQ_BITS                    (DPCD_LANE_CR_DONE|     \
 197                                                  DPCD_LANE_CHANNEL_EQ_DONE|\
 198                                                  DPCD_LANE_SYMBOL_LOCKED)
 199
 200 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
 201 #define DPCD_LINK_STATUS_UPDATED                (0x1 << 7)
 202 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED     (0x1 << 6)
 203 #define DPCD_INTERLANE_ALIGN_DONE               (0x1 << 0)
 204
 205 /* DPCD_ADDR_TEST_REQUEST */
 206 #define DPCD_TEST_EDID_READ                     (0x1 << 2)
 207
 208 /* DPCD_ADDR_TEST_RESPONSE */
 209 #define DPCD_TEST_EDID_CHECKSUM_WRITE           (0x1 << 2)
 210
 211 /* DPCD_ADDR_SINK_POWER_STATE */
 212 #define DPCD_SET_POWER_STATE_D0                 (0x1 << 0)
 213 #define DPCD_SET_POWER_STATE_D4                 (0x2 << 0)
 214
 215 #endif /* _EXYNOS_DP_CORE_H */