1 /* linux/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
3 * Samsung SoC MIPI-DSI lowlevel driver.
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd
7 * InKi Dae, <inki.dae@samsung.com>
8 * Donghwa Lee, <dh09.lee@samsung.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/mutex.h>
19 #include <linux/wait.h>
20 #include <linux/delay.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
27 #include <video/exynos_mipi_dsim.h>
29 #include "exynos_mipi_dsi_regs.h"
31 void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
35 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
39 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
42 void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
46 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
50 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
53 void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim)
57 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
59 reg |= INTSRC_SW_RST_RELEASE;
61 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
64 int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim)
66 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &
67 INTSRC_SW_RST_RELEASE;
70 unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim)
74 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
79 void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
80 unsigned int mode, unsigned int mask)
89 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
92 void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
97 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
99 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
103 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
107 * this function set PLL P, M and S value in D-PHY
109 void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
112 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
115 void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
120 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
122 reg &= ~DSIM_MAIN_STAND_BY;
125 reg |= DSIM_MAIN_STAND_BY;
127 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
130 void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
131 unsigned int width_resol, unsigned int height_resol)
135 /* standby should be set after configuration so set to not ready*/
136 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
137 ~(DSIM_MAIN_STAND_BY);
138 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
140 reg &= ~((0x7ff << 16) | (0x7ff << 0));
141 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
143 reg |= DSIM_MAIN_STAND_BY;
144 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
147 void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
148 unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
152 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
153 ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
154 (DSIM_MAIN_VBP_MASK));
156 reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) |
157 DSIM_STABLE_VFP_SHIFT(vfront & 0x7ff) |
158 DSIM_MAIN_VBP_SHIFT(vback & 0x7ff));
160 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
163 void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
164 unsigned int front, unsigned int back)
168 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &
169 ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
171 reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back);
173 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
176 void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
177 unsigned int vert, unsigned int hori)
181 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &
182 ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
184 reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) |
185 DSIM_MAIN_HSA_SHIFT(hori));
187 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
190 void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
191 unsigned int vert, unsigned int hori)
195 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &
196 ~(DSIM_SUB_STANDY_MASK);
198 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
200 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
201 reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) |
202 DSIM_SUB_HRESOL_SHIFT(hori & 0x7ff));
203 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
205 reg |= DSIM_SUB_STANDY_SHIFT(1);
206 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
209 void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
211 struct mipi_dsim_config *dsim_config = dsim->dsim_config;
213 unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
214 ~((1 << 28) | (0x1f << 20) | (0x3 << 5));
216 cfg = ((DSIM_AUTO_FLUSH(dsim_config->auto_flush)) |
217 (DSIM_EOT_DISABLE(dsim_config->eot_disable)) |
218 (DSIM_AUTO_MODE_SHIFT(dsim_config->auto_vertical_cnt)) |
219 (DSIM_HSE_MODE_SHIFT(dsim_config->hse)) |
220 (DSIM_HFP_MODE_SHIFT(dsim_config->hfp)) |
221 (DSIM_HBP_MODE_SHIFT(dsim_config->hbp)) |
222 (DSIM_HSA_MODE_SHIFT(dsim_config->hsa)) |
223 (DSIM_NUM_OF_DATALANE_SHIFT(dsim_config->e_no_data_lane)));
225 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
228 void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
229 struct mipi_dsim_config *dsim_config)
231 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
232 ~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) |
233 (0x3 << 16) | (0x7 << 8));
235 if (dsim_config->e_interface == DSIM_VIDEO)
237 else if (dsim_config->e_interface == DSIM_COMMAND)
240 dev_err(dsim->dev, "unknown lcd type.\n");
245 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |
246 ((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 |
247 ((u8) (dsim_config->e_pixel_format) & 0x7) << 12;
249 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
252 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
257 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);
260 reg |= DSIM_LANE_ENx(lane);
262 reg &= ~DSIM_LANE_ENx(lane);
264 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
268 void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
273 /* get the data lane number. */
274 cfg = DSIM_NUM_OF_DATALANE_SHIFT(count);
276 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
279 void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
280 unsigned int afc_code)
282 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
287 reg |= (afc_code & 0x7) << 5;
291 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
294 void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
297 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
298 ~(DSIM_PLL_BYPASS_SHIFT(0x1));
300 reg |= DSIM_PLL_BYPASS_SHIFT(enable);
302 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
305 void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
306 unsigned int m, unsigned int s)
308 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
310 reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
312 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
315 void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
316 unsigned int freq_band)
318 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
319 ~(DSIM_FREQ_BAND_SHIFT(0x1f));
321 reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f);
323 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
326 void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
327 unsigned int pre_divider, unsigned int main_divider,
330 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
333 reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
336 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
339 void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
340 unsigned int lock_time)
342 writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);
345 void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable)
347 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
348 ~(DSIM_PLL_EN_SHIFT(0x1));
350 reg |= DSIM_PLL_EN_SHIFT(enable & 0x1);
352 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
355 void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
358 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
359 ~(DSIM_BYTE_CLK_SRC_SHIFT(0x3));
361 reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src));
363 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
366 void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
369 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
370 ~(DSIM_BYTE_CLKEN_SHIFT(0x1));
372 reg |= DSIM_BYTE_CLKEN_SHIFT(enable);
374 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
377 void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
378 unsigned int enable, unsigned int prs_val)
380 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
381 ~(DSIM_ESC_CLKEN_SHIFT(0x1) | 0xffff);
383 reg |= DSIM_ESC_CLKEN_SHIFT(enable);
387 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
390 void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
391 unsigned int lane_sel, unsigned int enable)
393 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
396 reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
399 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
401 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
404 void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
407 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
408 ~(DSIM_FORCE_STOP_STATE_SHIFT(0x1));
410 reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1));
412 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
415 unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
417 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
420 * check clock and data lane states.
421 * if MIPI-DSI controller was enabled at bootloader then
422 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
423 * so it should be checked for two case.
425 if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
426 ((reg & DSIM_STOP_STATE_CLK) ||
427 (reg & DSIM_TX_READY_HS_CLK)))
433 void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
434 unsigned int cnt_val)
436 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
437 ~(DSIM_STOP_STATE_CNT_SHIFT(0x7ff));
439 reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff));
441 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
444 void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
445 unsigned int timeout)
447 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
448 ~(DSIM_BTA_TOUT_SHIFT(0xff));
450 reg |= (DSIM_BTA_TOUT_SHIFT(timeout));
452 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
455 void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
456 unsigned int timeout)
458 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
459 ~(DSIM_LPDR_TOUT_SHIFT(0xffff));
461 reg |= (DSIM_LPDR_TOUT_SHIFT(timeout));
463 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
466 void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
469 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
471 reg &= ~DSIM_CMD_LPDT_LP;
474 reg |= DSIM_CMD_LPDT_LP;
476 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
479 void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
482 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
484 reg &= ~DSIM_TX_LPDT_LP;
487 reg |= DSIM_TX_LPDT_LP;
489 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
492 void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
495 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
496 ~(DSIM_TX_REQUEST_HSCLK_SHIFT(0x1));
498 reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable);
500 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
503 void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
504 unsigned int swap_en)
506 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
509 reg |= (swap_en & 0x3) << 0;
511 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
514 void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
515 unsigned int hs_zero)
517 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
520 reg |= ((hs_zero & 0xf) << 28);
522 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
525 void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
527 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
530 reg |= ((prep & 0x7) << 20);
532 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
535 unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim)
537 return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
540 void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim,
543 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
547 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
550 void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim,
551 unsigned int src, unsigned int enable)
553 unsigned int reg = 0;
560 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
563 unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
567 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
569 return reg & (1 << 31) ? 1 : 0;
572 unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
574 return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f);
577 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
578 unsigned int di, unsigned int data0, unsigned int data1)
580 unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
582 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
585 void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim,
586 unsigned int di, unsigned int data0)
588 unsigned int reg = (data0 << 8) | (di << 0);
590 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
593 unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim)
595 return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO);
598 unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
600 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
602 return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
605 void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
607 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
609 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
613 void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
614 unsigned int tx_data)
616 writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);