5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/types.h>
18 #include <linux/err.h>
20 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/clock.h>
27 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
29 struct ipu_ch_param_word {
35 struct ipu_ch_param_word word[2];
38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
40 #define _param_word(base, w) \
41 (((struct ipu_ch_param *)(base))->word[w].data)
43 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
45 int off = (bit) % 32; \
46 _param_word(base, w)[i] |= (v) << off; \
47 if (((bit) + (size) - 1) / 32 > i) { \
48 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
52 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
54 int off = (bit) % 32; \
55 u32 mask = (1UL << size) - 1; \
56 u32 temp = _param_word(base, w)[i]; \
57 temp &= ~(mask << off); \
58 _param_word(base, w)[i] = temp | (v) << off; \
59 if (((bit) + (size) - 1) / 32 > i) { \
60 temp = _param_word(base, w)[i + 1]; \
61 temp &= ~(mask >> (32 - off)); \
62 _param_word(base, w)[i + 1] = \
63 temp | ((v) >> (off ? (32 - off) : 0)); \
67 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
70 int off = (bit) % 32; \
71 u32 mask = (1UL << size) - 1; \
72 u32 temp1 = _param_word(base, w)[i]; \
73 temp1 = mask & (temp1 >> off); \
74 if (((bit)+(size) - 1) / 32 > i) { \
75 temp2 = _param_word(base, w)[i + 1]; \
76 temp2 &= mask >> (off ? (32 - off) : 0); \
77 temp1 |= temp2 << (off ? (32 - off) : 0); \
82 #define IPU_SW_RST_TOUT_USEC 10000
84 static int clk_ipu_enable(struct clk *clk)
90 static void clk_ipu_disable(struct clk *clk)
95 static struct clk ipu_clk = {
97 .rate = CONFIG_IPUV3_CLK,
98 .enable = clk_ipu_enable,
99 .disable = clk_ipu_disable,
102 static int clk_ldb_enable(struct clk *clk)
109 static void clk_ldb_disable(struct clk *clk)
115 #if !defined CONFIG_SYS_LDB_CLOCK
116 #define CONFIG_SYS_LDB_CLOCK 65000000
119 static struct clk ldb_clk = {
121 .rate = CONFIG_SYS_LDB_CLOCK,
122 .enable = clk_ldb_enable,
123 .disable = clk_ldb_disable,
127 struct clk *g_ipu_clk;
128 struct clk *g_ldb_clk;
129 struct clk *g_di_clk[2];
130 struct clk *g_pixel_clk[2];
131 unsigned char g_dc_di_assignment[10];
132 int g_ipu_clk_enabled;
133 u32 *ipu_dc_tmpl_reg;
135 static uint32_t g_channel_init_mask;
136 static uint32_t g_channel_enable_mask;
137 static int ipu_dc_use_count;
138 static int ipu_dp_use_count;
139 static int ipu_dmfc_use_count;
140 static int ipu_di_use_count[2];
142 static u32 *ipu_cpmem_base;
144 /* Static functions */
146 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
148 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
151 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
153 return ((uint32_t) ch >> (6 * type)) & 0x3F;
156 /* Either DP BG or DP FG can be graphic window */
157 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
159 return (dma_chan == 23 || dma_chan == 27);
162 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
164 return ((dma_chan >= 23) && (dma_chan <= 29));
168 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
171 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
175 #define idma_is_valid(ch) (ch != NO_DMA)
176 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
177 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
179 static void ipu_pixel_clk_recalc(struct clk *clk)
181 u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
185 clk->rate = (clk->parent->rate * 16) / div;
188 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
195 * Fractional part is 4 bits,
196 * so simply multiply by 2^4 to get fractional part.
198 tmp = (u64)clk->parent->rate * 16;
201 if (div < 0x10) /* Min DI disp clock divider is 1 */
207 if ((tmp/div1 - tmp/div) < rate / 4)
214 debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
215 rate / 1000000, rate / 1000 % 1000,
216 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
217 tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
222 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
224 u32 div = ((u64)clk->parent->rate * 16) / rate;
226 debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
227 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
228 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
230 __raw_writel(div, DI_BS_CLKGEN0(clk->id));
232 /* Setup pixel clock timing */
233 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
235 clk->rate = ((u64)clk->parent->rate * 16) / div;
236 debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
237 clk->rate / 1000000, clk->rate / 1000 % 1000);
241 static int ipu_pixel_clk_enable(struct clk *clk)
243 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
244 disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
245 __raw_writel(disp_gen, IPU_DISP_GEN);
250 static void ipu_pixel_clk_disable(struct clk *clk)
252 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
253 disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
254 __raw_writel(disp_gen, IPU_DISP_GEN);
257 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
262 ret = clk_enable(clk);
266 di_gen = __raw_readl(DI_GENERAL(clk->id));
268 if (parent == g_ipu_clk)
269 di_gen &= ~DI_GEN_DI_CLK_EXT;
270 else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
271 di_gen |= DI_GEN_DI_CLK_EXT;
275 ret = clk_enable(parent);
278 __raw_writel(di_gen, DI_GENERAL(clk->id));
279 ipu_pixel_clk_recalc(clk);
280 clk->disable(clk->parent);
281 clk->parent = parent;
287 static struct clk pixel_clk[] = {
291 .recalc = ipu_pixel_clk_recalc,
292 .set_rate = ipu_pixel_clk_set_rate,
293 .round_rate = ipu_pixel_clk_round_rate,
294 .set_parent = ipu_pixel_clk_set_parent,
295 .enable = ipu_pixel_clk_enable,
296 .disable = ipu_pixel_clk_disable,
301 .recalc = ipu_pixel_clk_recalc,
302 .set_rate = ipu_pixel_clk_set_rate,
303 .round_rate = ipu_pixel_clk_round_rate,
304 .set_parent = ipu_pixel_clk_set_parent,
305 .enable = ipu_pixel_clk_enable,
306 .disable = ipu_pixel_clk_disable,
310 static int clk_ipu_di_enable(struct clk *clk)
312 ipu_di_clk_enable(clk->id);
316 static void clk_ipu_di_disable(struct clk *clk)
318 ipu_di_clk_disable(clk->id);
321 static struct clk di_clk[] = {
323 .name = "ipu_di_clk",
325 .enable = clk_ipu_di_enable,
326 .disable = clk_ipu_di_disable,
329 .name = "ipu_di_clk",
331 .enable = clk_ipu_di_enable,
332 .disable = clk_ipu_di_disable,
337 * This function resets IPU
339 static void ipu_reset(void)
343 int timeout = IPU_SW_RST_TOUT_USEC;
345 reg = (u32 *)SRC_BASE_ADDR;
346 value = __raw_readl(reg);
347 value = value | SW_IPU_RST;
348 __raw_writel(value, reg);
350 while (__raw_readl(reg) & SW_IPU_RST) {
353 printf("ipu software reset timeout\n");
360 * This function is called by the driver framework to initialize the IPU
363 * @param dev The device structure for the IPU passed in by the
366 * @return Returns 0 on success or negative error code on error
368 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
373 #if defined CONFIG_SOC_MX51
375 u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
376 u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
378 __raw_writel(0xF00, reg_hsc_mcd);
380 /* CSI mode reserved */
381 temp = __raw_readl(reg_hsc_mxt_conf);
382 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
384 temp = __raw_readl(reg_hsc_mxt_conf);
385 __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
387 ipu_base = (void *)IPU_SOC_BASE_ADDR;
389 if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
390 ipu_base += IPUV3H_REG_BASE;
391 else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M) /* IPUv3M */
392 ipu_base += IPUV3M_REG_BASE;
393 else /* IPUv3D, v3E, v3EX */
394 ipu_base += IPUV3DEX_REG_BASE;
395 ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
396 ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
398 printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
400 g_pixel_clk[0] = &pixel_clk[0];
401 g_pixel_clk[1] = &pixel_clk[1];
403 g_di_clk[0] = &di_clk[0];
404 g_di_clk[1] = &di_clk[1];
405 g_di_clk[di]->rate = di_clk_val;
407 g_ipu_clk = &ipu_clk;
408 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
410 g_ldb_clk = &ldb_clk;
411 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
413 ret = clk_enable(g_ipu_clk);
418 if (di_clk_parent == DI_PCLK_LDB) {
419 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
421 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
422 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
425 __raw_writel(0x807FFFFF, IPU_MEM_RST);
426 start = get_timer_masked();
427 while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
428 if (get_timer(start) > CONFIG_SYS_HZ)
432 ipu_init_dc_mappings();
434 __raw_writel(0, IPU_INT_CTRL(5));
435 __raw_writel(0, IPU_INT_CTRL(6));
436 __raw_writel(0, IPU_INT_CTRL(9));
437 __raw_writel(0, IPU_INT_CTRL(10));
440 ipu_dmfc_init(DMFC_NORMAL, 1);
442 /* Set sync refresh channels as high priority */
443 __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
445 /* Set MCU_T to divide MCU access window into 2 */
446 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
448 clk_disable(g_ipu_clk);
453 void ipu_dump_registers(void)
455 debug("IPU_CONF 0x%08X\n", __raw_readl(IPU_CONF));
456 debug("IDMAC_CONF 0x%08X\n", __raw_readl(IDMAC_CONF));
457 debug("IDMAC_CHA_EN1 0x%08X\n",
458 __raw_readl(IDMAC_CHA_EN(0)));
459 debug("IDMAC_CHA_EN2 0x%08X\n",
460 __raw_readl(IDMAC_CHA_EN(32)));
461 debug("IDMAC_CHA_PRI1 0x%08X\n",
462 __raw_readl(IDMAC_CHA_PRI(0)));
463 debug("IDMAC_CHA_PRI2 0x%08X\n",
464 __raw_readl(IDMAC_CHA_PRI(32)));
465 debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
466 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
467 debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
468 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
469 debug("DMFC_WR_CHAN 0x%08X\n",
470 __raw_readl(DMFC_WR_CHAN));
471 debug("DMFC_WR_CHAN_DEF 0x%08X\n",
472 __raw_readl(DMFC_WR_CHAN_DEF));
473 debug("DMFC_DP_CHAN 0x%08X\n",
474 __raw_readl(DMFC_DP_CHAN));
475 debug("DMFC_DP_CHAN_DEF 0x%08X\n",
476 __raw_readl(DMFC_DP_CHAN_DEF));
477 debug("DMFC_IC_CTRL 0x%08X\n",
478 __raw_readl(DMFC_IC_CTRL));
479 debug("IPU_FS_PROC_FLOW1 0x%08X\n",
480 __raw_readl(IPU_FS_PROC_FLOW1));
481 debug("IPU_FS_PROC_FLOW2 0x%08X\n",
482 __raw_readl(IPU_FS_PROC_FLOW2));
483 debug("IPU_FS_PROC_FLOW3 0x%08X\n",
484 __raw_readl(IPU_FS_PROC_FLOW3));
485 debug("IPU_FS_DISP_FLOW1 0x%08X\n",
486 __raw_readl(IPU_FS_DISP_FLOW1));
490 * This function is called to initialize a logical IPU channel.
492 * @param channel Input parameter for the logical channel ID to init.
494 * @param params Input parameter containing union of channel
495 * initialization parameters.
497 * @return Returns 0 on success or negative error code on fail
499 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
504 debug("init channel = %d\n", IPU_CHAN_ID(channel));
506 if (g_ipu_clk_enabled == 0) {
507 g_ipu_clk_enabled = 1;
508 clk_enable(g_ipu_clk);
512 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
513 printf("Warning: channel already initialized %d\n",
514 IPU_CHAN_ID(channel));
517 ipu_conf = __raw_readl(IPU_CONF);
521 if (params->mem_dc_sync.di > 1) {
526 g_dc_di_assignment[1] = params->mem_dc_sync.di;
527 ipu_dc_init(1, params->mem_dc_sync.di,
528 params->mem_dc_sync.interlaced);
529 ipu_di_use_count[params->mem_dc_sync.di]++;
531 ipu_dmfc_use_count++;
534 if (params->mem_dp_bg_sync.di > 1) {
539 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
540 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
541 params->mem_dp_bg_sync.out_pixel_fmt);
542 ipu_dc_init(5, params->mem_dp_bg_sync.di,
543 params->mem_dp_bg_sync.interlaced);
544 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
547 ipu_dmfc_use_count++;
550 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
551 params->mem_dp_fg_sync.out_pixel_fmt);
555 ipu_dmfc_use_count++;
558 printf("Missing channel initialization\n");
561 /* Enable IPU sub module */
562 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
563 if (ipu_dc_use_count == 1)
564 ipu_conf |= IPU_CONF_DC_EN;
565 if (ipu_dp_use_count == 1)
566 ipu_conf |= IPU_CONF_DP_EN;
567 if (ipu_dmfc_use_count == 1)
568 ipu_conf |= IPU_CONF_DMFC_EN;
569 if (ipu_di_use_count[0] == 1) {
570 ipu_conf |= IPU_CONF_DI0_EN;
571 clk_enable(g_di_clk[0]);
573 if (ipu_di_use_count[1] == 1) {
574 ipu_conf |= IPU_CONF_DI1_EN;
575 clk_enable(g_di_clk[1]);
578 __raw_writel(ipu_conf, IPU_CONF);
585 * This function is called to uninitialize a logical IPU channel.
587 * @param channel Input parameter for the logical channel ID to uninit.
589 void ipu_uninit_channel(ipu_channel_t channel)
592 uint32_t in_dma, out_dma = 0;
595 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
596 debug("Channel already uninitialized %d\n",
597 IPU_CHAN_ID(channel));
602 * Make sure channel is disabled
603 * Get input and output dma channels
605 in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
606 out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
608 if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
609 idma_is_set(IDMAC_CHA_EN, out_dma)) {
610 printf("Channel %d is not disabled, disable first\n",
611 IPU_CHAN_ID(channel));
615 ipu_conf = __raw_readl(IPU_CONF);
617 /* Reset the double buffer */
618 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
619 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
620 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
621 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
626 ipu_di_use_count[g_dc_di_assignment[1]]--;
628 ipu_dmfc_use_count--;
631 ipu_dp_uninit(channel);
633 ipu_di_use_count[g_dc_di_assignment[5]]--;
636 ipu_dmfc_use_count--;
639 ipu_dp_uninit(channel);
642 ipu_dmfc_use_count--;
648 g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
650 if (ipu_dc_use_count == 0)
651 ipu_conf &= ~IPU_CONF_DC_EN;
652 if (ipu_dp_use_count == 0)
653 ipu_conf &= ~IPU_CONF_DP_EN;
654 if (ipu_dmfc_use_count == 0)
655 ipu_conf &= ~IPU_CONF_DMFC_EN;
656 if (ipu_di_use_count[0] == 0 && ipu_conf & IPU_CONF_DI0_EN) {
657 ipu_conf &= ~IPU_CONF_DI0_EN;
658 clk_disable(g_di_clk[0]);
660 if (ipu_di_use_count[1] == 0 && ipu_conf & IPU_CONF_DI1_EN) {
661 ipu_conf &= ~IPU_CONF_DI1_EN;
662 clk_disable(g_di_clk[1]);
665 __raw_writel(ipu_conf, IPU_CONF);
667 /* clear interrupt status */
668 __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
671 clk_disable(g_ipu_clk);
672 g_ipu_clk_enabled = 0;
676 static inline void ipu_ch_param_dump(int ch)
679 struct ipu_ch_param *p = ipu_ch_param_addr(ch);
680 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
681 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
682 p->word[0].data[3], p->word[0].data[4]);
683 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
684 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
685 p->word[1].data[3], p->word[1].data[4]);
687 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
689 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
691 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
694 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
696 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
698 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
700 debug("Width0 %d+1, ",
701 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
702 debug("Width1 %d+1, ",
703 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
704 debug("Width2 %d+1, ",
705 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
706 debug("Width3 %d+1, ",
707 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
708 debug("Offset0 %d, ",
709 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
710 debug("Offset1 %d, ",
711 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
712 debug("Offset2 %d, ",
713 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
714 debug("Offset3 %d\n",
715 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
719 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
720 int red_width, int red_offset,
721 int green_width, int green_offset,
722 int blue_width, int blue_offset,
723 int alpha_width, int alpha_offset)
725 /* Setup red width and offset */
726 ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
727 ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
728 /* Setup green width and offset */
729 ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
730 ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
731 /* Setup blue width and offset */
732 ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
733 ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
734 /* Setup alpha width and offset */
735 ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
736 ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
739 static void ipu_ch_param_init(int ch,
740 uint32_t pixel_fmt, uint32_t width,
741 uint32_t height, uint32_t stride,
742 uint32_t u, uint32_t v,
743 uint32_t uv_stride, dma_addr_t addr0,
746 uint32_t u_offset = 0;
747 uint32_t v_offset = 0;
749 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
751 if ((ch == 8) || (ch == 9) || (ch == 10)) {
752 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
753 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
755 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
756 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
759 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
760 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
763 case IPU_PIX_FMT_GENERIC:
764 /*Represents 8-bit Generic data */
765 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5); /* bits/pixel */
766 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6); /* pix format */
767 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63); /* burst size */
770 case IPU_PIX_FMT_GENERIC_32:
771 /*Represents 32-bit Generic data */
773 case IPU_PIX_FMT_RGB565:
774 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
775 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
776 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
778 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
780 case IPU_PIX_FMT_BGR24:
781 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */
782 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
783 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */
785 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
787 case IPU_PIX_FMT_RGB24:
788 case IPU_PIX_FMT_YUV444:
789 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */
790 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
791 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */
793 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
795 case IPU_PIX_FMT_BGRA32:
796 case IPU_PIX_FMT_BGR32:
797 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
798 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
799 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
801 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
803 case IPU_PIX_FMT_RGBA32:
804 case IPU_PIX_FMT_RGB32:
805 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
806 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
807 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
809 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
811 case IPU_PIX_FMT_ABGR32:
812 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
813 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
815 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
817 case IPU_PIX_FMT_UYVY:
818 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
819 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA); /* pix format */
820 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
822 case IPU_PIX_FMT_YUYV:
823 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
824 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8); /* pix format */
825 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
827 case IPU_PIX_FMT_YUV420P2:
828 case IPU_PIX_FMT_YUV420P:
829 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2); /* pix format */
831 if (uv_stride < stride / 2)
832 uv_stride = stride / 2;
834 u_offset = stride * height;
835 v_offset = u_offset + (uv_stride * height / 2);
837 if ((ch == 8) || (ch == 9) || (ch == 10)) {
838 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
839 uv_stride = uv_stride*2;
841 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
844 case IPU_PIX_FMT_YVU422P:
845 /* BPP & pixel format */
846 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */
847 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
849 if (uv_stride < stride / 2)
850 uv_stride = stride / 2;
852 v_offset = (v == 0) ? stride * height : v;
853 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
855 case IPU_PIX_FMT_YUV422P:
856 /* BPP & pixel format */
857 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */
858 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
860 if (uv_stride < stride / 2)
861 uv_stride = stride / 2;
863 u_offset = (u == 0) ? stride * height : u;
864 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
866 case IPU_PIX_FMT_NV12:
867 /* BPP & pixel format */
868 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4); /* pix format */
869 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
871 u_offset = (u == 0) ? stride * height : u;
874 printf("mxc ipu: unimplemented pixel format: %08x\n",
880 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
882 /* Get the uv offset from user when need cropping */
888 /* UBO and VBO are 22-bit */
889 if (u_offset/8 > 0x3fffff)
890 puts("The value of U offset exceeds IPU limitation\n");
891 if (v_offset/8 > 0x3fffff)
892 puts("The value of V offset exceeds IPU limitation\n");
894 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
895 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
897 debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
901 * This function is called to initialize a buffer for logical IPU channel.
903 * @param channel Input parameter for the logical channel ID.
905 * @param type Input parameter which buffer to initialize.
907 * @param pixel_fmt Input parameter for pixel format of buffer.
908 * Pixel format is a FOURCC ASCII code.
910 * @param width Input parameter for width of buffer in pixels.
912 * @param height Input parameter for height of buffer in pixels.
914 * @param stride Input parameter for stride length of buffer
917 * @param phyaddr_0 Input parameter buffer 0 physical address.
919 * @param phyaddr_1 Input parameter buffer 1 physical address.
920 * Setting this to a value other than NULL enables
921 * double buffering mode.
923 * @param u private u offset for additional cropping,
926 * @param v private v offset for additional cropping,
929 * @return Returns 0 on success or negative error code on fail
931 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
933 uint16_t width, uint16_t height,
935 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
936 uint32_t u, uint32_t v)
941 dma_chan = channel_2_dma(channel, type);
942 if (!idma_is_valid(dma_chan))
945 if (stride < width * bytes_per_pixel(pixel_fmt))
946 stride = width * bytes_per_pixel(pixel_fmt);
949 printf("Stride %d not 32-bit aligned\n", stride);
952 /* Build parameter memory data for DMA channel */
953 ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
954 phyaddr_0, phyaddr_1);
956 if (ipu_is_dmfc_chan(dma_chan)) {
957 ipu_dmfc_set_wait4eot(dma_chan, width);
960 if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
961 ipu_ch_param_set_high_priority(dma_chan);
963 ipu_ch_param_dump(dma_chan);
965 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
967 reg |= idma_mask(dma_chan);
969 reg &= ~idma_mask(dma_chan);
970 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
972 /* Reset to buffer 0 */
973 __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
979 * This function enables a logical channel.
981 * @param channel Input parameter for the logical channel ID.
983 * @return This function returns 0 on success or negative error code on
986 int32_t ipu_enable_channel(ipu_channel_t channel)
992 if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
993 printf("Warning: channel already enabled %d\n",
994 IPU_CHAN_ID(channel));
997 /* Get input and output dma channels */
998 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
999 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1001 if (idma_is_valid(in_dma)) {
1002 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1003 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1005 if (idma_is_valid(out_dma)) {
1006 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1007 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1010 if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1011 (channel == MEM_FG_SYNC)) {
1012 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1013 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1015 ipu_dp_dc_enable(channel);
1018 g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1024 * This function clear buffer ready for a logical channel.
1026 * @param channel Input parameter for the logical channel ID.
1028 * @param type Input parameter which buffer to clear.
1030 * @param bufNum Input parameter for which buffer number clear
1034 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1037 uint32_t dma_ch = channel_2_dma(channel, type);
1039 if (!idma_is_valid(dma_ch))
1042 __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1044 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1045 __raw_writel(idma_mask(dma_ch),
1046 IPU_CHA_BUF0_RDY(dma_ch));
1049 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1050 __raw_writel(idma_mask(dma_ch),
1051 IPU_CHA_BUF1_RDY(dma_ch));
1054 __raw_writel(0x0, IPU_GPR); /* write one to set */
1058 * This function disables a logical channel.
1060 * @param channel Input parameter for the logical channel ID.
1062 * @param wait_for_stop Flag to set whether to wait for channel end
1063 * of frame or return immediately.
1065 * @return This function returns 0 on success or negative error code on
1068 int32_t ipu_disable_channel(ipu_channel_t channel)
1074 if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1075 debug("Channel already disabled %d\n",
1076 IPU_CHAN_ID(channel));
1080 /* Get input and output dma channels */
1081 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1082 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1084 if ((idma_is_valid(in_dma) &&
1085 !idma_is_set(IDMAC_CHA_EN, in_dma))
1086 && (idma_is_valid(out_dma) &&
1087 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1090 if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1091 (channel == MEM_DC_SYNC)) {
1092 ipu_dp_dc_disable(channel, 0);
1095 /* Disable DMA channel(s) */
1096 if (idma_is_valid(in_dma)) {
1097 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1098 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1099 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1101 if (idma_is_valid(out_dma)) {
1102 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1103 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1104 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1107 g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1109 /* Set channel buffers NOT to be ready */
1110 if (idma_is_valid(in_dma)) {
1111 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1112 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1114 if (idma_is_valid(out_dma)) {
1115 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1116 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1122 uint32_t bytes_per_pixel(uint32_t fmt)
1125 case IPU_PIX_FMT_GENERIC: /* generic data */
1126 case IPU_PIX_FMT_RGB332:
1127 case IPU_PIX_FMT_YUV420P:
1128 case IPU_PIX_FMT_YUV422P:
1130 case IPU_PIX_FMT_RGB565:
1131 case IPU_PIX_FMT_YUYV:
1132 case IPU_PIX_FMT_UYVY:
1134 case IPU_PIX_FMT_BGR24:
1135 case IPU_PIX_FMT_RGB24:
1137 case IPU_PIX_FMT_GENERIC_32: /* generic data */
1138 case IPU_PIX_FMT_BGR32:
1139 case IPU_PIX_FMT_BGRA32:
1140 case IPU_PIX_FMT_RGB32:
1141 case IPU_PIX_FMT_RGBA32:
1142 case IPU_PIX_FMT_ABGR32:
1150 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1153 case IPU_PIX_FMT_RGB666:
1154 case IPU_PIX_FMT_RGB565:
1155 case IPU_PIX_FMT_BGR24:
1156 case IPU_PIX_FMT_RGB24:
1157 case IPU_PIX_FMT_BGR32:
1158 case IPU_PIX_FMT_BGRA32:
1159 case IPU_PIX_FMT_RGB32:
1160 case IPU_PIX_FMT_RGBA32:
1161 case IPU_PIX_FMT_ABGR32:
1162 case IPU_PIX_FMT_LVDS666:
1163 case IPU_PIX_FMT_LVDS888:
1172 /* should be removed when clk framework is availiable */
1173 int ipu_set_ldb_clock(int rate)
1175 ldb_clk.rate = rate;