5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/types.h>
18 #include <linux/err.h>
20 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/clock.h>
27 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
29 struct ipu_ch_param_word {
35 struct ipu_ch_param_word word[2];
38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
40 #define _param_word(base, w) \
41 (((struct ipu_ch_param *)(base))->word[w].data)
43 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
45 int off = (bit) % 32; \
46 _param_word(base, w)[i] |= (v) << off; \
47 if (((bit) + (size) - 1) / 32 > i) { \
48 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
52 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
54 int off = (bit) % 32; \
55 u32 mask = (1UL << size) - 1; \
56 u32 temp = _param_word(base, w)[i]; \
57 temp &= ~(mask << off); \
58 _param_word(base, w)[i] = temp | (v) << off; \
59 if (((bit) + (size) - 1) / 32 > i) { \
60 temp = _param_word(base, w)[i + 1]; \
61 temp &= ~(mask >> (32 - off)); \
62 _param_word(base, w)[i + 1] = \
63 temp | ((v) >> (off ? (32 - off) : 0)); \
67 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
70 int off = (bit) % 32; \
71 u32 mask = (1UL << size) - 1; \
72 u32 temp1 = _param_word(base, w)[i]; \
73 temp1 = mask & (temp1 >> off); \
74 if (((bit)+(size) - 1) / 32 > i) { \
75 temp2 = _param_word(base, w)[i + 1]; \
76 temp2 &= mask >> (off ? (32 - off) : 0); \
77 temp1 |= temp2 << (off ? (32 - off) : 0); \
82 #define IPU_SW_RST_TOUT_USEC 10000
84 static int clk_ipu_enable(struct clk *clk)
90 static void clk_ipu_disable(struct clk *clk)
95 static struct clk ipu_clk = {
97 .rate = CONFIG_IPUV3_CLK,
98 .enable = clk_ipu_enable,
99 .disable = clk_ipu_disable,
102 static int clk_ldb_enable(struct clk *clk)
109 static void clk_ldb_disable(struct clk *clk)
115 static struct clk ldb_clk = {
118 .enable = clk_ldb_enable,
119 .disable = clk_ldb_disable,
123 struct clk *g_ipu_clk;
124 struct clk *g_ldb_clk;
125 struct clk *g_di_clk[2];
126 struct clk *g_pixel_clk[2];
127 unsigned char g_dc_di_assignment[10];
128 int g_ipu_clk_enabled;
129 u32 *ipu_dc_tmpl_reg;
131 static uint32_t g_channel_init_mask;
132 static uint32_t g_channel_enable_mask;
133 static int ipu_dc_use_count;
134 static int ipu_dp_use_count;
135 static int ipu_dmfc_use_count;
136 static int ipu_di_use_count[2];
138 static u32 *ipu_cpmem_base;
140 /* Static functions */
142 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
144 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
147 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
149 return ((uint32_t) ch >> (6 * type)) & 0x3F;
152 /* Either DP BG or DP FG can be graphic window */
153 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
155 return (dma_chan == 23 || dma_chan == 27);
158 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
160 return ((dma_chan >= 23) && (dma_chan <= 29));
164 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
167 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
171 #define idma_is_valid(ch) (ch != NO_DMA)
172 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
173 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
175 static void ipu_pixel_clk_recalc(struct clk *clk)
177 u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
181 clk->rate = (clk->parent->rate * 16) / div;
184 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
191 * Fractional part is 4 bits,
192 * so simply multiply by 2^4 to get fractional part.
194 tmp = (u64)clk->parent->rate * 16;
197 if (div < 0x10) /* Min DI disp clock divider is 1 */
203 if ((tmp/div1 - tmp/div) < rate / 4)
210 debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
211 rate / 1000000, rate / 1000 % 1000,
212 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
213 tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
218 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
220 u32 div = ((u64)clk->parent->rate * 16) / rate;
222 debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
223 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
224 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
226 __raw_writel(div, DI_BS_CLKGEN0(clk->id));
228 /* Setup pixel clock timing */
229 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
231 clk->rate = ((u64)clk->parent->rate * 16) / div;
232 debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
233 clk->rate / 1000000, clk->rate / 1000 % 1000);
237 static int ipu_pixel_clk_enable(struct clk *clk)
239 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
240 disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
241 __raw_writel(disp_gen, IPU_DISP_GEN);
246 static void ipu_pixel_clk_disable(struct clk *clk)
248 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
249 disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
250 __raw_writel(disp_gen, IPU_DISP_GEN);
253 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
258 ret = clk_enable(clk);
262 di_gen = __raw_readl(DI_GENERAL(clk->id));
264 if (parent == g_ipu_clk)
265 di_gen &= ~DI_GEN_DI_CLK_EXT;
266 else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
267 di_gen |= DI_GEN_DI_CLK_EXT;
271 ret = clk_enable(parent);
274 __raw_writel(di_gen, DI_GENERAL(clk->id));
275 ipu_pixel_clk_recalc(clk);
276 clk->disable(clk->parent);
277 clk->parent = parent;
283 static struct clk pixel_clk[] = {
287 .recalc = ipu_pixel_clk_recalc,
288 .set_rate = ipu_pixel_clk_set_rate,
289 .round_rate = ipu_pixel_clk_round_rate,
290 .set_parent = ipu_pixel_clk_set_parent,
291 .enable = ipu_pixel_clk_enable,
292 .disable = ipu_pixel_clk_disable,
297 .recalc = ipu_pixel_clk_recalc,
298 .set_rate = ipu_pixel_clk_set_rate,
299 .round_rate = ipu_pixel_clk_round_rate,
300 .set_parent = ipu_pixel_clk_set_parent,
301 .enable = ipu_pixel_clk_enable,
302 .disable = ipu_pixel_clk_disable,
306 static int clk_ipu_di_enable(struct clk *clk)
308 ipu_di_clk_enable(clk->id);
312 static void clk_ipu_di_disable(struct clk *clk)
314 ipu_di_clk_disable(clk->id);
317 static struct clk di_clk[] = {
319 .name = "ipu_di_clk",
321 .enable = clk_ipu_di_enable,
322 .disable = clk_ipu_di_disable,
325 .name = "ipu_di_clk",
327 .enable = clk_ipu_di_enable,
328 .disable = clk_ipu_di_disable,
333 * This function resets IPU
335 static void ipu_reset(void)
339 int timeout = IPU_SW_RST_TOUT_USEC;
341 reg = (u32 *)SRC_BASE_ADDR;
342 value = __raw_readl(reg);
343 value = value | SW_IPU_RST;
344 __raw_writel(value, reg);
346 while (__raw_readl(reg) & SW_IPU_RST) {
349 printf("ipu software reset timeout\n");
356 * This function is called by the driver framework to initialize the IPU
359 * @param dev The device structure for the IPU passed in by the
362 * @return Returns 0 on success or negative error code on error
364 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
369 #if defined CONFIG_SOC_MX51
371 u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
372 u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
374 __raw_writel(0xF00, reg_hsc_mcd);
376 /* CSI mode reserved */
377 temp = __raw_readl(reg_hsc_mxt_conf);
378 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
380 temp = __raw_readl(reg_hsc_mxt_conf);
381 __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
383 ipu_base = (void *)IPU_SOC_BASE_ADDR;
385 if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
386 ipu_base += IPUV3H_REG_BASE;
387 else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M) /* IPUv3M */
388 ipu_base += IPUV3M_REG_BASE;
389 else /* IPUv3D, v3E, v3EX */
390 ipu_base += IPUV3DEX_REG_BASE;
391 ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
392 ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
394 printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
396 g_pixel_clk[0] = &pixel_clk[0];
397 g_pixel_clk[1] = &pixel_clk[1];
399 g_di_clk[0] = &di_clk[0];
400 g_di_clk[1] = &di_clk[1];
401 g_di_clk[di]->rate = di_clk_val;
403 g_ipu_clk = &ipu_clk;
404 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
406 g_ldb_clk = &ldb_clk;
407 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
409 ret = clk_enable(g_ipu_clk);
414 if (di_clk_parent == DI_PCLK_LDB) {
415 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
417 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
418 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
421 __raw_writel(0x807FFFFF, IPU_MEM_RST);
422 start = get_timer_masked();
423 while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
424 if (get_timer(start) > CONFIG_SYS_HZ)
428 ipu_init_dc_mappings();
430 __raw_writel(0, IPU_INT_CTRL(5));
431 __raw_writel(0, IPU_INT_CTRL(6));
432 __raw_writel(0, IPU_INT_CTRL(9));
433 __raw_writel(0, IPU_INT_CTRL(10));
436 ipu_dmfc_init(DMFC_NORMAL, 1);
438 /* Set sync refresh channels as high priority */
439 __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
441 /* Set MCU_T to divide MCU access window into 2 */
442 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
444 clk_disable(g_ipu_clk);
449 void ipu_dump_registers(void)
451 debug("IPU_CONF 0x%08X\n", __raw_readl(IPU_CONF));
452 debug("IDMAC_CONF 0x%08X\n", __raw_readl(IDMAC_CONF));
453 debug("IDMAC_CHA_EN1 0x%08X\n",
454 __raw_readl(IDMAC_CHA_EN(0)));
455 debug("IDMAC_CHA_EN2 0x%08X\n",
456 __raw_readl(IDMAC_CHA_EN(32)));
457 debug("IDMAC_CHA_PRI1 0x%08X\n",
458 __raw_readl(IDMAC_CHA_PRI(0)));
459 debug("IDMAC_CHA_PRI2 0x%08X\n",
460 __raw_readl(IDMAC_CHA_PRI(32)));
461 debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
462 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
463 debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
464 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
465 debug("DMFC_WR_CHAN 0x%08X\n",
466 __raw_readl(DMFC_WR_CHAN));
467 debug("DMFC_WR_CHAN_DEF 0x%08X\n",
468 __raw_readl(DMFC_WR_CHAN_DEF));
469 debug("DMFC_DP_CHAN 0x%08X\n",
470 __raw_readl(DMFC_DP_CHAN));
471 debug("DMFC_DP_CHAN_DEF 0x%08X\n",
472 __raw_readl(DMFC_DP_CHAN_DEF));
473 debug("DMFC_IC_CTRL 0x%08X\n",
474 __raw_readl(DMFC_IC_CTRL));
475 debug("IPU_FS_PROC_FLOW1 0x%08X\n",
476 __raw_readl(IPU_FS_PROC_FLOW1));
477 debug("IPU_FS_PROC_FLOW2 0x%08X\n",
478 __raw_readl(IPU_FS_PROC_FLOW2));
479 debug("IPU_FS_PROC_FLOW3 0x%08X\n",
480 __raw_readl(IPU_FS_PROC_FLOW3));
481 debug("IPU_FS_DISP_FLOW1 0x%08X\n",
482 __raw_readl(IPU_FS_DISP_FLOW1));
486 * This function is called to initialize a logical IPU channel.
488 * @param channel Input parameter for the logical channel ID to init.
490 * @param params Input parameter containing union of channel
491 * initialization parameters.
493 * @return Returns 0 on success or negative error code on fail
495 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
500 debug("init channel = %d\n", IPU_CHAN_ID(channel));
502 if (g_ipu_clk_enabled == 0) {
503 g_ipu_clk_enabled = 1;
504 clk_enable(g_ipu_clk);
508 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
509 printf("Warning: channel already initialized %d\n",
510 IPU_CHAN_ID(channel));
513 ipu_conf = __raw_readl(IPU_CONF);
517 if (params->mem_dc_sync.di > 1) {
522 g_dc_di_assignment[1] = params->mem_dc_sync.di;
523 ipu_dc_init(1, params->mem_dc_sync.di,
524 params->mem_dc_sync.interlaced);
525 ipu_di_use_count[params->mem_dc_sync.di]++;
527 ipu_dmfc_use_count++;
530 if (params->mem_dp_bg_sync.di > 1) {
535 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
536 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
537 params->mem_dp_bg_sync.out_pixel_fmt);
538 ipu_dc_init(5, params->mem_dp_bg_sync.di,
539 params->mem_dp_bg_sync.interlaced);
540 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
543 ipu_dmfc_use_count++;
546 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
547 params->mem_dp_fg_sync.out_pixel_fmt);
551 ipu_dmfc_use_count++;
554 printf("Missing channel initialization\n");
557 /* Enable IPU sub module */
558 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
559 if (ipu_dc_use_count == 1)
560 ipu_conf |= IPU_CONF_DC_EN;
561 if (ipu_dp_use_count == 1)
562 ipu_conf |= IPU_CONF_DP_EN;
563 if (ipu_dmfc_use_count == 1)
564 ipu_conf |= IPU_CONF_DMFC_EN;
565 if (ipu_di_use_count[0] == 1) {
566 ipu_conf |= IPU_CONF_DI0_EN;
567 clk_enable(g_di_clk[0]);
569 if (ipu_di_use_count[1] == 1) {
570 ipu_conf |= IPU_CONF_DI1_EN;
571 clk_enable(g_di_clk[1]);
574 __raw_writel(ipu_conf, IPU_CONF);
581 * This function is called to uninitialize a logical IPU channel.
583 * @param channel Input parameter for the logical channel ID to uninit.
585 void ipu_uninit_channel(ipu_channel_t channel)
588 uint32_t in_dma, out_dma = 0;
591 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
592 debug("Channel already uninitialized %d\n",
593 IPU_CHAN_ID(channel));
598 * Make sure channel is disabled
599 * Get input and output dma channels
601 in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
602 out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
604 if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
605 idma_is_set(IDMAC_CHA_EN, out_dma)) {
606 printf("Channel %d is not disabled, disable first\n",
607 IPU_CHAN_ID(channel));
611 ipu_conf = __raw_readl(IPU_CONF);
613 /* Reset the double buffer */
614 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
615 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
616 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
617 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
622 ipu_di_use_count[g_dc_di_assignment[1]]--;
624 ipu_dmfc_use_count--;
627 ipu_dp_uninit(channel);
629 ipu_di_use_count[g_dc_di_assignment[5]]--;
632 ipu_dmfc_use_count--;
635 ipu_dp_uninit(channel);
638 ipu_dmfc_use_count--;
644 g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
646 if (ipu_dc_use_count == 0)
647 ipu_conf &= ~IPU_CONF_DC_EN;
648 if (ipu_dp_use_count == 0)
649 ipu_conf &= ~IPU_CONF_DP_EN;
650 if (ipu_dmfc_use_count == 0)
651 ipu_conf &= ~IPU_CONF_DMFC_EN;
652 if (ipu_di_use_count[0] == 0 && ipu_conf & IPU_CONF_DI0_EN) {
653 ipu_conf &= ~IPU_CONF_DI0_EN;
654 clk_disable(g_di_clk[0]);
656 if (ipu_di_use_count[1] == 0 && ipu_conf & IPU_CONF_DI1_EN) {
657 ipu_conf &= ~IPU_CONF_DI1_EN;
658 clk_disable(g_di_clk[1]);
661 __raw_writel(ipu_conf, IPU_CONF);
663 /* clear interrupt status */
664 __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
667 clk_disable(g_ipu_clk);
668 g_ipu_clk_enabled = 0;
672 static inline void ipu_ch_param_dump(int ch)
675 struct ipu_ch_param *p = ipu_ch_param_addr(ch);
676 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
677 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
678 p->word[0].data[3], p->word[0].data[4]);
679 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
680 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
681 p->word[1].data[3], p->word[1].data[4]);
683 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
685 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
687 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
690 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
692 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
694 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
696 debug("Width0 %d+1, ",
697 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
698 debug("Width1 %d+1, ",
699 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
700 debug("Width2 %d+1, ",
701 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
702 debug("Width3 %d+1, ",
703 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
704 debug("Offset0 %d, ",
705 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
706 debug("Offset1 %d, ",
707 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
708 debug("Offset2 %d, ",
709 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
710 debug("Offset3 %d\n",
711 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
715 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
716 int red_width, int red_offset,
717 int green_width, int green_offset,
718 int blue_width, int blue_offset,
719 int alpha_width, int alpha_offset)
721 /* Setup red width and offset */
722 ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
723 ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
724 /* Setup green width and offset */
725 ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
726 ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
727 /* Setup blue width and offset */
728 ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
729 ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
730 /* Setup alpha width and offset */
731 ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
732 ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
735 static void ipu_ch_param_init(int ch,
736 uint32_t pixel_fmt, uint32_t width,
737 uint32_t height, uint32_t stride,
738 uint32_t u, uint32_t v,
739 uint32_t uv_stride, dma_addr_t addr0,
742 uint32_t u_offset = 0;
743 uint32_t v_offset = 0;
745 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
747 if ((ch == 8) || (ch == 9) || (ch == 10)) {
748 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
749 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
751 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
752 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
755 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
756 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
759 case IPU_PIX_FMT_GENERIC:
760 /*Represents 8-bit Generic data */
761 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5); /* bits/pixel */
762 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6); /* pix format */
763 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63); /* burst size */
766 case IPU_PIX_FMT_GENERIC_32:
767 /*Represents 32-bit Generic data */
769 case IPU_PIX_FMT_RGB565:
770 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
771 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
772 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
774 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
776 case IPU_PIX_FMT_BGR24:
777 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */
778 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
779 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */
781 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
783 case IPU_PIX_FMT_RGB24:
784 case IPU_PIX_FMT_YUV444:
785 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */
786 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
787 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */
789 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
791 case IPU_PIX_FMT_BGRA32:
792 case IPU_PIX_FMT_BGR32:
793 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
794 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
795 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
797 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
799 case IPU_PIX_FMT_RGBA32:
800 case IPU_PIX_FMT_RGB32:
801 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
802 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
803 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
805 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
807 case IPU_PIX_FMT_ABGR32:
808 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
809 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
811 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
813 case IPU_PIX_FMT_UYVY:
814 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
815 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA); /* pix format */
816 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
818 case IPU_PIX_FMT_YUYV:
819 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
820 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8); /* pix format */
821 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
823 case IPU_PIX_FMT_YUV420P2:
824 case IPU_PIX_FMT_YUV420P:
825 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2); /* pix format */
827 if (uv_stride < stride / 2)
828 uv_stride = stride / 2;
830 u_offset = stride * height;
831 v_offset = u_offset + (uv_stride * height / 2);
833 if ((ch == 8) || (ch == 9) || (ch == 10)) {
834 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
835 uv_stride = uv_stride*2;
837 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
840 case IPU_PIX_FMT_YVU422P:
841 /* BPP & pixel format */
842 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */
843 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
845 if (uv_stride < stride / 2)
846 uv_stride = stride / 2;
848 v_offset = (v == 0) ? stride * height : v;
849 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
851 case IPU_PIX_FMT_YUV422P:
852 /* BPP & pixel format */
853 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */
854 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
856 if (uv_stride < stride / 2)
857 uv_stride = stride / 2;
859 u_offset = (u == 0) ? stride * height : u;
860 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
862 case IPU_PIX_FMT_NV12:
863 /* BPP & pixel format */
864 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4); /* pix format */
865 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
867 u_offset = (u == 0) ? stride * height : u;
870 printf("mxc ipu: unimplemented pixel format: %08x\n",
876 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
878 /* Get the uv offset from user when need cropping */
884 /* UBO and VBO are 22-bit */
885 if (u_offset/8 > 0x3fffff)
886 puts("The value of U offset exceeds IPU limitation\n");
887 if (v_offset/8 > 0x3fffff)
888 puts("The value of V offset exceeds IPU limitation\n");
890 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
891 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
893 debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
897 * This function is called to initialize a buffer for logical IPU channel.
899 * @param channel Input parameter for the logical channel ID.
901 * @param type Input parameter which buffer to initialize.
903 * @param pixel_fmt Input parameter for pixel format of buffer.
904 * Pixel format is a FOURCC ASCII code.
906 * @param width Input parameter for width of buffer in pixels.
908 * @param height Input parameter for height of buffer in pixels.
910 * @param stride Input parameter for stride length of buffer
913 * @param phyaddr_0 Input parameter buffer 0 physical address.
915 * @param phyaddr_1 Input parameter buffer 1 physical address.
916 * Setting this to a value other than NULL enables
917 * double buffering mode.
919 * @param u private u offset for additional cropping,
922 * @param v private v offset for additional cropping,
925 * @return Returns 0 on success or negative error code on fail
927 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
929 uint16_t width, uint16_t height,
931 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
932 uint32_t u, uint32_t v)
937 dma_chan = channel_2_dma(channel, type);
938 if (!idma_is_valid(dma_chan))
941 if (stride < width * bytes_per_pixel(pixel_fmt))
942 stride = width * bytes_per_pixel(pixel_fmt);
945 printf("Stride %d not 32-bit aligned\n", stride);
948 /* Build parameter memory data for DMA channel */
949 ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
950 phyaddr_0, phyaddr_1);
952 if (ipu_is_dmfc_chan(dma_chan)) {
953 ipu_dmfc_set_wait4eot(dma_chan, width);
956 if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
957 ipu_ch_param_set_high_priority(dma_chan);
959 ipu_ch_param_dump(dma_chan);
961 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
963 reg |= idma_mask(dma_chan);
965 reg &= ~idma_mask(dma_chan);
966 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
968 /* Reset to buffer 0 */
969 __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
975 * This function enables a logical channel.
977 * @param channel Input parameter for the logical channel ID.
979 * @return This function returns 0 on success or negative error code on
982 int32_t ipu_enable_channel(ipu_channel_t channel)
988 if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
989 printf("Warning: channel already enabled %d\n",
990 IPU_CHAN_ID(channel));
993 /* Get input and output dma channels */
994 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
995 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
997 if (idma_is_valid(in_dma)) {
998 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
999 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1001 if (idma_is_valid(out_dma)) {
1002 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1003 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1006 if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1007 (channel == MEM_FG_SYNC)) {
1008 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1009 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1011 ipu_dp_dc_enable(channel);
1014 g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1020 * This function clear buffer ready for a logical channel.
1022 * @param channel Input parameter for the logical channel ID.
1024 * @param type Input parameter which buffer to clear.
1026 * @param bufNum Input parameter for which buffer number clear
1030 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1033 uint32_t dma_ch = channel_2_dma(channel, type);
1035 if (!idma_is_valid(dma_ch))
1038 __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1040 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1041 __raw_writel(idma_mask(dma_ch),
1042 IPU_CHA_BUF0_RDY(dma_ch));
1045 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1046 __raw_writel(idma_mask(dma_ch),
1047 IPU_CHA_BUF1_RDY(dma_ch));
1050 __raw_writel(0x0, IPU_GPR); /* write one to set */
1054 * This function disables a logical channel.
1056 * @param channel Input parameter for the logical channel ID.
1058 * @param wait_for_stop Flag to set whether to wait for channel end
1059 * of frame or return immediately.
1061 * @return This function returns 0 on success or negative error code on
1064 int32_t ipu_disable_channel(ipu_channel_t channel)
1070 if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1071 debug("Channel already disabled %d\n",
1072 IPU_CHAN_ID(channel));
1076 /* Get input and output dma channels */
1077 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1078 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1080 if ((idma_is_valid(in_dma) &&
1081 !idma_is_set(IDMAC_CHA_EN, in_dma))
1082 && (idma_is_valid(out_dma) &&
1083 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1086 if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1087 (channel == MEM_DC_SYNC)) {
1088 ipu_dp_dc_disable(channel, 0);
1091 /* Disable DMA channel(s) */
1092 if (idma_is_valid(in_dma)) {
1093 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1094 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1095 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1097 if (idma_is_valid(out_dma)) {
1098 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1099 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1100 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1103 g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1105 /* Set channel buffers NOT to be ready */
1106 if (idma_is_valid(in_dma)) {
1107 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1108 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1110 if (idma_is_valid(out_dma)) {
1111 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1112 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1118 uint32_t bytes_per_pixel(uint32_t fmt)
1121 case IPU_PIX_FMT_GENERIC: /* generic data */
1122 case IPU_PIX_FMT_RGB332:
1123 case IPU_PIX_FMT_YUV420P:
1124 case IPU_PIX_FMT_YUV422P:
1126 case IPU_PIX_FMT_RGB565:
1127 case IPU_PIX_FMT_YUYV:
1128 case IPU_PIX_FMT_UYVY:
1130 case IPU_PIX_FMT_BGR24:
1131 case IPU_PIX_FMT_RGB24:
1133 case IPU_PIX_FMT_GENERIC_32: /* generic data */
1134 case IPU_PIX_FMT_BGR32:
1135 case IPU_PIX_FMT_BGRA32:
1136 case IPU_PIX_FMT_RGB32:
1137 case IPU_PIX_FMT_RGBA32:
1138 case IPU_PIX_FMT_ABGR32:
1146 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1149 case IPU_PIX_FMT_RGB666:
1150 case IPU_PIX_FMT_RGB565:
1151 case IPU_PIX_FMT_BGR24:
1152 case IPU_PIX_FMT_RGB24:
1153 case IPU_PIX_FMT_BGR32:
1154 case IPU_PIX_FMT_BGRA32:
1155 case IPU_PIX_FMT_RGB32:
1156 case IPU_PIX_FMT_RGBA32:
1157 case IPU_PIX_FMT_ABGR32:
1158 case IPU_PIX_FMT_LVDS666:
1159 case IPU_PIX_FMT_LVDS888: