5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
14 #ifndef __IPU_REGS_INCLUDED__
15 #define __IPU_REGS_INCLUDED__
17 #include <asm/arch/imx-regs.h>
19 #define IPU_DISP0_BASE 0x00000000
20 #define IPU_MCU_T_DEFAULT 8
21 #define IPU_DISP1_BASE (gd->arch.ipu_hw_rev < IPUV3_HW_REV_IPUV3H ? \
22 (IPU_MCU_T_DEFAULT << 25) : \
25 #define IPUV3DEX_REG_BASE 0x1E000000
26 #define IPUV3M_REG_BASE 0x1E000000
27 #define IPUV3H_REG_BASE 0x00200000
29 #define IPU_CM_REG_BASE 0x00000000
30 #define IPU_STAT_REG_BASE 0x00000200
31 #define IPU_IDMAC_REG_BASE 0x00008000
32 #define IPU_ISP_REG_BASE 0x00010000
33 #define IPU_DP_REG_BASE 0x00018000
34 #define IPU_IC_REG_BASE 0x00020000
35 #define IPU_IRT_REG_BASE 0x00028000
36 #define IPU_CSI0_REG_BASE 0x00030000
37 #define IPU_CSI1_REG_BASE 0x00038000
38 #define IPU_DI0_REG_BASE 0x00040000
39 #define IPU_DI1_REG_BASE 0x00048000
40 #define IPU_SMFC_REG_BASE 0x00050000
41 #define IPU_DC_REG_BASE 0x00058000
42 #define IPU_DMFC_REG_BASE 0x00060000
43 #define IPU_VDI_REG_BASE 0x00068000
44 #define IPU_CPMEM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
47 #define IPU_LUT_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
50 #define IPU_SRM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
53 #define IPU_TPM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
56 #define IPU_DC_TMPL_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
59 #define IPU_ISP_TBPR_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
63 #define IPU_DISP_REG_BASE_ADDR (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
64 IPU_SOC_BASE_ADDR + IPUV3H_REG_BASE : \
65 IPU_SOC_BASE_ADDR + IPUV3M_REG_BASE)
67 extern u32 *ipu_dc_tmpl_reg;
68 extern struct clk *g_ipu_clk;
69 extern struct clk *g_ldb_clk;
70 extern struct clk *g_di_clk[2];
71 extern struct clk *g_pixel_clk[2];
73 extern int g_ipu_clk_enabled;
74 extern unsigned char g_dc_di_assignment[];
79 #define DC_EVT_NFIELD 3
81 #define DC_EVT_EOFIELD 5
82 #define DC_EVT_NEW_ADDR 6
83 #define DC_EVT_NEW_CHAN 7
84 #define DC_EVT_NEW_DATA 8
86 #define DC_EVT_NEW_ADDR_W_0 0
87 #define DC_EVT_NEW_ADDR_W_1 1
88 #define DC_EVT_NEW_CHAN_W_0 2
89 #define DC_EVT_NEW_CHAN_W_1 3
90 #define DC_EVT_NEW_DATA_W_0 4
91 #define DC_EVT_NEW_DATA_W_1 5
92 #define DC_EVT_NEW_ADDR_R_0 6
93 #define DC_EVT_NEW_ADDR_R_1 7
94 #define DC_EVT_NEW_CHAN_R_0 8
95 #define DC_EVT_NEW_CHAN_R_1 9
96 #define DC_EVT_NEW_DATA_R_0 10
97 #define DC_EVT_NEW_DATA_R_1 11
99 /* Software reset for ipu */
103 IPU_CONF_DP_EN = 0x00000020,
104 IPU_CONF_DI0_EN = 0x00000040,
105 IPU_CONF_DI1_EN = 0x00000080,
106 IPU_CONF_DMFC_EN = 0x00000400,
107 IPU_CONF_DC_EN = 0x00000200,
109 DI0_COUNTER_RELEASE = 0x01000000,
110 DI1_COUNTER_RELEASE = 0x02000000,
112 DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
113 DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
115 DI_GEN_DI_CLK_EXT = 0x00100000,
116 DI_GEN_POLARITY_1 = 0x00000001,
117 DI_GEN_POLARITY_2 = 0x00000002,
118 DI_GEN_POLARITY_3 = 0x00000004,
119 DI_GEN_POLARITY_4 = 0x00000008,
120 DI_GEN_POLARITY_5 = 0x00000010,
121 DI_GEN_POLARITY_6 = 0x00000020,
122 DI_GEN_POLARITY_7 = 0x00000040,
123 DI_GEN_POLARITY_8 = 0x00000080,
124 DI_GEN_POL_CLK = 0x00020000,
126 DI_POL_DRDY_DATA_POLARITY = 0x00000080,
127 DI_POL_DRDY_POLARITY_15 = 0x00000010,
128 DI_VSYNC_SEL_OFFSET = 13,
130 DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
131 DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
132 DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
133 DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
134 DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
135 DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
137 DP_COM_CONF_FG_EN = 0x00000001,
138 DP_COM_CONF_GWSEL = 0x00000002,
139 DP_COM_CONF_GWAM = 0x00000004,
140 DP_COM_CONF_GWCKE = 0x00000008,
141 DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
142 DP_COM_CONF_CSC_DEF_OFFSET = 8,
143 DP_COM_CONF_CSC_DEF_FG = 0x00000300,
144 DP_COM_CONF_CSC_DEF_BG = 0x00000200,
145 DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
146 DP_COM_CONF_GAMMA_EN = 0x00001000,
147 DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
167 DI_SYNC_INT_HSYNC = 1,
194 u32 ch_db_mode_sel[2];
196 u32 alt_ch_db_mode_sel[2];
198 u32 ch_trb_mode_sel[2];
216 struct ipu_com_async {
218 u32 graph_wind_ctrl_async;
222 u32 gamma_c_async[8];
223 u32 gamma_s_async[4];
224 u32 dp_csca_async[4];
230 u32 graph_wind_ctrl_sync;
239 struct ipu_com_async async[2];
270 u32 triple_cur_buf[4];
273 u32 alt_ch_buf0_rdy[2];
274 u32 alt_ch_buf1_rdy[2];
285 struct ipu_dc_ch dc_ch0_1_2[3];
288 struct ipu_dc_ch dc_ch5_6[2];
289 struct ipu_dc_ch dc_ch8;
291 struct ipu_dc_ch dc_ch9;
303 u32 wr_ch_addr_5_alt;
321 #define IPU_CM_REG ((struct ipu_cm *)(IPU_DISP_REG_BASE_ADDR + \
323 #define IPU_CONF (&IPU_CM_REG->conf)
324 #define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
325 #define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
326 #define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
327 #define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
328 #define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
329 #define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
330 #define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
331 #define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
332 #define IPU_PM (&IPU_CM_REG->pm)
333 #define IPU_GPR (&IPU_CM_REG->gpr)
334 #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[(ch) / 32])
336 #define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \
338 #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[(ch) / 32])
339 #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[(ch) / 32])
340 #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[(ch) / 32])
342 #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
344 #define IDMAC_REG ((struct ipu_idmac *)(IPU_DISP_REG_BASE_ADDR + \
346 #define IDMAC_CONF (&IDMAC_REG->conf)
347 #define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[(ch) / 32])
348 #define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[(ch) / 32])
349 #define IDMAC_WM_EN(ch) (&IDMAC_REG->wm_en[(ch) / 32])
351 #define DI_REG(di) ((struct ipu_di *)(IPU_DISP_REG_BASE_ADDR + \
352 (((di) == 1) ? IPU_DI1_REG_BASE : \
355 #define DI_GENERAL(di) (&DI_REG(di)->general)
356 #define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
357 #define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
359 #define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[(gen) - 1])
360 #define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[(gen) - 1])
361 #define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[((gen) - 1) / 2])
362 #define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
363 #define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
364 #define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[(gen) + 12 * set])
365 #define DI_POL(di) (&DI_REG(di)->pol)
366 #define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
368 #define DMFC_REG ((struct ipu_dmfc *)(IPU_DISP_REG_BASE_ADDR + \
370 #define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
371 #define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
372 #define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
373 #define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
374 #define DMFC_GENERAL1 (&DMFC_REG->general[0])
375 #define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
377 #define DC_REG ((struct ipu_dc *)(IPU_DISP_REG_BASE_ADDR + \
379 #define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[(n) / 2])
380 #define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[(n) / 2])
382 DECLARE_GLOBAL_DATA_PTR;
384 static inline struct ipu_dc_ch *dc_ch_offset(int ch)
390 return &DC_REG->dc_ch0_1_2[ch];
393 return &DC_REG->dc_ch5_6[ch - 5];
395 return &DC_REG->dc_ch8;
397 return &DC_REG->dc_ch9;
399 printf("%s: invalid channel %d\n", __func__, ch);
404 #define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[(evt) / 2])
406 #define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
407 #define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
409 #define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
410 #define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
412 #define DC_GEN (&DC_REG->gen)
413 #define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
414 #define DC_STAT (&DC_REG->stat)
417 #define DP_ASYNC0 0x60
418 #define DP_ASYNC1 0xBC
420 #define DP_REG ((struct ipu_dp *)(IPU_DISP_REG_BASE_ADDR + \
422 #define DP_COM_CONF() (&DP_REG->com_conf_sync)
423 #define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
424 #define DP_CSC_A_0() (&DP_REG->csca_sync[0])
425 #define DP_CSC_A_1() (&DP_REG->csca_sync[1])
426 #define DP_CSC_A_2() (&DP_REG->csca_sync[2])
427 #define DP_CSC_A_3() (&DP_REG->csca_sync[3])
429 #define DP_CSC_0() (&DP_REG->csc_sync[0])
430 #define DP_CSC_1() (&DP_REG->csc_sync[1])
432 /* DC template opcodes */
433 #define WROD(lf) (0x18 | ((lf) << 1))